Fully integrated low-dropout linear voltage regulator and chip and system

Abstract

The application relates to the technical field of integrated circuits, and discloses a fully integrated low-dropout linear voltage regulator, a chip and a system. The voltage regulator comprises an overshoot suppression circuit composed of a high-pass operational amplifier and a first transistor, which directly acts on an output end to suppress overshoot; and an undershoot suppression circuit composed of a transconductance amplifier, a capacitor and a resistor, which acts on a power transistor gate to suppress undershoot. Through separate transient suppression paths, the application simultaneously suppresses output voltage fluctuation, generates a left half plane zero point by using the undershoot suppression circuit, and reduces high-frequency output impedance by using the overshoot suppression circuit, so that loop stability and high-frequency power supply rejection ratio are simultaneously improved. The design does not require an off-chip capacitor, thereby saving cost and area.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to low dropout linear regulator technology. BACKGROUND

[0002] A low dropout linear regulator (LDO) is a kind of DC voltage regulator, which can provide a stable, low-noise DC output voltage for the load when the input voltage and the output voltage have a small difference. The two key performance indicators of LDO are transient response and power supply rejection ratio (PSRR).

[0003] Transient response refers to the ability of LDO to maintain the stability of its output voltage when the load current changes suddenly. When the load current suddenly increases, the output voltage will drop instantaneously, resulting in "undershoot"; conversely, when the load current suddenly decreases, the output voltage will rise instantaneously, resulting in "overshoot". Fast transient response means that LDO can control the amplitude and duration of overshoot and undershoot within a very small range.

[0004] Power supply rejection ratio (PSRR) measures the ability of LDO to suppress noise or ripple from the input power supply. In practical applications, the input power supply of LDO is often not ideal pure DC, and may contain high-frequency ripple or other noise from the front stage of the switching power supply. High PSRR means that LDO can effectively prevent these input disturbances from being transmitted to the output, thereby ensuring the purity of the output voltage.

[0005] In traditional LDO design, a large-capacity off-chip capacitor is usually connected in parallel at the output, but this design will significantly increase the final cost of the product and the area occupied by the printed circuit board (PCB).

[0006] In order to improve the performance of LDO without off-chip capacitors, some enhancement circuits have been developed in existing technologies. For example Figure 1 The traditional scheme shown in FIG. 1 increases the overshoot and undershoot detection circuits at the output. When a transient event is detected, the corresponding slew rate enhancement circuit will forcibly charge or discharge the gate of the power tube to speed up its response. However, one inherent defect of this method is that the amplitude of the slew rate enhancement is difficult to control accurately. If the enhancement amplitude is insufficient, the improvement effect on the transient response will be limited; if the enhancement amplitude is too large, it will easily introduce too large a phase shift in the feedback loop, causing the circuit to oscillate and seriously affecting the stability of the system. SUMMARY

[0007] One object of the present application is to provide a fully integrated low-dropout linear regulator to solve the technical problem of how to achieve high power supply rejection ratio and fast transient response without sacrificing circuit stability and without significantly increasing design complexity in a fully integrated low-dropout linear regulator.

[0008] The present application discloses a low-dropout linear regulator, comprising:

[0009] a power transistor, whose source is connected to an input voltage, and whose drain is connected to an output terminal of the low-dropout linear regulator;

[0010] an error amplifier, whose two input terminals are respectively connected to a DC voltage reference and a feedback signal from the output terminal of the low-dropout linear regulator;

[0011] a source follower transistor, whose gate is connected to an output terminal of the error amplifier, whose source is connected to the output terminal of the low-dropout linear regulator, and whose drain is connected to a gate of the power transistor;

[0012] a bias current source, one end of which is connected to the drain of the source follower transistor, and the other end of which is grounded;

[0013] a high-pass operational amplifier, whose in-phase first input terminal is connected to the output terminal of the low-dropout linear regulator, and whose anti-phase second input terminal is connected to a DC bias voltage; and

[0014] a first transistor, whose gate is connected to an output terminal of the high-pass operational amplifier, and which is configured to form a conductive path between the output terminal of the low-dropout linear regulator and ground, which is controlled by the output terminal of the high-pass operational amplifier.

[0015] In a preferred embodiment, further comprising:

[0016] a capacitor, whose first end is connected to the output terminal of the low-dropout linear regulator;

[0017] a resistor, one end of which is connected to a second end of the capacitor, and the other end of which is grounded; and

[0018] a transconductance amplifier, whose input terminal is connected to a connection point of the capacitor and the resistor, and whose output terminal is connected to the gate of the power transistor; the transconductance amplifier is configured to output only negative current.

[0019] In a preferred embodiment, the transconductance amplifier comprises an NMOS transistor, wherein:

[0020] a gate of the NMOS transistor is connected to a fixed bias voltage;

[0021] a source of the NMOS transistor constitutes an input terminal of the transconductance amplifier;

[0022] The drain of the NMOS transistor constitutes the output terminal of the transconductance amplifier.

[0023] In one preferred embodiment, the high-pass op-amp comprises:

[0024] a low-pass op-amp;

[0025] a second transistor; and

[0026] a bias current source;

[0027] wherein the source of the second transistor serves as the non-inverting input terminal of the high-pass op-amp, the gate thereof is connected to the output terminal of the low-pass op-amp, and the drain thereof serves as the output terminal of the high-pass op-amp.

[0028] the non-inverting input terminal of the low-pass op-amp is connected to the output terminal of the high-pass op-amp, and the inverting input terminal thereof is used to connect the DC bias voltage;

[0029] the bias current source is connected between the output terminal of the high-pass op-amp and the ground terminal.

[0030] In one preferred embodiment, the source follower transistor is a PMOS transistor.

[0031] In one preferred embodiment, the power transistor is a PMOS transistor.

[0032] In one preferred embodiment, the first transistor is an NMOS transistor, the drain thereof is connected to the output terminal of the low-dropout linear regulator, and the source thereof is grounded; the non-inverting input terminal of the high-pass op-amp is connected to the output terminal of the low-dropout linear regulator, and the inverting input terminal of the high-pass op-amp is connected to the DC bias voltage.

[0033] In one preferred embodiment, the first transistor is a PMOS transistor, the source thereof is connected to the output terminal of the low-dropout linear regulator, and the drain thereof is grounded; the inverting input terminal of the high-pass op-amp is connected to the output terminal of the low-dropout linear regulator, and the non-inverting input terminal of the high-pass op-amp is connected to the DC bias voltage.

[0034] The present application also discloses a power management chip comprising the low-dropout linear regulator as described above.

[0035] The present application also discloses a system on chip comprising the low-dropout linear regulator as described above.

[0036] In the embodiments of the present application, by adopting a specific architecture of an overshoot suppression loop acting independently on the output and composed of a high-pass operational amplifier and a first transistor, precise regulation of the output voltage and fast response to transient events can be achieved without affecting the stability of the main loop. Specifically, when an overshoot occurs at the output, the high-pass operational amplifier amplifies the transient spike and controls the first transistor to form a conductive path between the output and ground, thereby rapidly discharging the excess charge at the output to suppress the overshoot amplitude; at the same time, since the high-pass operational amplifier has gain only at high frequencies, it reduces the output impedance and improves the high-frequency power supply rejection ratio (PSRR) without affecting the DC stability of the circuit; in addition, the overshoot and undershoot suppression circuits do not act jointly on the gate of the power transistor, which greatly improves the stability of the entire system.

[0037] Further, by adding an undershoot suppression circuit composed of a capacitor, a resistor, and a transconductance amplifier capable of outputting only negative current between the output and the gate of the power transistor, when an undershoot occurs at the output of the LDO, the circuit rapidly discharges the gate of the power transistor, thereby enhancing the transient slew rate of the gate and effectively suppressing the amplitude of the output undershoot; at the same time, the circuit acts jointly with the source follower transistor to introduce a left-half-plane zero in the system, thereby improving the loop stability, increasing the loop bandwidth, and further improving the PSRR of the LDO at high frequencies.

[0038] By implementing the transconductance amplifier as an NMOS transistor with a fixed bias voltage connected to the gate, an input terminal connected to the source, and an output terminal connected to the drain, a very simple and chip area-saving structure can be used to cleverly achieve the one-way working characteristic of the transconductance amplifier capable of outputting only negative current (sink current), ensuring that the undershoot suppression circuit only works when needed without adversely affecting the overshoot or steady state.

[0039] Further, by implementing the high-pass operational amplifier as a specific feedback structure composed of a conventional low-pass operational amplifier with low-pass characteristics, a second transistor, and a bias current source, a transfer function with a zero point and a pole much higher than the zero point frequency can be accurately constructed, thereby obtaining the ideal high-pass response characteristic of approximately zero gain at low frequencies and gain at high frequencies, ensuring that the overshoot suppression circuit only responds to high-frequency transient signals.

[0040] By integrating the aforementioned low-dropout linear regulator into a power management chip, the chip can be provided with a high-performance voltage regulation core without the need for an off-chip capacitor, with high PSRR and fast transient response, thereby significantly reducing the overall cost and package size of the power management chip and improving its market competitiveness.

[0041] By integrating the low dropout linear regulator into the system on chip, clean and stable power supply can be provided for the modules sensitive to power supply noise and voltage fluctuation in the SoC (such as analog circuit, phase-locked loop, etc.), thereby improving the working stability and performance of the entire system on chip and meeting the demand of modern SoC for high integration and high performance power management.

[0042] Each of the technical features disclosed in the above summary, each of the technical features disclosed in the following embodiments and examples, and each of the technical features disclosed in the drawings can be freely combined with each other to form various new technical solutions (all of which should be regarded as having been described in the present specification) unless such combination of technical features is technically infeasible. For example, features A+B+C are disclosed in one example, features A+B+D+E are disclosed in another example, features C and D are equivalent technical means playing the same role, and only one of them can be used in technology, and feature E can be combined with feature C in technology. Therefore, the scheme of A+B+C+D should not be regarded as having been described because it is technically infeasible, and the scheme of A+B+C+E should be regarded as having been described. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 is a schematic diagram of a transient enhancement circuit in the prior art;

[0044] Figure 2 is a schematic diagram of a circuit according to an embodiment of the present application;

[0045] Figure 3 is a schematic diagram of the amplitude-frequency curve of a high-pass operational amplifier according to an embodiment of the present application;

[0046] Figure 4 is an implementation of a high-pass operational amplifier according to an embodiment of the present application;

[0047] Figure 5 is a comparison diagram of PSR with overshoot and undershoot suppression circuit and PSR without overshoot and undershoot suppression circuit.

[0048] The main reference signs are as follows:

[0049] 1 - error amplifier,

[0050] 2 - undershoot suppression circuit,

[0051] 3 - power transistor,

[0052] 4 - source follower transistor,

[0053] 5 - bias current source,

[0054] 6 - overshoot suppression circuit. DETAILED DESCRIPTION

[0055] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one ordinarily skilled in the art that the application can be practiced without the specific details and that numerous implementation variations and modifications from these implementations can be possible.

[0056] Explanation of some concepts:

[0057] PMOS: P-channel Metal-Oxide-Semiconductor.

[0058] NMOS: N-channel Metal-Oxide-Semiconductor.

[0059] High-pass op-amp: an operational amplifier that has gain only at high frequencies, and no gain at low frequencies. High-pass and low-pass are conventional expressions in the art, and are commonly used in general terms such as high-pass filter, low-pass filter, etc.

[0060] For the purpose of making the present application, technical solutions and advantages more clear, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0061] Reference is made to Figure 2 , which shows a circuit schematic diagram of a high power supply rejection ratio, fast transient response, fully integrated low dropout linear regulator (LDO) provided by the preferred embodiment of the present application. The regulator mainly comprises: an error amplifier 1, a power transistor 3 (Mp), a source follower transistor 4 (MO), a bias current source 5, a undershoot suppression circuit 2 and an overshoot suppression circuit 6.

[0062] In the present embodiment, the power transistor Mp is preferably a PMOS transistor. Its source is connected to the input voltage Vin of the LDO, and its drain is used as the output terminal Vout of the LDO.

[0063] The non-inverting input terminal of the error amplifier 1 is connected to a DC voltage reference Vref, and the inverting input terminal is connected to a feedback signal from the output terminal Vout of the LDO. The feedback signal is obtained through a resistance dividing network connected between Vout and ground. For example, in Figure 2 , two resistors are connected in series between Vout and ground, and the feedback signal can be taken from the connection point of the two resistors and coupled to the inverting input terminal of the error amplifier 1.

[0064] The source follower transistor MO and the bias current source 5 constitute the core part of the main feedback loop. The source follower transistor MO is preferably a PMOS transistor, the gate of which is connected to the output terminal of the error amplifier 1, the source of which is connected to the output terminal Vout of the LDO, and the drain of which is connected to the gate of the power transistor Mp. One end of the bias current source 5 is connected to the drain of the source follower transistor MO, and the other end is grounded.

[0065] The overshoot suppression circuit 6 comprises a high-pass operational amplifier A(s) and a discharge transistor (hereinafter also referred to as "first transistor") M1. In the present embodiment, the first transistor M1 is preferably an NMOS transistor. The non-inverting input terminal of the high-pass operational amplifier is connected to the output terminal Vout of the LDO, and the inverting input terminal is connected to a DC bias voltage Vb. The output terminal of the high-pass operational amplifier is connected to the gate of the first transistor M1. The drain of the first transistor M1 is connected to the output terminal Vout of the LDO, and the source is grounded. In another embodiment, the first transistor M1 can also be replaced by a PMOS transistor, the source of which is connected to the output terminal Vout of the LDO, and the drain is grounded. Correspondingly, the two input terminals of the high-pass operational amplifier are also adjusted, the non-inverting input terminal of which is connected to the output terminal Vb of the LDO, and the inverting input terminal is connected to the DC bias voltage Vout.

[0066] When the output Vout of the LDO produces an overshoot, the voltage spike signal will be amplified by the high-pass operational amplifier, thereby raising the gate potential of the first transistor M1. M1 is then turned on, forming a conductive path between the output terminal of the LDO and the ground, rapidly discharging the excess charge at the output terminal, thereby effectively suppressing the overshoot amplitude of the output. Since the high-pass operational amplifier has no gain at low frequencies, the circuit does not work in the steady state or under DC changes, ensuring the stability of the system. When the output of the LDO produces an undershoot, the gate potential of M1 will be pulled down, so that it enters the cutoff region and does not work, so the entire overshoot suppression circuit does not work during the LDO output undershoot phase. In addition, the input impedance of the overshoot suppression circuit from the LDO output terminal can be represented as where g m1 is the transconductance of M1, and A(s) is the gain of the high-pass operational amplifier. At high frequencies, since the gain A(s) of the high-pass operational amplifier increases, the impedance becomes very small, thereby reducing the overall output impedance of the LDO, further improving the PSRR at high frequencies.

[0067] The high-pass operational amplifier and the discharge transistor form a feedback loop, and the discharge current can be adaptively matched to the initial overshoot amplitude of the LDO output. The initial overshoot amplitude is the overshoot amplitude before the overshoot suppression circuit is added. When the initial overshoot is large, the discharge current is also large, and when the initial overshoot is small, the discharge current is also small. Since the size of the discharge current can be adaptively matched to the overshoot amplitude, the stability of the overall circuit is also greatly improved.

[0068] Referring toFigure 4 which shows one specific embodiment of the high-pass op-amp in this application. The high-pass op-amp is composed of a conventional low-pass op-amp 61, a PMOS transistor M2 and a bias current source 62. The conventional low-pass op-amp 61 has low-pass transfer characteristic where G represents the gain of the low-pass op-amp 61, s is the complex frequency, and ω0 represents the cutoff frequency of the low-pass op-amp 61. The transconductance of the transistor M2 is and the impedance is The transfer function of the high-pass op-amp is

[0069]

[0070] where Vg is the voltage at the output of the high-pass op-amp 6. From the function, it can be seen that the circuit has a zero point and a pole The pole is far higher than the zero point, and the DC gain is approximately zero, so the circuit has an ideal high-pass amplitude-frequency characteristic as shown in Figure 3

[0071] Referring to Figure 2 , the undershoot suppression circuit 2 includes a capacitor Cf, a resistor Rf and a transconductance amplifier gmf. One end of the capacitor Cf is connected to the LDO output, the other end is connected to the input end of the resistor Rf and the transconductance amplifier gmf; the other end of the resistor Rf is grounded; the output end of the transconductance amplifier gmf is connected to the gate of the power transistor Mp.

[0072] When the output Vout of the LDO produces undershoot, the rapidly changing undershoot signal will be coupled to the input end of the transconductance amplifier gmf through the high-pass filter composed of Cf and Rf. The transconductance amplifier gmf then outputs a negative current (sink current) to rapidly discharge the gate of the power transistor Mp, thereby increasing the slew rate of the gate and effectively suppressing the amplitude of the output undershoot. A key point in this embodiment is that the transconductance amplifier gmf is designed to only output negative current, but not positive current. As one specific embodiment, the transconductance amplifier can be implemented by an NMOS transistor, whose gate is connected to a fixed bias, the source is the input, and the drain is the output. This structure naturally meets the one-way output current characteristic, ensuring that the circuit will not work when the output overshoots.

[0073] In addition, the undershoot suppression circuit and the source follower transistor MO together produce a left half plane zero point in the loop, whose frequency is where g mf is the transconductance of the transconductance amplifier, g mo is the transconductance of the transistor MO, and R f ​Rf is the resistance value of the resistor Rf f Cf is the capacitance value of the capacitor Cf. This zero effectively improves the phase margin of the loop, improves the stability, and enables the loop bandwidth to be increased, thereby further improving the PSRR of the LDO at the high frequency band.

[0074] Referring to Figure 5 , which shows a PSR simulation comparison chart of the embodiment of the present application and the prior art. The dashed line in the chart is the PSR curve of the LDO without the overshoot and undershoot suppression circuit, and the solid line is the PSR curve after the overshoot and undershoot suppression circuit designed in the present application is added. As can be clearly seen from the chart, the design of the present application greatly improves the PSRR performance in the high frequency band. Specifically, Figure 5 The horizontal axis of the chart is the frequency (freq) in hertz (Hz), and the higher to the right represents the higher frequency. The vertical axis is the gain of the LDO output to the input, representing the value of the power suppression, in decibels (dB). For PSR, the lower this value (i.e., the more negative), the better the suppression effect. Observing the high frequency region (e.g., the range from 105 Hz to 108 Hz) in the chart, it can be clearly seen that the solid line is obviously below the dashed line. This means that at the same high frequency, the LDO using the new circuit (solid line) has a significantly lower dB value than the LDO without using it (dashed line).

[0075] In summary, through the cooperative work of the designed undershoot suppression circuit and overshoot suppression circuit, the present application significantly improves the transient response speed and power supply rejection ratio of the LDO without the need for an external output capacitor, while also improving the loop stability. The present application has a simple structure and is easy to integrate, reduces the design complexity, saves chip area and cost, and greatly improves the competitiveness of the product.

[0076] It should be noted that in the present application, relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "includes one" does not exclude the presence of another identical element in the process, method, article or device including the element.

[0077] This specification includes combinations of the various embodiments described herein. References to an embodiment, or implementations, for example, do not necessarily refer to the same embodiment; however, such embodiments are not mutually exclusive, unless expressly stated otherwise. It is noted that the use of "or" herein is meant to be the inclusive or unless expressly indicated otherwise. It is further noted that the use of "a" or "an" herein is meant to be one or more unless expressly indicated otherwise.

[0078] All documents mentioned in this application are incorporated herein in their entirety by reference to disclose and enable the incorporation by reference of the disclosure thereof. In addition, it should be understood that various modifications and equivalents can be employed without departing from the scope of the application, which is intended to cover all modifications and equivalents within the scope of the claims.

Claims

1. A low-dropout linear regulator, characterized in that, include: A power transistor, the source of which is connected to the input voltage, and the drain of which serves as the output terminal of the low-dropout linear regulator; An error amplifier, whose two input terminals are respectively connected to a DC voltage reference and a feedback signal from the output terminal of the low dropout linear regulator; The source follower transistor has its gate connected to the output of the error amplifier, its source connected to the output of the low dropout linear regulator, and its drain connected to the gate of the power transistor. A bias current source, one end of which is connected to the drain of the source follower transistor, and the other end is grounded; A high-pass operational amplifier, whose first input terminal is connected to the output terminal of the low-dropout linear regulator, and whose second input terminal is connected to a DC bias voltage; the high-pass operational amplifier is an operational amplifier that has gain only at high frequencies and no gain at low frequencies; as well as A first transistor, whose gate is connected to the output of the high-pass op-amp, is configured to form a conductive path controlled by the output of the high-pass op-amp between the output of the low-dropout linear regulator and ground.

2. The low-dropout linear regulator according to claim 1, characterized in that, Also includes: A capacitor, the first end of which is connected to the output of the low-dropout linear regulator; A resistor, one end of which is connected to the second terminal of the capacitor, and the other end is grounded; as well as A transconductance amplifier, the input of which is connected to the junction of the capacitor and the resistor, and the output of which is connected to the gate of the power transistor; The transconductance amplifier is configured to output only negative current.

3. The low-dropout linear regulator according to claim 2, characterized in that, The transconductance amplifier includes an NMOS transistor, wherein: The gate of the NMOS transistor is connected to a fixed bias voltage; The source of the NMOS transistor forms the input terminal of the transconductance amplifier; The drain of the NMOS transistor forms the output terminal of the transconductance amplifier.

4. The low-dropout linear regulator according to claim 1, characterized in that, The high-pass operational amplifier includes: Low-pass op-amp; The second transistor; and Bias current source; In this configuration, the source of the second transistor serves as the non-inverting input terminal of the high-pass operational amplifier, its gate is connected to the output terminal of the low-pass operational amplifier, and its drain serves as the output terminal of the high-pass operational amplifier. The non-inverting input of the low-pass operational amplifier is connected to the output of the high-pass operational amplifier, and its inverting input is used to connect to the DC bias voltage. The bias current source is connected between the output terminal of the high-pass operational amplifier and the ground terminal.

5. The low-dropout linear regulator according to claim 1, characterized in that, The source follower transistor is a PMOS transistor.

6. The low-dropout linear regulator as described in claim 1, characterized in that, The power transistor is a PMOS transistor.

7. The low-dropout linear regulator according to claim 1, characterized in that, The first transistor is an NMOS transistor, with its drain connected to the output terminal of the low dropout linear regulator and its source grounded; the non-inverting input terminal of the high-pass operational amplifier is connected to the output terminal of the low dropout linear regulator, and the inverting input terminal of the high-pass operational amplifier is connected to a DC bias voltage.

8. The low-dropout linear regulator according to claim 1, characterized in that, The first transistor is a PMOS transistor, with its source connected to the output terminal of the low dropout linear regulator and its drain grounded; the inverting input terminal of the high-pass operational amplifier is connected to the output terminal of the low dropout linear regulator, and the non-inverting input terminal of the high-pass operational amplifier is connected to a DC bias voltage.

9. A power management chip, characterized in that, Includes the low-dropout linear regulator as described in any one of claims 1-8.

10. A system-on-a-chip, characterized in that, Includes the low-dropout linear regulator as described in any one of claims 1-8.

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