Storage device and operating method of storage device

Abstract

A memory device and an operating method thereof are provided. The storage device includes: a non-volatile memory device; and a controller including a plurality of counters, wherein the controller is configured to: increase a first count of a first counter of the plurality of counters based on a first input / output (IO) request received from an external host device; and after receiving a first clear request from the external host device, increasing a second count of a second counter of the plurality of counters based on a second IO request received from the external host device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0024486 filed on February 20, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to an electronic device, and more particularly, to a storage device supporting a clear operation and an operating method of the storage device. Background Art

[0004] The storage device may include a nonvolatile memory device. The storage device can retain data even when power is off, and data can be written to and read from the nonvolatile memory device. The storage device can access the nonvolatile memory device in response to a request from an external host device.

[0005] The storage device may buffer requests from the external host device and may send a response to the external host device indicating that the buffered request has been fully processed. The external host device may receive the response and then send any other requests to the storage device. In certain circumstances, the external host device may need to actually complete the requests buffered in the storage device. Alternatively, in certain circumstances, the storage device may need to actually complete the requests buffered therein. Summary of the Invention

[0006] One or more embodiments provide a storage device that performs a flush operation that actually completes requests buffered in the storage device and supports the flush operation with reduced resources, and a method of operating the storage device.

[0007] According to one aspect of the embodiments, a storage device includes: a nonvolatile memory device; and a controller including a plurality of counters, wherein the controller is configured to: increase a first count of a first counter among the plurality of counters based on a first input / output (IO) request received from an external host device; and increase a second count of a second counter among the plurality of counters based on a second IO request received from the external host device after receiving a first clear request from the external host device.

[0008] According to another aspect of the embodiment, a method for operating a storage device including a nonvolatile memory device and a controller includes: receiving, at the controller, a first IO request from an external host device; increasing, at the controller, a first count of a first counter based on the first IO request; decreasing, at the controller, the first count based on accessing the nonvolatile memory device according to at least one of the first IO requests; and increasing, at the controller, a second count of a second counter based on receiving a second IO request from the external host device after receiving a clear request.

[0009] According to another aspect of the embodiment, a storage device includes: a nonvolatile memory device; and a controller including a plurality of counters. The controller is configured to: increase a first count of a first counter among the plurality of counters based on receiving a first IO request from an external host device; increase a second count of a second counter among the plurality of counters based on receiving a second IO request from the external host device after receiving a first clear request from the external host device; decrease the first count based on accessing the nonvolatile memory device according to one of the first IO requests, independent of the first clear request; manage a first bitmap, the first bitmap including bits corresponding to the plurality of counters; set a bit of the first bitmap corresponding to the first counter to a first value based on receiving the first clear request and the first count being not "0"; and set a bit of the first bitmap corresponding to the first counter to a second value based on receiving the first clear request and the first count being "0." BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects and features will become more apparent from the following description of embodiments with reference to the accompanying drawings.

[0011] Figure 1 A computing system according to an embodiment is shown.

[0012] Figure 2 An operating method of a storage device according to an embodiment is shown.

[0013] Figure 3 Counters and registers of a memory controller according to an embodiment are shown.

[0014] Figure 4 An example is shown in which a memory controller manages an input / output (IO) request of a host device by using a counter according to an embodiment.

[0015] Figure 5 An example of a process in which IO requests are managed by a counter according to an embodiment is shown.

[0016] Figure 6 An example is shown in which a memory controller manages an IO request and a flush request of a host device by using a counter and a register according to an embodiment.

[0017] Figure 7 An example of a process in which IO requests and clear requests are managed by counters and registers according to an embodiment is shown.

[0018] Figure 8 A subsequent operation in which a memory controller manages IO requests of a host device by using a counter according to an embodiment is shown.

[0019] Figure 9 An example of a process in which IO requests are managed by a counter according to an embodiment is shown.

[0020] Figure 10 A subsequent operation in which a memory controller manages IO requests and flush requests of a host device by using counters and registers according to an embodiment is shown.

[0021] Figure 11 An example of a process in which IO requests and clear requests are managed by counters and registers according to an embodiment is shown.

[0022] Figure 12 A subsequent operation in which a memory controller manages IO requests of a host device by using a counter according to an embodiment is shown.

[0023] Figure 13 and Figure 14 An example of a process in which IO requests are managed by a counter according to an embodiment is shown.

[0024] Figure 15 is a diagram illustrating a system according to an embodiment. DETAILED DESCRIPTION

[0025] Below, embodiment will be described with reference to accompanying drawings. Throughout this specification, identical parts are represented by identical figure numerals, and repeated description thereof is omitted. It should be understood that when an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it can be directly on another element or layer, directly connected to or directly coupled to another element or layer, or there can be an intermediate element or layer. On the contrary, when an element is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there is no intermediate element or layer. The embodiments described here are example embodiments, and therefore, the present disclosure is not limited thereto, and can be realized in various other forms. Each embodiment provided in the following description does not exclude being associated with one or more features of another example or another embodiment that is also provided herein or not provided herein but consistent with the present disclosure.

[0026] Figure 1 FIG. 1 shows a computing system 10 according to an embodiment. Figure 1 , the computing system 10 may include a storage device 100 and a host device 200 .

[0027] The memory device 100 may include a nonvolatile memory device 110, a memory controller 120, and an external buffer 130. The nonvolatile memory device 110 may include a plurality of memory cells, each of which may store two or more bits.

[0028] For example, the nonvolatile memory device 110 may include at least one of various nonvolatile memory devices such as a flash memory device, a phase-change memory device, a ferroelectric memory device, a magnetic memory device, and a resistive memory device.

[0029] The memory controller 120 may receive various requests from the external host device 200 for writing data into the nonvolatile memory device 110 or reading data from the nonvolatile memory device 110. The memory controller 120 may store (or buffer) user data communicated with the external host device 200 in the external buffer 130, and may store metadata for managing the memory device 100 in the external buffer 130.

[0030] The memory controller 120 may access the nonvolatile memory device 110 through the first signal line SIGL1 and the second signal line SIGL2. For example, the memory controller 120 may transmit a command and an address to the nonvolatile memory device 110 through the first signal line SIGL1. The memory controller 120 may exchange data with the nonvolatile memory device 110 through the first signal line SIGL1.

[0031] The memory controller 120 may transmit the first control signal to the nonvolatile memory device 110 through the second signal line SIGL2. The memory controller 120 may receive the second control signal from the nonvolatile memory device 110 through the second signal line SIGL2.

[0032] In an embodiment, the memory controller 120 may be configured to control two or more nonvolatile memory devices.The memory controller 120 may include a first signal line and a second signal line independently for each of the two or more nonvolatile memory devices.

[0033] As another example, the memory controller 120 may share a first signal line with two or more nonvolatile memory devices.The memory controller 120 may share some of the second signal lines with two or more nonvolatile memory devices and may provide other second signal lines separately.

[0034] The external buffer 130 may include a random access memory. For example, the external buffer 130 may include at least one of a dynamic random access memory, a phase change random access memory, a ferroelectric random access memory, a magnetic random access memory, and a resistive random access memory.

[0035] The memory controller 120 may include a bus 121 , a host interface 122 , an internal buffer 123 , a processor 124 , a buffer controller 125 , a memory manager 126 , and an error correction code (ECC) block 127 .

[0036] The bus 121 may provide a communication channel between components of the memory controller 120 . The host interface 122 may receive various requests from the external host device 200 and may parse the received requests. The host interface 122 may store the parsed requests in the internal buffer 123 .

[0037] The host interface 122 can send various responses to the external host device 200. The host interface 122 can exchange signals with the external host device 200 according to the communication protocol. The internal buffer 123 can include a random access memory. For example, the internal buffer 123 can include a static random access memory or a dynamic random access memory.

[0038] The processor 124 may execute an operating system or firmware for driving the memory controller 120. The processor 124 may read the parsed request stored in the internal buffer 123 and may generate an address and a command for controlling the nonvolatile memory device 110. The processor 124 may provide the generated command and address to the memory manager 126.

[0039] The processor 124 may store various metadata for managing the storage device 100 in the internal buffer 123. The processor 124 may access the external buffer 130 through the buffer controller 125. The processor 124 may control the buffer controller 125 and the memory manager 126 so that user data stored in the external buffer 130 is provided to the nonvolatile memory device 110.

[0040] The processor 124 may control the host interface 122 and the buffer controller 125 so that the data stored in the external buffer 130 is provided to the external host device 200. The processor 124 may control the buffer controller 125 and the memory manager 126 so that the data received from the nonvolatile memory device 110 is stored in the external buffer 130. The processor 124 may control the host interface 122 and the buffer controller 125 so that the data received from the external host device 200 is stored in the external buffer 130.

[0041] The processor 124 may include a counter circuit CNT and a register circuit REG. The counter circuit CNT may include multiple counters. The processor 124 may manage input / output (IO) requests and clear requests from the external host device 200 by using the multiple counters of the counter circuit CNT. The register circuit REG may include multiple registers. The processor 124 may manage clear requests from the external host device 200 by using the multiple registers of the register circuit REG.

[0042] Under the control of the processor 124, the buffer controller 125 may write data into the external buffer 130 or may read data from the external buffer 130. The memory manager 126 may communicate with the nonvolatile memory device 110 through the first and second signal lines SIGL1 and SIGL2 under the control of the processor 124.

[0043] The memory manager 126 can access the nonvolatile memory device 110 under the control of the processor 124. For example, the memory manager 126 can access the nonvolatile memory device 110 through the first signal line SIGL1 and the second signal line SIGL2. The memory manager 126 can communicate with the nonvolatile memory device 110 based on a protocol that complies with a standard or is defined by a manufacturer.

[0044] The error correction code block 127 may perform error correction encoding on data to be provided to the nonvolatile memory device 110 by using the error correction code ECC. The error correction code block 127 may perform error correction decoding on data received from the nonvolatile memory device 110 by using the error correction code ECC.

[0045] In an embodiment, the external buffer 130 and the buffer controller 125 may be omitted from the memory device 100. When the external buffer 130 and the buffer controller 125 are omitted, the functions described as being performed by the external buffer 130 and the buffer controller 125 may be performed by the internal buffer 123.

[0046] The host device 200 may be an external host device 200 of the storage device 100, in that the host device 200 is external to the storage device 100. The host device 200 may be implemented, for example, using a fixed computing system including a personal computer, a server, or a workstation, or a mobile computing system including a notebook computer, a smart phone, a smart tablet, or a wearable computing device.

[0047] The host device 200 may include a first input / output (IO) requester 210 (e.g., an IO requester circuit), a second IO requester 220, and a third IO requester 230. The first IO requester 210, the second IO requester 220, and the third IO requester 230 may generate IO requests for the storage device 100 independently of one another, and may send the generated IO requests to the storage device 100 independently of one another. For example, the IO requests may include a request to direct the host device 200 to write data to the storage device 100, and a request to direct an operation associated with the host device 200 writing data to the storage device 100, such as a read request or a trim request.

[0048] The first IO requester 210, the second IO requester 220, and the third IO requester 230 may generate flush requests independently of each other and may send the generated flush requests independently of each other to the storage apparatus 100. The flush request may be a request instructing the storage apparatus 100 to complete the buffered IO request.

[0049] In an embodiment, the processor 124 may internally generate a purge request independently of the first IO requester 210, the second IO requester 220, and the third IO requester 230. For example, the processor 124 may internally generate a purge request when a sudden power off (SPO) event is detected.

[0050] Figure 2 FIG. 1 shows an operation method of the storage device 100 according to an embodiment. Figure 1 and Figure 2 In operation S110 , the memory device 100 may manage IO requests by using counters. For example, the processor 124 of the memory controller 120 of the memory device 100 may manage IO requests received from the host device 200 by using a plurality of counters of the counter circuit CNT.

[0051] In operation S120, the memory device 100 may manage the flush request using counters and bitmaps. For example, the processor 124 of the memory controller 120 of the memory device 100 may manage the flush request using counters of the counter circuit CNT and bitmaps stored in registers of the register circuit REG.

[0052] In some embodiments, IO requests and clear requests can be managed using a bitmap. In this case, as the number of IO requesters of the host device 200 increases or as the maximum number of IO commands that can be processed simultaneously by the memory controller 120 increases, the required capacity of the bitmap managed by the processor 124 of the memory controller 120 of the storage device 100 may increase. When the capacity of the bitmap managed by the processor 124 increases, the number of registers (i.e., required resources) required for the memory controller 120 to manage IO requests and clear requests may increase.

[0053] According to an embodiment, the memory controller 120 can manage IO requests and clear requests by using bitmaps and counters. Some bitmaps can be replaced with binary information of the counters by replacing some bitmaps with counters. Therefore, the resources required for the memory controller 120 to manage IO requests and clear requests can be reduced.

[0054] Figure 3 1 shows a counter circuit CNT and a register circuit REG of the memory controller 120 according to an embodiment. In an embodiment, Figure 3 , a relationship between the counter circuit CNT and the register circuit REG of the memory controller 120 , the host device 200 , and the nonvolatile memory device 110 is shown.

[0055] Reference Figure 3 The counter circuit CNT may include a first counter 310, a second counter 320, and a third counter 330. The first counter 310, the second counter 320, and the third counter 330 may be identified as having a first index IDX1, a second index IDX2, and a third index IDX3, respectively. Each of the first counter 310, the second counter 320, and the third counter 330 may count the number of IO requests received and buffered from the host device 200. For example, each of the first counter 310, the second counter 320, and the third counter 330 may count the number of IO requests corresponding to different purge requests. The first index IDX1 of the first counter 310, the second index IDX2 of the second counter 320, and the third index IDX3 of the third counter 330 may be dump indexes indicating different purge requests.

[0056] In an embodiment, when receiving a flush request, the memory controller 120 may sequentially select the first counter 310 , the second counter 320 , and the third counter 330 (or the first index IDX1 , the second index IDX2 , and the third index IDX3 ) to count in a round robin manner.

[0057] In an embodiment, each of the first IO requester 210, the second IO requester 220, and the third IO requester 230 of the host device 200 may send a flush request to the memory controller 120, and then may not send additional IO requests or additional flush requests to the memory controller 120 until the memory controller 120 notifies the flush request completion, for example, receives a response indicating completion of the operation according to the flush request. According to the above rule, the number of counters of the counter circuit CNT may be equal to the number of IO requesters of the host device 200. When the processor 124 is implemented to generate flush requests internally, the number of counters of the counter circuit CNT may be greater than the number of IO requesters of the host device 200 by the same number of flush requests generated internally by the processor 124.

[0058] Each of the first IO requester 210, the second IO requester 220, and the third IO requester 230 of the host device 200 may send a flush request to the memory controller 120, and then may send an additional IO request or an additional flush request to the memory controller 120, regardless of whether the completion of the flush request is notified from the memory controller 120, for example, whether a response indicating completion of the operation according to the flush request is received. According to the above rule, the number of counters of the counter circuit CNT may be greater than the number of IO requesters of the host device 200.

[0059] The register circuit REG may include a first register 340, a second register 350, a third register 360, and a fourth register 370. The first register 340 may store information about the current status of the count values ​​of the first counter 310, the second counter 320, and the third counter 330 in the form of a bitmap. For example, when a clear request is received, when the count value of the counter corresponding to the clear request is "0", the memory controller 120 may set the bit indicating the counter corresponding to the clear request in the bitmap of the first register 340 to a second value (e.g., 0). When a clear request is received, when the count value of the counter corresponding to the clear request is not "0", the memory controller 120 may set the bit indicating the counter corresponding to the clear request in the bitmap of the first register 340 to a first value (e.g., 1).

[0060] When a flush request is received from any one of the first IO requester 210, the second IO requester 220, and the third IO requester 230 of the host device 200 (or when a flush request is internally generated by the processor 124), the memory controller 120 may capture the bitmap of the first register 340 by using the second register 350. In this regard, the bitmap of the first register 340 may be copied in the second register 350. For example, when a flush request is received from any one of the IO requesters, a bit of the bitmap of the second register 350 may be set to have the same value as a bit of the bitmap of the first register 340.

[0061] When receiving a flush request from another one of the first IO requester 210, the second IO requester 220, and the third IO requester 230 of the host device 200 (or when the flush request is internally generated by the processor 124), the memory controller 120 may capture the bitmap of the first register 340 by using the third register 360. For example, when receiving the flush request from another IO requester, a bit of the bitmap of the third register 360 may be set to have the same value as a bit of the bitmap of the first register 340.

[0062] When receiving a flush request from another one of the first IO requester 210, the second IO requester 220, and the third IO requester 230 of the host device 200 (or when the flush request is internally generated by the processor 124), the memory controller 120 may capture the bitmap of the first register 340 by using the fourth register 370. For example, when receiving the flush request from another IO requester, the bit of the bitmap of the fourth register 370 may be set to have the same value as the bit of the bitmap of the first register 340.

[0063] In an embodiment, when a flush request is received, the memory controller 120 may select registers for capture in a round-robin manner. In an embodiment, the number of registers of the register circuit REG may be greater than the number of counters of the counter circuit CNT by "1."

[0064] As another example, a register for capturing may be designated specifically for each of the first IO requester 210, the second IO requester 220, and the third IO requester 230. For example, the second register 350 may be configured to capture the first register 340 when the first IO requester 210 sends a clear request. The third register 360 may be configured to capture the first register 340 when the second IO requester 220 sends a clear request. The fourth register 370 may be configured to capture the first register 340 when the third IO requester 230 sends a clear request.

[0065] When the processor 124 is configured to internally generate a clear request, the register circuit REG may further include a register configured to capture the first register 340 when the processor 124 generates the clear request.

[0066] In an embodiment, the memory controller 120 may perform scheduling for IO requests received from the host device 200 (or for flush requests generated internally by the processor 124). The memory controller 120 may process IO requests with a high priority before any other IO requests, or process IO requests that are set to be processed first (i.e., based on an internal policy).

[0067] In an embodiment, the memory controller 120 can be configured to guarantee the order in which the purge requests (or purge requests generated internally by the processor 124) are processed. The memory controller 120 can be configured to process the purge request received first and process purge requests received later. The scheduling of IO requests can be performed regardless of the guaranteed order of the purge requests.

[0068] In an embodiment, the memory controller 120 may manage information about IO requests to be processed by each flush request received from the host device 200 by using a counter of the counter circuit CNT. The memory controller 120 may determine whether all IO requests corresponding to each flush request are processed, that is, whether each flush request is processed, by using the counter of the counter circuit CNT.

[0069] In an embodiment, the memory controller 120 can guarantee the order in which the purge requests received from the host device 200 are processed by using a bitmap captured (or stored) in a register of the register circuit REG. The memory controller 120 can manage the purge requests by using the bitmap of the register circuit REG so that the purge requests received first are processed and then the purge requests received later are processed.

[0070] Figure 4 An example is shown in which the memory controller 120 manages the IO request of the host device 200 by using the counter circuit CNT. Figure 5 Shown according to Figure 4 This embodiment describes an example of a method for managing I / O request processing by counter circuit CNT. In the following, an example will be described in which first I / O requester 210, second I / O requester 220, or third I / O requester 230 generates a flush request. However, processor 124 may also generate a flush request internally. A flush request generated internally by processor 124 may be processed identically to flush requests generated by first I / O requester 210, second I / O requester 220, and third I / O requester 230.

[0071] Reference Figure 1 、 Figure 4 and Figure 5 In operation S210, the host device 200 may send an IO request to the memory controller 120 (eg, the processor 124 of the memory controller 120). In an embodiment, the host device 200 may sequentially send five IO requests IO to the memory controller 120, such as Figure 5 As shown in operation S211, operation S212, operation S213, operation S214 and operation S215.

[0072] For example, in operation S211, the first IO requester 210 may send an IO request IO to the memory controller 120. In operation S212, the third IO requester 230 may send an IO request IO to the memory controller 120. In operation S213, the second IO requester 220 may send an IO request IO to the memory controller 120. In operation S214, the third IO requester 230 may send an IO request IO to the memory controller 120. In operation S215, the first IO requester 210 may send the IO request IO to the memory controller 120.

[0073] In operation S220, the processor 124 of the memory controller 120 may buffer the IO request received from the host device 200. For example, the processor 124 may add the IO request to an IO queue provided in the internal buffer 123. When write data is received together with the IO request, the memory controller 120 may store the write data in the external buffer 130. The memory controller 120 may send a response to the host device 200 indicating that the IO request is fully buffered.

[0074] In operation S230, the processor 124 of the memory controller 120 may increment a counter corresponding to a current index. In an embodiment, the index may be a clear index identified by the first counter 310, the second counter 320, or the third counter 330. In an embodiment, the current index may be the first index IDX1. At the same index (i.e., the first index IDX1), the IO requests of the first IO requester 210, the second IO requester 220, and the third IO requester 230 may increment the same counter (e.g., the first counter 310).

[0075] When the count value of the first counter 310 of the current index (eg, the first index IDX1) is not “0”, the memory controller 120 may set the corresponding bit of the first register 340 to “1”. The bitmap of the first register 340 may be “100”.

[0076] In an embodiment, the processor 124 may increase the first count CT1 of the first counter 310 each time the IO request IO is received from the host device 200. Since five IO requests IO are received from the host device 200, the first count CT1 of the first counter 310 may increase to "5" in operation S230.

[0077] In operation S240, the processor 124 of the memory controller 120 may send an IO statement (IO issue) with a current index to the memory manager 126. For example, the IO statement may be an internal request or instruction that includes a corresponding index generated based on the IO request. For example, the IO statement corresponding to the IO request managed by the first counter 310 may be associated with the first index IDX1 and sent to the memory manager 126. For example, the IO statement may also include a command type, an address, and a data pointer associated with the IO statement.

[0078] In operation S250, the memory manager 126 may send an IO command to the nonvolatile memory device 110 so that an operation according to the IO request is performed. When the IO request is a write request, the memory manager 126 may also send data to the nonvolatile memory device 110. When the IO request is a read request, the memory manager 126 may receive data from the nonvolatile memory device 110. The memory manager 126 may recognize the completion of the operation according to the IO request by recognizing the transition of a specific signal (e.g., a ready / busy signal from the nonvolatile memory device 110).

[0079] When the operation according to the IO request is recognized to be completed, in operation S260, the memory manager 126 may send an IO response with the current index to the processor 124. For example, the IO response may further include a command type, a status indicating success or failure, and a data pointer.

[0080] Upon receiving the IO response, the processor 124 may transmit a response to the host device 200, notifying the completion of the operation according to the IO request. For example, when the IO request is a write request, the IO response may include information about the write result. When the IO request is a read request, the IO response may be transmitted to the host device 200 along with the data. Upon receiving the IO response, the processor 124 may decrement the count of the counter corresponding to the current index in operation S270.

[0081] In an embodiment, Figure 5As shown in operations S251 and S252, the memory manager 126 of the memory controller 120 may send two IO commands corresponding to the first index IDX1 to the nonvolatile memory device 110. Therefore, in operation S270, the first count CT1 of the first counter 310 corresponding to the first index IDX1 may be reduced to "3".

[0082] In an embodiment, the memory manager 126 may queue the IO declaration provided from the processor 124. The memory manager 126 may send an IO command to the non-volatile memory device 110 based on the queued IO declaration. The processor 124 and the memory manager 126 may identify the index corresponding to the processed IO declaration (or a counter associated with the index) by adding the first index IDX1 to the IO declaration and the IO response.

[0083] Figure 6 An example is shown in which the memory controller 120 manages the IO request and the clear request of the host device 200 by using the counter circuit CNT and the register circuit REG. Figure 7 Shown according to Figure 6 This is an example of a method in which the processing of IO requests and clear requests is managed by the counter circuit CNT and the register circuit REG.

[0084] Reference Figure 1 、 Figure 6 and Figure 7 In operation S310 , the host device 200 may send a flush request FL to the memory controller 120 (eg, the processor 124 of the memory controller 120 ). For example, the first IO requester 210 of the host device 200 may send the flush request FL to the memory controller 120 .

[0085] In operation S320, the processor 124 of the memory controller 120 may capture a bitmap. The processor 124 may capture the bitmap of the first register 340 and may store the captured bitmap in the second register 350. That is, the processor 124 may set the value of the bit of the bitmap of the second register 350 to be the same as the value of the bit of the bitmap of the first register 340. Therefore, the bitmap of the first register 340 may be "100", and the bitmap of the second register 350 may also be "100".

[0086] In operation S330, the processor 124 of the memory controller 120 may select a next index. For example, the next index may be the second index IDX2. For counting, the processor 124 may select the second counter 320 corresponding to the second index IDX2.

[0087] In operation S340, the processor 124 of the memory controller 120 may transmit an IO declaration having a current index to the memory manager 126. For example, an IO declaration corresponding to an IO request managed by the first counter 310 may be associated with the first index IDX1 and transmitted to the memory manager 126. For example, the IO declaration may further include a command type, an address, and a data pointer associated with the IO declaration.

[0088] In operation S350, the memory manager 126 may send an IO command to the nonvolatile memory device 110 so that an operation according to the IO request is performed. When the IO request is a write request, the memory manager 126 may also send data to the nonvolatile memory device 110. When the IO request is a read request, the memory manager 126 may receive data from the nonvolatile memory device 110. The memory manager 126 may recognize the completion of the operation according to the IO request by recognizing the transition of a specific signal (e.g., a ready / busy signal from the nonvolatile memory device 110).

[0089] When the operation according to the IO request is recognized to be completed, in operation S360, the memory manager 126 may send an IO response with the current index to the processor 124. For example, the IO response may further include a command type, a status indicating success or failure, and a data pointer.

[0090] When receiving the IO response, the processor 124 may transmit a response providing notification of completion of the operation according to the IO request to the host device 200. When receiving the IO response, the processor 124 may decrement a count of a counter corresponding to the current index in operation S370.

[0091] In an embodiment, Figure 7 As shown in operation S351, the memory manager 126 of the memory controller 120 may send one IO command corresponding to the first index IDX1 to the nonvolatile memory device 110. Therefore, in operation S370, the first count CT1 of the first counter 310 corresponding to the first index IDX1 may be reduced to '2'.

[0092] In an embodiment, when the first count CT1 of the first counter 310 corresponding to the first index IDX1 is "0", the memory controller 120 may send a response indicating the completion of the flush operation to the host device 200 in response to the flush request FL in operation S310. Then, operations S320 and S330 may be omitted. Alternatively, the memory controller 120 may perform operations S320 and S330 so that the first counter 310, the second counter 320, and the third counter 330 are sequentially selected for counting in a round-robin manner, and the second register 350, the third register 360, and the fourth register 370 are sequentially selected for capturing in a round-robin manner.

[0093] Figure 8 1 and 2. It shows the subsequent operation of the memory controller 120 managing the IO request of the host device 200 using the counter circuit CNT. Figure 9 Shown according to Figure 8 An example of a method for managing processing of IO requests by a counter circuit CNT.

[0094] Reference Figure 1 、 Figure 8 and Figure 9 In operation S410, the host device 200 may send an IO request to the memory controller 120 (eg, the processor 124 of the memory controller 120). Figure 9 As shown in operations S411 , S412 , and S413 , the host device 200 may sequentially send three IO requests IO to the memory controller 120 .

[0095] For example, in operation S411, the second IO requester 220 may send an IO request IO to the memory controller 120. In operation S412, the second IO requester 220 may send an IO request IO to the memory controller 120. In operation S413, the third IO requester 230 may send an IO request IO to the memory controller 120. In an embodiment, the first IO requester 210 that sends a purge request to the memory controller 120 may not send an IO request to the memory controller 120. For example, the first IO requester 210 may not send an IO request to the memory controller 120 until a response indicating completion of the purge request is received from the memory controller 120. However, the embodiment is not limited thereto. Even if no response is received after sending the purge request, the first IO requester 210 may send an IO request to the memory controller 120.

[0096] In operation S420, the processor 124 of the memory controller 120 may buffer the IO request received from the host device 200. For example, the processor 124 may add the IO request to an IO queue provided in the internal buffer 123. When write data is received together with the IO request, the memory controller 120 may store the write data in the external buffer 130. The memory controller 120 may send a response to the host device 200 indicating that the IO request is fully buffered.

[0097] In operation S425, the processor 124 of the memory controller 120 may increase the count of the counter corresponding to the current index. In an embodiment, the current index may be the second index IDX2. When the count value of the second counter 320 of the current index (e.g., the second index IDX2) is not "0", the memory controller 120 may set the corresponding bit of the first register 340 to "1". The bitmap of the first register 340 may be "110".

[0098] In an embodiment, the processor 124 may increase the second count CT2 of the second counter 320 each time the IO request IO is received from the host device 200. Since three IO requests IO are received from the host device 200, the second count CT2 of the second counter 320 may increase to "3" in operation S425.

[0099] In operation S430, the processor 124 of the memory controller 120 may send an IO declaration with an index to the memory manager 126. For example, an IO declaration corresponding to an IO request managed by the first counter 310 may be associated with the first index IDX1 and sent to the memory manager 126. An IO declaration corresponding to an IO request managed by the second counter 320 may be associated with the second index IDX2 and sent to the memory manager 126. For example, the IO declaration may further include a command type, an address, and a data pointer associated with the IO declaration.

[0100] In operation S440, the memory manager 126 may send an IO command to the nonvolatile memory device 110 so that an operation according to the IO request is performed. When the IO request is a write request, the memory manager 126 may also send data to the nonvolatile memory device 110. When the IO request is a read request, the memory manager 126 may receive data from the nonvolatile memory device 110. The memory manager 126 may recognize the completion of the operation according to the IO request by recognizing the transition of a specific signal (e.g., a ready / busy signal from the nonvolatile memory device 110).

[0101] When the operation according to the IO request is recognized to be completed, in operation S450, the memory manager 126 may send an IO response with an index to the processor 124. For example, the IO response may further include a command type, a status indicating success or failure, and a data pointer.

[0102] When the IO response is received, the processor 124 may transmit a response providing a notification of completion of the operation according to the IO request to the host device 200. When the IO response is received, the processor 124 may decrement a count of a counter corresponding to the index in operation S455.

[0103] In an embodiment, Figure 9 As shown in operation S441, the memory manager 126 of the memory controller 120 may send one IO command corresponding to the first index IDX1 to the nonvolatile memory device 110. Therefore, in operation S455, the first count CT1 of the first counter 310 corresponding to the first index IDX1 may be reduced to '1'.

[0104] In operation S460, the processor 124 of the memory controller 120 may transmit the IO declaration with the index to the memory manager 126. In operation S470, the memory manager 126 may transmit the IO command to the nonvolatile memory device 110 so that an operation according to the IO request is performed.

[0105] When the operation according to the IO request is recognized to be completed, in operation S480, the memory manager 126 may send an IO response with an index to the processor 124. For example, the IO response may further include a command type, a status indicating success or failure, and a data pointer.

[0106] When receiving the IO response, the processor 124 may transmit a response providing a notification of completion of the operation according to the IO request to the host device 200. When receiving the IO response, the processor 124 may decrement a count of a counter corresponding to the index in operation S490.

[0107] In an embodiment, Figure 9 As shown in operation S471, the memory manager 126 of the memory controller 120 may send one IO command corresponding to the second index IDX2 to the nonvolatile memory device 110. Therefore, in operation S490, the second count CT2 of the second counter 320 corresponding to the second index IDX2 may be reduced to "2".

[0108] Figure 10 It shows that the memory controller 120 utilizes the counter circuit CNT and the register circuit REG to manage subsequent operations of the IO request and the flush request of the host device 200 . Figure 11 Shown according to Figure 10 An example of a method in which the processing of IO requests and clear requests is managed by the counter circuit CNT and the register circuit REG.

[0109] Reference Figure 1 、 Figure 10 and Figure 11 In operation S510 , the host device 200 may send a flush request FL to the memory controller 120 (eg, the processor 124 of the memory controller 120 ). For example, the second IO requester 220 of the host device 200 may send the flush request FL to the memory controller 120 .

[0110] In operation S520, the processor 124 of the memory controller 120 may capture a bitmap. The processor 124 may capture the bitmap of the first register 340 and may store the captured bitmap in the third register 360. That is, the processor 124 may set the value of the bit of the bitmap of the third register 360 to be the same as the value of the bit of the bitmap of the first register 340. Therefore, the bitmap of the third register 360 may be "110".

[0111] In operation S530, the processor 124 of the memory controller 120 may select a next index. For example, the next index may be the third index IDX3. For counting, the processor 124 may select the third counter 330 corresponding to the third index IDX3.

[0112] In operation S540, the processor 124 of the memory controller 120 may send an IO declaration with an index to the memory manager 126. For example, an IO declaration corresponding to an IO request managed by the first counter 310 may be sent to the memory manager 126 in association with the first index IDX1. An IO declaration corresponding to an IO request managed by the second counter 320 may be sent to the memory manager 126 in association with the second index IDX2. An IO declaration corresponding to an IO request managed by the third counter 330 may be sent to the memory manager 126 in association with the third index IDX3. For example, the IO declaration may further include a command type, an address, and a data pointer associated with the IO declaration. An IO declaration corresponding to an IO request managed by the second counter 320 may be sent to the memory manager 126 in association with the second index IDX2.

[0113] In operation S550 , the memory manager 126 may transmit an IO command to the nonvolatile memory device 110 so that an operation according to the IO request is performed.

[0114] When the operation according to the IO request is recognized to be completed, in operation S560, the memory manager 126 may send an IO response with an index to the processor 124. For example, the IO response may further include a command type, a status indicating success or failure, and a data pointer.

[0115] When receiving the IO response, the processor 124 may transmit a response providing a notification of completion of the operation according to the IO request to the host device 200. When receiving the IO response, the processor 124 may decrement a count of a counter corresponding to the index in operation S570.

[0116] In an embodiment, Figure 11 As shown in operation S551, the memory manager 126 of the memory controller 120 may send one IO command corresponding to the second index IDX2 to the nonvolatile memory device 110. Therefore, in operation S570, the second count CT2 of the second counter 320 corresponding to the second index IDX2 may be reduced to "1".

[0117] Figure 12 1 and 2. It shows the subsequent operation of the memory controller 120 managing the IO request of the host device 200 using the counter circuit CNT. Figure 13 and Figure 14 Shown according to Figure 12 An example of a method for managing processing of IO requests by a counter circuit CNT.

[0118] Reference Figure 1 、 Figure 12 and Figure 13 In operation S610, the host device 200 may send an IO request to the memory controller 120 (eg, the processor 124 of the memory controller 120). Figure 13 As shown in operations S611 and S612 in FIG. 1 , the host device 200 may sequentially send two IO requests IO to the memory controller 120 .

[0119] For example, in operation S611, the third IO requester 230 may transmit an IO request IO to the memory controller 120. In operation S612, the third IO requester 230 may transmit the IO request IO to the memory controller 120.

[0120] In operation S620, the processor 124 of the memory controller 120 may buffer the IO request received from the host device 200. For example, the processor 124 may add the IO request to an IO queue provided in the internal buffer 123. When write data is received together with the IO request, the memory controller 120 may store the write data in the external buffer 130. The memory controller 120 may send a response to the host device 200 indicating that the IO request is fully buffered.

[0121] In operation S630, the processor 124 of the memory controller 120 may increase the count of the counter corresponding to the current index. In an embodiment, the current index may be the third index IDX3. When the count value of the third counter 330 of the current index (e.g., the third index IDX3) is not "0", the memory controller 120 may set the corresponding bit of the first register 340 to "1". The bitmap of the first register 340 may be "111".

[0122] In one embodiment, the processor 124 may increase the first count CT1 of the first counter 310 each time the IO request IO is received from the host device 200. Since the IO request IO is received twice from the host device 200, the third count CT3 of the third counter 330 may increase to "2" in operation S625.

[0123] In operation S630, the processor 124 of the memory controller 120 may send an IO declaration with an index to the memory manager 126. For example, an IO declaration corresponding to an IO request managed by the first counter 310 may be sent to the memory manager 126 in association with the first index IDX1. An IO declaration corresponding to an IO request managed by the second counter 320 may be sent to the memory manager 126 in association with the second index IDX2. An IO declaration corresponding to an IO request managed by the third counter 330 may be sent to the memory manager 126 in association with the third index IDX3. For example, the IO declaration may further include a command type, an address, and a data pointer associated with the IO declaration.

[0124] In operation S640, the memory manager 126 may send an IO command to the nonvolatile memory device 110 so that an operation according to the IO request is performed. When the IO request is a write request, the memory manager 126 may also send data to the nonvolatile memory device 110. When the IO request is a read request, the memory manager 126 may receive data from the nonvolatile memory device 110. The memory manager 126 may recognize the completion of the operation according to the IO request by recognizing the transition of a specific signal, such as a ready / busy signal from the nonvolatile memory device 110.

[0125] When the operation according to the IO request is recognized to be completed, in operation S650, the memory manager 126 may send an IO response with an index to the processor 124. For example, the IO response may further include a command type, a status indicating success or failure, and a data pointer.

[0126] Upon receiving the IO response, the processor 124 may transmit a response to the host device 200, notifying the completion of the operation according to the IO request. For example, when the IO request is a write request, the IO response may include information about the write result. When the IO request is a read request, the IO response may be transmitted to the host device 200 along with the data. Upon receiving the IO response, the processor 124 may decrement the count of the counter corresponding to the index in operation S655.

[0127] In an embodiment, Figure 13 As shown in operation S641, the memory manager 126 of the memory controller 120 may send one IO command corresponding to the second index IDX2 to the nonvolatile memory device 110. Therefore, in operation S655, the second count CT2 of the second counter 320 corresponding to the second index IDX2 may be reduced to '0'.

[0128] Because the second count CT2 is "0," the processor 124 may set the bit corresponding to the second index IDX2 of the second counter 320 (i.e., the second bit) in the bitmap of the first register 340 to "0." Furthermore, the processor 124 may set the bit corresponding to the second index IDX2 of the second counter 320 (i.e., the second bit) in the bitmap of the third register 360 to "0." However, a bit having a value of "1" exists in the bitmap of the second register 350 corresponding to the second index IDX2. For example, because the clearing operation of the first index IDX1 has not been completed, the bit corresponding to the first index IDX1 in the bitmap of the second register 350 (e.g., the first bit) may be "1." Therefore, the clearing operation of the second index IDX2 has not been completed.

[0129] Then, for example, based on a round-robin manner, the processor 124 may set the second bit corresponding to the second index IDX2 in the bitmap of the third register 360 to “0” and may set the second bit corresponding to the second index IDX2 in the bitmap of the second register 350 to “0”.

[0130] Reference Figure 1 、 Figure 12 and Figure 14 ,like Figure 14As shown in operation S642, the memory manager 126 of the memory controller 120 may send one IO command corresponding to the first index IDX1 to the nonvolatile memory device 110. Therefore, in operation S655, the first count CT1 of the first counter 310 corresponding to the first index IDX1 may be reduced to '0'.

[0131] Because the first count CT1 is "0", the processor 124 may set the bit corresponding to the first index IDX1 of the first counter 310 (i.e., the first bit) in the bitmap of the first register 340 to "0". In addition, the processor 124 may set the bit corresponding to the first index IDX1 of the first counter 310 (i.e., the first bit) in the bitmap of the second register 350 to "0". All bits of the bitmap of the second register 350 corresponding to the first index IDX1 may have a value of "0". Therefore, the clear operation of the first index IDX1 may be completed. In operation S660, the memory controller 120 may send a response to the host device 200, which provides a notification that the clear operation of the first index IDX1 is completed.

[0132] Then, for example, in a round-robin manner, the processor 124 may set the first bit corresponding to the first index IDX1 in the bitmap of the third register 360 to "0," and may set the first bit corresponding to the first index IDX1 in the bitmap of the fourth register 370 to "0." All bits of the bitmap of the third register 360 corresponding to the second index IDX2 may have a value of "0." Thus, the clear operation for the second index IDX2 may be completed. In operation S670, the memory controller 120 may transmit a response to the host device 200, notifying the completion of the clear operation for the second index IDX2.

[0133] As described above, the storage device 100 can manage buffered IO requests using counters. When a purge request is received, the storage device 100 can manage new IO requests using any other counters, and can manage IO requests corresponding to the purge request using the previous counters. Furthermore, the storage device 100 can ensure the order in which purge requests are completed using a register bitmap. Therefore, the storage device 100 can support IO requests and purge requests from multiple IO requesters with reduced resources.

[0134] In the above embodiment, an example of the storage device 100 processing IO requests and flush requests from multiple IO requesters is described. However, the storage device 100 according to the embodiment is not limited to processing IO requests and flush requests from multiple IO requesters. The storage device 100 can also process IO requests and flush requests from a single IO requester by using a bitmap of a counter and a register.

[0135] Figure 15 is a diagram of a system 1000 to which a storage device according to an embodiment is applied. Figure 15 The system 1000 may basically be a mobile system such as a portable communication terminal (eg, mobile phone), a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of Things (IoT) device. However, Figure 15 The system 1000 is not necessarily limited to a mobile system and may be a PC, a laptop, a server, a media player, or an automotive device (eg, a navigation device).

[0136] Reference Figure 15 The system 1000 may include a main processor 1100, memories (e.g., 1200a and 1200b), and storage devices (e.g., 1300a and 1300b). In addition, the system 1000 may include at least one of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply 1470, and a connection interface 1480.

[0137] The main processor 1100 may control all operations of the system 1000, and more specifically, control operations of other components included in the system 1000. The main processor 1100 may be implemented as a general-purpose processor, a dedicated processor, or an application processor.

[0138] The main processor 1100 may include at least one CPU core 1110 and further include a controller 1120 configured to control memories 1200a and 1200b and / or storage devices 1300a and 1300b. In some embodiments, the main processor 1100 may further include an accelerator 1130, which is a dedicated circuit for high-speed data operations (e.g., artificial intelligence (AI) data operations). The accelerator 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and may be implemented as a chip physically separated from other components of the main processor 1100.

[0139] Memories 1200a and 1200b may be used as main memory devices of system 1000. Although each of memories 1200a and 1200b may include volatile memory, such as static random access memory (SRAM) and / or dynamic RAM (DRAM), each of memories 1200a and 1200b may include non-volatile memory, such as flash memory, phase change RAM (PRAM), and / or resistive RAM (RRAM). Memories 1200a and 1200b may be implemented in the same package as main processor 1100.

[0140] The memory devices 1300a and 1300b can be used as non-volatile memory devices configured to store data regardless of whether power is supplied thereto, and have a larger storage capacity than the memories 1200a and 1200b. The memory devices 1300a and 1300b can include memory controllers (STRG CTRL) 1310a and 1310b, respectively, and NVM (non-volatile memory) 1320a and 1320b, respectively, which are configured to store data under the control of the memory controllers 1310a and 1310b. Although the NVMs 1320a and 1320b may include flash memories having a two-dimensional (2D) structure or a three-dimensional (3D) V-NAND structure, the NVMs 1320a and 1320b may include other types of NVMs, such as PRAM and / or RRAM.

[0141] The storage devices 1300a and 1300b may be physically separated from the main processor 1100 and included in the system 1000, or implemented in the same package as the main processor 1100. In addition, the storage devices 1300a and 1300b may be of the type of solid-state device (SSD) or memory card, and may be removably combined with other components of the system 100 through an interface such as the connection interface 1480 to be described below. The storage devices 1300a and 1300b may be devices applying a standard protocol, such as Universal Flash Storage (UFS), embedded MultiMediaCard (eMMC), or Non-Volatile Memory Express (NVMe), but are not limited thereto.

[0142] The image capturing device 1410 may capture still images or moving images. The image capturing device 1410 may include a still camera, a video camera, and / or a webcam.

[0143] The user input device 1420 may receive various types of data input by a user of the system 1000 and include a touch pad, a keypad, a mouse, and / or a microphone.

[0144] The sensor 1430 may detect various types of physical quantities available from outside the system 1000 and convert the detected physical quantities into electrical signals. The sensor 1430 may include a temperature sensor, a pressure sensor, an illumination sensor, a position sensor, an acceleration sensor, a biosensor, and / or a gyro sensor.

[0145] The communication device 1440 may transmit and receive signals between other devices outside the system 1000 according to various communication protocols. The communication device 1440 may include an antenna, a transceiver, and / or a modem.

[0146] The display 1450 and the speaker 1460 may serve as output devices configured to output visual information and auditory information, respectively, to a user of the system 1000 .

[0147] The power supply device 1470 may appropriately convert power supplied from a battery (not shown) embedded in the system 1000 and / or an external power source and supply the converted power to each component of the system 1000 .

[0148] The connection interface 1480 may provide a connection between the system 1000 and an external device that is connected to the system 1000 and can transmit and receive data to and from the system 1000. The connection interface 1480 may be implemented using various interface schemes, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), external SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCIe), NVMe, IEEE 1394, a Universal Serial Bus (USB) interface, a Secure Digital (SD) card interface, a MultiMediaCard (MMC) interface, an eMMC interface, a UFS interface, an embedded UFS (eUFS) interface, and a Compact Flash (CF) card interface.

[0149] In the examples, reference Figures 1 to 14 The described memory device 100 may be implemented with memory devices 1300a and 1300b. The memory devices 1300a and 1300b may process IO requests of the main processor 1100 by using a counter, and may process flush requests of the main processor 1100 by using a counter and a register.

[0150] In the above embodiments, components according to the present disclosure are described using the terms "first," "second," "third," etc. However, the terms "first," "second," "third," etc. may be used to distinguish components from one another and do not limit the present disclosure. For example, the terms "first," "second," "third," etc. do not refer to any form of order or numerical meaning.

[0151] In the above embodiments, components according to embodiments of the present disclosure are referred to by using blocks. These blocks can be implemented with various hardware devices such as integrated circuits, application specific ICs (ASICs), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), or firmware driven in the hardware devices. In addition, these blocks can include circuits implemented with semiconductor elements in integrated circuits, or circuits registered as intellectual property (IP).

[0152] According to an embodiment, a storage device is provided that manages IO requests by using counters and uses different counters based on the index of a purge request. Therefore, a storage device that supports a purge operation with reduced resources and an operating method of the storage device are provided.

[0153] While various aspects of the embodiments have been described, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the disclosure as set forth in the following claims.

Claims

1. A storage device comprising: non-volatile memory devices; as well as A controller comprising a plurality of counters, wherein the controller is configured to: incrementing a first count of a first counter of the plurality of counters based on a first input / output request received from an external host device; as well as After receiving a first clear request from the external host device, a second count of a second counter among the plurality of counters is increased based on a second input / output request received from the external host device.

2. The storage device according to claim 1, wherein The controller is further configured to decrement the first count based on accessing the nonvolatile memory device according to one of the first input / output requests, independent of the first clear request.

3. The storage device according to claim 2, wherein: The controller is further configured to, after receiving the first clear request, decrement the second count based on accessing the nonvolatile memory device according to one of the second input / output requests. The storage device according to claim 3 , wherein: The controller is further configured to, after receiving a second clear request from the external host device, increment a third count of a third counter among the plurality of counters based on receiving a third input / output request from the external host device. The storage device according to claim 4 , wherein: The controller is further configured to: decrementing the first count based on accessing the nonvolatile memory device according to the one first input / output request, independently of the first purge request and the second purge request; after receiving the first purge request and independently of the second purge request, decrementing the second count based on accessing the non-volatile memory device according to the one second input / output request; as well as After receiving the second clear request, the third count is decremented based on accessing the nonvolatile memory device according to one of the third input / output requests. The storage device according to claim 2 , wherein: The controller is configured to: generating an input / output declaration including a first index indicating the first counter based on the one first input / output request; and Based on the input / output declaration, the first count is decremented.

7. The storage device according to claim 1, wherein The controller is further configured to: managing a first bitmap, the first bitmap including bits corresponding to the plurality of counters respectively; In response to the first count not being "0", based on the first clear request, setting a bit of the first bitmap corresponding to the first counter to a first value; and In response to the first count being “0”, a bit of the first bitmap corresponding to the first counter is set to a second value based on the first clear request. The storage device according to claim 7 , wherein: The controller is further configured to generate a second bitmap including bits corresponding to the first bitmap after setting the first bitmap in response to the first clear request.

9. The storage device according to claim 8, wherein: The controller is further configured to set a bit of the first bitmap corresponding to the first counter to the second value and set a bit of the second bitmap corresponding to the first counter to the second value in response to the first count being “0”.

10. The storage device according to claim 9, wherein: The controller is further configured to send a response indicating completion of the first clear request to the external host device based on all bits of the second bitmap having the second value.

11. The storage device according to claim 8, wherein The controller is further configured to generate a third bitmap including bits corresponding to the first bitmap based on receiving a second clear request from the external host device.

12. The storage device according to claim 11, wherein The controller is further configured to send a response indicating completion of the second clear request to the external host device based on all bits of the third bitmap having the second value.

13. The storage device according to claim 8, wherein The controller is further configured to manage a plurality of bitmaps, the plurality of bitmaps including the first bitmap and the second bitmap, and The number of the plurality of bitmaps is greater than the number of the plurality of counters by "1".

14. The storage device according to claim 1, wherein The controller is further configured to: sending a response to the external host device indicating completion of the first input / output request after the first input / output request was buffered; and A response is sent to the external host device indicating that the second input / output request is completed after the second input / output request is buffered.

15. The storage device according to claim 1, wherein The controller is further configured to provide information indicating the number of the plurality of counters to the external host device based on a request of the external host device.

16. A method for operating a storage device, the storage device comprising a nonvolatile memory device and a controller, the method comprising: receiving, at the controller, a first input / output request from an external host device; incrementing, at the controller, a first count of a first counter based on the first input / output request; decrementing, at the controller, the first count based on accessing the nonvolatile memory device according to at least one of the first input / output requests; as well as At the controller, a second count of a second counter is incremented based on receiving a second input / output request from the external host device after receiving the clear request.

17. The method according to claim 16, wherein The controller includes a plurality of counters, the plurality of counters including the first counter and the second counter, wherein the controller is configured to manage a first bitmap including bits respectively corresponding to the plurality of counters, and The method further comprises: upon receiving the clearing request, Based on the first count being greater than “0”, setting a bit of the first bitmap corresponding to the first counter to a first value; and Based on the first count being not greater than “0”, setting a bit of the first bitmap corresponding to the first counter to a second value.

18. The method according to claim 17, further comprising: generating a second bitmap including bits corresponding to the first bitmap after setting the first bitmap in response to the clear request; Based on the count of each of the plurality of counters being “0”, setting the corresponding bit of the second bitmap to the second value; and Based on all bits of the second bitmap having the second value, a response indicating completion of the clear request is sent to the external host device.

19. The method according to claim 18, further comprising: generating, based on receiving a second clear request, a third bitmap including bits corresponding to the first bitmap; Based on the count of each of the plurality of counters being “0”, setting the corresponding bit of the third bitmap to the second value; and Based on all bits of the third bitmap having the second value, a response indicating completion of the second clear request is sent to the external host device.

20. A storage device comprising: non-volatile memory devices; as well as A controller comprising a plurality of counters, wherein the controller is configured to: incrementing a first count of a first counter of the plurality of counters based on receiving a first input / output request from an external host device; incrementing a second count of a second counter of the plurality of counters based on receipt of a second input / output request from the external host device after receipt of the first clear request from the external host device; decrementing the first count based on accessing the nonvolatile memory device according to one of the first input / output requests, independent of the first clear request; managing a first bitmap including bits respectively corresponding to the plurality of counters; upon receiving the first clear request and the first count not being “0”, setting a bit of the first bitmap corresponding to the first counter to a first value; and Based on receiving the first clear request and the first count being “0”, a bit of the first bitmap corresponding to the first counter is set to a second value.

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