A CAM-based multi-stream sub-packet hardware reordering method and circuit

Abstract

The present invention relates to a CAM-based multi-stream sub-packet hardware reordering method and circuit. The method comprises: receiving out-of-order sub-packets carrying data stream identifiers and sequence numbers; querying the FID through the CAM, obtaining the entry address if a hit occurs, and allocating a new entry if a miss occurs; concatenating the entry address and the SN into a dual-port RAM storage address; maintaining an n-bit register and counter for each FID; and supporting two transmission strategies. The circuit comprises interconnected modules: a CAM module that performs FID queries; a DPRAM module that stores sub-packets according to {CAM entry address, SN}; a controller module that drives the CAM query and generates the DPRAM address, and is also responsible for populating the CAM and DPRAM with new entries in the event of a CAM miss; and a transmission module that coordinates the determination of transmission timing using registers and counters. The present invention supports concurrent processing of multiple data sources and multiple streams, eliminating operating system dependency and the risk of security vulnerabilities.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a CAM-based multi-stream sub-packet hardware reordering method and circuit. Background Art

[0002] As technology advances, the complexity of integrated circuits continues to increase, driving the need for greater data processing and storage. Data stream reordering is a key technology in the integrated circuit field, and reordering algorithms are primarily used to optimize data stream processing and storage. Reordering can more effectively manage the flow of data within the chip, improving data processing efficiency and reducing energy consumption.

[0003] Reordering algorithms play an important role in specific integrated circuit applications, such as memory management, image processing, and signal processing. For example, in memory management, reordering can more effectively utilize cache resources and improve data access speed; in image processing, reordering algorithms can be used to optimize the rendering order of images and improve rendering efficiency.

[0004] Traditional sorting algorithms, such as bubble sort and quick sort, are implemented in software. While these algorithms perform well on general-purpose computers, they can face performance bottlenecks in integrated circuit hardware environments. Software-implemented performance can be limited by hardware resources like processor speed and memory size. Software is also vulnerable to security threats like viruses and hacker attacks, which can lead to system crashes or data loss. Furthermore, software implementations often rely on specific operating systems, programming languages, or hardware platforms, leading to compatibility issues.

[0005] In view of the characteristics of integrated circuits, researchers have developed a series of optimized data stream sorting algorithms. These algorithms are more efficient in hardware implementation and can better adapt to the parallel processing characteristics of integrated circuits. Although existing reordering algorithms have made some progress in the field of integrated circuits, they still have some shortcomings:

[0006] Existing reordering algorithms are complex to implement in hardware, requiring significant chip resources and increasing the difficulty and cost of hardware design. Furthermore, these complex algorithms can result in high energy consumption during execution, impacting overall device performance. Existing reordering algorithms are often optimized for specific application scenarios and lack sufficient flexibility to adapt to diverse data processing requirements.

[0007] Therefore, there is an urgent need for a reordering method that uses hardware timing circuits to release part of the processor's performance and ensure higher processing speed and lower latency. Summary of the Invention

[0008] To solve the above technical problems, the present invention provides a CAM-based multi-stream sub-packet hardware reordering method, comprising the following steps:

[0009] Step S1: Receive out-of-order sub-data packets, each of which is bound to a flow identifier (FID) and a sequence number (SN);

[0010] Step S2: Query the CAM based on the FID of the sub-packet:

[0011] If the FID exists in the CAM, obtain its storage address;

[0012] If the FID does not exist in the CAM, the controller allocates a new entry and writes the FID based on the CAM status and the miss signal;

[0013] Step S3: Concatenate the address returned by the CAM with the sub-data packet SN to generate a DPRAM write address, and store the sub-data packet in the DPRAM;

[0014] Step S4: Maintain an n-bit register and a counter for each FID:

[0015] According to the sub-packet SN, mark the corresponding SN bit in the register as received;

[0016] The counter records the number of sub-packets sent in the current data flow;

[0017] Step S5: Send sub-data packets according to the following strategy:

[0018] Strategy 1: After all sub-packets with the same FID are received, they are sent in SN order;

[0019] Strategy 2: When the SN of a sub-packet is equal to the counter value and the SN bit in the register is marked, the sub-packet is sent immediately and the counter is incremented by 1.

[0020] That is, it is designed as a register + counter collaborative mechanism and a dual-mode sending strategy.

[0021] In one embodiment of the present invention, the sending strategy of step S5 is configured by: an external input signal; or a configuration field carried by a sub-data packet, and its priority is higher than the external signal.

[0022] The present invention also provides a CAM-based multi-stream sub-packet hardware reordering circuit, comprising:

[0023] CAM module:

[0024] The input port receives the FID query request sent by the controller module (CTRL);

[0025] The output port returns the hit signal, entry address and available entry status to the controller module, and outputs the hit signal and entry address to the DPRAM module;

[0026] DPRAM module:

[0027] The write address port is connected to the spliced ​​{CAM entry address, SN} splicing signal output by the controller module;

[0028] The write data port directly receives the input sub-data packets;

[0029] The read data port is connected to the read enable and read address input of the transmit module (TX);

[0030] Controller module (CTRL):

[0031] The main input terminal receives the sub-data packet and its bound FID / SN and valid signal;

[0032] The second input terminal receives a hit signal, a hit address, and a CAM status signal of the CAM;

[0033] The first output terminal is connected to the FID query and entry filling interface of the CAM module;

[0034] The second output terminal generates a DPRAM write address and drives the DPRAM write address port;

[0035] The third output terminal sends register update instructions (including SN information) to the TX module;

[0036] Transmitter module (TX):

[0037] The register management terminal receives the SN update instruction from CTRL;

[0038] The read command generator generates the DPRAM read address and read enable signal according to the counter value;

[0039] The data output terminal sends the reordered sub-data packets;

[0040] The release request end is connected to the entry release interface of the CAM module.

[0041] In one embodiment of the present invention, three physical paths are provided between the CAM module and the controller module:

[0042] The FID query request path is directed from the controller module to the CAM module; the hit status signal feedback path and the miss status signal feedback path are directed from the CAM module to the controller module, transmitting the hit or miss signal, the hit entry storage address and the available entry number;

[0043] The entry filling path in case of a miss is directed from the controller module to the CAM module, transmitting the filling command, filling data and filling address.

[0044] Specifically, the number of entries in the CAM module limits the maximum number of concurrently processed data streams; when the CAM entries are exhausted, the reception of sub-data packets of new FIDs is stopped; when all sub-data packets of a certain FID are sent, its CAM entries and associated register / counter resources are released.

[0045] In one embodiment of the present invention, the hit status signal feedback path includes two subpaths: a hit signal path: activated when the data flow identifier is queried; and a miss signal path: activated when the data flow identifier is not queried.

[0046] In one embodiment of the present invention, the sending module includes:

[0047] Register: The bit width is equal to the maximum number of sub-packets in a single data stream. When receiving a sub-packet, the corresponding bit is set according to the SN.

[0048] Counter: The bit width matches the SN range and increments after the sub-packet is successfully sent;

[0049] Send judgment unit: When the register bit corresponding to the counter value is high, the sending operation is triggered;

[0050] The sending module contains three output paths:

[0051] DPRAM read address path: drives DPRAM read address port;

[0052] Data sending path: output reordered sub-data packets;

[0053] CAM entry release path: Sends entry clear signal to CAM.

[0054] In one embodiment of the present invention, the sending judgment unit operates in real time under strategy 2: if the SN bit corresponding to the current counter value is marked, the SN sub-packet in the sending judgment unit is sent and the counter is incremented;

[0055] If not marked, wait until marking is complete.

[0056] In one embodiment of the present invention, the controller module's write operation on the DPRAM includes two levels of control:

[0057] First level: Get the corresponding write flag signal according to the entry address of the filled CAM;

[0058] Second level: concatenate the padding entry address and sub-packet SN into a physical address bus signal.

[0059] In one embodiment of the present invention, the FID and SN of the sub-packet are bound and transmitted by the source, and the source does not store the FID / SN state information;

[0060] Supports interleaved input of sub-packets with different FIDs.

[0061] In one embodiment of the present invention, it is applicable to: parallel reordering of multiple data streams from the same data source; and parallel reordering of multiple data streams from multiple data sources.

[0062] The above technical solution of the present invention has the following advantages over the existing technology: the present invention implements the reordering method through a hardware timing circuit, releasing part of the processor's performance, with higher processing speed and lower latency; the hardware implementation will not be affected by software vulnerabilities or virus attacks, and has higher stability; the functions implemented by the hardware do not depend on a specific operating system or programming language, and are more convenient to run in different environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0064] Figure 1 1 is a schematic structural diagram of a CAM-based multi-data stream multi-sub-data packet hardware reordering digital sequential circuit according to an embodiment of the present invention;

[0065] Figure 2 1 is a flow chart of a CAM-based multi-data stream multi-sub-data packet hardware reordering method according to an embodiment of the present invention;

[0066] Figure 3 3 is a schematic diagram of the structural connection of three physical paths between the content-addressable memory module and the controller module according to an embodiment of the present invention. DETAILED DESCRIPTION

[0067] like Figure 1 As shown, this embodiment provides a CAM-based multi-stream sub-packet hardware reordering circuit, which comprises a content addressable memory (CAM) module, a dual-port RAM (DPRAM) module, a controller module, and a transmitting (TX) module.

[0068] The CAM module is used to store and query the FLOW ID of the data flow;

[0069] The DPRAM module is used to store sub-data packets that need to be reordered;

[0070] The controller module is used to fill the controller module of CAM and DPRAM;

[0071] The TX module is used to record the receiving status of the sub-packets and send out the reordered sub-packets in the DPRAM;

[0072] Furthermore, in order to increase parallelism or reduce the load on a single processor core, a large data flow is divided into multiple smaller data packets. After processing, the multiple data packets are restored to their order and then spliced ​​together. This method is suitable for restoring the order of each data packet in the data flow;

[0073] Furthermore, after the sub-packets whose order has been disrupted are reordered and restored, they need to be sent out again. There are two ways to send the reordered sub-packets: first, wait until all sub-packets of the entire data stream are collected before sending; second, send the sub-packets of the received data stream if there is no hole in front of it. If there is a hole in the front of the received sub-packet, the current sub-packet is stored and put into a waiting state;

[0074] Furthermore, the transmission mode is configurable in two ways: one is configured by the input signal; the other is configured by the information carried by the sub-packet; and the priority of the information carried by the sub-packet is higher than the priority of the input signal. The default is mode 2. Usually, all sub-packets within a flow are sent in the same mode.

[0075] Furthermore, the reordering method supports simultaneous reordering of multiple data streams from the same data stream source, as well as simultaneous reordering of multiple data streams from multiple data stream sources; and supports interleaved transmission and sorting of sub-data packets of different data streams.

[0076] Furthermore, each data flow is numbered, called a FID (Flow ID); the sequential sub-packets belonging to a data flow are numbered in sequence, called a SN (Sequence Number), and the FID, SN, and sub-packet are bundled together for transmission. After the generated FID and SN are bundled with the sub-packet and sent out, the source does not need to store the FID and SN.

[0077] Furthermore, the reordering method includes the following steps: when the order of sub-packets is disrupted during transmission, the sub-packets are sent to the digital sequential circuit when reordering is required; after receiving the sub-packets, the digital sequential circuit searches for the FID in the CAM based on the FID information carried by the sub-packets; the CTRL writes the sub-packets into the DPRAM based on the search result returned by the CAM and the SN carried by the sub-packets; and the TX module sends the sub-packets in the restored original order according to the reordering transmission conditions;

[0078] Furthermore, the maximum number of data streams waiting for reordering that the digital sequential circuit can receive is the number of entries in the CAM. Whenever an incoming sub-packet belongs to a new data stream FID, it occupies an entry in the CAM. Once all entries in the CAM are occupied, the circuit stops receiving data streams with new FIDs. When all sub-packets of a data stream FID are reordered and sent by the TX module, the corresponding entry in the CAM is released, and the digital sequential circuit can now receive sub-packets of the new entry.

[0079] Further, such as Figure 3 As shown, there are three physical paths between the CAM module and the controller module:

[0080] FID query request path, from the controller module to the CAM module;

[0081] The hit / miss signal feedback path points from the CAM module to the controller module, transmitting the hit or miss signal, the hit entry storage address and the available entry number; the entry fill path in case of a miss points from the controller module to the CAM module, transmitting the fill command, fill data and fill address.

[0082] Furthermore, in the TX module, each CAM entry is allocated an n-bit register (n is the maximum number of sub-packets in a single data stream) and a transmit counter. Upon receiving a sub-packet from the corresponding data stream, the register sets the SN bit high based on the sub-packet's SN. The counter records the number of sub-packets that have been reordered and transmitted for the data stream corresponding to the current CAM entry.

[0083] Furthermore, when a sub-packet is received, the FID information carried by the sub-packet is first checked to see if the FID has been stored in the CAM. If the FID already exists in the CAM, it means that the data stream corresponding to the FID already has a sub-packet waiting for reordering. If the FID does not exist in the CAM, it means that the sub-packet is the first sub-packet waiting for reordering in the data stream corresponding to the FID.

[0084] Furthermore, if the FID of the sub-packet is found in the CAM, a hit signal and a hit address are generated and sent to the controller module. The controller module then concatenates the address output by the CAM with the SN number of the sub-packet as the address of the DPRAM and writes the sub-packet into the DPRAM. If the FID is not found in the CAM, the CAM generates a miss signal and the number of the currently available CAM entry in the CAM and sends them to the controller module. The controller module selects one of the available entries, writes the FID into the CAM, and concatenates the selected available entry number with the SN number of the sub-packet as the address of the DPRAM and writes the sub-packet into the DPRAM.

[0085] Furthermore, in the TX module, the counters of each data stream will be increased by 1 after the sub-packets to which the data stream belongs are reordered and sent, and then the count value of the counter and whether the corresponding bit of the register is high are used to determine whether the next data to be sent has been received. If it has been received and the counter count has reached the SN of the current sub-packet, the data will be sent out; after all the sub-packets of the data stream to which the counter belongs have been sent out, the counter will be reset to zero.

[0086] Sub-data packets that do not need to be reordered can also be collected using the digital sequential circuit of the present invention, and after collection, they are sent out as a continuous data stream.

[0087] like Figure 2 As shown, an embodiment of a multi-stream sub-packet hardware reordering method based on CAM is provided, comprising the following steps:

[0088] Step 100: Configure the digital sequential circuit:

[0089] On the one hand, the reordered transmission mode of the reordering digital sequential circuit is set to the second mode: if there is no hole in front of the received data stream sub-packet, it will be sent; if there is a hole in front of the received sub-packet, the current sub-packet will be stored and enter a waiting state;

[0090] On the other hand, the configuration CAM contains 8 entries, so the CAM's fill address, output index, and available entries are each represented by an 8-bit one-hot code; there are also 8 registers and 8 counters corresponding to the 8 entries.

[0091] Step 101: The number of all sent and received data streams needs to be monitored to avoid exhaustion of entries in the CAM due to excessive data streams, which could lead to deadlock. If the CAM is not full, the reordering circuit receives one or more sub-packets of data streams that need to be reordered, sent by one or more sources. The sub-packet information needs to include the data stream ID (FID) to which the sub-packet belongs and the sub-packet sequence number (SN).

[0092] Step 102: After receiving the sub-packet that needs to be reordered, the FID carried by the sub-packet is sent to the CAM for query to determine whether the FID is already stored in the CAM. If it is stored, it means that the FID is a hit. The output of the CAM includes a hit signal, an available entry status signal, and the hit entry number.

[0093] Step 103: Receive a sub-packet. Since it is the first sub-packet, the CAM outputs a miss signal and the available entry signal is 8'b1111_1111. Since it is a miss, the hit entry number is ignored.

[0094] Step 104: CTRL receives a miss signal and an available entry 8'b1111_1111, selects the lowest bit of the available entry, where entry number 0 is selected, generates an FID fill address 8'b0000_0001, and writes the FID to the CAM address 8'b0000_0001. Simultaneously, the FID fill address 8'b0000_0001 is concatenated with SN00 to generate the DPRAM write address {8'b0000_0001, SN00}, and the sub-data packet is written to the DPRAM.

[0095] Step 105: While writing the sub-data packet into the DPRAM, the TX module pulls the SN00th bit of the register corresponding to entry 0 high, indicating that the current sequential circuit has received the SN00th sub-data packet of the data stream;

[0096] Step 106: Determine whether the bit corresponding to the corresponding counter value of the register corresponding to CAM entry 0 is high. Because the reordered sub-packet has not yet been sent, the corresponding counter should be 0. Therefore, it is determined whether bit 0 of the counter value is high. If it is high, it indicates that SN00 of the current sub-packet is 1, indicating that it is the first sub-packet in the data stream. This sub-packet can be sent directly, and the counter value is increased by 1. If bit 0 of the counter value is not high, it indicates that there is a sub-packet with an SN number less than SN00 in the current data stream that has not been sent. In this case, the current sub-packet continues to wait in the DPRAM, and the counter value remains unchanged.

[0097] Step 107: Receive the next sub-packet. If its FID is the same as the sub-packet FID in step 3, send the FID of this sub-packet to the CAM for query. The CAM outputs a hit signal, outputs the index 8'b0000_0001, and the available entry is 8'b1111_1110, indicating that this sub-packet is not the first sub-packet of the current FID, and its FID is stored in the 0th entry of the CAM.

[0098] Step 108: The controller module receives the hit signal, outputs the index 8'b0000_0001, and the available entry is 8'b1111_1110. The output index 8'b0000_0001 and SN01 are concatenated into the DPRAM write address {8'b0000_0001, SN01}, and the sub-data packet is written into the DPRAM.

[0099] Step 109: While writing the sub-data packet into the DPRAM, the TX module pulls the SN01 bit of the register corresponding to entry 0 high, indicating that the current sequential circuit has received the SN01 sub-data packet of the data stream;

[0100] Step 110: Determine whether the bit corresponding to the corresponding counter value in the register corresponding to CAM entry 0 is high. If it is high, it indicates that the sub-packet with an SN number less than SN01 in the current data stream has been sent. This sub-packet can be sent directly, and the counter value is increased by 1. If the corresponding bit of the counter value in the register is not high, it indicates that a sub-packet with an SN number less than SN01 in the current data stream has not been sent. Then, the current sub-packet continues to wait in the DPRAM, and the counter value remains unchanged.

[0101] Step 111: After the sub-packet corresponding to SN01 is sent out, if the bit corresponding to the new value after the counter in the register is incremented by 1 is high, it means that all sub-packets with SN numbers smaller than SN02 in the data stream have been sent out, and the sub-packet SN02 can continue to be sent out;

[0102] Step 112: Receive the next sub-packet. If the sub-packet belongs to a new data stream, send the FID of the sub-packet to the CAM for query. The CAM outputs a miss signal and the available entry is 8'b1111_1110, indicating that the sub-packet is the first sub-packet of the current FID.

[0103] Step 113: CTRL receives a miss signal and an available entry 8'b1111_1110, selects the lowest bit of the available entry (here, the entry number is 1), generates an FID address 8'b0000_0010, and writes the FID to the CAM address 8'b0000_0010. Simultaneously, the FID address 8'b0000_0010 is concatenated with SN10 to generate the DPRAM write address {8'b0000_0010, SN10}, and the sub-packet is written to the DPRAM.

[0104] Step 114: While writing the sub-data packet into the DPRAM, the TX module pulls the SN10 bit of the register corresponding to entry 1 high, indicating that the current sequential circuit has received the SN10 sub-data packet of the data stream;

[0105] Step 115: Determine whether the bit corresponding to the corresponding counter value of the register corresponding to CAM entry 1 is high. Because the reordered sub-packet has not yet been sent, the corresponding counter should be 0. Therefore, it is determined whether bit 0 of the counter value is high. If it is high, it indicates that SN10 of the current sub-packet is 1, indicating that it is the first sub-packet in the data stream. This sub-packet can be sent directly, and the counter value is increased by 1. If bit 0 of the counter value is not high, it indicates that there are sub-packets with SN numbers less than SN10 in the current data stream that have not been sent. In this case, the current sub-packet continues to wait in the DPRAM, and the counter value remains unchanged.

[0106] Step 116: Continue receiving sub-packets and perform corresponding processing according to the previous different situations. If the received sub-packet is the last sub-packet in FLOW, after writing is completed, bits 0 to SN-1 of the corresponding register are all high, and all sub-packets stored in DPRAM of FLOW can be sent.

[0107] Step 117: After all sub-packets corresponding to a certain FLOW are reordered and sent, an entry clear signal and the corresponding FID are sent to the CAM. The CAM then sets the entry corresponding to the internal FID as an available entry for use by subsequent new FLOWs, and simultaneously resets the corresponding register and the corresponding counter value.

[0108] This embodiment supports the simultaneous reordering of multiple data streams from the same data stream source, and also supports the simultaneous reordering of multiple data streams from multiple data stream sources. It is capable of simultaneously reordering sub-data packets of up to 8 data streams. This embodiment uses a method of sending sub-data packets immediately while ensuring the order, without waiting for the sub-data packets to be collected, which speeds up the scheduling of sub-data packets and thus speeds up the speed of the processor in processing data streams. The reordering method is implemented through hardware timing circuits, which releases part of the processor's performance, has higher processing speed and lower latency; the hardware implementation will not be affected by software vulnerabilities or virus attacks, and has higher stability; the functions implemented by the hardware do not depend on a specific operating system or programming language, and are more convenient to run in different environments.

[0109] In summary, the two sets of data packet hardware reordering methods and digital sequential circuits described in this embodiment are used to restore the order of multiple sub-packets belonging to the same data stream after their original order has been disrupted. This method includes a CAM (content-addressable memory) for storing data stream labels, a DPRAM (dual-port RAM) for storing sub-packets, a controller module CTRL for filling the CAM and DPRAM, and a transmitter module TX for receiving counts and generating transmit commands. Multiple out-of-order sub-packets from the data stream are received and stored in the DPRAM. These packets are then scheduled when conditions are met. Transmission conditions can be configured into two categories: 1. Waiting for all sub-packets in the entire data stream to be collected before transmission; 2. Transmission is performed when there are no holes preceding a received sub-packet (i.e., all sub-packets preceding the current sub-packet in the data stream have been transmitted in their original order). If a received sub-packet still has holes preceding it, the current sub-packet is stored and placed in a waiting state. This method supports simultaneous reordering of multiple data streams from the same data stream source, as well as multiple data streams from multiple data stream sources.

[0110] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.

Claims

1. A multi-stream sub-packet hardware reordering method based on CAM, characterized in that: The steps include: Step S1: receiving out-of-order sub-data packets, and binding each sub-data packet with a data flow identifier and a sequence number; Step S2: Query the CAM based on the FID of the sub-packet: If the FID exists in the CAM, obtain its storage address; If the FID does not exist in the CAM, the controller allocates a new entry and writes the FID based on the CAM status and the miss signal; Step S3: Concatenate the address returned by the CAM with the sub-data packet SN to generate a DPRAM write address, and store the sub-data packet in the DPRAM; Step S4: Maintain an n-bit register and a counter for each FID: According to the sub-packet SN, mark the corresponding SN bit in the register as received; The counter records the number of sub-packets sent in the current data flow; Step S5: Send sub-data packets according to the following strategy: Strategy 1: After all sub-packets with the same FID are received, they are sent in SN order; Strategy 2: When the SN of a sub-packet is equal to the counter value and the SN bit in the register is marked, the sub-packet is sent immediately and the counter is incremented by 1.

2. The CAM-based multi-stream sub-packet hardware reordering method according to claim 1, characterized in that: The sending strategy of step S5 is configured in the following ways: an external input signal; or a configuration field carried by a sub-data packet, and its priority is higher than the external signal.

3. The CAM-based multi-stream sub-packet hardware reordering method according to claim 1, characterized in that: Applicable to: Parallel reordering of multiple data streams from the same data source; Parallel reordering of multiple data streams from multiple data sources.

4. A CAM-based multi-stream sub-packet hardware reordering circuit, used to implement the reordering method according to claim 1, characterized in that: include: CAM module: The input port receives the FID query request sent by the controller module; The output port returns the hit signal and available entry status to the controller module, and outputs the hit signal and entry address to the DPRAM module; DPRAM module: The write address port is connected to the spliced ​​{CAM entry address, SN} splicing signal output by the controller module; The write data port directly receives the input sub-data packets; The read data port is connected to the read enable and read address input of the sending module; Controller module: The main input terminal receives the sub-data packet and its bound FID / SN and valid signal; The second input terminal receives a hit signal, a hit address, and a CAM status signal of the CAM; The first output terminal is connected to the FID query and entry filling interface of the CAM module; The second output terminal generates a DPRAM write address and drives the DPRAM write address port; The third output terminal sends a register update instruction to the TX module; Sending module: The register management terminal receives the SN update instruction from CTRL; The read command generator generates the DPRAM read address and read enable signal according to the counter value; The data output terminal sends the reordered sub-data packets; The release request end is connected to the entry release interface of the CAM module.

5. The CAM-based multi-stream sub-packet hardware reordering circuit according to claim 4, characterized in that: There are three physical paths between the CAM module and the controller module: FID query request path, from the controller module to the CAM module; The hit status signal feedback path and the miss status signal feedback path are directed from the CAM module to the controller module to transmit the hit or miss signal, the hit entry storage address and the available entry number; The entry filling path in case of a miss is directed from the controller module to the CAM module, transmitting the filling command, filling data and filling address.

6. The CAM-based multi-stream sub-packet hardware reordering circuit according to claim 5, characterized in that: The hit status signal feedback path includes two subpaths: a hit signal path: activated when the data flow identifier is queried; and a miss signal path: activated when the data flow identifier is not queried.

7. The CAM-based multi-stream sub-packet hardware reordering circuit according to claim 4, characterized in that: The sending module includes: Register: The bit width is equal to the maximum number of sub-packets in a single data stream. When receiving a sub-packet, the corresponding bit is set according to the SN. Counter: The bit width matches the SN range and increments after the sub-packet is successfully sent; Send judgment unit: When the register bit corresponding to the counter value is high, the sending operation is triggered; The sending module contains three output paths: DPRAM read address path: drives DPRAM read address port; Data sending path: output reordered sub-data packets; CAM entry release path: Sends entry clear signal to CAM.

8. The CAM-based multi-stream sub-packet hardware reordering circuit according to claim 7, characterized in that: The sending judgment unit operates in real time under strategy 2: if the SN bit corresponding to the current counter value is marked, the SN sub-packet in the sending judgment unit is sent and the counter is incremented; If not marked, wait until marking is complete.

9. The CAM-based multi-stream sub-packet hardware reordering circuit according to claim 4, characterized in that: The controller module's write operation to the DPRAM includes two levels of control: First level: Get the corresponding write flag signal according to the entry address of the filled CAM; Second level: concatenate the padding address and sub-packet SN into a physical address bus signal.

10. The CAM-based multi-stream sub-packet hardware reordering circuit according to claim 4, characterized in that: The FID and SN of the sub-packet are bound and transmitted by the source, and the source does not save the FID / SN status information; it supports interleaved input of sub-packets with different FIDs.

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