On-chip dual-band radio frequency rectifier of fully-integrated passive matching network

Through fully integrated passive matching network and on-chip dual-band RF rectifier with full NMOS architecture, the problems of insufficient frequency band coverage and low integration in the existing technology are solved, and efficient miniaturized RF energy collection is achieved.

CN120528262AActive Publication Date: 2025-08-22NANJING UNIV OF POSTS & TELECOMM
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Patent Information

Application Number
CN202511013481.4
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-07-23
Publication Date
2025-08-22
Estimated Expiration
2045-07-23

AI Technical Summary

Technical Problem

Existing RF rectifiers are mostly designed for single frequency bands, making it difficult to cover multi-band signals from Sub-6 GHz to millimeter waves, resulting in limited energy collection efficiency. Traditional rectifier circuits are large in size and low in integration, making it difficult to meet the needs of miniaturized electronic devices.

Method used

The on-chip dual-band RF rectifier with a fully integrated passive matching network is adopted, and the lumped parameter matching network and full NMOS architecture is used to realize the miniaturization of the dual-band and achieve the maximum power output through the peak voltage detection circuit.

Benefits of technology

The operating bandwidth and rectification efficiency of the rectifier are improved in the two frequency bands 1.7GHz~2.5GHz and 5.2GHz~6.8GHz, reducing the physical size of the circuit, and improving the sensitivity and input power range of the rectifier.

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Abstract

The invention provides an on-chip dual-band radio frequency rectifier of a fully-integrated passive matching network, which comprises a microwave source, a balun, an impedance matching network, a rectification network and a peak detection network, and is characterized in that the input end of the impedance matching network is in differential connection with the microwave source passing through the balun, and the output end of the impedance matching network is connected with the input end of the rectification network; the rectification network is connected with the peak detection network; wherein the impedance matching network is realized by using an on-chip lumped parameter element and only consists of four inductors and five capacitors, and the rectification network and the peak value detection network are realized by NMOS (N-channel Metal Oxide Semiconductor) tubes. Through the dual-band impedance matching technology, the working bandwidth and the rectification efficiency of the rectifier are improved, separation of two frequency bands is achieved by constructing a high-resistance path and a low-resistance path in a matching network, and the rectification efficiency of each frequency band is maximized; by adopting a full NMOS (N-channel Metal Oxide Semiconductor) framework rectifier, the rectification sensitivity and the input power range are improved; the peak detection circuit can detect the peak voltage of the rectifier in real time under the condition that the rectifier is not affected.
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Description

Technical Field

[0001] The present invention relates to the field of radio frequency circuits, and in particular to an on-chip dual-band radio frequency rectifier with a fully integrated passive matching network. Background Art

[0002] In recent years, the global energy transition has accelerated, with a surge in demand for low-carbon and distributed energy. Simultaneously, the number of IoT devices has grown exponentially, projected to exceed 100 billion by 2030. These devices generally rely on batteries, but frequent battery replacement is both costly and environmentally damaging. Wireless energy harvesting technology, which captures ambient radio frequency signals (such as Wi-Fi, 5G, and Bluetooth) and converts them into DC power, has become a key solution to this problem, providing a sustainable energy supply for low-power electronic devices.

[0003] With the commercialization of 5G communication technology, RF signal bands have expanded into the millimeter wave range (such as 28 GHz and 39 GHz), and the RF energy density in the environment has increased significantly. However, existing RF rectifiers are mostly designed for a single frequency band and have difficulty covering multi-band signals from Sub-6 GHz to millimeter waves, resulting in limited energy collection efficiency. Furthermore, traditional rectifier circuits rely on complex impedance matching networks and discrete components, which are not only bulky but also prone to efficiency degradation due to parasitic effects at high frequencies, making them difficult to meet the integration requirements of miniaturized electronic devices.

[0004] Multi-band rectifiers are a hot topic in the field of RF energy harvesting. Traditional rectifiers have the problems of low rectifier efficiency, narrow frequency range, and low integration, making them unsuitable for some small devices. Summary of the Invention

[0005] To address the specific needs of RF rectifiers, the present invention proposes an on-chip dual-band RF rectifier with a fully integrated passive matching network. This rectifier utilizes a lumped parameter matching network and an all-NMOS architecture to achieve dual-band and miniaturization. Furthermore, a novel peak voltage detection circuit is employed, utilizing two NMOS transistors to detect the rectifier's peak voltage. Detecting the peak voltage facilitates achieving maximum power output for the rectifier. The present invention provides the following technical solutions:

[0006] An on-chip dual-band RF rectifier with a fully integrated passive matching network includes a microwave source, a balun, an impedance matching network, a rectification network, and a peak detection network. The invention is characterized in that the input end of the impedance matching network is differentially connected to the microwave source through the balun, the output end is connected to the input end of the rectification network, and the rectification network is connected to the peak detection network. The impedance matching network is implemented using on-chip lumped parameter elements and consists of only four inductors and five capacitors. The rectification network and the peak detection network are implemented by NMOS transistors.

[0007] Preferably, the impedance matching network consists of four inductors and five capacitors. The microwave source is converted into a differential input signal through a balun, and is first connected to a capacitor C1 on the differential branch. Capacitor C1 is connected to inductor L1, and inductor L1 is simultaneously connected to capacitor C2 and inductor L2. Capacitor C2 is connected across the differential branch, and the other end of inductor L2 is connected to DC blocking capacitor C3; wherein inductors L1 and L2 are coupled to each other.

[0008] Preferably, the rectifier network consists of a DC blocking capacitor, a full NMOS differential cross-coupled rectifier, a pass-through filter and a DC load; the input end of the DC blocking capacitor is differentially connected to the impedance matching network, and the output end is differentially connected to the full NMOS differential cross-coupled rectifier and the peak detection network; the output end of the full NMOS differential cross-coupled rectifier is connected to the pass-through filter and the DC load.

[0009] Preferably, the full NMOS differential cross-coupled rectifier uses four NMOS tubes, divided into two pairs; the source and drain of each pair of NMOS tubes are connected, the drain end of one NMOS tube is grounded, and the source end of the other NMOS tube is connected to the DC load as the output end; one gate end of each pair of NMOS tubes is connected to the positive pole of the differential signal, and the other gate end is connected to the negative pole of the differential signal.

[0010] Preferably, the straight-through filter is composed of a capacitor CL, an input end of which is connected to the output end of the full-NMOS differential cross-coupled rectifier, and the other end is grounded.

[0011] Preferably, the peak detection network is connected in parallel with the rectification network, the input end is connected to the DC blocking capacitor in a differential form, the output end is connected to the capacitive load, and the other end of the capacitive load is grounded.

[0012] Preferably, the peak detection network consists of two NMOS transistors and a capacitive load, the drain terminals of the two NMOS transistors are connected to the capacitive load, and the gate terminals and source terminals of the two NMOS transistors are connected to the positive and negative terminals of the differential input, respectively.

[0013] Preferably, one end of the microwave source is converted into a differential signal through a balun and connected to the impedance matching network, and the other end is grounded, with an internal resistance of 50Ω.

[0014] Compared with the existing technology, the beneficial effects achieved by the present invention are as follows: through dual-band impedance matching technology, the input impedance of the circuit is matched to the impedance of the microwave source in the two frequency bands of 1.7GHz to 2.5GHz and 5.2GHz to 6.8GHz, effectively increasing the operating bandwidth and rectification efficiency of the rectifier; by constructing high-resistance paths and low-resistance paths in the matching network, the two frequency bands can be separated to maximize the rectification efficiency of each frequency band; the matching network is entirely composed of lumped parameters, and the inductive elements are coupled with each other, which greatly reduces the physical size of the rectifier circuit; the full NMOS architecture rectifier adopted improves the rectification sensitivity and input power range; the proposed peak detection circuit can detect the rectifier peak voltage in real time without affecting the rectifier to adjust the maximum output power. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0016] Figure 1 This is a circuit diagram of the dual-band radio frequency rectifier proposed in the present invention;

[0017] Figure 2 1 is a diagram of simulated rectification efficiency when the input power is 0 dBm in an embodiment of the present invention;

[0018] Figure 3 This is a diagram of the simulated rectification efficiency when the input frequency is 2.4 GHz in an embodiment of the present invention;

[0019] Figure 4 This is a diagram of the simulated rectification efficiency when the input frequency is 5.8 GHz in an embodiment of the present invention;

[0020] In the figure: C1, C2, C3, L1, L2 are impedance matching networks, Crf is a DC blocking capacitor, M1, M2, M3, M4 are all-NMOS differential cross-coupled rectifiers, CL is a pass filter, RL is a DC load, and M5, M6, CV are peak detection circuits. DETAILED DESCRIPTION

[0021] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0022] In order to make the above-mentioned objects, features and effects of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] An on-chip dual-band RF rectifier with a fully integrated passive matching network, the structure of which is as follows Figure 1 As shown, it includes a microwave source, a balun, an impedance matching network, a rectifier network and a peak detection network; the input end of the impedance matching network is differentially connected to the microwave source passing through the balun, the output end is connected to the input end of the rectifier network, and the rectifier network is connected to the peak detection network; the impedance matching network includes four inductive elements and five capacitive elements; the impedance matching network is implemented using on-chip lumped parameter elements, consisting of only four inductors and five capacitors, and the rectifier network and peak detection network are implemented by NMOS tubes.

[0024] One end of the microwave source is converted into a differential signal through a balun and connected to the impedance matching network, and the other end is grounded with an internal resistance of 50Ω.

[0025] The impedance matching network consists of four inductors and five capacitors. The microwave source is converted into a differential input signal through a balun. On the differential branch, it is first connected to a capacitor C1, which is then connected to the inductor L1. The inductor L1 is also connected to the capacitor C2 and the inductor L2. The capacitor C2 is connected across the differential branch, and the other end of the inductor L2 is connected to the DC blocking capacitor C3. The inductors L1 and L2 are coupled to each other.

[0026] The rectifier network consists of a DC blocking capacitor, an all-NMOS differential cross-coupled rectifier, a pass-through filter and a DC load; the input end of the DC blocking capacitor is differentially connected to the impedance matching network, and the output end is differentially connected to the all-NMOS differential cross-coupled rectifier and the peak detection network; the output end of the all-NMOS differential cross-coupled rectifier is connected to the pass-through filter and the DC load.

[0027] The all-NMOS differential cross-coupled rectifier uses four NMOS transistors, divided into two pairs: M1 and M4, and M2 and M3. Each pair has its source and drain connected, with the drain of one NMOS transistor grounded and the source of the other connected to a DC load as the output. One gate of each pair is connected to the positive and negative terminals of the differential signal, respectively. The pass-through filter consists of a capacitor, CL, with its input connected to the output of the all-NMOS differential cross-coupled rectifier and its other terminal grounded.

[0028] The peak detection network consists of two NMOS tubes and a capacitive load. The drain terminals of the two NMOS tubes are connected to the capacitive load, and the gate and source terminals of the two NMOS tubes are connected to the positive and negative terminals of the differential input respectively. The peak detection network is connected in parallel with the rectifier network. The input terminal is connected to the DC blocking capacitor in a differential form, the output terminal is connected to the capacitive load, and the other end of the capacitive load is grounded.

[0029] This invention utilizes an impedance matching network based on an all-NMOS differential cross-coupled rectifier. By introducing parallel branch capacitors, a series resonant path and a parallel resonant path are formed in a symmetrical LC network, creating low-impedance and high-impedance paths. Ultimately, the impedance is matched to 50 ohms at the signal source within two frequency bands ranging from 1 GHz to 10 GHz. The rectifier utilizes an all-NMOS differential cross-coupled structure and consists of four NMOS transistors. Impedance matching is achieved using on-chip lumped parameter elements, requiring only four inductors and five capacitors. Overlapping the inductors creates coupling, further reducing the physical size. The peak detection circuit consists of two NMOS transistors. Simulation results demonstrate that the rectifier exhibits excellent dual-band characteristics. At an input power of 0 dBm and a DC load of 250 Ω, the rectification efficiency exceeds 46% in the 1.7 GHz to 2.5 GHz and 5.2 GHz to 6.8 GHz frequency bands. The proposed on-chip dual-band RF rectifier with a fully integrated passive matching network measures 468 x 386 μm².

[0030] Figure 2 The simulated rectification efficiency of the rectifier circuit at different frequencies when the input power is 0dBm is given. As can be seen from the figure, the rectification efficiency is greater than 46% in the two frequency bands of 1.7GHz~2.5GHz and 5.2GHz~6.8GHz.

[0031] Figure 3 The simulated rectification efficiency of the rectifier circuit at different input powers when the input frequency is 2.4 GHz is given. As can be seen from the figure, within the input power range of -4.2 dBm to 6.7 dBm, the rectification efficiency is greater than 25%, reaching a maximum of 47%.

[0032] Figure 4 The simulated rectification efficiency of the rectifier circuit at different input powers when the input frequency is 5.8 GHz is given. As can be seen from the figure, within the input power range of -5.4 dBm to 6.4 dBm, the rectification efficiency is greater than 25%, reaching a maximum of 53%.

[0033] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art will be able to modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein with equivalents. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. An on-chip dual-band RF rectifier with a fully integrated passive matching network, comprising a microwave source, a balun, an impedance matching network, a rectifier network, and a peak detection network, characterized in that: The input end of the impedance matching network is differentially connected to the microwave source passing through the balun, the output end is connected to the input end of the rectifier network, and the rectifier network is connected to the peak detection network; the impedance matching network is implemented using on-chip lumped parameter elements and consists of only four inductors and five capacitors, and the rectifier network and peak detection network are implemented by NMOS tubes.

2. The on-chip dual-band RF rectifier with a fully integrated passive matching network according to claim 1, characterized in that: The impedance matching network consists of four inductors and five capacitors. The microwave source is converted into a differential input signal through a balun. On the differential branch, it is first connected to a capacitor C1, which is then connected to the inductor L1. The inductor L1 is also connected to the capacitor C2 and the inductor L2. The capacitor C2 is connected across the differential branch, and the other end of the inductor L2 is connected to the DC blocking capacitor C3. The inductors L1 and L2 are coupled to each other.

3. The on-chip dual-band RF rectifier with a fully integrated passive matching network according to claim 1, wherein: The rectifier network consists of a DC blocking capacitor, an all-NMOS differential cross-coupled rectifier, a pass-through filter and a DC load; the input end of the DC blocking capacitor is differentially connected to the impedance matching network, and the output end is differentially connected to the all-NMOS differential cross-coupled rectifier and the peak detection network; the output end of the all-NMOS differential cross-coupled rectifier is connected to the pass-through filter and the DC load.

4. The on-chip dual-band RF rectifier with a fully integrated passive matching network according to claim 3, characterized in that: The full-NMOS differential cross-coupled rectifier uses four NMOS transistors, divided into two pairs; the source and drain of each pair of NMOS transistors are connected, the drain of one NMOS transistor is grounded, and the source of the other NMOS transistor is used as the output terminal to connect to the DC load; one gate terminal of each pair of NMOS transistors is connected to the positive electrode of the differential signal, and the other gate terminal is connected to the negative electrode of the differential signal.

5. The on-chip dual-band RF rectifier with a fully integrated passive matching network according to claim 4, characterized in that: The pass filter is composed of a capacitor CL, whose input end is connected to the output end of the full NMOS differential cross-coupled rectifier and the other end is grounded.

6. The on-chip dual-band RF rectifier with a fully integrated passive matching network according to claim 3, characterized in that: The peak detection network is connected in parallel with the rectification network, the input end is connected to the DC blocking capacitor in a differential form, the output end is connected to the capacitive load, and the other end of the capacitive load is grounded.

7. The on-chip dual-band RF rectifier with a fully integrated passive matching network according to claim 6, characterized in that: The peak detection network consists of two NMOS tubes and a capacitive load. The drain terminals of the two NMOS tubes are connected to the capacitive load, and the gate terminals and source terminals of the two NMOS tubes are connected to the positive and negative terminals of the differential input respectively.

8. The on-chip dual-band RF rectifier with a fully integrated passive matching network according to claim 1, characterized in that: One end of the microwave source is converted into a differential signal through a balun and connected to the impedance matching network, and the other end is grounded with an internal resistance of 50Ω.

Citation Information

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