Pipeline ADC sampling method, sampling hold circuit and pipeline ADC

Abstract

The invention relates to the technical field of integrated circuits, in particular to a pipeline ADC. The invention discloses a pipeline ADC sampling method, which comprises the following steps: a, carrying out first sampling on an input voltage delta VIN, and outputting a sampling voltage delta VOUT1; b, the sampling capacitor and the feedback capacitor are reset, and charges on the sampling capacitor and the feedback capacitor are removed; c, sampling the input voltage for the second time, and outputting a sampling voltage delta VOUT2; and d, taking the arithmetic mean value of the delta VOUT1 and the delta VOUT2 as the sampling data of the input voltage. The invention also discloses a sample hold circuit and a pipeline ADC. The offset voltage of the operational amplifier and the matching error of the sampling capacitor and the feedback capacitor are reduced by adopting an error averaging technology, the offset error of the sampling hold circuit is reduced, the gain error of the sampling hold circuit is also reduced, the overall performance of the sampling hold circuit is optimized, and the reliability of the sampling hold circuit is improved. Therefore, the output precision of the assembly line ADC is improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a pipeline ADC (Analog-to-Digital Converter ADC). Specifically, the present application relates to a pipeline ADC sampling method, a sample-and-hold circuit, and a pipeline ADC. Background Art

[0002] Analog-to-Digital Converter (ADC), as a bridge connecting analog signals and digital signals, has been widely used in wireless communication systems, radar and other electronic information systems.

[0003] With the rapid development of modern digital communication technology, pipeline ADC has become the mainstream architecture among many ADC structures because of its advantages of high speed and high precision.

[0004] The basic structure of a pipeline ADC consists of multiple sub-ADCs. The first-stage sub-ADC includes a sample-and-hold circuit to sample the input differential signal, and the subsequent sub-ADCs perform digital conversion of the sampled signal in a pipeline form.

[0005] The sample-and-hold circuit is the core circuit of a pipeline ADC, and its performance directly determines the overall performance of the pipeline ADC. In particular, during the hold phase, the offset and gain errors of the sample-and-hold circuit directly affect its accuracy, thus determining the performance of the entire pipeline ADC. Therefore, to improve the conversion accuracy of the overall sample-and-hold circuit, it is necessary to minimize the offset and gain errors of the sample-and-hold circuit.

[0006] Figure 1 This is a schematic diagram of the structure of the sampling and holding circuit of the prior art, including the sampling capacitor C S , feedback capacitor C F , an operational amplifier (also referred to as op amp) A1 and a sampling switch composed of NMOS transistors MN1 to MN15 and PMOS transistors MP1 to MP11. Figure 1 In the CMOS circuit, each sampling switch is composed of a pair of NMOS and PMOS transistors, which can be regarded as two switches in parallel. This structure is mainly used to reduce the on-resistance and improve the stability of the circuit. Figure 1 Among them, S1~S3 and SN1~SN3 represent both the corresponding switches and the corresponding switch signals. IP It is the positive input terminal of the sample and hold circuit, V IN It is the negative input terminal of the sample and hold circuit, V IP and V IN It also represents the corresponding input signal. VCOM1 and VCOM2 are two common-mode input reference voltages.OP It is the positive output terminal of the sample and hold circuit, V ON It is the negative output terminal of the sample and hold circuit, V OP and V ON It also represents the corresponding output signal. Usually the sampling capacitor Cs and the feedback capacitor C F The design capacity is equal, so ideally, the sampling capacitor Cs and the feedback capacitor C F The capacity is equal. Figure 2 This is the working timing diagram of the sample-and-hold circuit. The switch signals Si and SNi (i=1,2...3) are inverse signals to each other. When Si is high, the corresponding SNi is low, the corresponding NMOS transistor and PMOS transistor are turned on, and the sampling switch is closed. Conversely, when Si is low, the corresponding SNi is high, the corresponding NMOS transistor and PMOS transistor are turned off, and the sampling switch is open. The function of the sample-and-hold circuit is to sample the input signal and store the input voltage charge through the sampling capacitor Cs. After the sampling is completed, the charge on the sampling capacitor Cs is transferred to the feedback capacitor C F superior.

[0007] In order to improve the linearity of the circuit, a fully differential circuit structure is usually adopted. This structure can effectively suppress common-mode noise and reduce the distortion introduced by various nonlinear factors. According to the working timing diagram of the sampling and holding circuit, the working process of the sampling and holding circuit in the prior art can be divided into two stages, one is the sampling stage, which completes the sampling of the input signal; the other is the holding stage, which completes the holding and amplification of the sampled signal. In the sampling mode, switches S1~SN1 and S2~SN2 are turned on, and switches S3~SN3 are turned off. At this time, the top plates of the two sampling capacitors are connected to the differential input signal (marked as V in the figure) through switches S1~SN1. IP and V IN ), the bottom plate is also connected to the common-mode input level VCOM1 through switches S2~SN2, and the top plate and bottom plate of the feedback capacitor are connected to the common-mode input reference voltage VCOM1 and the common-mode output reference voltage VCOM2 respectively through switches S1~SN1 and S2~SN2, as shown in Figure 1 shown.

[0008] from Figure 2It can be seen that the rising edge of switch S3 is later than the falling edge of switch S1, and the rising edge of switch SN3 is later than the rising edge of switch SN1, with a time difference of Δt2. The falling edge of switch S1 is later than the falling edge of switch S2, and the rising edge of switch SN1 is later than the rising edge of switch SN2, with a time difference of Δt1. This indicates that after sampling is completed, the switch connected to the bottom plate of the sampling capacitor is opened first, followed by the switch connected to the input signal. This ensures that the charge injected into the differential sampling capacitors is equal, preventing differential error voltage, thereby effectively reducing the error introduced by switch channel charge injection. After switches S1-SN1 and S2-SN2 are opened and switches S3-SN3 are turned on, the circuit enters hold mode. The top plates of the sampling capacitors are connected together, and the input terminals of the op amp are virtually shorted. The differential charge on the sampling capacitors is fully transferred to the feedback capacitor, making the output voltage equal to the input voltage at the sampling moment.

[0009] The offset error of existing sample-and-hold circuits is primarily determined by the offset voltage of the operational amplifier (OPA). The smaller the OPA offset voltage, the smaller the offset error of the sample-and-hold circuit. Therefore, to meet the accuracy requirements of pipelined ADCs, it is necessary to reduce the OPA offset voltage to ensure that the overall accuracy meets the requirements.

[0010] The gain error of the sample-and-hold circuit is mainly determined by the ratio of the sampling capacitor to the feedback capacitor. Therefore, the matching accuracy of the sampling capacitor and the feedback capacitor directly determines the gain error of the sample-and-hold circuit.

[0011] Generally, the op amp's offset voltage can be reduced by increasing the area of ​​its input stage. To reduce the matching error between the sampling capacitor and the feedback capacitor, the capacitor area needs to be increased, which also increases the capacitance. However, increasing the sampling and feedback capacitor values ​​reduces the sampling rate of the sample-and-hold circuit. The op amp's offset voltage and capacitor matching error can also be optimized by adding a trimming circuit, but these methods increase the chip area, thereby increasing chip cost. Summary of the Invention

[0012] The main purpose of this application is to provide a pipeline ADC sampling method, a sample-and-hold circuit, and a pipeline ADC to solve the problem of reducing sampling error by increasing the layout area of ​​the prior art ADC.

[0013] To achieve the above object, according to one aspect of the specific implementation of the present application, a pipeline ADC sampling method is provided, characterized in that it includes the following steps:

[0014] a. Input voltage ΔV IN Perform the first sampling and output the sampling voltage ΔV OUT1 ;

[0015] b. Reset the sampling capacitor and feedback capacitor to clear the charge on the sampling capacitor and feedback capacitor;

[0016] c. Sample the input voltage for the second time and output the sampled voltage ΔV OUT2 ;

[0017] d. ΔV OUT1 and ΔV OUT2 The arithmetic mean is the sampling data of the input voltage.

[0018] In some embodiments, the input voltage ΔV IN is the differential voltage input to the sample-and-hold circuit, and its expression is:

[0019] ΔV IN =(V IP -V IN )

[0020] Among them, V IP is the positive input voltage of the sample and hold circuit, V IN It is the negative input voltage of the sample and hold circuit.

[0021] In some embodiments, the sampling capacitor and the feedback capacitor are designed to have equal capacitance.

[0022] According to another aspect of the specific implementation of the present application, a pipeline ADC sample-and-hold circuit is provided, comprising an operational amplifier, a sampling capacitor, a feedback capacitor, and a plurality of sampling switches for switching between sampling and holding states. The circuit is characterized in that it also comprises a switching switch for switching between a first sampling, resetting the sampling capacitor and the feedback capacitor, and a second sampling.

[0023] In some embodiments, the sampling switch is formed by a CMOS transistor.

[0024] In some embodiments, the CMOS transistor includes an NMOS transistor and a PMOS transistor connected in parallel.

[0025] In some embodiments, the switch is formed by a CMOS transistor.

[0026] In some embodiments, the CMOS transistor includes an NMOS transistor and a PMOS transistor connected in parallel.

[0027] According to another aspect of the specific implementation of the present application, a pipeline ADC is provided, including n-stage sub-ADCs, wherein the first-stage sub-ADC includes a sample-and-hold circuit, characterized in that the sample-and-hold circuit has the above-mentioned sample-and-hold circuit structure, wherein n is a natural number greater than 1.

[0028] In some embodiments, the pipeline ADC is manufactured using a CMOS process.

[0029] According to the technical solution of the present application and the further improved technical solution in certain exemplary embodiments thereof, the present application has the following beneficial effects:

[0030] The present application adopts error averaging technology to reduce the offset voltage of the op amp and the matching error between the sampling capacitor and the feedback capacitor, which not only reduces the offset error of the sample-and-hold circuit, but also reduces the gain error of the sample-and-hold circuit. The present application optimizes the overall performance of the sample-and-hold circuit, thereby improving the output accuracy of the pipeline ADC.

[0031] The present application will be further described below in conjunction with the accompanying drawings and specific embodiments. Additional aspects and advantages of the present application will be partially given in the following description, partially become apparent from the following description, or be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The drawings that constitute part of this application are used to provide a further understanding of this application. The specific implementation methods, illustrative examples, and their descriptions of this application are used to explain this application and do not constitute an improper limitation on this application. In the drawings:

[0033] Figure 1 This is a structural diagram of a sampling and holding circuit in the prior art;

[0034] Figure 2 This is the working timing diagram of the existing sampling and holding circuit

[0035] Figure 3 This is a structural diagram of a sampling and holding circuit according to a specific embodiment of the present application;

[0036] Figure 4 This is a timing diagram of the sample-and-hold circuit according to a specific embodiment of the present application;

[0037] Figure 5 This is an equivalent circuit diagram of the sampling and holding circuit structure of the specific embodiment of the present application at the switching time stage t4;

[0038] Figure 6 This is an equivalent circuit diagram of the sampling and holding circuit structure of the specific embodiment of the present application at the switching time stage t5;

[0039] Figure 7 This is a simulation diagram of the offset error of the sampling and holding circuit in the prior art;

[0040] Figure 8 This is a simulation diagram of the offset error of the sample-and-hold circuit according to a specific embodiment of the present application;

[0041] Figure 9This is a simulation diagram of the gain error of the sampling and holding circuit in the prior art;

[0042] Figure 10 This is a simulation diagram of the gain error of the sample-and-hold circuit according to a specific embodiment of the present application;

[0043] Figure 11 This is a flow chart of the pipeline ADC sampling method according to a specific embodiment of the present application. DETAILED DESCRIPTION

[0044] It should be noted that, in the absence of conflict, the specific implementations, exemplary embodiments, and features thereof in this application may be combined with each other. This application will now be described in detail with reference to the accompanying drawings and in conjunction with the following content.

[0045] In order to enable those skilled in the art to better understand the solution of this application, the following will be combined with the drawings in the specific implementation methods and exemplary embodiments of this application to clearly and completely describe the technical solutions in the specific implementation methods and exemplary embodiments of this application. Obviously, the exemplary embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the specific implementation methods and exemplary embodiments in this application, all other implementation methods and embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of this application.

[0046] The sampling and holding circuit structure of the specific embodiment of this application is as follows Figure 3 shown.

[0047] The circuit includes NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MN9, MN10, MN11, MN12, MN13, MN14, MN15, MN16, MN17, MN18, MN19, MN20, MN21, MN22, MN23, MN24, MN25, MN26, MN27, MN28, MN29, MN30, and MN31; PMOS transistors MP1, MP2, and MP3. MOS transistor MP2, PMOS transistor MP3, PMOS transistor MP4, PMOS transistor MP5, PMOS transistor MP6, PMOS transistor MP7, PMOS transistor MP8, PMOS transistor MP9, PMOS transistor MP10, PMOS transistor MP11, PMOS transistor MP12, PMOS transistor MP13, PMOS transistor MP14, PMOS transistor MP15, PMOS transistor MP16, PMOS transistor MP17, PMOS transistor MP18, PMOS transistor MP19, PMOS transistor MP20, PMOS transistor MP21, PMOS transistor MP22, PMOS transistor MP23, PMOS transistor MP24, PMOS transistor MP25, PMOS transistor MP26, PMOS transistor MP27; op amp positive input terminal signal VIP, op amp negative input terminal signal VIN, op amp positive output terminal VOP, op amp negative output terminal VON; input switch control signals S1-S11 and SN1-SN11. Here, S1-S11 and SN1-SN11 also represent corresponding switches.

[0048] The specific connection method is as follows: the gate terminal of the NMOS tube MN1 is connected to the switching signal S1, the drain terminal is connected to the source terminal of the PMOS tube MP1, and the source terminal is connected to the drain terminal of the PMOS tube MP1; the gate terminal of the NMOS tube MN2 is connected to the switching signal S1, the drain terminal is connected to the source terminal of the PMOS tube MP2, and the source terminal is connected to the drain terminal of the PMOS tube MP2; the gate terminal of the NMOS tube MN3 is connected to the switching signal S2, the drain terminal is connected to the source terminal of the PMOS tube MP3, and the source terminal is connected to the drain terminal of the PMOS tube MP3; the gate terminal of the NMOS tube MN4 is connected to the switching signal S2, the drain terminal is connected to the source terminal of the PMOS tube MP4, and the source terminal is connected to the drain terminal of the PMOS tube MP4; the gate terminal of the NMOS tube MN5 is connected to the switching signal S2, the drain terminal is connected to the source terminal of the PMOS tube MP4, and the source terminal is connected to the drain terminal of the PMOS tube MP4; The gate terminal of the NMOS tube MN6 is connected to the switching signal S8, the drain terminal is connected to the source terminal of the PMOS tube MP5, and the source terminal is connected to the drain terminal of the PMOS tube MP5; the gate terminal of the NMOS tube MN6 is connected to the switching signal S8, the drain terminal is connected to the source terminal of the PMOS tube MP6, and the source terminal is connected to the drain terminal of the PMOS tube MP6; the gate terminal of the NMOS tube MN7 is connected to the switching signal S5, the drain terminal is connected to the source terminal of the PMOS tube MP7, and the source terminal is connected to the drain terminal of the PMOS tube MP7; the gate terminal of the NMOS tube MN8 is connected to the switching signal S5, the drain terminal is connected to the source terminal of the PMOS tube MP8, and the source terminal is connected to the drain terminal of the PMOS tube MP8; the gate terminal of the NMOS tube MN9 is connected to the switching signal S3, and the drain terminal is connected to the PMOS tube MP 9, the source end of the source end is connected to the drain end of the PMOS tube MP9; the gate end of the NMOS tube MN10 is connected to the switching signal S4, the drain end is connected to the source end of the PMOS tube MP10, and the source end is connected to the drain end of the PMOS tube MP10; the gate end of the NMOS tube MN11 is connected to the switching signal S4, the drain end is connected to the source end of the PMOS tube MP11, and the source end is connected to the drain end of the PMOS tube MP11; the gate end of the NMOS tube MN12 is connected to the switching signal S6, the drain end is connected to the source end of the PMOS tube MP12, and the source end is connected to the drain end of the PMOS tube MP12; the gate end of the NMOS tube MN13 is connected to the switching signal S6, the drain end is connected to the source end of the PMOS tube MP13, and the source end is connected to the PM The drain of the OS transistor MP13; the gate of the NMOS transistor MN14 is connected to the switching signal S9, the drain is connected to the source of the PMOS transistor MP14, and the source is connected to the drain of the PMOS transistor MP14; the gate of the NMOS transistor MN15 is connected to the switching signal S9, the drain is connected to the source of the PMOS transistor MP15, and the source is connected to the drain of the PMOS transistor MP15; the gate of the NMOS transistor MN16 is connected to the switching signal S7, the drain is connected to the source of the PMOS transistor MP16, and the source is connected to the drain of the PMOS transistor MP16; the gate of the NMOS transistor MN17 is connected to the switching signal S7, the drain is connected to the source of the PMOS transistor MP17, and the source is connected to the drain of the PMOS transistor MP17;The gate terminal of the NMOS tube MN18 is connected to the switching signal S7, the drain terminal is connected to the source terminal of the PMOS tube MP18, and the source terminal is connected to the drain terminal of the PMOS tube MP18; the gate terminal of the NMOS tube MN19 is connected to the switching signal S7, the drain terminal is connected to the source terminal of the PMOS tube MP19, and the source terminal is connected to the drain terminal of the PMOS tube MP19; the gate terminal of the NMOS tube MN20 is connected to the switching signal S10, the drain terminal is connected to the source terminal of the PMOS tube MP20, and the source terminal is connected to the drain terminal of the PMOS tube MP20; the gate terminal of the NMOS tube MN21 is connected to the switching signal S10, and the drain terminal is connected to The source terminal of the PMOS transistor MP21 is connected to the drain terminal of the PMOS transistor MP21; the gate terminal of the NMOS transistor MN22 is connected to the switching signal S9, the drain terminal is connected to the source terminal of the PMOS transistor MP22, and the source terminal is connected to the drain terminal of the PMOS transistor MP22; the gate terminal of the NMOS transistor MN23 is connected to the switching signal S9, the drain terminal is connected to the source terminal of the PMOS transistor MP23, and the source terminal is connected to the drain terminal of the PMOS transistor MP23; the gate terminal of the NMOS transistor MN24 is connected to the switching signal S7, the drain terminal is connected to the source terminal of the PMOS transistor MP24, and the source terminal is connected to the drain terminal of the PMOS transistor MP24 The gate terminal of the NMOS tube MN25 is connected to the switching signal S7, the drain terminal is connected to the source terminal of the PMOS tube MP25, and the source terminal is connected to the drain terminal of the PMOS tube MP25; the gate terminal of the NMOS tube MN26 is connected to the switching signal S11, the drain terminal is connected to the source terminal of the PMOS tube MP26, and the source terminal is connected to the drain terminal of the PMOS tube MP26; the gate terminal of the NMOS tube MN27 is connected to the switching signal S11, the drain terminal is connected to the source terminal of the PMOS tube MP27, and the source terminal is connected to the drain terminal of the PMOS tube MP27; the gate terminal of the NMOS tube MN28 is connected to the switching signal S5, and the drain terminal is connected to The drain terminal of the NMOS transistor MN29 is connected to the drain terminal of the NMOS transistor MN4, and the source terminal is connected to the drain terminal of the NMOS transistor MN4. The gate terminal of the NMOS transistor MN29 is connected to the switching signal S4, the drain terminal is connected to the drain terminal of the NMOS transistor MN28, and the source terminal is connected to the source terminal of the NMOS transistor MN31. The gate terminal of the NMOS transistor MN30 is connected to the switching signal S4, the drain terminal is connected to the drain terminal of the NMOS transistor MN31, and the source terminal is connected to the source terminal of the NMOS transistor MN28. The gate terminal of the NMOS transistor MN31 is connected to the switching signal S5, the drain terminal is connected to the drain terminal of the NMOS transistor MN30, and the source terminal is connected to the source terminal of the NMOS transistor MN3.

[0049] The gate terminal of the PMOS tube MP1 is connected to the switching signal SN1, the drain terminal is connected to the source terminal of the NMOS tube MN1, and the source terminal is connected to the drain terminal of the NMOS tube MN1; the gate terminal of the PMOS tube MP2 is connected to the switching signal SN1, the drain terminal is connected to the source terminal of the NMOS tube MN2, and the source terminal is connected to the drain terminal of the NMOS tube MN2; the gate terminal of the PMOS tube MP3 is connected to the switching signal SN2, the drain terminal is connected to the source terminal of the NMOS tube MN3, and the source terminal is connected to the drain terminal of the NMOS tube MN3; the gate terminal of the PMOS tube MP4 is connected to the switching signal SN2, the drain terminal is connected to the source terminal of the NMOS tube MN4, and the source terminal is connected to the drain terminal of the NMOS tube MN4; the gate terminal of the PMOS tube MP5 is connected to the switching signal SN8, the drain end is connected to the source end of the NMOS tube MN5, and the source end is connected to the drain end of the NMOS tube MN5; the gate end of the PMOS tube MP6 is connected to the switching signal SN8, the drain end is connected to the source end of the NMOS tube MN6, and the source end is connected to the drain end of the NMOS tube MN6; the gate end of the PMOS tube MP7 is connected to the switching signal SN5, the drain end is connected to the source end of the NMOS tube MN7, and the source end is connected to the drain end of the NMOS tube MN7; the gate end of the PMOS tube MP8 is connected to the switching signal SN5, the drain end is connected to the source end of the NMOS tube MN8, and the source end is connected to the drain end of the NMOS tube MN8; the gate end of the PMOS tube MP9 is connected to the switching signal SN3, and the drain end is connected to the source end of the NMOS tube MN9. The source end is connected to the drain end of the NMOS tube MN9; the gate end of the PMOS tube MP10 is connected to the switching signal SN4, the drain end is connected to the source end of the NMOS tube MN10, and the source end is connected to the drain end of the NMOS tube MN10; the gate end of the PMOS tube MP11 is connected to the switching signal SN4, the drain end is connected to the source end of the NMOS tube MN11, and the source end is connected to the drain end of the NMOS tube MN11; the gate end of the PMOS tube MP12 is connected to the switching signal SN6, the drain end is connected to the source end of the NMOS tube MN12, and the source end is connected to the drain end of the NMOS tube MN12; the gate end of the PMOS tube MP13 is connected to the switching signal SN6, the drain end is connected to the source end of the NMOS tube MN13, and the source end is connected to the NMOS tube The drain terminal of MN13; the gate terminal of the PMOS transistor MP14 is connected to the switching signal SN9, the drain terminal is connected to the source terminal of the NMOS transistor MN14, and the source terminal is connected to the drain terminal of the NMOS transistor MN14; the gate terminal of the PMOS transistor MP15 is connected to the switching signal SN9, the drain terminal is connected to the source terminal of the NMOS transistor MN15, and the source terminal is connected to the drain terminal of the NMOS transistor MN15; the gate terminal of the PMOS transistor MP16 is connected to the switching signal SN7, the drain terminal is connected to the source terminal of the NMOS transistor MN16, and the source terminal is connected to the drain terminal of the NMOS transistor MN16; the gate terminal of the PMOS transistor MP17 is connected to the switching signal SN7, the drain terminal is connected to the source terminal of the NMOS transistor MN17, and the source terminal is connected to the drain terminal of the NMOS transistor MN17;The gate terminal of the PMOS transistor MP18 is connected to the switching signal SN7, the drain terminal is connected to the source terminal of the NMOS transistor MN18, and the source terminal is connected to the drain terminal of the NMOS transistor MN18; the gate terminal of the PMOS transistor MP19 is connected to the switching signal SN7, the drain terminal is connected to the source terminal of the NMOS transistor MN19, and the source terminal is connected to the drain terminal of the NMOS transistor MN19; the gate terminal of the PMOS transistor MP20 is connected to the switching signal SN10, the drain terminal is connected to the source terminal of the NMOS transistor MN20, and the source terminal is connected to the drain terminal of the NMOS transistor MN20; the gate terminal of the PMOS transistor MP21 is connected to the switching signal SN10, the drain terminal is connected to the source terminal of the NMOS transistor MN21, and the source terminal is connected to the drain terminal of the NMOS transistor MN21; the gate terminal of the PMOS transistor MP22 is connected to the switching signal SN7, the drain terminal is connected to the source terminal of the NMOS transistor MN22, and the source terminal is connected to the drain terminal of the NMOS transistor MN22; The gate terminal of the PMOS transistor MP23 is connected to the switching signal SN7, the drain terminal is connected to the source terminal of the NMOS transistor MN23, and the source terminal is connected to the drain terminal of the NMOS transistor MN23. The gate terminal of the PMOS transistor MP24 is connected to the switching signal SN7, the drain terminal is connected to the source terminal of the NMOS transistor MN24, and the source terminal is connected to the drain terminal of the NMOS transistor MN24. The gate terminal of the PMOS transistor MP25 is connected to the switching signal SN7, the drain terminal is connected to the source terminal of the NMOS transistor MN25, and the source terminal is connected to the drain terminal of the NMOS transistor MN25. The gate terminal of the PMOS transistor MP26 is connected to the switching signal SN11, the drain terminal is connected to the source terminal of the NMOS transistor MN26, and the source terminal is connected to the drain terminal of the NMOS transistor MN26. The gate terminal of the PMOS transistor MP27 is connected to the switching signal SN11, the drain terminal is connected to the source terminal of the NMOS transistor MN27, and the source terminal is connected to the drain terminal of the NMOS transistor MN27.

[0050] The op amp positive input signal VIP is connected to the source terminal of the NMOS transistor MN12; the op amp negative input signal VIN is connected to the source terminal of the NMOS transistor MN15; the op amp positive output terminal VOP is connected to the drain terminal of the NMOS transistor MN10; the op amp negative output terminal VON is connected to the drain terminal of the NMOS transistor MN8.

[0051] The switch signals Si and SNi (i=1,2......11) are opposite switch signals. Figure 4 As shown in the figure, similar to the switch signal in the prior art, when Si is high, the corresponding SNi is low, the corresponding NMOS transistor and PMOS transistor are turned on, and the switch is closed. Conversely, when Si is low, the corresponding SNi is high, the corresponding NMOS transistor and PMOS transistor are turned off, and the switch is open.

[0052] When a device mismatch error occurs in a sample-and-hold circuit, it introduces offset error and gain error, ultimately reducing the output accuracy of the sample-and-hold circuit. To improve the output accuracy of a pipeline ADC, it is necessary to reduce the impact of offset error and gain error to achieve improved conversion accuracy. This application, based on the prior art sample-and-hold circuit, employs error averaging technology to reduce the offset error and gain error of the sample-and-hold circuit, thereby improving the accuracy of the sample-and-hold circuit.

[0053] Figure 3 This is a structural diagram of a sampling and holding circuit according to a specific embodiment of the present application. Compared with the structural diagram of the sampling and holding circuit in the prior art, switching switches S4 to S11 and SN4 to SN11 are added. Figure 4 This is the working timing diagram of the sampling and holding circuit. Compared with the working timing of the sampling and holding circuit in the prior art, the working mode of the sampling and holding circuit of the present application is generally divided into three stages: the first stage is the first sampling and conversion stage, and the first conversion output voltage is obtained after the conversion is completed; the second stage performs a capacitor reset operation to clear the charge on the sampling capacitor and the feedback capacitor; the third stage is the second sampling and conversion stage, and the second conversion output voltage is obtained after the conversion is completed. At the same time, the holding stage is divided into two stages: switching time t4 and switching time t5. In the sampling mode, switches S4~SN4 and S5~SN5 are disconnected; at switching time t4, switches S4~SN4 are turned on and S5~SN5 are disconnected; at switching time t5, switches S4~SN4 are turned off and S5~SN5 are turned on. The time during which the switching signal S3 is high and the time during which SN3 is low is t3. At switching time t4, the switching signals S4 and SN5 are low, and the switching signals SN4 and S5 are high. At switching time t5, the switching signals S4 and SN5 are high, and the switching signals SN4 and S5 are low. Switching time t4 is equal to switching time t5 and is exactly half of switching time t3. At switching time t4, the post-stage pipeline conversion stage circuit samples the output signal of the sample-and-hold circuit for the first time. At switching time t5, the post-stage pipeline conversion stage circuit samples the output signal of the sample-and-hold circuit for the second time. The post-stage pipeline conversion stage circuit adds and averages the two sampled signals to obtain the final output voltage of the first stage. After the second-stage reset operation, the charge of the sampling capacitor and the feedback capacitor is cleared within switching time t6. The third stage repeats the first-stage operation and obtains the corresponding output voltage of the third stage. The post-stage pipeline conversion stage circuit then adds and averages the first-stage output voltage and the third-stage output voltage to obtain the final output voltage. By adding and averaging the sampled signals twice, the post-stage pipeline conversion stage circuit can effectively reduce the offset error and gain error of the sample-and-hold circuit.

[0054] The following analyzes how the sample-and-hold circuit of this application reduces the offset error:

[0055] Assume that the op amp A1 in the sample-and-hold circuit has an offset voltage of V OS1 , then after the sampling is completed, the input voltage sampled by the sampling capacitor is ΔV IN , we can get ΔV IN The expression is as follows:

[0056] ΔV IN =(V IP -V IN )+V OS1 (1)

[0057] Where V IP is the positive input voltage of the sample and hold circuit, V IN is the voltage at the negative input of the sample-and-hold circuit. After the sampling phase, the sample-and-hold circuit enters the hold mode. The hold mode is divided into two switching time phases: switching time t4 and switching time t5. Immediately after entering the hold mode, the charge on the sampling capacitor is transferred to the feedback capacitor and stabilizes to form the output voltage. At switching time t4, according to the law of conservation of charge, the output voltage ΔV of the sample-and-hold circuit at switching time t4 can be obtained. OUT1

[0058]

[0059] Among them C S is the sampling capacitor value, C F is the feedback capacitor value.

[0060] At switching time t5, the positive and negative input terminals and output terminals of the op amp are swapped by switching the switch, and a new output voltage is formed after the closed loop stabilizes. According to the law of conservation of charge, the output voltage ΔV of the sample and hold circuit at switching time t5 can be obtained OUT2

[0061]

[0062] Finally, the two output voltage values ​​generated in the holding phase are sampled by the subsequent pipeline conversion stage circuit at switching time t4 and switching time t5 respectively. The two sampled voltage values ​​ΔV OUT1 and ΔV OUT2 The arithmetic mean value is solved in the subsequent pipeline conversion stage circuit, and the obtained result is used as the sampling data of the input voltage for subsequent analog-to-digital conversion processing.

[0063] The solution process is as follows:

[0064] Add the output voltages of the two stages and divide by 2 to get the final output voltage ΔVOUT ,Right now

[0065]

[0066] It can be seen from formula (4) that the sampling and holding circuit of the present application can offset the offset voltage of the operational amplifier, reduce the offset error of the sampling and holding circuit, and improve the output accuracy of the sampling and holding circuit.

[0067] The following analyzes how the sample-and-hold circuit reduces the gain error:

[0068] When using the existing sampling and holding circuit structure, when there is a matching error between the sampling capacitor and the feedback capacitor, the sampling and holding circuit may generate a gain error. Figure 1 We can know that the sampling capacitor is C S , the feedback capacitor is C F , then from the above derivation we can know that the gain G of the sample and hold circuit can be written as follows:

[0069] G=C S / C F (5)

[0070] In the hold phase, assuming the sampling capacitor C S With the feedback capacitor C F There is a mismatch, and the feedback capacitor becomes C F ±ΔC, the gain of the sample-and-hold circuit can be written as follows:

[0071] G1=C S / (C F ±ΔC) (6)

[0072] It can be seen that when the prior art sample-and-hold circuit structure is used, if there is a mismatch error between capacitors, the gain of the sample-and-hold circuit will change, thereby affecting the accuracy of the entire pipeline ADC.

[0073] In order to reduce the influence of mismatch error between capacitors on the conversion accuracy of the sampling and holding circuit and improve the accuracy of the entire pipeline ADC, the sampling and holding circuit diagram of the present application is as follows: Figure 3 For ease of analysis, we will now use a single-ended structure to illustrate how the sample-and-hold circuit of this application reduces the mismatch error between capacitors.

[0074] The working timing diagram of the sampling and holding circuit of this application is as follows: Figure 4 As shown, the whole working process can be roughly divided into three stages: In the first stage, the capacitor C S As a sampling capacitor and samples the input once, the capacitor C F As a feedback capacitor and convert the input sampling voltage once; in the second stage, the capacitor CS and capacitor C F Reset to clear the charge on the sampling capacitor and feedback capacitor; in the third stage, the capacitor C F As a sampling capacitor and samples the input once, the capacitor C S As a feedback capacitor and convert the input sample voltage once. Ideally, the capacitor C S and capacitor C F Completely equal, there is no deviation. Now assume that the capacitor C F There is a deviation of ΔC on the capacitor, and the capacitance value becomes C F -ΔC. In the first sampling phase, the total charge Q S1 It can be written as the following expression

[0075] Q S1 =ΔV IN1 *C S (7)

[0076] ΔV IN1 The differential voltage of the first stage input sample and hold circuit

[0077] In the first stage, the equivalent circuit diagram is as follows: Figure 5 As shown, the total charge Q H1 It can be written as the following expression

[0078] Q H1 =(C F -ΔC)*V OUT1 (8)

[0079] Since the charge is conserved during the sampling and holding phases, we can obtain the output voltage value ΔV in the first phase: OUT1

[0080] Q S1 =Q H1 (10)

[0081]

[0082] Similarly, after the third stage of sampling and conversion, we can get the new output ΔV OUT2 , the equivalent circuit diagram of the third stage is as follows Figure 6 As shown,

[0083]

[0084] ΔV IN2 The differential voltage of the third stage input sample and hold circuit

[0085] Assumption C S =C F=C, and the sample-and-hold circuit operates in oversampling mode, and the sampling clock frequency is much greater than the input signal frequency, then we can assume that ΔV IN1 and ΔV IN2 and its average value ΔV IN_A Approximately equal, add the output voltage value of the first stage and the output voltage value of the third stage and then average them (that is, solve the arithmetic mean), add equation (11) and equation (12) and divide by 2 to get the final output voltage value ΔV OUT

[0086]

[0087] The output voltage ΔV obtained by the existing sampling and holding structure is OUT_ORI

[0088]

[0089] ΔC / C represents the matching accuracy of the capacitor. Ideally, the value of ΔC / C should be 0 and the gain coefficient should be 1. Due to the deviation in actual production and processing accuracy, the capacitance value has some deviation, so the value of ΔC / C cannot be completely 0, and it can only be reduced as much as possible. The smaller the value of ΔC / C, the smaller the matching error of the capacitor and the higher the matching accuracy of the capacitor. Assuming that the value of ΔC / C is 0.0005, and substituting the value of ΔC / C into equations (14) and (15) respectively, we can obtain that the gain coefficient of the prior art sampling and holding circuit is approximately 1.0005, and the gain error is approximately 0.0005; while the gain coefficient of the sampling and holding circuit proposed in this application is approximately 1.000000125, and the gain error is approximately 0.000000125. The above theoretical derivation shows that, ideally, using the sample-and-hold circuit of this application, by adding and averaging the two output signals of the sample-and-hold circuit, the gain error of the output voltage is reduced from 0.0005 to 0.000000125, and the gain error of the circuit is reduced to 0.25% of the original value. This greatly reduces the gain error of the sample-and-hold circuit caused by capacitor matching error, thereby improving the accuracy of the entire pipeline ADC. In actual circuit design, in addition to capacitor matching error affecting gain error, other non-ideal factors can also cause gain error, but capacitor matching error is the primary source. Therefore, the actual design value of gain error will be greater than the theoretical value.

[0090] against Figure 1 and Figure 3 The circuit structure shown in the figure is designed and simulated using a 5V power supply voltage in a 0.18μm CMOS process. The simulation results are shown in Figure 2. Figures 7 to 10 As shown, Figure 7 express Figure 1The simulation results of the offset error of the prior art sample-and-hold circuit are shown. Figure 8 express Figure 3 The figure shows the simulation results of the offset error of the sampling and holding circuit of this application. Figure 9 express Figure 1 The simulation results of gain error of the prior art sample-and-hold circuit are shown. Figure 10 express Figure 3 The simulation results of the gain error of the sampling and holding circuit of the present application are shown in FIG. It can be found that the circuit structure of the present application can make the sampling and holding circuit have higher conversion accuracy and effectively reduce the offset error and gain error of the output signal. Figure 1 When the circuit structure is shown, the offset error 3δ value of the sampling and holding circuit is about 6.68mV (5.47LSB) (LSB is the accuracy index of the ADC), and the gain error 3δ value is about 7.86mV (6.44LSB); using Figure 3 When the structure is shown, the offset error 3δ of the sample-and-hold circuit is about 0.812mV (0.66LSB), and the gain error 3δ is about 1.142mV (0.93LSB). The offset error is reduced to about 12% of the original offset error, and the gain error is reduced to about 14.5% of the original gain error.

[0091] exist Figure 3 In the circuit structure shown, the sampling and holding circuit structure of the present application is adopted to reduce the offset error and gain error in the conversion process, optimize the overall performance of the sampling and holding circuit, and thus improve the output accuracy of the pipeline ADC.

[0092] According to the above description, the pipeline ADC sampling process of this application can be obtained as follows: Figure 11 As shown, the main steps are as follows:

[0093] S1101 responds to input voltage ΔV IN Perform the first sampling and output the sampling voltage ΔV OUT1 .

[0094] Here ΔV IN The expression is:

[0095] ΔV IN =(V IP -V IN )

[0096] Among them, V IP is the positive input voltage of the sample and hold circuit, V IN It is the negative input voltage of the sample and hold circuit.

[0097] S1102 resets the sampling capacitor and the feedback capacitor to clear the charges on the sampling capacitor and the feedback capacitor, and prepares for the next sampling.

[0098] S1103 samples the input voltage for the second time and outputs a sampled voltage ΔV OUT2 ;

[0099] S1104 with ΔV OUT1 and ΔV OUT2 The arithmetic mean value is used as the sampling data of the input voltage for subsequent analog-to-digital conversion.

[0100] The arithmetic mean expression is:

[0101] ΔV OUT =(ΔV OUT1 +ΔV OUT2 )÷2

[0102] ΔV OUT ΔV OUT1 and ΔV OUT2 The arithmetic mean of .

Claims

1. A pipeline ADC sampling method, characterized in that: The steps include: a. Input voltage ΔV IN Perform the first sampling and output the sampling voltage ΔV OUT1 ; b. Reset the sampling capacitor and feedback capacitor to clear the charge on the sampling capacitor and feedback capacitor; c. Sample the input voltage for the second time and output the sampled voltage ΔV OUT2 ; d. ΔV OUT1 and ΔV OUT2 The arithmetic mean is the sampling data of the input voltage.

2. The pipeline ADC sampling method according to claim 1, wherein: The input voltage ΔV IN is the differential voltage input to the sample-and-hold circuit, and its expression is: ΔV IN =(V IP -V IN ) Among them, V IP is the positive input voltage of the sample and hold circuit, V IN It is the negative input voltage of the sample and hold circuit.

3. The pipeline ADC sampling method according to claim 1, wherein: The sampling capacitor and feedback capacitor are designed to have equal capacity.

4. A pipeline ADC sample-and-hold circuit, comprising an operational amplifier, a sampling capacitor, a feedback capacitor, and a plurality of sampling switches for switching between sampling and holding states, characterized in that: The invention also includes a switch for switching between the first sampling, resetting the sampling capacitor and the feedback capacitor, and the second sampling.

5. The pipeline ADC sample-and-hold circuit according to claim 4, wherein: The sampling switch is composed of CMOS transistors.

6. The pipeline ADC sample-and-hold circuit according to claim 5, wherein: The CMOS transistor includes an NMOS transistor and a PMOS transistor connected in parallel.

7. The pipeline ADC sample-and-hold circuit according to claim 4, wherein: The switch is composed of CMOS transistors.

8. The pipeline ADC sample-and-hold circuit according to claim 7, wherein: The CMOS transistor includes an NMOS transistor and a PMOS transistor connected in parallel.

9. A pipeline ADC comprising n stages of sub-ADCs, wherein the first stage of the sub-ADC comprises a sample-and-hold circuit, characterized in that: The sample-and-hold circuit has the sample-and-hold circuit structure according to claims 4 to 8, wherein n is a natural number greater than 1.

10. The pipeline ADC according to claim 9, wherein: The pipeline ADC is manufactured using a CMOS process.

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