Semiconductor device and manufacturing method thereof

Abstract

The present disclosure provides an embodiment of a semiconductor device and a method for manufacturing the same. The semiconductor device may include a silicon carbide body, a gate trench, a body region, a source region, and a shielding region. The gate trench is provided on a first surface of the silicon carbide body; the body region constitutes a portion of the sidewall of the gate trench; the source region constitutes a portion of the sidewall of the gate trench, and the source region is located between the body region and the first surface; the shielding region extends from the first surface into the silicon carbide body and is provided on both sides of the gate trench, and the shielding region includes a semi-enclosed shielding region located between any two adjacent gate trenches among a plurality of gate trenches; wherein the semi-enclosed shielding region constitutes the sidewall and a portion of the bottom of one of the two gate trenches, and covers a side of the source region located between the two gate trenches away from the body region; a side of the source region located between the two gate trenches away from the semi-enclosed shielding region is partially exposed to the other gate trench among the two gate trenches.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for manufacturing the same. Background Art

[0002] With the rapid development of semiconductor technology, the performance of power devices has become a key factor in promoting the development of electronic devices towards higher efficiency, smaller size and higher performance.

[0003] Silicon carbide metal-oxide-semiconductor field-effect transistors (MOSFETs) have become a leader among power semiconductor devices due to their exceptional electron mobility, high voltage resistance, low on-resistance, high switching frequency, and wide operating temperature range. However, the large bandgap of silicon carbide material results in a high body diode turn-on voltage and poor reverse recovery performance, which to some extent limits its widespread deployment in high-end applications.

[0004] However, under high-voltage turn-off conditions, the local electric field concentration at the bottom of the gate trench of traditional silicon carbide MOSFETs can easily lead to premature breakdown of the oxide layer, limiting the device's voltage resistance and reliability. The excessively high on-resistance of the body diode increases reverse recovery losses and reduces system efficiency. Summary of the Invention

[0005] In view of this, the embodiments of the present disclosure hope to provide a semiconductor device and a method for manufacturing the same, which can solve the problems of poor voltage resistance reliability and low system efficiency of silicon carbide MOSFET in the prior art.

[0006] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0007] In a first aspect, an embodiment of the present disclosure provides a semiconductor device, including:

[0008] Silicon carbide body;

[0009] A plurality of gate trenches are formed on the first surface of the silicon carbide body;

[0010] a body region constituting a portion of a sidewall of at least one of the gate trenches;

[0011] a source region, constituting a portion of a sidewall of at least one of the gate trenches and located between the body region and the first surface;

[0012] a shielding region extending from the first surface to the silicon carbide body and located on both sides of the gate trench, the shielding region comprising:

[0013] a semi-enclosing shielding region, located between two adjacent gate trenches among the plurality of gate trenches, constituting a sidewall and a portion of a bottom of one of the two gate trenches, and covering a side of the source region located between the two gate trenches away from the body region;

[0014] Wherein, a side of the source region located between the two gate trenches and away from the semi-enclosed shielding region is partially exposed to the other gate trench of the two gate trenches.

[0015] In a second aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, comprising:

[0016] forming a plurality of gate trenches opened on the first surface of the silicon carbide body;

[0017] forming a body region and a source region respectively constituting a portion of sidewalls of the gate trench, wherein the source region is located between the gate trench and the first surface of the body region;

[0018] forming a shielding region extending from the first surface into the silicon carbide body on both sides of the gate trench, the shielding region including a semi-enclosed shielding region between two adjacent gate trenches among the plurality of gate trenches;

[0019] The semi-enclosed shielding region constitutes the side wall and part of the bottom of one of the two gate trenches, and completely covers the side of the source region located between the two gate trenches away from the body region; the side of the source region located between the two gate trenches away from the semi-enclosed shielding region is partially exposed to the other gate trench of the two gate trenches.

[0020] Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same. This semiconductor device achieves its core benefits through the following structural design: a semi-enclosed shielding region covers the side of the source region between two adjacent gate trenches, away from the body region, and simultaneously forms the sidewalls and part of the bottom of the gate trench, providing active shielding for the electric field at the trench bottom, effectively suppressing electric field concentration near the gate oxide layer and improving the device's withstand voltage reliability. A portion of the source region between the two gate trenches, away from the semi-enclosed shielding region, is exposed to the second gate trench, forming a contact window. This structure enables the source metal layer to simultaneously contact three areas: the horizontal top of the shielding region covering the upper surface of the source region and the vertical surface of the shielding region extending along the trench sidewalls. The source metal layer and the shielding region form a composite contact structure (sidewall + top), significantly increasing the contact area, directly reducing contact resistance, optimizing carrier injection efficiency, and thus reducing resistive losses in the body diode conduction path. The overall structure achieves synergistic optimization of electric field control and ohmic contact through geometric arrangement, improving conduction efficiency while maintaining high blocking capability. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A cross-sectional view of a semiconductor device provided in an embodiment of the present disclosure.

[0022] Figure 2 A cross-sectional view of another semiconductor device provided in an embodiment of the present disclosure.

[0023] Figure 3 A cross-sectional view of another semiconductor device provided in an embodiment of the present disclosure.

[0024] Figure 4 A cross-sectional view of another semiconductor device provided in an embodiment of the present disclosure.

[0025] Figure 5 A cross-sectional view of a semiconductor device including a buffer layer provided in an embodiment of the present disclosure.

[0026] Figure 6 A cross-sectional view of a semiconductor device including a source metal layer provided in an embodiment of the present disclosure.

[0027] Figure 7 A cross-sectional view of a semiconductor device including a drain structure provided in an embodiment of the present disclosure.

[0028] Figure 8 A flowchart of a method for manufacturing a semiconductor device provided in an embodiment of the present disclosure.

[0029] Figure 9 A cross-sectional view of a semiconductor device with a gate trench formed therein according to an embodiment of the present disclosure.

[0030] Figure 10 A cross-sectional view of a semiconductor device after forming a source region and a body region according to an embodiment of the present disclosure is provided.

[0031] Figure 11 A cross-sectional view of a silicon carbide body provided in an embodiment of the present disclosure.

[0032] Figure 12 A cross-sectional view of a semiconductor device after forming a source region according to an embodiment of the present disclosure.

[0033] Figure 13 A cross-sectional view of a semiconductor device after forming a body region according to an embodiment of the present disclosure is provided.

[0034] Figure 14 A cross-sectional view of a semiconductor device after a shielding region is formed according to an embodiment of the present disclosure.

[0035] Figure 15 A cross-sectional view of another semiconductor device after forming a gate trench according to an embodiment of the present disclosure.

[0036] Figure 16 A cross-sectional view of a semiconductor device after forming a gate dielectric and a conductive gate electrode according to an embodiment of the present disclosure is provided.

[0037] Figure 17 A cross-sectional view of a semiconductor device after etching a conductive gate electrode according to an embodiment of the present disclosure.

[0038] Figure 18 A cross-sectional view of a semiconductor device after a dielectric layer is formed according to an embodiment of the present disclosure.

[0039] Figure 19 A cross-sectional view of a semiconductor device after etching a dielectric layer according to an embodiment of the present disclosure.

[0040] Figure 20 A cross-sectional view of a semiconductor device after a metal layer is formed according to an embodiment of the present disclosure.

[0041] Description of reference numerals:

[0042] 1. Silicon carbide body; 11. Gate trench; 11-1. First trench; 11-2. Middle trench; 11-3. Second trench; 111. Conductive gate electrode; 112. Gate dielectric; 113. Contact window; 12. Shielding region; 12A. Semi-enclosed shielding region; 13. Source region; 14. Body region; 15. Buffer layer; 1A. First surface; 1B. Second surface; 16. Source metal layer; 17. Drain layer; 18. Drain metal layer.

[0043] The above drawings illustrate specific embodiments of the present disclosure, which will be described in more detail below. These drawings and textual descriptions are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of the present disclosure to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0044] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and in which are shown by way of illustration specific embodiments in which silicon carbide devices may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. For example, features illustrated or described for one embodiment may be used on other embodiments or used in combination with other embodiments to produce yet another embodiment. It is intended that the present disclosure include such modifications and variations. Examples are described using specific language, which should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. Unless otherwise stated, corresponding elements in different drawings are represented by the same reference symbols.

[0045] The terms "having," "comprising," "including," and "comprising" and the like are open ended, and the terms indicate the presence of stated structures, elements, or features but do not preclude the presence of additional elements or features. The quantifiers and pronouns "a," "an," and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0046] The figures illustrate the relative doping concentrations by indicating "-" or "+" next to the doping type "n" or "p". For example, "n-" means a doping concentration that is lower than the doping concentration of an "n"-doped region, while an "n+"-doped region has a higher doping concentration than an "n"-doped region. Doping regions of the same doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n"-doped regions may have the same or different absolute doping concentrations. Two adjacent doping regions of the same conductivity type and having different dopant concentrations form a unipolar junction, for example, an n / n+ or p / p+ junction along the boundary surface between the two doping regions. At a unipolar junction, the dopant concentration profile orthogonal to the unipolar junction may show a step or turning point where the dopant concentration profile changes from concave to convex, or vice versa.

[0047] The main components of a layer or structure from a chemical composition or alloy are the elements whose atoms form the chemical composition or alloy. For example, nickel and silicon are the main components of a nickel silicide layer, and copper and aluminum are the main components of a copper-aluminum alloy.

[0048] Trench-gate MOSFETs are a relatively new device structure. Compared to traditional planar MOSFETs, the trench-gate design shifts the conductive channel from a horizontal to a vertical orientation, effectively reducing cell size and lowering on-resistance. However, conventional SiC MOSFETs face significant technical bottlenecks under high-voltage turn-off conditions, primarily due to performance limitations of the gate trench structure and the body diode. During the high-voltage turn-off process, due to the uneven electric field distribution within the device, a localized electric field concentration forms at the bottom of the gate trench. This electric field enhancement effect subjects the gate oxide to excessive electric field stress, which can easily lead to premature breakdown of the dielectric layer, severely limiting the device's long-term withstand voltage reliability. Furthermore, the body diode in conventional structures, due to the wide bandgap characteristics of SiC material, has a relatively high on-resistance, resulting in significant power loss during reverse recovery. This high on-resistance not only results in a larger reverse recovery current peak but also significantly increases switching losses, ultimately reducing the efficiency of the entire power conversion system. These critical issues directly impact the performance and reliability of SiC power devices and urgently require innovative device structure design to address them.

[0049] Based on the above problems, the present disclosure first proposes a semiconductor device. Figure 1The figure shows a single cell in a semiconductor device. The semiconductor device may include multiple cells, the specific number of which can be customized based on user needs and will not be described in detail in this exemplary embodiment. Among them, the cell is the basic unit that constitutes the device. Figure 1 The cross-sectional view of the semiconductor device is shown in FIG. 1 . It can be understood that the cellular structure has consistency and periodicity. Figure 1 The views of the sections shown are all the same Figure 1 Totally consistent.

[0050] The semiconductor device includes a silicon carbide body 1 , a gate trench 11 , a body region 14 , a source region 13 and a shield region 12 .

[0051] Among them, multiple gate trenches 11 extend from the first surface 1A of the silicon carbide body 1 into the silicon carbide body 1; the body region 14 constitutes a portion of the sidewall of the gate trench 11; the source region 13 constitutes a portion of the sidewall of the gate trench 11, and the source region 13 is located between the first surface 1A of the body region 14; the shielding region 12 extends from the first surface 1A into the silicon carbide body 1 and is arranged on both sides of the gate trench 11.

[0052] Optionally, the plurality of gate trenches 11 may include a first type of trench and a second type of trench, wherein the first type of trench is Figure 1 The first type of trench is a trench completely filled with a gate structure, and the second type of trench is a trench partially filled with a gate structure at its bottom, the gate structure includes a conductive gate electrode 111 of a first conductive type and a gate dielectric 112 at least between the body region 14 and the conductive gate electrode 111, the gate dielectric 112 is used to wrap the conductive gate electrode 111 (such as a polysilicon gate), the gate dielectric 112 is in contact with the sidewall of the gate trench 11, and the gate dielectric 112 covers the gate structure to prevent an electrical short circuit between the conductive gate electrode 111 and the source metal layer 16 after the source metal layer 16 is generated.

[0053] The shielding region 12 includes a semi-enclosed shielding region 12A located between any two adjacent gate trenches 11 in the gate trenches 11; Figure 1 As shown, the two adjacent gate trenches 11 are respectively a type I trench and a type II trench, wherein the semi-enclosed shielding region 12A constitutes the sidewall and part of the bottom of the type I trench, and covers the side of the source region 13 located between the two adjacent gate trenches 11 away from the body region 14; the side of the source region 13 located between the two gate trenches 11 away from the semi-enclosed shielding region 12A is partially exposed to the other gate trench 11 of the two gate trenches 11.

[0054] By way of example, the silicon carbide body 1 may be of the polytype 15R-SiC, 2H-SiC, 4H-SiC or 6H-SiC. In addition to the main components silicon and carbon, the silicon carbide body 1 may also include dopant atoms, such as nitrogen N, phosphorus P, beryllium Be, boron B, aluminum Al and / or gallium Ga. Furthermore, the silicon carbide body 1 may include unwanted impurities, such as hydrogen and / or oxygen. Figure 1 , the silicon carbide body 1 may include a first surface 1A at a front side and an opposite second surface 1B at a back side.

[0055] It should be noted that the conductivity type of the silicon carbide body 1 may be a first conductivity type, which may be an n-type or a p-type. Here and below, the conductivity type of the silicon carbide body 1 is named the first conductivity type.

[0056] It should be noted that the first conductivity type and the second conductivity type in the present disclosure are used to distinguish between n-type and p-type. When the first conductivity type is n-type, the second conductivity type is p-type. When the first conductivity type is p-type, the second conductivity type is n-type.

[0057] Reference Figure 1 The gate trench 11 extends from the first surface 1A of the silicon carbide body 1 into the silicon carbide body 1. Specifically, when forming the gate trench 11, a masked etching process can be used to etch the gate trench 11 into the silicon carbide body 1. The formed gate trench 11 has sidewalls and a bottom. The specific location of the gate trench 11 region can be customized based on user needs and is not described in detail in this exemplary embodiment.

[0058] In some examples, the body region 14 and the source region 13 are both formed in the silicon carbide body 1. The body region 14 and the source region 13 are doped with opposite conductivity types to form a pn junction. Specifically, the conductivity type of the source region 13 after doping is the first conductivity type, and the conductivity type of the body region 14 after doping is the second conductivity type.

[0059] The body region 14 contacts the sidewalls of the gate trench 11, the source region 13 contacts the sidewalls of the gate trench 11, and the source region 13 is located between the body region 14 and the first surface 1A. The body region 14 has the second conductivity type, and the source region 13 has the first conductivity type.

[0060] The shielding region 12 extends from the first surface 1A into the silicon carbide body 1 and is disposed on both sides of the gate trench 11 . The shielding region 12 includes a semi-enclosed shielding region 12A located between any two adjacent gate trenches 11 among the plurality of gate trenches 11 .

[0061] Among them, the semi-enclosed shielding area 12A constitutes the side wall and part of the bottom of one type of trench in the two gate trenches 11, and covers the side of the source region 13 located between the two gate trenches 11 away from the body region 14; the side of the source region 13 located between the two gate trenches 11 away from the semi-enclosed shielding area 12A is partially exposed to the second type of trench in the two gate trenches 11.

[0062] It should be noted that the shielding region 12 has a second conductivity type and can form a pn junction with the silicon carbide body 1 and the source region 13. Shielding regions 12 are provided on both sides of each gate trench 11. It should be noted that the semi-enclosed shielding region 12A is also part of the shielding region, and the shielding regions 12 of the non-semi-enclosed structure on both sides of the gate trench are spaced apart from the gate trench 11. Furthermore, the bottom of the shielding region 12 is closer to the second surface 1B than the bottom of the gate trench 11, which can disperse the originally concentrated electric field to a wider area. By optimizing the current path and reducing the concentration of current in a specific area, the electric field concentration is reduced, thereby improving the long-term reliability of the manufactured semiconductor device.

[0063] Semi-enclosed shielding region 12A forms the sidewalls and part of the bottom of a type of trench in two adjacent gate trenches 11, forming a three-dimensional, enclosing electric field shielding structure. This contact mechanism reshapes the electric field distribution at the bottom of the trench, distributing the peak electric field intensity concentrated in the gate oxide layer in traditional structures to shielding region 12, effectively suppressing the risk of dielectric layer breakdown.

[0064] At the same time, the gate structure of the other gate trench 11 of the two gate trenches 11 adopts a partially filled design. Partial filling refers to filling the side of the gate trench 11 close to the second surface 1B, and not completely filling the gate trench 11. A contact hole is formed inside the trench, so that the side of the source region 13 located between the two gate trenches 11, away from the shielding region 12, can be partially exposed in the contact hole. This exposed area constitutes a contact window 113, creating spatial conditions for the subsequent composite contact of the source metal layer 16.

[0065] In some examples, reference Figure 2 The source region 13 on both sides of the other gate trench 11 of the two gate trenches 11 is covered by a semi-enclosed shielding region 12A on the side away from the body region 14. This further increases the contact area between the shielding region 12 and the subsequently generated source metal layer, thereby optimizing the on-resistance of the body diode of the semiconductor device.

[0066] At the groove arrangement level, refer to Figure 3 The semiconductor device adopts a topological configuration of a first trench 11-1, an intermediate trench 11-2 and a second trench 11-3, wherein the first trench 11-1 and the second trench 11-3 are the first type trenches described above, and the intermediate trench 11-2 is the second type trench described above.

[0067] The middle trench 11-2 is located between the first trench 11-1 and the second trench 11-3, and the semi-enclosed shielding area 12A is respectively arranged in the gap between the first trench 11-1 and the middle trench 11-2 and the gap between the second trench 11-3 and the middle trench 11-2, forming a symmetrically distributed electric field modulation unit. It is worth noting that the first trench 11-1 and the second trench 11-3 are arranged in the edge area of ​​the device, and each edge trench shares the same semi-enclosed shielding area 12A with the adjacent middle trench 11-2. This sharing mechanism not only maintains the continuity of the electric field shielding, but also significantly improves the area utilization of the device active area.

[0068] In some examples, when a semiconductor device needs to expand the current channel, refer to Figure 4 , multiple intermediate trenches 11-2 can be provided. In this configuration, the shielding region 12 of the non-semi-enclosed structure between two adjacent intermediate trenches 11-2 is designed as a vertical structure that penetrates the source region 13 and the body region 14. This penetrating shielding region 12 is physically separated from the sidewalls and bottom of the intermediate trench 11-2, avoiding interference with the gate control area while constructing an independent carrier transmission path. This design optimizes the current distribution in the on-state while maintaining electric field uniformity.

[0069] In some examples, the body region 14 in the middle trench 11-2 region extends deeper than the body regions 14 corresponding to the first and second trenches 11-1, 11-3, to form gate channels of different depths. This also facilitates the provision of two gate channels of different lengths. The body regions 14 in the edge first and second trenches 11-1, 11-3 regions are closer to the first surface 1A, forming a wider depletion layer under blocking conditions, significantly suppressing the edge electric field peak and enhancing structural reliability. This depth gradient distribution synergistically balances conduction and blocking performance, simultaneously reducing conduction losses and maintaining high voltage withstand capability.

[0070] In some examples, the side of the source region 13 on both sides of the middle trench away from the body region 14 can be covered by the shielding region 12 (including the semi-enclosed shielding region 12A). Specifically, the side of the source region 13 between the two middle trenches 11-2 away from the body region 14 can be covered by the shielding region 12 of the non-semi-enclosed structure, and the side of the source region 13 located between the first trench 11-1 and the middle trench 11-2 away from the body region 14 can be covered by the semi-enclosed shielding region 12A, thereby further increasing the contact area between the shielding region 12 and the subsequently generated source metal layer to optimize the on-resistance of the body diode of the semiconductor device.

[0071] The three-dimensional contact of the semi-enclosed shielding region 12A in this embodiment fundamentally improves the electric field concentration problem at the bottom of the gate trench 11, enhancing the device's withstand voltage reliability. The through-hole design of the shielding region 12 optimizes carrier extraction efficiency during reverse recovery and reduces switching losses. This overall structure achieves comprehensive performance improvements for silicon carbide power devices while maintaining process compatibility.

[0072] In some examples, reference Figure 5 The semiconductor device may further include a buffer layer 15 having the same conductivity type as the silicon carbide body 1 and a doping concentration greater than that of the silicon carbide body 1 . The buffer layer 15 is disposed on a side of the silicon carbide body 1 away from the first surface 1A.

[0073] The disclosed embodiment further optimizes breakdown voltage and short-circuit withstand capability by adding a buffer layer 15 to the device's longitudinal structure. This buffer layer 15 has the same conductivity type as the silicon carbide body 1, but its doping concentration is higher than that of the bulk material of the silicon carbide body 1, forming a highly doped n-region. Spatially, the buffer layer 15 is precisely positioned on the side of the silicon carbide body 1 facing away from the first surface 1A, i.e., on the side of the drift region facing away from the first surface 1A.

[0074] It should be noted that the drift region refers to a region in the silicon carbide body 1 that is not specially doped, ie, the n-region in the drawings.

[0075] In some examples, reference Figure 6 The semiconductor device may further include a source metal layer 16, which forms an ohmic contact with the shielding region 12 and the source region 13. The added source metal layer 16 structure in the embodiment of the present disclosure improves electrical performance by optimizing the contact mechanism.

[0076] The source metal layer 16 forms an ohmic contact with the semi-enclosed shielding area 12A and the exposed source area 13 at the same time, constructing a three-dimensional contact interface. Specifically, the source metal layer 16 first covers the upper surface of the shielding area 12, and at the same time extends downward along the side wall where the shielding area 12 contacts the gate trench 11, thereby achieving a three-dimensional wrapping of the shielding area 12. Secondly, the source metal layer 16 directly contacts the exposed area of ​​the source area 13 between the two gate trenches 11 through the contact hole. This composite contact structure forms a parallel current path of metal-shielding area 12-semiconductor and metal-source area 13-semiconductor at the physical level.

[0077] The contact area of ​​the three-dimensional interface between the source metal layer 16 and the shielding region 12 is larger than that of the traditional planar structure. At the same time, the contact window 113 overlaps with the source region 13, thereby reducing the overall contact resistance and lowering the conduction loss.

[0078] In some examples, reference Figure 7, a composite drain structure can also be constructed on the back of the semiconductor device, optimizing the performance of the vertical conductive path. The drain layer 17 in the drain structure covers the second surface 1B of the silicon carbide body 1 (i.e., the bottom surface opposite the gate structure), forming a heavily doped contact interface. After the buffer layer 15 is formed, the drain layer 17 covers the side of the buffer layer 15 facing away from the silicon carbide body 1. The drain metal layer 18 in the drain structure is disposed on the side of the drain layer 17 facing away from the silicon carbide body 1, forming a metallurgical bond with the drain layer 17.

[0079] Among them, the conductivity type of the drain layer 17 is the same as the conductivity type of the silicon carbide body 1, and the doping concentration is greater than that of the silicon carbide body 1 and the buffer layer 15. The heavily doped characteristics of the drain layer 17 cause a strong electron tunneling effect to occur at the metal-semiconductor contact interface. At the same time, the buffer layer 15 is located between the above-mentioned silicon carbide body 1 and the drain layer 17. As a buffer area, it effectively alleviates the electric field concentration caused by the sudden doping interface between the drain layer 17 and the drift region. The setting of the buffer layer 15 can smooth the electric field distribution, avoid local electric field spikes, and thus increase the breakdown voltage. In the event of a short circuit, the buffer layer 15 can disperse the current path, slow down the formation of hot spots, and extend the short-circuit withstand time of the semiconductor device. The high conductivity of the drain metal layer 18 can achieve a uniform lateral distribution of current.

[0080] In the semiconductor device provided by the disclosed embodiments, the provision of a semi-enclosed shielding region 12A effectively optimizes the electric field distribution within the device. The design of the semi-enclosed shielding region 12A partially contacting the sidewalls and bottom of the gate trench 11 significantly disperses the electric field intensity that is concentrated at the bottom of the trench in traditional structures, thereby improving the reliability of the gate oxide layer under high-voltage blocking conditions. In adjacent gate trenches 11, a contact hole formed by partially filling the gate exposes a specific area of ​​the source region 13. This, combined with the three-dimensional contact interface constructed by the source metal layer 16, significantly increases the effective contact area and significantly reduces the contact impedance in the conduction path.

[0081] The trench arrangement employs a shared shielding region 12 (including a semi-enclosed shielding region 12A) between the edge trenches (i.e., the first trench 11-1 and the second trench 11-3) and the middle trench 11-2. This design maintains electric field shielding continuity while improving active area utilization. The shielding region 12, which extends through the source region 13 and the body region 14 in the configuration of multiple middle trenches 11-2, forms an independent carrier transport channel, effectively accelerating carrier motion during body diode conduction and significantly improving reverse recovery characteristics. The addition of a buffer layer 15 to the semiconductor device's longitudinal structure optimizes electric field distribution and, in conjunction with the heavily doped drain layer 17, achieves a smooth electric field transition, significantly enhancing the device's breakdown voltage, dynamic performance, reliability, and thermal stability.

[0082] The back-side composite drain structure achieves dual performance improvements through the combination of a heavily doped drain layer 17 and a drain metal layer 18. The drain layer 17 mitigates material thermal expansion mismatch and reduces interface resistance, while the drain metal layer 18 ensures uniform lateral current distribution, eliminating local hotspots. The synergistic effect of these structural elements enables systematic breakthroughs in key device performance indicators such as blocking capability, conduction loss, switching characteristics, and thermal reliability.

[0083] Furthermore, the present disclosure also provides a method for manufacturing a semiconductor device, referring to Figure 8 , the manufacturing method of the semiconductor device may include steps S810 to S830.

[0084] In step S810 , a plurality of gate trenches are formed on a first surface of a silicon carbide body.

[0085] In an exemplary embodiment of the present disclosure, referring to Figure 9 A trench can be formed on the silicon carbide body 1 , starting from the first surface 1A and extending into the interior of the silicon carbide body 1 . A gate structure will be formed in the trench in a subsequent process, and the trench is named a gate trench 11 .

[0086] Specifically, when forming the gate trench 11, a mask etching process (i.e., by constructing a mask plate) can be used to etch the gate trench 11 on the silicon carbide body 1, and the formed gate trench 11 has sidewalls and a bottom. The specific position of the gate trench 11 can be customized based on user needs and will not be described in detail in this example embodiment. A gate structure is provided in the gate trench 11. In order to better reflect the subsequent formation process of the body region 14 and the source region 13, the gate structure is Figure 9 Not shown in the figure.

[0087] by Figure 7 Taking the semiconductor device as an example, the gate trench 11 may include a first trench 11-1, an intermediate trench 11-2 and a second trench 11-3, wherein the specific structures of the first trench 11-1, the intermediate trench 11-2 and the second trench 11-3 have been described in detail above, so they will not be repeated here.

[0088] In step S820 , a body region and a source region constituting a portion of a sidewall of the gate trench are formed, with the source region being located between the body region and the first surface.

[0089] After the gate trench 11 is formed, refer to Figure 10First, a body region 14 can be formed on the silicon carbide body 1, and then a source region 13 can be formed between the body region 14 and the first surface 1A. Different dopants are used in the body region 14 and the source region 13 to achieve opposite conductivity types in the body region 14 and the source region 13, thereby forming a pn junction. The conductivity type of the source region 13 is the first conductivity type, and the conductivity type of the body region 14 is the second conductivity type.

[0090] The body region 14 constitutes a portion of the sidewall of the gate trench 11 , and the source region 13 constitutes a portion of the sidewall of the gate trench 11 .

[0091] Specifically, when the second conductivity type is p-type, a p-type body region mask may be first manufactured using a photolithography process, and then p-type impurity aluminum may be implanted based on the p-type body region mask to form the p-type body region 14 .

[0092] After the body region 14 is formed, n-type dopants may be implanted by ion implantation to form the source region 13 .

[0093] In step S830 , shielding regions extending from the first surface into the silicon carbide body are formed on both sides of the gate trenches, wherein the shielding regions include a semi-enclosed shielding region between two adjacent gate trenches among the plurality of gate trenches.

[0094] Among them, the semi-enclosed shielding area 12A constitutes the side wall and part of the bottom of one of the two gate trenches 11, and completely covers the side of the source region 13 located between the two gate trenches 11 away from the body region 14; the side of the source region 13 located between the two gate trenches 11 away from the semi-enclosed shielding area 12A is partially exposed to the other gate trench 11 of the two gate trenches 11.

[0095] After forming the body region 14 and the source region 13, a shielding region 12 is formed on both sides of the gate trench 11 by implanting second conductive type impurities. The specific structure of the shielding region 12 can refer to the structure of the semiconductor device. Figure 4 The description is not repeated here.

[0096] In some examples, the body region 14 , the source region 13 , and the shield region 12 may be formed before the gate trench 11 is formed. The specific formation order may be customized based on user needs and will not be described in detail in this example embodiment.

[0097] The manufacturing process of the semiconductor device disclosed herein uses an ordered process flow to achieve a specific structure. Figure 11 The preparation begins with sequentially generating an n-type epitaxial layer and a lightly doped n-type epitaxial layer on a heavily doped n-type silicon carbide substrate, which serve as a buffer layer 15 and a silicon carbide body 1 (drift region), respectively.

[0098] This is followed by the key doping step, referring to Figure 12 First, use the source region mask to implant n-type impurities to form the source region 13, wherein the implantation depth of the middle region is greater than that of the edge region, so that the source region 13 in this region is closer to the second surface 1B. Figure 13 , p-type impurities are injected through the p-type body region mask to form the body region 14. Figure 14 , and then a p+ region mask is used to implant to form a shielding region 12, whose layout meets two core characteristics: multiple shielding regions 12 are distributed at intervals and penetrate the body region 14 and the source region 13, and adjacent shielding regions 12 in the middle area are connected to each other on the first surface 1A side.

[0099] After doping is completed, a high-temperature activation process is performed, the covered carbon film is annealed to activate the impurities, and then the carbon film is removed.

[0100] Then enter the structural forming stage, refer to Figure 15 , using a trench mask to etch and form a gate trench array 11, including multiple middle trenches 11-2 located in the middle area and the first trench 11-1, middle trench 11-2 and second trench 11-3 at the edge. After etching, the sidewalls of the gate trench 11 are in direct contact with the body region 14 and the source region 13. After that, the gate structure is constructed, referring to Figure 16 A gate dielectric 112 is grown on the first surface 1A and the inner wall of the gate trench 11, and polysilicon is filled to form a conductive gate electrode 111. Figure 17 , selectively etch the polysilicon in the middle trench 11-2 to a partial depth to form a contact window 113 with exposed sidewalls, and form a Figure 18 The gate dielectric 112 shown covers the first surface 1A and one side of the polysilicon source silicon carbide body 1 .

[0101] After completion, refer to Figure 19 , the source region 13, the surface of the shielding region 12 and the sidewall of the contact window 113 can be exposed by etching; after the etching is completed, refer to Figure 20 , forming a source metal layer 16 that establishes ohmic contact with the shielding region 12 and the source region 13; finally, forming a drain metal layer 18 on the back side of the substrate to form a Figure 6 The semiconductor device shown in FIG. This process accurately constructs the semi-enclosed shield region 12A, differentiated source region 13 depths, and an optimized contact system, achieving simultaneous electric field control and electrical performance improvement.

[0102] In the above embodiments, the description of each embodiment has its own emphasis. For parts not described in detail in a particular embodiment, please refer to the relevant description of other embodiments. The technical features of the above embodiments can be combined in any way. To keep the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0103] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention claimed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not claimed in this disclosure.

[0104] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A semiconductor device, characterized in that: include: Silicon carbide body; A plurality of gate trenches are formed on the first surface of the silicon carbide body; a body region constituting a portion of a sidewall of at least one of the gate trenches; a source region, constituting a portion of a sidewall of at least one of the gate trenches and located between the body region and the first surface; a shielding region extending from the first surface to the silicon carbide body and located on both sides of the gate trench, the shielding region comprising: a semi-enclosing shielding region, located between two adjacent gate trenches among the plurality of gate trenches, constituting a sidewall and a portion of a bottom of one of the two gate trenches, and covering a side of the source region located between the two gate trenches away from the body region; Wherein, a side of the source region located between the two gate trenches and away from the semi-enclosed shielding region is partially exposed to the other gate trench of the two gate trenches.

2. The semiconductor device according to claim 1, wherein A side of the source region on both sides of the other gate trench of the two gate trenches away from the body region is covered by the shielding region.

3. The semiconductor device according to claim 1, wherein The gate trench includes a first trench, a second trench and an intermediate trench, wherein the intermediate trench is located between the first trench and the second trench; wherein the semi-enclosed shielding area is provided between the first trench and the middle trench, and between the second trench and the middle trench; The gate structure in the middle trench partially fills the middle trench to partially expose the source region between the two gate trenches.

4. The semiconductor device according to claim 3, wherein The distance between the body region corresponding to the middle trench and the first surface is greater than the distance between the body regions corresponding to the first trench and the second trench and the first surface.

5. The semiconductor device according to claim 3, wherein There are a plurality of intermediate trenches, and a shielding region between two adjacent intermediate trenches penetrates the source region and the body region and is spaced apart from the sidewalls and the bottom of the intermediate trenches. The semiconductor device according to claim 1 , wherein: The semiconductor device further includes: The source metal layer forms an ohmic contact with the shielding region and the source region.

7. The semiconductor device according to claim 1, wherein The semiconductor device further includes: A buffer layer having the same conductivity type as the silicon carbide body and a greater doping concentration than the silicon carbide body, wherein the buffer layer is disposed on a side of the silicon carbide body away from the first surface.

8. A method for manufacturing a semiconductor device, characterized in that: include: forming a plurality of gate trenches opened on the first surface of the silicon carbide body; forming a body region and a source region constituting a portion of a sidewall of the gate trench, wherein the source region is located between the body region and the first surface; forming a shielding region extending from the first surface into the silicon carbide body on both sides of the gate trench, the shielding region including a semi-enclosed shielding region between two adjacent gate trenches among the plurality of gate trenches; The semi-enclosed shielding region constitutes a sidewall and a portion of a bottom of one of the two gate trenches, and completely covers a side of the source region located between the two gate trenches away from the body region; A side of the source region located between the two gate trenches and away from the semi-enclosing shielding region is partially exposed to the other gate trench of the two gate trenches.

9. The method according to claim 8, characterized in that A side of the source region on both sides of the other gate trench of the two gate trenches away from the body region is covered by the shielding region.

10. The method according to claim 8, characterized in that The gate trench includes a first trench, a second trench and an intermediate trench; The forming of a plurality of gate trenches extending from a first surface of the silicon carbide body into the silicon carbide body comprises: constructing a mask plate, wherein the mask plate exposes the first surface at intervals; Etching the silicon carbide body from the area of ​​the first surface exposed by the mask plate to form the first trench, the second trench, and the middle trench, wherein the middle trench is located between the first trench and the second trench; wherein the semi-enclosed shielding area is provided between the first trench and the middle trench, and between the second trench and the middle trench; The gate structure in the middle trench partially fills the middle trench to partially expose the source region between the two gate trenches.

11. The method according to claim 10, characterized in that The forming of the body region and the source region respectively contacting the sidewalls of the gate trench comprises: When forming the body region and the source region, the distance between the body region corresponding to the middle trench and the first surface is greater than the distance between the body regions corresponding to the first trench and the second trench and the first surface.

12. The method according to claim 10, characterized in that There are multiple intermediate trenches, and the shielding regions formed on both sides of the gate trench and extending from the first surface into the silicon carbide body include: A shielding region penetrating the source region and the body region is formed between two adjacent middle trenches, and the shielding region is spaced apart from sidewalls and a bottom of the middle trench.

13. The method according to claim 8, characterized in that The method further comprises: A source metal layer is formed, wherein the source metal layer forms an ohmic contact with the shielding region and the source region.

14. The method according to claim 8, characterized in that A buffer layer having the same conductivity type as the silicon carbide body and a doping concentration greater than that of the silicon carbide body is formed in the silicon carbide body. The buffer layer is arranged on a side of the silicon carbide body away from the first surface.

Images