A low UVID back contact battery and its preparation method

Abstract

The present invention belongs to the technical field of back-contact batteries, and specifically relates to a low-UVID back-contact battery and a preparation method thereof, comprising: S2, sequentially forming a first semiconductor layer and a mask layer on the back of a silicon wafer; S3, forming a second semiconductor opening region; S4, texturing and cleaning; S5, using a remote plasma source to perform phosphine treatment on the front of the silicon wafer in a remote plasma device to dope the surface of the silicon wafer to form a shallow doped region, wherein the doping depth of the shallow doped region is 0.01-0.5µm; S6, then using a remote plasma device to first perform low-oxygen oxidation and then perform high-oxygen oxidation, thereby forming an oxygen-rich phosphorus-doped region in the shallow doped region on the surface of the silicon wafer; the oxygen content in the remote plasma source used for the low-oxygen oxidation is lower than the oxygen content in the remote plasma source used for the high-oxygen oxidation. The present invention can improve the attenuation performance of UVID and enhance the battery stability while taking into account the improvement of battery conversion efficiency.

Description

Technical Field

[0001] The present invention belongs to the technical field of back contact batteries, and in particular relates to a low UVID back contact battery and a preparation method thereof. Background Art

[0002] At present, the process flow of back contact battery equipment with low cost is generally as follows: S101, providing a double-sided polished silicon wafer; S102, coating the first semiconductor layer and the first mask layer on the back of the silicon wafer in sequence; S103, laser or etching an opening on the back of the silicon wafer, removing the first mask layer and part of the first semiconductor layer, and forming a second semiconductor opening area; S104, texturing and cleaning the silicon wafer, and removing the first semiconductor layer in the second semiconductor opening area; S105, forming a third semiconductor layer on the front side, the third semiconductor layer including a front passivation layer and an anti-reflection layer, and the front passivation layer and the anti-reflection layer are formed by PECVD or Hot-wire method. S106, removing the back-side coating, and cleaning to further purify the second semiconductor opening area; S107, forming a second semiconductor layer on the back of the silicon wafer; S108, laser or etching openings on the back of the silicon wafer to form first semiconductor opening areas alternately arranged with the second semiconductor opening areas; S109, depositing a conductive film layer on the back of the silicon wafer; S110, etching isolation grooves on the conductive film layer in the corresponding areas between the first semiconductor opening area and the second semiconductor opening area by laser or etching; S111, forming metal electrodes outside the corresponding areas of the first semiconductor opening area and the second semiconductor opening area on the silicon wafer.

[0003] However, in the above-mentioned post-texturing preparation process of the existing back-contact battery, the passivation layer and the anti-reflection layer of the third semiconductor layer are deposited on the front side in S105. If plate-type PECVD equipment is used for deposition, the cost is relatively high; if tube-type PECVD equipment is used, the deposited film layer will have certain UVID attenuation problems, which need to be overcome.

[0004] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or public known technology. Summary of the Invention

[0005] The purpose of the present invention is to overcome the defects of the prior art in the existing back contact post-texturing process using tubular PECVD to deposit the front passivation layer and anti-reflection layer, such as large UVID attenuation and poor battery stability, and to provide a low-UVID back contact battery and a preparation method thereof, which can improve the UVID attenuation performance and enhance the battery stability while taking into account the improvement of battery conversion efficiency.

[0006] In order to achieve the above objectives, in a first aspect, the present invention provides a method for preparing a low UVID back contact cell, comprising the following steps:

[0007] S1, provide double-sided polished silicon wafers;

[0008] S2. forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer;

[0009] S3, performing a first etching opening on the back surface obtained in S2 to form a second semiconductor opening region;

[0010] S4, texturing and cleaning, forming a texture surface on the front side of the silicon wafer and the second semiconductor opening area, and then completely removing the mask layer or retaining a portion of the mask layer;

[0011] S5. Using a remote plasma source, perform phosphine treatment on the front side of the silicon wafer in a remote plasma device to form a shallow doping region on the surface of the silicon wafer. The doping depth of the shallow doping region is 0.01-0.5µm.

[0012] S6. Then, a remote plasma device is used to perform oxygen oxidation, wherein the oxygen oxidation includes first performing low-oxygen oxidation and then performing high-oxygen oxidation, thereby forming an oxygen-rich phosphorus-doped region in a shallowly doped region on the surface of the silicon wafer; the oxygen content in the remote plasma source used for the low-oxygen oxidation is lower than the oxygen content in the remote plasma source used for the high-oxygen oxidation;

[0013] S7, forming a passivation layer and an anti-reflection layer in sequence on the front surface, then removing the back surface coating and cleaning the second semiconductor opening area;

[0014] S8. Depositing a second semiconductor layer on the back surface obtained in S7.

[0015] In some preferred embodiments of the present invention, the doping concentration of the shallow doping region is 5×10 17 cm -3 -6×10 18 cm -3 .

[0016] In some preferred embodiments of the present invention, the conditions for the phosphine treatment in S5 include: the power of the ionization process is 50-1000 W, and the gas pressure of the ionization process is 200-1500 mtorr.

[0017] In some preferred embodiments of the present invention, the plasma density of the ionized S5 phosphine treatment process is controlled at 10 9 cm -3 -10 12 cm -3 .

[0018] In some preferred embodiments of the present invention, the processing conditions of the process chamber corresponding to the silicon wafer during the S5 phosphine treatment process include: a processing temperature of 250-500° C., and a processing time t1 of 30-250 s.

[0019] In some preferred embodiments of the present invention, the remote plasma source used in the phosphine treatment process in S5 comprises a mixed gas containing phosphine and hydrogen, the volume content of phosphine in the mixed gas is 2%-8%, and the flow rate of the mixed gas is 0.5-5L.

[0020] In some preferred embodiments of the present invention, in S6, the volume content of oxygen in the remote plasma source used for low-oxygen oxidation is 3%-10%, and the volume content of oxygen in the remote plasma source used for high-oxygen oxidation is 10%-50%.

[0021] In some preferred embodiments of the present invention, in S6, the remote plasma source used in the low-oxygen oxidation and the high-oxygen oxidation respectively contains an inert gas in addition to oxygen.

[0022] In some preferred embodiments of the present invention, in S6, the plasma density of the ionization in the hypoxic oxidation is controlled at 10 9 cm -3 -10 10 cm -3 The plasma density of ionization in high oxygen oxidation is controlled at 10 10 cm -3 -10 11 cm -3 .

[0023] In some preferred embodiments of the present invention, in S6, the conditions for low oxygen oxidation and high oxygen oxidation independently include: the gas flow rate is 0.5-5 L, the power of the ionization process is 50-1000 W, and the gas pressure is 200-1000 mtorr.

[0024] In some preferred embodiments of the present invention, in S6, the processing conditions of the process chamber corresponding to the silicon wafer in the low-oxygen oxidation process include: a processing temperature of 250-450° C., and an oxidation time t2 of 30-100 s.

[0025] In some preferred embodiments of the present invention, in S6, the processing conditions of the process chamber corresponding to the silicon wafer during the high oxygen oxidation process include: a processing temperature of 250-450° C., and an oxidation time t3 of 50-150 s.

[0026] In some preferred embodiments of the present invention, the phosphine treatment time t1, the silicon wafer oxidation time t2 in low-oxygen oxidation, and the silicon wafer oxidation time t3 in high-oxygen oxidation satisfy: t1=at2+bt3, where the coefficient a is between 1.5-3.5 and the coefficient b is between 0.5-2.0.

[0027] In some preferred embodiments of the present invention, the passivation layer is at least one of amorphous silicon, oxygen-doped amorphous silicon, phosphorus-doped amorphous silicon, silicon oxide and aluminum oxide film, and the anti-reflection layer is one of silicon nitride, silicon oxynitride, carbon-doped silicon nitride, silicon oxide and carbon-doped silicon oxide.

[0028] In some preferred embodiments of the present invention, the first semiconductor layer includes a first tunneling oxide layer and a first doped polysilicon layer, and the second semiconductor layer is a stack selected from an intrinsic silicon layer and a second doped silicon layer or a stack of a second tunneling oxide layer and a second doped polysilicon layer.

[0029] In some preferred embodiments of the present invention, the preparation method further comprises:

[0030] S9, performing a second etching opening on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region spaced apart from the second semiconductor opening region;

[0031] S10, depositing a conductive film layer on the back surface obtained in S9;

[0032] S11, performing a third etching opening on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench;

[0033] S12 , forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

[0034] In a second aspect, the present invention provides a low-UVID back-contact battery, which is prepared by the preparation method of the low-UVID back-contact battery described in the first aspect.

[0035] Beneficial effects:

[0036] The present invention adopts the above-mentioned technical scheme, especially in the post-texturing method, and adopts S5 remote plasma phosphine treatment after texturing cleaning to form a suitably thin shallow doping area on the surface of the silicon wafer. By treating the surface with phosphine, the interface damage is reduced while the hydrogen atoms are promoted to be more evenly distributed in the silicon network. The stability of this hydrogen distribution reduces the generation of ultraviolet-induced hydrogen migration and recombination defects, thereby prolonging the photoelectric stability of the film; cooperates with specific S6 oxygen oxidation to improve the interface passivation level, and the two oxygen oxidations form oxygen-rich phosphorus-doped areas, which is beneficial to repair the defects that may be caused by the phosphine treatment, effectively reduces the dangling bond density on the silicon wafer surface, and inhibits the impact of ultraviolet-excited high-energy electrons on interface defects, thereby reducing the formation of carrier recombination centers, which is beneficial to the attenuation of UVID; then the passivation layer and anti-reflection layer are deposited in S7 to further improve the passivation effect. At the same time, the wrap-around plating formed on the back side by the S5-S6 process is removed by S7 cleaning; thereby, while taking into account the improvement of battery conversion efficiency, the attenuation performance of UVID is improved and the battery stability is improved. The doping depth of the shallow doped region of the present invention should not be too large, otherwise the density of defect states will be too high, and even high oxidation will make it difficult to repair the defects, which will greatly reduce the passivation effect.

[0037] Among them, the present invention S6 specifically uses two specific oxygen oxidations with different oxygen contents. Compared with single oxygen concentration oxidation, it can greatly improve the uniformity of oxidation, which is beneficial to improving battery passivation and thus battery efficiency. At the same time, it can further effectively repair defects that may be caused by phosphine treatment, effectively reduce the dangling bond density on the silicon wafer surface, and inhibit the impact of high-energy electrons excited by ultraviolet light on interface defects, thereby reducing the formation of carrier recombination centers and further facilitating UVID attenuation. DETAILED DESCRIPTION

[0038] In the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0039] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0040] The endpoints of the ranges and any values ​​disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoints of each range, the endpoints of each range and individual point values, and the individual point values ​​can be combined to form one or more new numerical ranges, and these numerical ranges should be considered to be specifically disclosed herein. The terms "optional" and "optional" both mean that a range may or may not be included (or may or may not be present).

[0041] In the present invention, the area close to the silicon wafer is considered as the inside, and the area far from the silicon wafer is considered as the outside.

[0042] In a first aspect, the present invention provides a method for preparing a low UVID back contact cell, comprising the following steps:

[0043] S1, provide double-sided polished silicon wafers;

[0044] S2. forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer;

[0045] S3, performing a first etching opening on the back surface obtained in S2 to form a second semiconductor opening region;

[0046] S4, texturing and cleaning, forming a texture surface on the front side of the silicon wafer and the second semiconductor opening area, and then completely removing the mask layer or retaining a portion of the mask layer;

[0047] S5. Using a remote plasma source, perform phosphine treatment on the front side of the silicon wafer in a remote plasma device to form a shallow doping region on the surface of the silicon wafer. The doping depth of the shallow doping region is 0.01-0.5µm.

[0048] S6. Then, a remote plasma device is used to perform oxygen oxidation, wherein the oxygen oxidation includes first performing low-oxygen oxidation and then performing high-oxygen oxidation, thereby forming an oxygen-rich phosphorus-doped region in a shallowly doped region on the surface of the silicon wafer; the oxygen content in the remote plasma source used for the low-oxygen oxidation is lower than the oxygen content in the remote plasma source used for the high-oxygen oxidation;

[0049] S7, forming a passivation layer and an anti-reflection layer in sequence on the front surface, then removing the back surface coating and cleaning the second semiconductor opening area;

[0050] S8. Depositing a second semiconductor layer on the back surface obtained in S7.

[0051] The conditions for the texturing cleaning described in S4 of the present invention can be carried out with reference to the prior art. For example, the texturing solution used is a mixture of alkali (such as potassium hydroxide or sodium hydroxide), a texturing additive and water, wherein the mass percentage of the alkali is 1%-5%, and the mass percentage of the texturing additive is 0.5%-1%. Furthermore, the texturing conditions may include: a texturing time of 8-30 minutes, and a texturing temperature of 75°C-85°C. The texturing additive can be obtained commercially. The final cleaning conditions in the texturing cleaning can be adjusted according to whether it is necessary to remove the mask layer. For example, when it is necessary to remove the mask layer, the final cleaning conditions include: the cleaning solution used for the final cleaning is an acid solution such as HF, the mass percentage of HF in the HF acid solution is 0.5%-5%, the mass percentage of deionized water contained is 95%-99.5%, the processing temperature is 20°C-30°C, and the removal time is 60-300s.

[0052] The remote plasma equipment described in this invention is an existing device. Its operating principle is as follows: a reactive gas is introduced into the remote plasma source chamber, where radio frequency energy is applied to the reactive gas, ionizing the gas molecules to form a plasma (i.e., the remote plasma source). The plasma is then transferred from the generation chamber to the main process chamber (i.e., the process chamber where the silicon wafer is located) via a gas baffle. This process extends the lifespan of the active species and reduces energy loss. During the transfer process, the gas baffle separates the high-energy ions, retaining only neutral free radicals and low-energy electrons that enter the processing chamber, thus preventing physical damage to the silicon wafer surface.

[0053] The doping depth of the shallow doped region is 0.01-0.5µm; for example, it can be 0.01µm, 0.02µm, 0.03µm, 0.04µm, 0.05µm, 0.06µm, 0.07µm, 0.08µm, 0.09µm, 0.10µm, 0.11µm, 0.15µm, 0.18µm, 0.20µm, 0.22µm, 0.25µm, 0.27µm, 0.30µm, 0.33µm, 0.35µm, 0.38µm, 0.40µm, 0.42µm, 0.45µm, 0.48µm, 0.50µm and the range between any two point values, and in some embodiments, it is preferably 0.06-0.5µm.

[0054] In some preferred embodiments of the present invention, the doping concentration of the shallow doping region is 5×10 17 cm -3 -6×10 18 cm -3 , more preferably 5×10 17 cm -3 -5×10 18 cm -3The present invention adopts a shallow doping region with a suitable doping depth, which is more conducive to optimizing the UVID attenuation effect and taking into account the subsequent passivation.

[0055] In some preferred embodiments of the present invention, the phosphine treatment conditions in S5 include: an ionization power of 50-1000 W, preferably 50-900 W, and a gas pressure of 200-1500 mtorr, preferably 200-1100 mtorr. The use of appropriate ionization power and gas pressure during the ionization process of the present invention helps ensure a stable plasma density and degree of ionization, ensuring a sufficiently high active species density, while effectively avoiding damage to the silicon wafer surface and further promoting passivation of shallowly doped regions.

[0056] In some preferred embodiments of the present invention, the plasma density of the ionized S5 phosphine treatment process is controlled at 10 9 cm -3 -10 12 cm -3 The present invention adopts a plasma density suitable for ionization to carry out phosphine treatment, which is more conducive to sufficient doping of phosphorus atoms on the surface of the silicon wafer.

[0057] In some preferred embodiments of the present invention, the S5 phosphine treatment process conditions in the process chamber corresponding to the silicon wafer include a treatment temperature of 250-500°C and a treatment time t1 of 30-250 seconds. The phosphine treatment of the present invention utilizes an appropriate temperature and treatment time to achieve both sufficient phosphorus doping and subsequent passivation repair.

[0058] In some preferred embodiments of the present invention, the remote plasma source used in the phosphine treatment process in S5 comprises a mixed gas containing phosphine and hydrogen. Further preferably, the volume content of phosphine in the mixed gas is 2%-8%, and / or the flow rate of the mixed gas is 0.5-5 L. The present invention employs an appropriate phosphine content and mixed gas to more effectively balance the uniformity and doping effect of the phosphorus treatment.

[0059] Preferably, in the present invention, the volume content of oxygen in the remote plasma source used for S6 oxygen oxidation is 5%-50%.

[0060] In some preferred embodiments of the present invention, in S6, the volume content of oxygen in the remote plasma source used for low-oxygen oxidation is 3%-10%, more preferably 5%-10%, and the volume content of oxygen in the remote plasma source used for high-oxygen oxidation is 10%-50%, more preferably 10%-34%. Using this preferred and appropriate oxygen content scheme is more conducive to improving the passivation effect of the silicon wafer surface.

[0061] In some preferred embodiments of the present invention, in S6, the remote plasma source used in the low-oxygen oxidation and high-oxygen oxidation respectively includes an inert gas in addition to oxygen, such as argon, helium, etc.

[0062] In some preferred embodiments of the present invention, in S6, the plasma density of the ionization in the hypoxic oxidation is controlled at 10 9 cm -3 -10 10 cm -3 The plasma density of ionization in high oxygen oxidation is controlled at 10 10 cm -3 -10 11 cm -3 Using different ionized plasma densities in different oxygen oxidation processes is more conducive to improving the uniformity of oxidation.

[0063] In some preferred embodiments of the present invention, in S6, the conditions for low oxygen oxidation and high oxygen oxidation independently include: the gas flow rate is 0.5-5 L, the power of the ionization process is 50-1000 W, and the gas pressure is 200-1000 mtorr.

[0064] In some preferred embodiments of the present invention, in S6, the processing conditions of the process chamber corresponding to the silicon wafer in the low-oxygen oxidation process include: a processing temperature of 250-450° C., and an oxidation time t2 of 30-100 s.

[0065] In some preferred embodiments of the present invention, in S6, the processing conditions of the process chamber corresponding to the silicon wafer during the high oxygen oxidation process include: a processing temperature of 250-450° C., and an oxidation time t3 of 50-150 s.

[0066] In some preferred embodiments of the present invention, the phosphine treatment time t1, the silicon wafer oxidation time t3 during low-oxygen oxidation, and the silicon wafer oxidation time t3 during high-oxygen oxidation satisfy the following equation: t1 = at2 + bt3, where coefficient a is between 1.5 and 3.5, and coefficient b is between 0.5 and 2.0, preferably between 0.5 and 1.5. This preferred embodiment of the present invention further reduces UVID attenuation while maintaining silicon wafer passivation.

[0067] In some preferred embodiments of the present invention, the passivation layer is at least one of amorphous silicon, oxygen-doped amorphous silicon, phosphorus-doped amorphous silicon, silicon oxide and aluminum oxide film layers.

[0068] In the present invention, the anti-reflection layer is preferably made of one of silicon nitride, silicon oxynitride, carbon-doped silicon nitride, silicon oxide, and carbon-doped silicon oxide.

[0069] In the present invention, the thicknesses of the passivation layer and the anti-reflection layer can refer to the prior art respectively. For example, the thickness of the passivation layer is 5-15 nm, and the thickness of the anti-reflection layer is 50-150 nm.

[0070] In S7 of the present invention, the backside coating is removed and the second semiconductor opening region is cleaned using a conventional solution. For example, standard cleaning solution No. 1 (SC1), standard cleaning solution No. 2 (SC2), or HF solution can be used. The mass concentration of the HF solution is 0.1%-10%. Standard cleaning solution No. 1 is a mixture of NH4OH / H2O2 / H2O (ammonia / hydrogen peroxide / water) in a ratio of 1:1:5, and standard cleaning solution No. 2 is a mixture of HCl / H2O2 / H2O (hydrochloric acid / hydrogen peroxide / water) in a ratio of 1:1:6. Preferably, the cleaning conditions include: a processing temperature of 20°C-30°C and a cleaning time of 50-900s.

[0071] In some preferred embodiments of the present invention, the first semiconductor layer comprises a first tunneling oxide layer and a first doped polysilicon layer, and the second semiconductor layer is a stack of an intrinsic silicon layer and a second doped silicon layer, or a stack of a second tunneling oxide layer and a second doped polysilicon layer. In the present invention, the second doped silicon layer may be doped amorphous silicon or microcrystalline silicon. The intrinsic silicon layer is preferably an intrinsic amorphous silicon layer (e.g., an intrinsic hydrogenated amorphous silicon layer). One of the first doped polysilicon layer and the second doped silicon layer or the second doped polysilicon layer is n-type and the other is p-type.

[0072] Preferably, the deposition temperature of the second semiconductor layer is 150-250° C. The second semiconductor layer can be formed, for example, by plate-type CVD.

[0073] Further preferably, the first semiconductor layer comprises a first tunneling oxide layer and a first doped polysilicon layer, and the second semiconductor layer is a stack of an intrinsic silicon layer and a second doped silicon layer. The present invention utilizes a combined passivation structure, combined with the fabrication method of the present invention, to further enhance the passivation effect on both the front and back surfaces, thereby further improving the cell conversion efficiency.

[0074] The thicknesses and corresponding doping concentrations of the first tunneling oxide layer, the first doped polysilicon layer, the intrinsic silicon layer, and the second doped silicon layer of the present invention can refer to the ranges of the prior art and can all be used in the present invention. For example, the thickness of the first tunneling oxide layer is 1-2 nm, the thickness of the first doped polysilicon layer is 80-150 nm, and the effective doping concentration is greater than 5e18 cm -3 The thickness of the intrinsic silicon layer is 3-10nm; the thickness of the second doped silicon layer is 5-15nm, and the effective doping concentration is 2e18cm -3 -3e20cm -3 .

[0075] The type and thickness of the mask layer in the present invention can refer to the range of the prior art and can be used in the present invention. Exemplarily, the mask layer is at least one of silicon nitride, silicon oxide, silicon oxynitride or nitrogen-containing polysilicon, and the thickness of the mask layer is 50-100 nm.

[0076] In some preferred embodiments of the present invention, the preparation method further comprises:

[0077] S9, performing a second etching opening on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region spaced apart from the second semiconductor opening region;

[0078] S10, depositing a conductive film layer on the back surface obtained in S9;

[0079] S11, performing a third etching opening on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench;

[0080] S12 , forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

[0081] In a second aspect, the present invention provides a low-UVID back-contact battery, which is produced by the method for producing a low-UVID back-contact battery described in the first aspect. The back-contact battery of the present invention can improve UVID attenuation performance and enhance battery stability while simultaneously improving battery conversion efficiency.

[0082] The embodiments of the present invention are described in detail below, which are exemplary and only used to explain the present invention, and are not to be construed as limiting the present invention.

[0083] Example 1

[0084] A low UVID back contact cell is prepared by the following preparation method:

[0085] S1, double-sided polishing of silicon wafer;

[0086] S2. Forming a first semiconductor layer and a mask layer on the back side of the silicon wafer:

[0087] The first semiconductor layer includes a tunneling silicon oxide layer and an N-type doped polysilicon layer. The mask layer is silicon nitride. The thickness of the tunneling silicon oxide layer is 1.5 nm, the thickness of the N-type doped polysilicon layer is 120 nm, and the effective doping concentration is 3e20 cm -3 , the mask layer thickness is 80nm.

[0088] S3. Performing a first etching operation on the first semiconductor layer and its corresponding mask layer on the back side of the silicon wafer to form second semiconductor opening regions arranged at intervals.

[0089] S4, texturing and cleaning the second semiconductor opening areas on the front and back sides of the silicon wafer:

[0090] The texturing solution is a mixture of potassium hydroxide, a texturing additive, and water, with the mass percentage of potassium hydroxide being 1% and the mass percentage of the texturing additive being 0.5%. The texturing time is 20 minutes and the texturing temperature is 80°C.

[0091] During the front texturing process, the mask layer on the back of the silicon wafer is also removed by the final cleaning solution. The solution used to remove the mask layer is HF acid solution, with HF mass percentage of 1% and deionized water mass percentage as the balance. The processing temperature is 25℃ and the removal time is 200s.

[0092] S5. Perform phosphine treatment on the front side of the silicon wafer to form a lightly doped region on the surface of the silicon wafer.

[0093] The phosphine treatment is carried out using a remote plasma device. During the ionization process, a mixture of phosphine (volume concentration is 2%) and hydrogen is introduced into the plasma generation chamber. The gas flow rate is 2 L, the power of the ionization process is 500 W, the gas pressure is 900 mtorr, and the ionized plasma density is controlled at 8.5×10 10 cm -3 The plasma generated in the generation chamber is transferred to the main process chamber where the silicon wafer is located through a gas baffle. The processing temperature of the main process chamber is 300°C, and the processing time t1 is 205s. The doping depth of the shallow doping region is 0.2µm, and the doping concentration is 9.6×10 17 cm -3 .

[0094] S6, oxygen oxidation:

[0095] The surface of the silicon wafer after the phosphine treatment is subjected to oxygen oxidation. The oxygen oxidation is also performed using a remote plasma device and is carried out in two steps:

[0096] First, during the ionization process of the remote plasma device, a hypoxic mixed gas of oxygen (volume concentration of 7%) and argon was introduced into the generation chamber. The gas flow rate was 3 L, the power of the ionization process was 600 W, the gas pressure was 700 mtorr, and the ionized plasma density was controlled at 3.6×10 9 cm -3 The oxygen plasma generated in the generation chamber is transferred to the main process chamber where the silicon wafer is located through the gas baffle. The processing temperature of the main process chamber is 350°C, and the oxidation time t2 is 50s.

[0097] Then, during the ionization process of the remote plasma device, a high-oxygen mixed gas of oxygen (volume concentration of 20%) and argon was introduced into the generation chamber. The gas flow rate was 3 L, the power of the ionization process was 800 W, the gas pressure was 700 mtorr, and the ionized plasma density was controlled at 5.3×10 10 cm -3 The oxygen plasma generated in the generation chamber is transferred to the main process chamber where the silicon wafer is located through the gas baffle. The processing temperature of the main process chamber is 350°C, and the oxidation time t3 is 80s, satisfying: t1=2.5t2+1.0t3.

[0098] S7. Forming a passivation layer and an anti-reflection layer on the front side of the silicon wafer, wherein the passivation layer is amorphous silicon and has a thickness of 12 nm, and the anti-reflection layer is silicon nitride and has a thickness of 100 nm; then removing the back side coating and cleaning the second semiconductor opening area;

[0099] S8, forming a second semiconductor layer on the back side of the silicon wafer;

[0100] The second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a P-type doped amorphous silicon layer deposited sequentially. The second semiconductor layer is formed by plate-type CVD at a deposition temperature of 200°C. The intrinsic hydrogenated amorphous silicon layer has a thickness of 6nm, the P-type doped amorphous silicon layer has a thickness of 10nm, and the effective doping concentration is 2e19cm -3 .

[0101] S9. Perform a second etching to open the second semiconductor layer on the back side of the silicon wafer to expose the first semiconductor layer, thereby forming a first semiconductor opening region spaced apart from the first semiconductor opening region.

[0102] S10, depositing a conductive film layer (ITO) on the back side of the silicon wafer;

[0103] S11. Perform a third etching opening on the conductive film layer on the back side of the silicon wafer to form an isolation trench on the conductive film layer between the first semiconductor opening region and the second semiconductor opening region. After etching, the resistance between the first semiconductor and the second semiconductor is greater than 1 kΩ.

[0104] S12, forming metal electrodes at corresponding areas of the first semiconductor opening region and the second semiconductor opening region on the back side of the silicon wafer.

[0105] Example 2

[0106] The process was carried out in accordance with Example 1, except that the doping depth of the shallow doped region in S5 was adjusted to 0.05 μm. To meet this condition, the process parameters of the phosphine treatment were adjusted as follows: the phosphine treatment time was shortened by 70%, the ionized plasma density was adjusted to 4.8×10 9 cm -3 .

[0107] Example 3

[0108] The process was carried out in accordance with Example 1, except that the conditions of the phosphine treatment in S5 were adjusted: the power of the ionization process was 1000 W, the doping depth of the shallowly doped region was 0.45 μm, and the doping concentration was 5.2×10 18 cm -3 ; The ionized plasma density is 7.2×10 11 cm -3 .

[0109] Example 4

[0110] The process was carried out in accordance with Example 1, except that the conditions of the phosphine treatment in S5 were adjusted: the gas pressure during the ionization process was 1200 mtorr, the doping depth of the shallowly doped region was 0.39 μm, and the doping concentration was 2.8×10 18 cm -3 ; The ionized plasma density is 3.5×10 11 cm -3 .

[0111] Example 5

[0112] The process was carried out in accordance with Example 1, except that the volume content of oxygen in the remote plasma source used for the hypoxic oxidation in S6 was adjusted to 3%, so that the plasma density of the ionization in the hypoxic oxidation was controlled at 1.2×10 9 cm -3 .

[0113] Example 6

[0114] The process was carried out in accordance with Example 1, except that the volume content of oxygen in the remote plasma source used in the high oxygen oxidation in S6 was adjusted to 35%, so that the plasma density of the ionization in the high oxygen oxidation was controlled at 8.5×10 10 cm -3 .

[0115] Example 7

[0116] The method is carried out in accordance with Example 1, except that the second semiconductor layer is adjusted to a stack of a second tunneling silicon oxide layer and a P-type second doped polysilicon layer. The thickness of the second tunneling silicon oxide layer is 1.5 nm, the thickness of the P-type second doped polysilicon layer is 80 nm, and the effective doping concentration is 8.9×10 18 cm -3 .

[0117] Comparative Example 1

[0118] The process is carried out in accordance with Example 1, except that the phosphine treatment and oxygen oxidation in S5-S6 are not performed, but S7 is directly performed after S4 to deposit the passivation layer and the anti-reflection layer.

[0119] Comparative Example 2

[0120] The same procedure was followed as in Example 1, except that the phosphine treatment of S5 was not performed.

[0121] Comparative Example 3

[0122] The same process as in Example 1 was carried out except that the oxygen oxidation of S6 was not carried out.

[0123] Comparative Example 4

[0124] The process was carried out with reference to Example 1, except that the oxygen oxidation of S6 was carried out using constant oxygen oxidation, i.e., the oxygen content was consistent, the oxygen content was the same as the conditions of high oxygen oxidation, and the continuous oxidation time was equal to the overall time of first performing low oxygen oxidation and then performing high oxygen oxidation in Example 1.

[0125] Comparative Example 5

[0126] The method is carried out in accordance with Example 1, except that the doping depth of the shallow doping region in S5 is adjusted to 0.8 μm and the doping concentration is adjusted to 6.5×10 18 cm -3 , corresponding to the modified phosphine treatment time t1 = 315s, the ionized plasma density is 1.9×10 12 cm -3 .

[0127] Test Case

[0128] The back-contact cells obtained from the above examples and comparative examples were subjected to performance testing, and the results are shown in Table 1. The performance indicators of each example and comparative example were converted using Example 1 as a reference benchmark. The data for Example 1 was normalized to a benchmark of 1.000, and the other examples were converted based on Example 1. For example, the UVID power attenuation ratio of Comparative Example 1 / UVID power attenuation ratio of Example 1 was 77.970. UVID refers to the light-induced attenuation phenomenon produced by a cell under ultraviolet irradiation. The testing method is to use an ultraviolet light box (wavelength range 280-400nm) for 2 hours of continuous irradiation and evaluate the power attenuation ratio of the cell before and after the cumulative irradiation to determine the light attenuation. The power attenuation ratio is calculated as: (power before irradiation - power after irradiation) / power before irradiation. The smaller the pre- and post-UVID power attenuation ratio, the stronger the UVID anti-attenuation capability and the higher the cell stability.

[0129] Table 1

[0130]

[0131] The above results show that, compared with the comparative example, the embodiment of the present invention can improve the UVID attenuation performance and enhance the battery stability while improving the short-circuit current, open-circuit voltage and battery conversion efficiency.

[0132] Furthermore, according to Example 1 and Examples 2-7, it can be seen that the preferred solution of the present invention is more conducive to improving the UVID attenuation performance and enhancing the battery stability while taking into account the improvement of battery conversion efficiency.

[0133] The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited thereto. Within the technical concept of the present invention, various simple variations of the technical solution of the present invention may be made, including combining the various technical features in any other appropriate manner. These simple variations and combinations should also be regarded as disclosed in the present invention and fall within the scope of protection of the present invention.

Claims

1. A method for preparing a low UVID back contact battery, characterized in that: The steps include: S1, provide double-sided polished silicon wafers; S2. forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer; S3, performing a first etching opening on the back surface obtained in S2 to form a second semiconductor opening region; S4, texturing and cleaning, forming a texture surface on the front side of the silicon wafer and the second semiconductor opening area, and then completely removing the mask layer or retaining a portion of the mask layer; S5. Using a remote plasma source, perform phosphine treatment on the front side of the silicon wafer in a remote plasma device to form a shallow doping region on the surface of the silicon wafer. The doping depth of the shallow doping region is 0.01-0.5µm. S6. Then, a remote plasma device is used to perform oxygen oxidation, wherein the oxygen oxidation includes first performing low-oxygen oxidation and then performing high-oxygen oxidation, thereby forming an oxygen-rich phosphorus-doped region in a shallowly doped region on the surface of the silicon wafer; the oxygen content in the remote plasma source used for the low-oxygen oxidation is lower than the oxygen content in the remote plasma source used for the high-oxygen oxidation; S7, forming a passivation layer and an anti-reflection layer in sequence on the front surface, then removing the back surface coating and cleaning the second semiconductor opening area; S8. Depositing a second semiconductor layer on the back surface obtained in S7.

2. The method for preparing a low UVID back contact battery according to claim 1, wherein: The doping concentration of the shallow doping region is 5×10 17 cm -3 -6×10 18 cm -3 .

3. The method for preparing a low UVID back contact battery according to claim 1, wherein: The conditions for the phosphine treatment in S5 include: the power of the ionization process is 50-1000 W, the gas pressure of the ionization process is 200-1500 mtorr; and / or, The plasma density of the ionized S5 phosphine treatment process was controlled at 10 9 cm -3 -10 12 cm -3 .

4. The method for preparing a low UVID back contact battery according to claim 1 or 3, characterized in that: During the S5 phosphine treatment process, the processing conditions of the process chamber where the silicon wafer is located include: a processing temperature of 250-500° C., and a processing time t1 of 30-250 s.

5. The method for preparing a low UVID back contact battery according to claim 1, wherein: The remote plasma source used in the phosphine treatment process in S5 includes a mixed gas containing phosphine and hydrogen, the volume content of phosphine in the mixed gas is 2%-8%, and the flow rate of the mixed gas is 0.5-5L.

6. The method for preparing a low UVID back contact battery according to claim 1, wherein: In S6, the volume content of oxygen in the remote plasma source used for low-oxygen oxidation is 3%-10%, and the volume content of oxygen in the remote plasma source used for high-oxygen oxidation is 10%-50%; and / or, In S6, the remote plasma sources used in the low-oxygen oxidation and high-oxygen oxidation respectively contain an inert gas in addition to oxygen.

7. The method for preparing a low UVID back contact battery according to claim 1, wherein: In S6, the plasma density of ionization in hypoxic oxidation is controlled at 10 9 cm -3 -10 10 cm -3 The plasma density of ionization in high oxygen oxidation is controlled at 10 10 cm -3 -10 11 cm -3 ; and / or, In S6, the conditions for hypoxic oxidation and hyperoxic oxidation each independently include: The gas flow rate is 0.5-5L, the power of the ionization process is 50-1000W, and the gas pressure is 200-1000mtorr.

8. The method for preparing a low UVID back contact battery according to claim 1, wherein: In S6, the processing conditions of the process chamber corresponding to the silicon wafer in the low-oxygen oxidation process include: a processing temperature of 250-450° C., and an oxidation time t2 of 30-100 seconds; and / or, In S6 , the processing conditions of the process chamber corresponding to the silicon wafer during the high oxygen oxidation process include: a processing temperature of 250-450° C., and an oxidation time t3 of 50-150 seconds.

9. The method for preparing a low UVID back contact battery according to claim 1, wherein: The phosphine treatment time t1, the silicon wafer oxidation time t2 in the low oxygen oxidation, and the silicon wafer oxidation time t3 in the high oxygen oxidation satisfy: t1=at2+bt3, where the coefficient a is between 1.5-3.5 and the coefficient b is between 0.5-2.

0.

10. The method for preparing a low UVID back contact battery according to claim 1, wherein: The passivation layer is at least one of amorphous silicon, oxygen-doped amorphous silicon, phosphorus-doped amorphous silicon, silicon oxide and aluminum oxide film, and the anti-reflection layer is one of silicon nitride, silicon oxynitride, carbon-doped silicon nitride, silicon oxide and carbon-doped silicon oxide; And / or, the first semiconductor layer includes a first tunneling oxide layer and a first doped polysilicon layer, and the second semiconductor layer is a stack of an intrinsic silicon layer and a second doped silicon layer or a stack of a second tunneling oxide layer and a second doped polysilicon layer.

11. The method for preparing a low UVID back contact battery according to claim 1, wherein: The preparation method further comprises: S9, performing a second etching opening on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region spaced apart from the second semiconductor opening region; S10, depositing a conductive film layer on the back surface obtained in S9; S11, performing a third etching opening on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench; S12 , forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

12. A low UVID back contact battery, characterized in that The battery is prepared by the method for preparing a low-UVID back contact battery according to any one of claims 1 to 11.

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