Display device

Abstract

A display device may include: a display area on a substrate and including a plurality of light emitting elements and a plurality of transistors; the non-display area surrounds the display area; a first area in the display area and including a hole; and a second region between the first region and the display region and including a structure.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] Display devices are applied to various electronic devices such as TVs, mobile phones, laptop PCs, and tablet computers. For this reason, research on developing thinner, lighter, and lower-power-consuming display devices is continuously being conducted.

[0003] Examples of the display device may include a liquid crystal display device (LCD), a field emission display device (FED), an organic light emitting diode (OLED) display device, and the like. Summary of the Invention

[0004] In order to set a camera or the like in the display area, a hole should be provided. However, the hole formed in the display device may cause external moisture or oxygen to penetrate into the display area due to the occurrence of cracks.

[0005] Aspects of the present disclosure are directed to providing a display device capable of preventing cracks.

[0006] Additional features, advantages, and aspects will be set forth in the following description, and in part will become apparent from the description, or may be learned by practicing the inventive concepts provided herein. Other features, advantages, and aspects of the present disclosure may be realized and obtained by the structures specifically pointed out in the written description or structures derivable therefrom, the claims, and the accompanying drawings.

[0007] A display device according to an embodiment of the present disclosure may include: a display area, which is located on a substrate and includes a plurality of light-emitting elements and a plurality of transistors; a non-display area, which surrounds the display area; a first area, which is located in the display area and includes a hole; and a second area, which is located between the first area and the display area and includes a structure.

[0008] According to an embodiment of the present disclosure, since the barrier pattern is provided between the hole and the display area, penetration of external moisture or oxygen into the display area may be blocked or reduced.

[0009] According to an embodiment of the present disclosure, the crack propagation time may be delayed by increasing the length of the crack propagation path along which the crack propagates toward the display area.

[0010] According to the embodiment of the present disclosure, since the structure is provided between the hole and the display area, it is possible to prevent cracks caused by the hole from extending to the display area or to delay the crack extension time.

[0011] This prevents dark spot defects (where pixels don't emit light), reduced brightness, and vertical line defects. This allows for a display device that can be driven at low power, reducing power consumption. Furthermore, dark spot defects and vertical line defects can be prevented, enhancing the user's immersive screen experience and improving the reliability of the display device.

[0012] Other systems, methods, features, and advantages will be or will become apparent to one skilled in the art upon examination of the following figures and detailed description. All such additional systems, methods, features, and advantages are intended to be included within this description, be within the scope of the present disclosure, and be protected by the following claims. Nothing in this section should be construed as limiting these claims. Further aspects and advantages are discussed below in conjunction with aspects of the present disclosure.

[0013] It is to be understood that both the foregoing description and the following description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this disclosure, illustrate aspects and embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

[0015] Figure 1 A perspective view illustrating a display device according to an embodiment of the present disclosure is shown.

[0016] Figure 2 The present invention is shown in FIG. Figure 1 A cross-sectional view of one side of a display device.

[0017] Figure 3 is a plan view schematically showing a portion of a display device according to an embodiment of the present disclosure.

[0018] Figure 4 The embodiment according to the present disclosure is shown Figure 3 An enlarged plan view of the region 4 where the holes are provided.

[0019] Figure 5 The embodiment according to the present disclosure is shown Figure 4 A cross-sectional view taken along line II' in FIG.

[0020] Figure 6 The embodiment according to the present disclosure is shown Figure 4 A cross-sectional view taken along line II-II'.

[0021] Figure 7 The embodiment according to the present disclosure is shown Figure 6Magnified cross-sectional view of region 7 in FIG.

[0022] Figure 8 The embodiment according to the present disclosure is shown Figure 6 Another modified example of the structure in region 8 in .

[0023] Figure 9 The embodiment according to the present disclosure is shown Figure 6 Another modified example of the structure in region 9 in .

[0024] Figure 10 The embodiment according to the present disclosure is shown Figure 6 Another modified example of the structure in region 10 in .

[0025] Figure 11 The embodiment according to the present disclosure is shown Figure 4 A cross-sectional view taken along line II-II'.

[0026] Figure 12 The embodiment according to the present disclosure is shown Figure 11 An enlarged cross-sectional view of region 12 in FIG.

[0027] Figure 13 The embodiment according to the present disclosure is shown Figure 11 Another modified example of the structure in region 13 in .

[0028] Figure 14 The embodiment according to the present disclosure is shown Figure 11 Another modified example of the structure in region 14 in .

[0029] Figure 15 The embodiment according to the present disclosure is shown Figure 11 Another modified example of the structure in region 15 in .

[0030] Throughout the drawings and detailed description, unless otherwise specified, the same reference numerals should be understood to refer to the same elements, features, and structures. The sizes, lengths, and thicknesses of layers, regions, and elements and their descriptions may be exaggerated for clarity, illustration, and / or convenience. DETAILED DESCRIPTION

[0031] Reference will now be made in detail to embodiments of the present disclosure, examples of which may be illustrated in the accompanying drawings. In the following description, where a detailed description of a known method, function, structure, or configuration may unnecessarily obscure aspects of the present disclosure, such detailed description may be omitted for the sake of brevity. Furthermore, for the sake of brevity, repeated descriptions may be omitted. The described progression of processing steps and / or operations is a non-limiting example.

[0032] Except that the steps and / or operations must occur in a specific order, the order of the steps and / or operations is not limited to the order set forth herein and can be changed to occur in an order different from the order described herein. In one or more examples, two consecutive operations can be performed substantially simultaneously, or the two operations can be performed in a reverse order or a different order depending on the functions or operations involved.

[0033] Unless otherwise stated, similar reference numerals may all indicate similar elements, even if they are shown in different drawings. Unless otherwise stated, throughout the specification and all drawings, the same reference numerals may be used to indicate the same or substantially the same elements. In one or more aspects, the same elements (or elements with the same name) in different drawings may have the same or substantially the same functions and characteristics, unless otherwise stated. The names of the various elements used in the description below are selected for convenience only and may therefore be different from the names used in the actual product.

[0034] The advantages and features of the present disclosure and their implementation methods are illustrated by the embodiments described with reference to the accompanying drawings. However, the present disclosure may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are examples and are provided so that the present disclosure may be complete and comprehensive, to help those skilled in the art understand the inventive concept without limiting the scope of protection of the present disclosure.

[0035] The shapes, dimensions (e.g., size, length, width, height, thickness, position, radius, diameter, and area), proportions, ratios, angles, quantities, number of components, etc. disclosed herein (including the shapes, dimensions, proportions, ratios, angles, quantities, number of components, etc. shown in the drawings) are merely examples, and thus, the present disclosure is not limited to the details shown. However, it should be noted that the relative dimensions of the components shown in the drawings are part of this disclosure.

[0036] When the terms "including," "having," "comprising," "containing," "consisting of," "made of," "formed of," etc. are used for one or more elements (e.g., layers, films, regions, components, segments, members, parts, areas, parts, steps, operations, etc.), one or more other elements may be added unless terms such as "only" are used. The terms used in the present disclosure are only for describing example embodiments and are not intended to limit the scope of the present disclosure. Terms in the singular form may include plural forms unless the context clearly indicates otherwise.

[0037] The word "exemplary" is used to mean serving as an example or illustration. An embodiment is an example embodiment. An aspect is an example aspect. References to "embodiment," "example," "aspect," etc., with respect to one or more embodiments, should not be construed as preferred or advantageous over other embodiments. References to an embodiment, an example, an example embodiment, an aspect, etc., may refer to one or more embodiments, one or more examples, one or more example embodiments, one or more aspects, etc., unless otherwise indicated.

[0038] In one or more aspects, unless otherwise expressly stated, elements, features, or corresponding information (e.g., levels, ranges, dimensions, sizes, etc.) are interpreted as including errors or tolerances, even if no explicit description of such errors or tolerances is provided. Errors or tolerances may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). When interpreting numerical values, the values ​​are interpreted as including the error range unless otherwise expressly stated.

[0039] When describing a positional relationship, for example, when using "on...", "over...", "on top of...", "above...", "below...", "above...", "below...", "near...", "near...", "adjacent...", "next to...", "close to...", "on the side of...", etc. to describe the positional relationship between two parts (e.g., layers, films, regions, components, segments, etc.), one or more parts may be located between two other parts unless more restrictive terms such as "immediately", "directly", or "close to..." are used. For example, when a structure is described as being located "on", "top", "above", "top", "above", "below", "above", "below", "near", "near", "on the side" or "near", "adjacent", "close to" another structure, the description should be interpreted as including situations where the structures are in contact with each other and situations where one or more additional structures are arranged or interposed between them. In addition, the terms "front", "rear", "back", "left", "right", "top", "bottom", "down", "up", "up", "up", "down", "below", "column", "row", "vertical", "horizontal", etc. refer to any reference system.

[0040] Spatially relative terms such as “below,” “under,” “lower,” “on,” “above,” “upper,” etc. may be used to describe the relationships between various elements (e.g., layers, films, regions, components, segments, etc.) as shown in the accompanying drawings. Spatially relative terms are understood to be terms that include different orientations of elements in use or operation in addition to the orientations shown in the drawings. For example, if the elements shown in the drawings were turned over, elements described as “below” or “beneath” other elements would be oriented “above” the other elements. Thus, the term “below” is an example term that may include all orientations of “above” and “below.” Similarly, the exemplary terms “above” or “on” may include both an orientation of “above” and “below.”

[0041] When describing a temporal relationship, when the temporal sequence is described as "after", "subsequently", "next", "before", "in front of", "precedes", etc., discontinuities may be included so that one or more other events may occur between them, unless more restrictive terms such as "only", "immediately" or "directly" are used.

[0042] Terms such as "below," "lower," "above," "upper," etc. may be used herein to describe the relationship between elements as illustrated in the drawings. It will be understood that these terms are spatially relative and based on the orientation shown in the drawings.

[0043] It should be understood that although the terms "first", "second" etc. can be used in this article to describe various elements (for example, layer, film, region, assembly, section, member, component, region, position, part, step, operation, etc.), these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of this disclosure, the first element can represent the second element, and similarly, the second element can represent the first element. In addition, without departing from the scope of this disclosure, according to the convenience of those skilled in the art, the first element, the second element, etc. can be arbitrarily named. For the sake of clarity, the function or structure of these elements (for example, the first element, the second element, etc.) is not limited by the ordinal number or name in front of the element. In addition, the first element can include one or more first elements. Similarly, the second element, etc. can include one or more second elements, etc.

[0044] When describing elements of the present disclosure, terms such as "first," "second," "A," "B," "(a)," "(b)," etc. may be used. These terms are intended to distinguish the corresponding elements from other elements, but are not used to define the nature, basis, sequence, order, or quantity of the elements.

[0045] When an element (for example, a layer, a film, a region, a component, a segment, etc.) is “connected,” “coupled,” “attached,” “bonded,” etc. to another element, the element can not only be directly connected, coupled, attached, bonded, etc. to the other element, but also can be indirectly connected, coupled, attached, bonded, etc. to the other element with one or more intermediate elements disposed or interposed therebetween, unless otherwise specified.

[0046] When an element (for example, a layer, film, region, component, segment, etc.) is “in contact with,” “overlapped with,” etc., another element, the element may not only be directly in contact with, overlapped with, etc., but may also be indirectly in contact with, overlapped with, etc., the other element with one or more intermediate elements disposed or interposed therebetween, unless otherwise specified.

[0047] Phrases that state that an element (e.g., a layer, a film, a region, a component, a segment, etc.) is disposed “in,” “on,” or “connected,” “coupled,” etc. to another element may be understood to mean, for example, that at least a portion of the element is disposed “in,” “on,” or “connected,” “coupled,” etc. to at least a portion of the other element, or that the entire element is disposed “in,” “on,” or “connected,” etc. to the other element. Phrases that state that an element (e.g., a layer, a film, a region, a component, a segment, etc.) is “in contact with,” “overlaps,” etc. to another element may be understood to mean, for example, that at least a portion of the element is in contact with, overlaps, etc. to at least a portion of the other element, that the entire element is in contact with, overlaps, etc. to at least a portion of the other element, or that at least a portion of the element is in contact with, overlaps, etc. to the entire other element.

[0048] Terms such as "line" or "direction" should not be interpreted solely based on the geometric relationship of the respective lines or directions being parallel or perpendicular to each other, but may refer to lines or directions having a wider range of directionality within the range in which the components of the present disclosure can function. For example, terms such as "first direction," "second direction," and the like, which are directions parallel to or perpendicular to the "x-axis," "y-axis," or "z-axis," should not be interpreted solely based on the geometric relationship of the respective directions being parallel or perpendicular to each other, but may refer to directions having a wider range of directionality within the range in which the components of the present disclosure can function.

[0049] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, each of the phrases "at least one of the first, second, or third item" and "at least one of the first, second, and third items" can mean (i) a combination of two or more of the listed items from the first, second, and third items, or (ii) only one of the first, second, and third items.

[0050] The expression "a first element, a second element, and / or" a third element should be understood to mean one of the first element, the second element, and the third element, or any and all combinations of the first element, the second element, and the third element. For example, A, B, and / or C can mean: only A; only B; only C; any one of A, B, and C (e.g., A, B, or C); some combination of A, B, and C (e.g., A and B; A and C; or B and C); or all of A, B, and C. In addition, the expression "A / B" can be understood to mean A and / or B. For example, the expression "A / B" can mean: only A; only B; A or B; or A and B.

[0051] In one or more aspects, the terms "between" and "among" may be used interchangeably for convenience only, unless otherwise indicated. For example, the expression "between a plurality of elements" may be understood as meaning among a plurality of elements. In another example, the expression "among a plurality of elements" may be understood as meaning between a plurality of elements. In one or more examples, the number of elements may be two. In one or more examples, the number of elements may be more than two. Furthermore, when an element (e.g., a layer, a film, a region, a component, a segment, etc.) is referred to as being "between" at least two elements, the element may be the only element between the at least two elements, or one or more intermediate elements may also be present.

[0052] In one or more aspects, the phrases "one another" and "mutually" may be used interchangeably for convenience only, unless otherwise indicated. For example, the expression "different from each other" may be understood to mean different from each other. In another example, the expression "different from each other" may be understood to mean different from each other. In one or more examples, the number of elements referred to in the foregoing expressions may be two. In one or more examples, the number of elements referred to in the foregoing expressions may be more than two.

[0053] In one or more aspects, the phrases "one or more of" and "one or more of" may be used interchangeably for convenience only, unless otherwise indicated.

[0054] The term "or" means "inclusive or," not "exclusive or." That is, unless otherwise specified or clear from the context, the statement "x uses a or b" means any of the natural inclusive permutations. For example, "a or b" means "a," "b," or "a and b." For example, "a, b, or c" means "a," "b," "c," "a and b," "b and c," "a and c," or "a, b, and c."

[0055] The features of the various embodiments of the present disclosure may be combined or joined with each other in part or in whole, may be technically associated with each other, and may interoperate, link, or drive together in various ways. The embodiments of the present disclosure may be implemented or executed independently of each other, or may be implemented or executed together under a mutual dependence or correlation relationship. In one or more aspects, the components of each device according to the various embodiments of the present disclosure may be operably combined and configured.

[0056] Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments belong. It should be further understood that, for example, terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and should not be interpreted in an idealized or overly formal sense unless otherwise explicitly defined herein.

[0057] In the following description, various exemplary aspects of the present disclosure are described in detail with reference to the accompanying drawings. With respect to the reference numerals of the elements of each drawing, the same elements may be shown in other drawings, and similar reference numerals may indicate similar elements, unless otherwise specified. The same or similar elements may be indicated by the same reference numerals even if they are shown in different drawings.

[0058] Furthermore, for ease of description, the proportions, dimensions, sizes, and thicknesses of each element shown in the drawings may be different from actual proportions, dimensions, sizes, and thicknesses. Therefore, aspects of the present disclosure are not limited to the proportions, dimensions, sizes, and thicknesses shown in the drawings.

[0059] Hereinafter, a display device according to an embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0060] Figure 1 A perspective view illustrating a display device according to an embodiment of the present disclosure is shown. Figure 2 The present invention is shown in FIG. Figure 1 A cross-sectional view of one side of a display device. Figure 3 1 is a plan view schematically showing a portion of a display device according to an embodiment of the present disclosure. All components of each display device according to all embodiments of the present disclosure may be operatively combined and configured.

[0061] refer to Figure 1 and Figure 3 The display device 10 according to an embodiment of the present disclosure may include a first substrate 110 and a second substrate 170 including a display area (or active area) AA and a non-display area (or non-active area) NAA located outside the display area AA.

[0062] The first substrate 110 may comprise transparent plastic or glass, but the embodiments of the present disclosure are not limited thereto. The second substrate 170 may comprise a plastic film, a glass substrate, or an encapsulation film of a transparent material, but the embodiments of the present disclosure are not limited thereto. In a plan view, the first substrate 110 or the second substrate 170 may have a rectangular shape having long sides in a first direction and short sides in a second direction. In another example, the first substrate 110 or the second substrate 170 may have a quadrilateral shape with each corner being rounded, but is not limited thereto. For example, the first direction may be the X-axis direction or the horizontal direction of the first substrate 110, and the second direction may be the Y-axis direction or the vertical direction of the first substrate 110. The second substrate 170 may be disposed on the first substrate 110. The second substrate 170 may cover the first substrate 110. The second substrate 170 may be a cover window, a window cover, or cover glass, but the embodiments of the present disclosure are not limited thereto.

[0063] Multiple pixels may be provided in the display area AA. Video or images may be displayed in the display area AA via the multiple pixels. Multiple drivers configured to drive the multiple pixels provided in the display area AA may be provided in the non-display area NAA. For example, the drivers may include, but are not limited to, a gate driver, a data driver, a touch driver, and a timing controller.

[0064] The display area AA may include a first area HA having a hole. In the drawings, the first area HA is shown as being disposed at a central portion of the display area AA, but is not limited thereto.

[0065] The first area HA may be an area where electronic components for adding various functions to the display device 10 are provided. Examples of electronic components may include a camera module configured to take photos or videos or various sensor devices configured to detect external objects. The sensor device may include at least one or more of a proximity sensor, a gesture sensor, a color sensor, a biometric sensor, and an infrared sensor, but the embodiments of the present disclosure are not limited thereto.

[0066] The display device may include a second area MA. The second area MA may be an area between the display area AA and the first area HA. ​​The second area MA may be an area adjacent to the first area HA. ​​The second area MA may be an area surrounding the first area HA and not provided with a light-emitting element. The first area HA may be an aperture area, but embodiments of the present disclosure are not limited thereto. The second area MA may be an aperture boundary area, but embodiments of the present disclosure are not limited thereto.

[0067] refer to Figure 2The display device 10 may include a structure in which a first substrate 110 and a second substrate 170 are combined (or attached). A transistor array portion (also referred to as a transistor array layer) 120, a light emitting array portion (also referred to as a light emitting array layer) 130, an encapsulation portion (also referred to as an encapsulation layer) 140, and a touch portion (also referred to as a touch layer) 150 may be disposed between the first substrate 110 and the second substrate 170. The first substrate 110 and the second substrate 170 may be combined (or attached) via a protective member 160.

[0068] The transistor array section 120 may be disposed on the first substrate 110. The transistor array section 120 may include one or more thin film transistors, one or more scan lines, and one or more data lines. Figure 5 A description is provided of the transistor array section 120 .

[0069] The light emitting array section 130 may be provided on the transistor array section 120. A light emitting element including a first electrode, a light emitting layer, and a second electrode may be provided in the light emitting array section 130. The light emitting layer may be an organic light emitting layer including an organic material, but the embodiments of the present disclosure are not limited thereto. By applying a driving current to the first electrode and the second electrode provided above and below the light emitting layer, the light emitting layer may emit light. This will be referred to below. Figure 5 A description of the light emitting array unit 130 is provided. The display device may be an OLED display device, but the embodiments of the present disclosure are not limited thereto. For example, the display device may be an inorganic light emitting display device, a quantum dot light emitting display device, a mini LED display device, or a micro LED display device.

[0070] The encapsulation unit 140 may be provided on the light emitting array unit 130. The light emitting layer includes an organic material and may be susceptible to oxygen and moisture. Therefore, the encapsulation unit 140 may prevent the penetration of oxygen or moisture by sealing the light emitting layer including the organic material. The encapsulation unit 140 may include an inorganic insulating layer or an organic insulating layer having a multi-layer structure, but the embodiments of the present disclosure are not limited thereto. Figure 5 A description of the packaging section 140 is provided.

[0071] The touch portion 150 may be provided on the packaging portion 140. The touch portion 150 may include one or more touch electrodes configured to detect a user's touch, a bridge electrode configured to electrically connect adjacent touch electrodes, and a protective layer provided on the touch electrodes, but the embodiments of the present disclosure are not limited thereto. Figure 5A description of the touch portion 150 is provided. The protective member 160 may be provided on the touch portion 150. The protective member 160 may cover the touch portion 150. The protective member 160 may be provided between the first substrate 110 and the second substrate 170. The protective member 160 may further include an adhesive member for enhancing adhesive force between the first substrate 110 and the second substrate 170.

[0072] refer to Figure 2 and Figure 3 One or more data lines DL and one or more scan lines SL may be provided in the display area AA of the first substrate 110. One or more data lines DL and one or more scan lines SL may be provided on the transistor array portion 120. Each of the one or more data lines DL may be provided to intersect each of the one or more scan lines SL. Pixels P may be formed by the data lines DL and / or the scan lines SL, and a plurality of pixels P may be provided in the display area AA. For example, the pixels P may be electrically connected to the scan lines SL and the data lines DL.

[0073] A scan line SL may extend in a first direction on the first substrate 110. Each of the plurality of scan lines SL may be spaced apart from one another in a second direction intersecting the first direction. A data line DL may extend in a second direction. Each of the plurality of data lines DL may be spaced apart from one another in the first direction intersecting the second direction. The first direction may be an X-axis direction or a horizontal direction of the first substrate 110, and the second direction may be a Y-axis direction or a vertical direction of the first substrate 110.

[0074] A plurality of pixels P may be arranged in a matrix (M×N, where M and N are natural numbers) on the display area AA of the first substrate 110, but the embodiments of the present disclosure are not limited thereto. A light-emitting element may be provided at each pixel P to emit red, green, or blue light, but the embodiments of the present disclosure are not limited thereto. In addition, the pixel may further include a sub-pixel that emits white light.

[0075] The non-display area NAA may be disposed near the display area AA. The driver 1000 may be disposed in the non-display area NAA surrounding the display area AA. The driver 1000 may be disposed on the non-display area NAA located on at least one side of the first substrate 110, but the embodiments of the present disclosure are not limited thereto. The driver 1000 may include a gate driver, a data driver, or a timing controller, but the embodiments of the present disclosure are not limited thereto. In addition, the driver 1000 may include a power line through which a power supply voltage is supplied. For example, the gate driver may supply a scan signal to the selected pixel P through the scan line SL, and the data driver may supply a data voltage to the selected pixel P through the data line DL.

[0076] The pad portion 1005 may be provided on the non-display area NAA of the first substrate 110 and may include a plurality of electrode pads. The pad portion 1005 may be attached to a flexible circuit board and electrically connected to a printed circuit board. The printed circuit board may include an integrated circuit chip and provide power configured to drive the light-emitting element and various signals to the display area AA. For example, the various signals may include a high potential voltage, a low potential voltage, a scan signal, a data signal, or a touch drive signal, but the embodiments of the present disclosure are not limited thereto.

[0077] The holes H can be formed by cutting the first substrate 110 using a laser ablation method. Therefore, external moisture or oxygen may penetrate into the display area AA through the cross-section exposed by the holes H formed by the laser ablation method. Furthermore, when external forces are applied to the display device 10, cracks may form in the area where the holes H are provided. Once cracks form, they may spread toward the display area AA, causing defects such as dark spots where pixels do not emit light. Therefore, a structure that can prevent cracks will be described below. This structure may also be referred to as a crack prevention structure.

[0078] Figure 4 The embodiment according to the present disclosure is shown Figure 3 An enlarged plan view of the region 4 where the holes are provided.

[0079] refer to Figure 3 and Figure 4 , the display area AA of the first substrate 110 may include a first area HA provided with a hole H. The first area HA provided in the display area AA may be a region provided with the hole H penetrating from the upper surface to the lower surface of the first substrate 110. The first area HA may be a non-display area because no image is displayed.

[0080] The hole H may pass through the first substrate 110 in the thickness direction. The hole H may have a closed curve shape in a plan view, but the embodiments of the present disclosure are not limited thereto. In one example, the hole H may have a circular shape, but is not limited thereto.

[0081] According to an embodiment of the present disclosure, the second area MA may be included between the first area HA and the display area AA. The second area MA may surround the first area HA. ​​Pixels P are not provided in the second area MA, and thus the second area MA may be a non-display area. A blocking pattern BT may be provided in the second area MA. By providing the blocking pattern BT within the second area MA, the light-emitting elements within the display area AA can be protected from damage by moisture or oxygen. Furthermore, by preventing external moisture or oxygen from penetrating into the first area HA, defects such as dark spots or reduced brightness of the light-emitting elements can be prevented.

[0082] The dam portion DM may be provided in the second area MA.

[0083] The dam DM may be disposed between the hole H and the display area AA. The dam DM may have a closed curve shape surrounding the hole H, but embodiments of the present disclosure are not limited thereto. The dam DM may have the same shape as the hole H, but embodiments of the present disclosure are not limited thereto. In one example, since the dam DM is formed to surround the hole H on the outside, the dam DM may have a diameter larger than that of the hole H. Therefore, the dam DM and the hole H may be spaced apart from each other. Since the dam DM is patterned, the dam DM may be a dam pattern, but embodiments of the present disclosure are not limited thereto.

[0084] The barrier pattern BT may include a first barrier pattern OPT and a second barrier pattern IPT. The first barrier pattern OPT may be provided in a first portion between the hole H and the dam DM in the second area MA. The second barrier pattern IPT may be provided in a second portion between the dam DM and the boundary of the display area AA in the second area MA. The barrier pattern BT may be a pattern, but the embodiments of the present disclosure are not limited thereto.

[0085] The first barrier pattern OPT may have a closed curve shape surrounding the hole H, but embodiments of the present disclosure are not limited thereto. The first barrier pattern OPT may have the same shape as the hole H, but embodiments of the present disclosure are not limited thereto. In one example, since the first barrier pattern OPT is formed to surround the hole H on the outside of the hole H, the first barrier pattern OPT may have a diameter larger than the diameter of the hole H. Therefore, the first barrier pattern OPT may be disposed at a position spaced a predetermined distance from the hole H. In one example, the first barrier pattern OPT may include one or more patterns, but embodiments of the present disclosure are not limited thereto.

[0086] The second barrier pattern IPT may have a closed curve shape surrounding the hole H. The second barrier pattern IPT may have the same shape as the hole H. In one example, the second barrier pattern IPT may be formed to surround the hole H from the outside of the hole H and, therefore, may have a diameter larger than the diameter of the hole H. Furthermore, since the second barrier pattern IPT is formed to surround the dam portion DM from the outside, the second barrier pattern IPT may have a size larger than the diameter of the dam portion DM. Therefore, the second barrier pattern IPT may be disposed at a position spaced a predetermined distance from the hole H. In one example, the second barrier pattern IPT may include one or more patterns, but embodiments of the present disclosure are not limited thereto.

[0087] The first barrier pattern OPT, the dam DM, and the second barrier pattern IPT may be disposed outward from the hole H relative to the hole H. The first barrier pattern OPT, the dam DM, and the second barrier pattern IPT may be disposed outside the hole H relative to the hole H. Therefore, the diameter of the first barrier pattern OPT disposed closest to (or proximate to) the hole H may be the smallest, and the diameter of the second barrier pattern IPT disposed at the farthest distance from the hole H may be the largest.

[0088] By disposing the dam portion DM, the first barrier pattern OPT, and the second barrier pattern IPT in the second area MA between the hole H and the display area AA, the light-emitting layer, which is a component of the light-emitting element, can be partitioned or separated in the second area MA. By partitioning or separating the light-emitting layer in the second area MA, the diffusion of moisture or oxygen that may penetrate into the display area AA through the hole H can be prevented or delayed.

[0089] According to an embodiment of the present disclosure, a structure may be further provided in the second area MA. The structure CPT may be provided to overlap with at least one structure in the first barrier pattern OPT or the dam portion DM. For example, the structure CPT may overlap with at least one structure in the first barrier pattern OPT or the dam portion DM in a vertical direction (or in an up-down direction). The structure CPT may prevent external moisture or oxygen from penetrating into the display area AA, or prevent cracks from extending through the first area HA. ​​The structure CPT may prevent cracks occurring in the hole H from extending to the display area AA, or delay the expansion time of the cracks. Therefore, dark spot defects or vertical line defects may be prevented from occurring on the display area AA. The structure CPT may be an anti-crack structure or a crack-stopping structure, but the embodiments of the present disclosure are not limited thereto.

[0090] The structure CPT may have a closed curve shape surrounding the hole H, but the embodiments of the present disclosure are not limited thereto. The structure CPT may have the same shape as the hole H. In one example, since the structure CPT is disposed below the dam DM, the width of the structure CPT may be smaller than the width of the dam DM, but the embodiments of the present disclosure are not limited thereto.

[0091] Figure 5 The embodiment according to the present disclosure is shown Figure 4 A cross-sectional view taken along line II' in FIG. Figure 6 The embodiment according to the present disclosure is shown Figure 4 A cross-sectional view taken along line II-II'. Figure 7 The embodiment according to the present disclosure is shown Figure 6 For ease of description, the enlarged cross-sectional view of region 7 in FIG. Figure 6 The second substrate 170 is omitted.

[0092] refer to Figures 5 to 7, the first substrate 110 may include a barrier layer 103, and a first base layer 101 and a second base layer 105 respectively disposed on both surfaces of the barrier layer 103. The first base layer 101 and the second base layer 105 may include a flexible insulating material, but the embodiments of the present disclosure are not limited thereto. For example, the first base layer 101 and the second base layer 105 may include polyimide, but the embodiments of the present disclosure are not limited thereto. The barrier layer 103 may be disposed between the first base layer 101 and the second base layer 105. The barrier layer 103 may support the first base layer 101 and the second base layer 105 having flexibility (or softness or ductility). The barrier layer 103 may include an insulating material, but the embodiments of the present disclosure are not limited thereto. Since the first substrate 110 is formed as a multilayer of the first base layer 101, the barrier layer 103 and the second base layer 105, moisture can be prevented from penetrating from the back side (or rear surface) of the first substrate 100.

[0093] The first transistor TR1 may be disposed on the first substrate 110. The first transistor TR1 may include a first semiconductor layer ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1.

[0094] The buffer layer 113 may be disposed between the first substrate 110 and the first transistor TR1. The buffer layer 113 may be disposed on the first substrate 110. The buffer layer 113 may cover the surface of the first substrate 110. For example, the buffer layer 113 may completely cover the surface of the first substrate 110. The buffer layer 113 may reduce or prevent moisture, oxygen, or impurities from penetrating through the first substrate 110. Therefore, the first transistor TR1 may be protected from moisture, oxygen, or impurities that penetrate through the first substrate 110. The buffer layer 113 may include multiple layers, but the embodiments of the present disclosure are not limited thereto. The buffer layer 113 may include a silicon oxide (SiO x ) or silicon nitride (SiN x ), but the embodiments of the present disclosure are not limited thereto. For example, the buffer layer 113 may be formed of a multilayer formed by alternately arranging one or more inorganic insulating films, but is not limited thereto.

[0095] The first transistor TR1 may be formed of one or a combination of an oxide semiconductor layer, a polycrystalline silicon semiconductor layer, and a low-temperature polycrystalline silicon semiconductor layer. For example, the first semiconductor layer ACT1 may include a silicon-based semiconductor material. The first semiconductor layer ACT1 may include a polycrystalline silicon semiconductor material or a low-temperature polycrystalline silicon semiconductor material, but the embodiments of the present disclosure are not limited thereto. As another example, the first semiconductor layer ACT1 may include an oxide semiconductor material. The first semiconductor layer ACT1 may include a channel region, a source region, and a drain region. The region of the first semiconductor layer ACT1 that overlaps with the first gate GE1 may be a channel region. For example, the region of the first semiconductor layer ACT1 that overlaps with the first gate GE1 in the vertical direction (or in the up and down direction) may be a channel region. The source region and the drain region may be arranged on both sides of the channel region.

[0096] The first insulating layer 115 may be provided between the first semiconductor layer ACT1 and the first gate electrode GE1. The first semiconductor layer ACT1 may be covered by the first insulating layer 115. The first insulating layer 115 may be formed of a single layer or multiple layers of silicon oxide (SiO x ) or silicon nitride (SiN x The first insulating layer 115 may be a gate insulating layer, but the embodiments of the present disclosure are not limited thereto.

[0097] A light shielding layer may be further included between the buffer layer 113 and the first semiconductor layer ACT1 or between the first substrate 110 and the buffer layer 113. The light shielding layer may block external light incident on the first semiconductor layer ACT1.

[0098] The first gate electrode GE1 may be disposed on the first insulating layer 115. The first gate electrode GE1 may be formed of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof. However, embodiments of the present disclosure are not limited to such materials.

[0099] The first pattern SL1 may be provided on the first insulating layer 115. A plurality of first patterns SL1 may be provided, but the present disclosure is not limited thereto. For example, the plurality of first patterns SL1 may be provided on the first insulating layer 115 at locations different from the location where the first gate electrode GE1 is formed. The plurality of first patterns SL1 may include the same material as the first gate electrode GE1, but the present disclosure is not limited thereto. For example, the plurality of first patterns SL1 may be provided on the non-display area NAA in a wiring region where a gate driver is provided. Each of the plurality of first patterns SL1 may be provided to be spaced apart from one another.

[0100] The second insulating layer 117 may be disposed on the first gate electrode GE1 and the plurality of first patterns SL1. The second insulating layer 117 may cover the first gate electrode GE1 and the plurality of first patterns SL1. The second insulating layer 117 may include an inorganic insulating material, but the present disclosure is not limited thereto. The second insulating layer 117 may be an interlayer insulating layer, but the present disclosure is not limited thereto.

[0101] The metal pattern TM may be provided on the second insulating layer 117. The metal pattern TM may be provided at a position different from the region where the first transistor TR1 is provided. For example, the metal pattern TM may be provided in the wiring region where the gate driver is provided on the non-display area NAA. The metal pattern TM may be provided so as not to overlap with the plurality of first patterns SL1. For example, the metal pattern TM may be provided so as not to overlap with the plurality of first patterns SL1 in the vertical direction (or in the vertical direction). For example, the metal pattern TM may be provided on another layer between two first patterns SL1 provided adjacent to each other.

[0102] The protective layer 119 may be disposed on the second insulating layer 117. The protective layer 119 may be disposed to cover the metal pattern TM. The protective layer 119 may be a passivation layer, but the embodiments of the present disclosure are not limited thereto.

[0103] The second transistor TR2 may be disposed on the protective layer 119. The second transistor TR2 may include a second semiconductor layer ACT2, a second gate GE2, a second source electrode SE2, and a second drain electrode DE2.

[0104] The second transistor TR2 may be formed of one or a combination of an oxide semiconductor layer, a polycrystalline silicon semiconductor layer, and a low-temperature polycrystalline silicon semiconductor layer. For example, the second semiconductor layer ACT2 may include an inorganic insulating material, but the embodiments of the present disclosure are not limited thereto. The second semiconductor layer ACT2 may include an oxide semiconductor material such as indium gallium zinc oxide (IGZO) or indium zinc oxide (IZO), but the embodiments of the present disclosure are not limited thereto. As another example, the second semiconductor layer ACT2 may include a polycrystalline silicon semiconductor material or a low-temperature polycrystalline silicon semiconductor material. The second semiconductor layer ACT2 may include a channel region, a source region, and a drain region. The region of the second semiconductor layer ACT2 that overlaps with the second gate GE2 in the vertical direction (or in the up and down direction) may be a channel region. The source region and the drain region may be arranged on both sides of the channel region. The second semiconductor layer ACT2 may be formed of low-temperature polycrystalline silicon or polycrystalline silicon, but the embodiments of the present disclosure are not limited thereto.

[0105] The third insulating layer 121 may be provided between the second semiconductor layer ACT2 and the second gate electrode GE2. The third insulating layer 121 may be formed of a single layer or multiple layers of silicon oxide (SiO x ) or silicon nitride (SiNx The third insulating layer 121 may be a gate insulating layer, but the embodiments of the present disclosure are not limited thereto.

[0106] The second gate electrode GE2 may be disposed on the third insulating layer 121. The second gate electrode GE2 may be formed of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof.

[0107] The second pattern SL2 may be disposed on the third insulating layer 121. A plurality of second patterns SL2 may be provided, but the present disclosure is not limited thereto. For example, the plurality of second patterns SL2 may be disposed on the third insulating layer 121 at locations different from the location where the second gate electrode GE2 is formed. The plurality of second patterns SL2 may include the same material as the second gate electrode GE2 of the second transistor TR2, but the present disclosure is not limited thereto. For example, the plurality of second patterns SL2 may be disposed in a wiring region where a gate driver is disposed on the non-display area NAA. Each of the plurality of second patterns SL2 may be spaced apart from one another.

[0108] The fourth insulating layer 123 may be disposed on the second gate GE2 and the plurality of second patterns SL2. The fourth insulating layer 123 may cover the second gate GE2 and the plurality of second patterns SL2. The fourth insulating layer 123 may include an inorganic insulating material, but the embodiment of the present disclosure is not limited thereto. For example, the fourth insulating layer 123 may include silicon oxide (SiO x ) or silicon nitride (SiN x ) of an inorganic insulating film, but the embodiments of the present disclosure are not limited thereto. The fourth insulating layer 123 may be a gate insulating layer, but the embodiments of the present disclosure are not limited thereto.

[0109] The second source electrode SE2 and the second drain electrode DE2 may be disposed on the fourth insulating layer 123. The second source electrode SE2 and the second drain electrode DE2 may be electrically connected to the source region and the drain region of the second semiconductor layer ACT2 through holes passing through the fourth insulating layer 123 and the third insulating layer 121, respectively.

[0110] The fifth insulating layer 124 may be provided on the fourth insulating layer 123. The fifth insulating layer 124 may include an inorganic insulating material, but the embodiment of the present disclosure is not limited thereto. For example, the fifth insulating layer 124 may include a silicon oxide (SiO x ) or silicon nitride (SiN x ) of an inorganic insulating film, but the embodiments of the present disclosure are not limited thereto. The fifth insulating layer 124 may be an interlayer insulating layer, but the embodiments of the present disclosure are not limited thereto.

[0111] The first source electrode SE1 and the first drain electrode DE1 may be disposed on the fifth insulating layer 124. The first source electrode SE1 and the first drain electrode DE1 may be disposed at positions different from the second source electrode SE2 and the second drain electrode DE2. The first source electrode SE1 and the first drain electrode DE1 may be electrically connected to the source region and the drain region of the first semiconductor layer ACT1, respectively, through holes passing through the fourth insulating layer 123, the third insulating layer 121, the protective layer 119, the second insulating layer 117, and the first insulating layer 115.

[0112] The planarization layers 125 and 127 may be disposed on the fifth insulating layer 124. The planarization layers 125 and 127 may include a first planarization layer 125 and a second planarization layer 127, but the embodiments of the present disclosure are not limited thereto.

[0113] The first planarization layer 125 may include a contact hole that exposes a portion of the surface of the first drain electrode DE1 of the first transistor TR1, but is not limited thereto. For example, a portion of the surface of the first source electrode SE1 may be exposed. The first contact electrode 126 may fill the contact hole while one surface is in contact with the first drain electrode DE1. The first contact electrode 126 may partially extend to the surface of the first planarization layer 125 while filling the contact hole.

[0114] The first planarization layer 125 can planarize the step caused by the lower components including the first transistor TR1 and the second transistor TR2. The first planarization layer 125 can be formed of an organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. However, the embodiments of the present disclosure are not limited thereto, and the planarization layer 115 can include an organic insulating material capable of planarizing the step.

[0115] The second planarization layer 127 may include a contact hole exposing a portion of a surface of the first contact electrode 126. The contact hole passing through the second planarization layer 127 may be filled with the second contact electrode 129, and one surface of the second contact electrode 129 may be electrically connected to the first contact electrode 126.

[0116] The light emitting array section 130 may be disposed on the second planarization layer 127. The light emitting array section 130 may include a bank 132, a plurality of light emitting elements ED, and a spacer 133, but the embodiments of the present disclosure are not limited thereto. Each of the plurality of light emitting elements ED may include a first electrode 131, a light emitting layer 134, and a second electrode 135. The first electrode 131 may be an anode or a pixel electrode, and the second electrode 135 may be a cathode or the opposite electrode, but the embodiments of the present disclosure are not limited thereto.

[0117] The first electrode 131 may be disposed on the second planarization layer 127. One surface of the first electrode 131 may contact an upper surface of the second contact electrode 129. Thus, the first electrode 131 may be electrically connected to the drain DE1 of the first transistor TR1 through the second contact electrode 129 and the first contact electrode 126.

[0118] The first electrode 131 may include a metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO), but the embodiments of the present disclosure are not limited thereto. In another example, the first electrode 131 may include a single-layer or multi-layer structure including a reflective metal film formed of silver (Ag), aluminum (Al), gold (Au), nickel (Ni), chromium (Cr), or an alloy of the foregoing metals, but is not limited thereto.

[0119] The bank 132 may be provided on the second planarization layer 127. The bank 132 may define each pixel P (see FIG. Figure 3 ). Therefore, the embankment 132 can be formed to cover the edge (periphery) of the first electrode 131. In addition, the embankment 132 can prevent light of different colors from mixing and outputting between adjacent pixels. The embankment 132 may include an organic insulating film such as polyimide or epoxy resin, but is not limited thereto. For example, the embankment 132 may be formed of a material including a black pigment, or formed of an organic material such as a benzocyclobutene resin, a polyimide resin, an acrylic resin, or a photosensitive polymer, but the embodiments of the present disclosure are not limited thereto. When the embankment 132 is formed of a material including a black pigment or a black dye, the embankment 132 may be a black embankment. When the embankment 132 is formed of a material including a black pigment or a black dye, light from the outside or light reflected from the outside can be blocked, thereby further increasing the brightness of the display device.

[0120] The spacer 133 may be provided on the bank 132. The spacer 133 may be formed of the same material as the bank 132, but the embodiment of the present disclosure is not limited thereto. The spacer 133 may prevent the light emitting layer 134 from being directly impacted by the outside, thereby protecting the light emitting layer 134.

[0121] The light-emitting layer 134 may be disposed on the first electrode 131. In one example, the light-emitting layer 134 may include an organic material that emits a different color in each pixel, but the embodiments of the present disclosure are not limited thereto. For example, the light-emitting layer 134 may emit light in one of red, green, blue, and white, but is not limited thereto. In another example, the light-emitting layer 134 may be formed of an organic material that emits white light and may display one of red, green, or blue through a color filter.

[0122] The light-emitting layer 134 may include a stacked structure including a hole transport layer HTL, a light-emitting material layer EML, an electron transport layer ETL, a hole blocking layer HBL, a hole injection layer HIL, an electron blocking layer EBL, and an electron injection layer EIL, but the embodiments of the present disclosure are not limited thereto. When the light-emitting layer 134 includes a stacked structure, the light-emitting layer 134 may include one or more stacked structures, but the embodiments of the present disclosure are not limited thereto. For example, a charge generation layer may be further included between one or more stacked structures. The charge generation layer may include a P-type charge generation layer and an N-type charge generation layer. The light-emitting material layer EML of the light-emitting layer 134 may emit light by recombination of holes injected from the first electrode 131 and electrons injected from the second electrode 135.

[0123] The light emitting material layer EML may be formed on the entire surface of the display area AA to cover the exposed surfaces of the first electrode 131 and the bank 132. Figure 6 As shown, the light emitting layer 134 may be formed to extend from the display area AA to the second area MA.

[0124] The second electrode 135 may be provided on the light emitting layer 134. The second electrode 135 may be formed to cover the light emitting layer 134. The second electrode 135 may be formed together on a plurality of pixels P. The second electrode 135 may include a metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO), but the embodiments of the present disclosure are not limited thereto. In another example, the second electrode 135 may include a single layer or multilayer structure including a reflective metal film formed of silver (Ag), aluminum (Al), gold (Au), nickel (Ni), chromium (Cr), or an alloy of the foregoing metals, but is not limited thereto.

[0125] A light-emitting element ED including a first electrode 131, a light-emitting layer 134, and a second electrode 135 may be formed. An encapsulation portion 140 may be provided on the light-emitting element ED. The encapsulation portion 140 may protect the light-emitting element ED from external oxygen or moisture. The encapsulation portion 140 may cover the display area AA and extend to the non-display area NAA surrounding the display area AA.

[0126] The encapsulation portion 140 may include a multilayer structure including a first encapsulation layer 141, a second encapsulation layer 143, and a third encapsulation layer 145, but the embodiments of the present disclosure are not limited thereto. The encapsulation portion 140 may have a configuration in which the second encapsulation layer 143 is disposed between the first encapsulation layer 141 and the third encapsulation layer 145, but the embodiments of the present disclosure are not limited thereto. In one example, the first encapsulation layer 141, the second encapsulation layer 143, and the third encapsulation layer 145 may extend to the hole end HE of the second area MA, as shown in FIG. Figure 6 shown.

[0127] The first encapsulation layer 141 may be provided on the second electrode 135. The first encapsulation layer 141 may include an inorganic insulating material. For example, the first encapsulation layer 141 may include silicon nitride (SiN x ), silicon oxide (SiO x ) and at least one or more inorganic insulating materials of silicon oxynitride (SiON), but the embodiments of the present disclosure are not limited thereto.

[0128] The second encapsulation layer 143 may be disposed on the first encapsulation layer 141. For example, the second encapsulation layer 143 may cover the first encapsulation layer 141 and have a sufficient thickness to have a flat surface. The second encapsulation layer 143 may prevent foreign matter from penetrating the light-emitting element ED. The second encapsulation layer 143 may include an organic insulating material, but the embodiments of the present disclosure are not limited thereto. For example, the second encapsulation layer 143 may include at least one or more materials selected from epoxy resin, polyimide, polyethylene, and acrylate, but the embodiments of the present disclosure are not limited thereto.

[0129] The third encapsulation layer 145 may be provided on the second encapsulation layer 143. The third encapsulation layer 145 may include an organic insulating material, but the embodiments of the present disclosure are not limited thereto. For example, the third encapsulation layer 145 may include silicon nitride (SiN x ), silicon oxide (SiO x ) and at least one or more inorganic insulating materials of silicon oxynitride (SiON), but the embodiments of the present disclosure are not limited thereto.

[0130] The touch portion 150 may be provided on the encapsulation portion 140. The touch portion 150 may include a buffer layer 151, an insulating layer 153, a plurality of touch electrodes 155, and an interlayer insulating layer 157, but the embodiments of the present disclosure are not limited thereto. The plurality of touch electrodes 155 may include a plurality of conductive patterns 154 and a plurality of bridge electrodes 152. The plurality of conductive patterns 154 and the plurality of bridge electrodes 152 may be provided on different layers. For example, the plurality of bridge electrodes 152 may be provided on the buffer layer 151. The plurality of conductive patterns 154 may be provided on the insulating layer 153.

[0131] An insulating layer 153 may be provided between the conductive pattern 154 and the bridge electrode 152. A plurality of conductive patterns 154 may be provided spaced apart from each other on the insulating layer 153. The bridge electrode 152 may electrically connect adjacent conductive patterns 154. To this end, the conductive pattern 154 may pass through the insulating layer 153 and be electrically connected to the bridge electrode 152. Adjacent conductive patterns 154 may be insulated from each other by an interlayer insulating layer 157.

[0132] One or more crack sensing patterns (or crack detection patterns) CSP may be provided on the insulating layer 153. For example, one or more crack sensing patterns CSP may be provided on the insulating layer 153 at positions different from positions where the conductive patterns 154 are formed. Figure 6 One or more crack sensing patterns CSP may be provided on the second area MA. At least one of the one or more crack sensing patterns CSP may be provided to overlap with the dam portion DM. For example, at least one of the one or more crack sensing patterns CSP may be provided to overlap with the dam portion DM in a vertical direction (or in a vertical direction). The crack sensing pattern CSP may detect defects such as cracks that may occur during the process of forming the hole H.

[0133] The conductive pattern 154, the bridge electrode 152, and the crack sensing pattern CSP may include a single layer or a multilayer including any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy of the foregoing metals, but the embodiments of the present disclosure are not limited thereto.

[0134] The protective member 160 may be disposed on the touch portion 150. The protective member 160 may cover a step caused by the touch portion 150 and may have a sufficient thickness to have a flat surface. The protective member 160 may prevent foreign matter, moisture, or oxygen from penetrating the touch portion 150. The protective member 160 may be formed of a multilayer structure formed by alternating organic insulating layers and inorganic insulating layers, but the embodiments of the present disclosure are not limited thereto.

[0135] For example, the protective member 160 may include a first protective layer 161 and a second protective layer 163. The first protective layer 161 and the second protective layer 163 may include organic insulating layers, but the embodiments of the present disclosure are not limited thereto.

[0136] The second substrate 170 may be disposed on the protective member 160. The second substrate 170 may cover the first substrate 110. The second substrate 170 may serve as a cover window or a cover substrate. The second substrate 170 may include a plastic film or a glass substrate, but embodiments of the present disclosure are not limited thereto. An adhesive member may be further included between the protective member 160 and the second substrate 170. The adhesive member may enhance the adhesive force between the first substrate 110 and the second substrate 170. The adhesive member may include a pressure-sensitive adhesive (PSA), an optically clear resin (OCR), or an optically clear adhesive (OCA), but embodiments of the present disclosure are not limited thereto.

[0137] refer to Figure 4 and Figure 6The display device according to an embodiment of the present disclosure may include the dam DM, the pattern BT, and the first structure body CPTa disposed in the second area MA. The dam DM may prevent the second encapsulation layer 143 including an organic insulating material from overflowing into the hole H.

[0138] The dam portion DM may include a first layer 310a, a second layer 310b, a third layer 310c, and a fourth layer 310d, but the embodiments of the present disclosure are not limited thereto. For example, the dam portion DM may include a structure in which the first layer 310a, the second layer 310b, the third layer 310c, and the fourth layer 310d are arranged or stacked from bottom to top, but the embodiments of the present disclosure are not limited thereto. The first layer 310a may be formed during the process of forming the fifth insulating layer 124, but the embodiments of the present disclosure are not limited thereto. The second layer 310b may be formed during the process of forming the second planarization layer 127, but the embodiments of the present disclosure are not limited thereto. The third layer 310c may be formed during the process of forming the bank 132, but the embodiments of the present disclosure are not limited thereto. The fourth layer 310d may be formed during the process of forming the spacer 133, but the embodiments of the present disclosure are not limited thereto. For example, the first layer 310a of the dam portion DM may include the same material as the fifth insulating layer 124, but the embodiments of the present disclosure are not limited thereto. The second layer 310b may include the same material as the second planarization layer 127, but the embodiments of the present disclosure are not limited thereto. The third layer 310c may include the same material as the bank 132, but the embodiments of the present disclosure are not limited thereto. The fourth layer 310d may include the same material as the spacer 133, but the embodiments of the present disclosure are not limited thereto.

[0139] Since the second layer 310b of the dam portion DM is smaller than the first layer 310a, the edge portion (or peripheral portion) of the upper surface of the first layer 310a may be exposed. The third layer 310c of the dam portion DM may cover the second layer 310b. The third layer 310c of the dam portion DM may cover the exposed surface of the first layer 310a. In addition, since the fourth layer 310d of the dam portion DM is larger than the third layer 310c, the fourth layer 310d may cover the third layer 310c and cover the exposed surface of the first layer 310a not covered by the third layer 310c.

[0140] The hole H may be formed through the second protective layer 163 to the first substrate 110 by a laser ablation method. External moisture or oxygen may penetrate into the display area AA through the exposed cross-section of the hole H. For example, moisture may penetrate into the display area AA from the hole end HE of the second area MA. Therefore, a barrier pattern BT that prevents external moisture or oxygen from penetrating into or into the display area AA may be provided on the second area MA together with the dam portion DM.

[0141] refer to Figure 4 and Figure 6The barrier pattern BT according to an embodiment of the present disclosure may include a first barrier pattern OPT and a second barrier pattern IPT. The first barrier pattern OPT may be disposed in a first region between the hole H and the dam DM within the second area MA, and the second barrier pattern IPT may be disposed in a second region between the dam DM and the boundary of the display area AA within the second area MA.

[0142] The first barrier pattern OPT may include a lower structure 210a and an upper structure 210b, but the embodiments of the present disclosure are not limited thereto. The first barrier pattern OPT may include a structure in which the lower structure 210a and the upper structure 210b are provided or stacked, but the embodiments of the present disclosure are not limited thereto. The first barrier pattern OPT may be an outer barrier pattern, but the embodiments of the present disclosure are not limited thereto.

[0143] The lower structure 210a may be formed of the same material as the third insulating layer 121 in the same process, but is not limited thereto. For example, the lower structure 210a may be made of a material such as silicon oxide (SiO x ) or silicon nitride (SiN x ) is formed by a single layer or multiple layers of an inorganic insulating layer, but is not limited thereto.

[0144] The upper structure 210b may be formed of the same material as the second planarization layer 127 in the same process, but is not limited thereto. For example, the upper structure 210b may include an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but is not limited thereto.

[0145] The second barrier pattern IPT can be formed in the same process as the first barrier pattern OPT, but the embodiments of the present disclosure are not limited thereto. Therefore, the lower structure 220a of the second barrier pattern IPT can be the same as the lower structure 210a of the first barrier pattern OPT, and the upper structure 220b of the second barrier pattern IPT can be the same as the upper structure 210b of the first barrier pattern OPT, but the embodiments of the present disclosure are not limited thereto. The second barrier pattern IPT can be an inner barrier pattern, but the embodiments of the present disclosure are not limited thereto.

[0146] The upper structures 210b and 220b of the first and second barrier patterns OPT and IPT may have a regular tapered shape with a lower surface width greater than an upper surface width, but the embodiments of the present disclosure are not limited thereto. The lower structures 210a and 220a of the first and second barrier patterns OPT and IPT may have a regular tapered shape with a lower surface width greater than an upper surface width, but the embodiments of the present disclosure are not limited thereto. Furthermore, the lower surface widths of the upper structures 210b and 220b of the first and second barrier patterns OPT and IPT may be greater than the upper surface widths of the lower structures 210a and 220a thereof, but the embodiments of the present disclosure are not limited thereto. The lower structures 210a and 220a of the first and second barrier patterns OPT and IPT may have an undercut structure, but the embodiments of the present disclosure are not limited thereto. For example, the outermost portions of the lower structures 210a and 220a of the first and second barrier patterns OPT and IPT may have an undercut structure that is more inwardly undercut than the outermost portions of the lower surfaces of the upper structures 210b and 220b, but the embodiments of the present disclosure are not limited thereto. Therefore, the outermost portions of the lower surfaces of the upper structures 210b and 220b of the first and second barrier patterns OPT and IPT may have a shape that protrudes more than the lower structures 210a and 220a.

[0147] When the light emitting layer 134 is formed in a state where the second barrier pattern IPT and the first barrier pattern OPT are provided, the light emitting layer 134 may be formed on the surfaces of the upper structures 210 b and 220 b of the first barrier pattern OPT and the second barrier pattern IPT. Furthermore, the light emitting layer 134 may also be formed on the surface of the fourth insulating layer 123 exposed between adjacent second barrier patterns IPT and between adjacent first barrier patterns OPT. Furthermore, the light emitting layer 134 may be formed on the exposed surface of the dam portion DM.

[0148] Since each of the second and first barrier patterns IPT and OPT has an undercut structure, the light emitting layer 134 may not be formed on the sidewalls of the lower structures 210a and 220a. Therefore, the continuity of the light emitting layer 134 is interrupted in the second region MA, and thus the light emitting layer 134 may be disconnected.

[0149] The light emitting layer 134 can serve as a permeation path for moisture or oxygen. Therefore, the light emitting layer 134 can be disconnected between adjacent second barrier patterns IPT and adjacent first barrier patterns OPT, thereby preventing moisture or oxygen permeating from the outside from permeating into the display area AA or delaying the permeation time.

[0150] The first encapsulation layer 141 may be disposed on the light-emitting layer 134 within the second area MA. The first encapsulation layer 141 may be disposed on the second barrier pattern IPT and the first barrier pattern OPT. The first encapsulation layer 141 may be disposed to cover the surfaces of the upper structures 210 b and 220 b of the first and second barrier patterns OPT and the side surfaces of the lower structures 210 a and 220 a. The first encapsulation layer 141 may be disposed on the dam DM. The first encapsulation layer 141 may have a shape that fills the spaces between adjacent second barrier patterns IPT and adjacent first barrier patterns OPT, and fills the spaces between the second barrier pattern IPT and the dam DM, and between the dam DM and the first barrier pattern OPT, but is not limited thereto. For example, because the spaces between the second barrier patterns IPT and the spaces between the first barrier patterns OPT may be small, the first encapsulation layer 141 may not fill all the spaces. In this case, a space may remain on a portion (or portions) of the side surfaces of the lower structure 210a of the first barrier pattern OPT and the lower structure 220a of the second barrier pattern IPT. The space remaining on a portion of the side surface of the lower structure 210a of the first barrier pattern OPT may be covered by the third encapsulation layer 145. In addition, the space remaining on a portion of the side surface of the lower structure 220a of the second barrier pattern IPT may be covered (or filled) by the second encapsulation layer 143.

[0151] The second encapsulation layer 143 may be disposed on the first encapsulation layer 141. The second encapsulation layer 143 may be formed to extend to a second portion of the second area MA, disposed between the display area AA and the dam DM. The second portion may be an area within the second area MA located between the dam DM and the boundary of the display area AA. Because the dam DM can block overflow of the second encapsulation layer 143, the second barrier pattern IPT disposed on the second portion is covered by the second encapsulation layer 143, while the first barrier pattern OPT disposed on the first portion of the second area MA may not be covered by the second encapsulation layer 143. The first portion may be an area within the second area MA located between the hole H and the dam DM.

[0152] The third encapsulation layer 145 may be disposed on the second encapsulation layer 143. The third encapsulation layer 145 may be formed to extend from the display area AA to the second area MA. Therefore, the first portion of the second area MA where the first barrier pattern OPT is disposed may be formed in a structure in which the first encapsulation layer 141 and the third encapsulation layer 145 are disposed or stacked in contact with each other. In one example, the first encapsulation layer 141 does not completely fill the gaps between the second barrier patterns IPT and the gaps between the first barrier patterns OPT, and a gap may remain on the side surfaces of the lower structures 210a and 220a. In this case, the gaps may be sealed by the structure in which the first encapsulation layer 141 and the third encapsulation layer 145 are disposed or stacked in contact with each other.

[0153] The insulating structures 151 and 153 may be disposed on the third encapsulation layer 145. The insulating structures 151 and 153 may be structures 151 and 153 including a buffer layer 151 and an insulating layer 153. The insulating structures 151 and 153 may include an inorganic insulating material, but the embodiments of the present disclosure are not limited thereto. The insulating structures 151 and 153 may be disposed on the first barrier pattern OPT. The insulating structures 151 and 153 may cover the first barrier pattern OPT.

[0154] A first protective layer 161 and a second protective layer 163 may be disposed on the insulating structures 151 and 153. The first protective layer 161 and the second protective layer 163 may include an organic insulating layer, but embodiments of the present disclosure are not limited thereto. The first protective layer 161 and the second protective layer 163 may extend from the display area AA to the hole end HE of the second area MA. Therefore, the first protective layer 161 and the second protective layer 163 may cover at least one or more of the second barrier pattern IPT and the first barrier pattern OPT. For example, the first protective layer 161 and the second protective layer 163 may cover both the second barrier pattern IPT and the first barrier pattern OPT. Furthermore, cracks may occur at the hole end HE of the hole area HA. ​​Cracks may occur when external forces such as laser ablation are applied. For example, cracks that occur at the hole end HE may occur in a layer containing an inorganic insulating material. For example, cracks may occur in the fourth insulating layer 123 or the fifth insulating layer 124. Cracks that occur in the fourth insulating layer 123 or the fifth insulating layer 124 may extend toward the display area AA in the direction of the inorganic insulating material.

[0155] If a crack that appears at the hole end HE extends to the area where the second barrier pattern IPT is located, a dark spot defect may occur, where pixels adjacent to the second barrier pattern IPT in the display area AA do not emit light. Furthermore, if the crack further extends into the display area AA and into the wiring area where the plurality of first patterns SL1 are located, a vertical line defect visible to the user may occur. These dark spot or line defects may be visible to the user, reducing the immersive video or image experience and, consequently, the reliability of the display device.

[0156] Therefore, in an embodiment of the present disclosure, the first structure body CPTa may be disposed in the second area MA to prevent or delay the crack from extending toward the display area AA.

[0157] refer to Figure 6 and Figure 7 , the first structure body CPTa may be arranged to overlap with the dam portion DM. For example, the first structure body CPTa may be arranged to overlap with the dam portion DM in the vertical direction (or in the up and down directions). For example, the first structure body CPTa may be arranged below the first layer 310a of the dam portion DM. The first structure body CPTa may include one or more first patterns 320a and 320b, a third pattern 330, and second patterns 340 and 341. For example, the first structure body CPTa may be a structure provided with one or more first patterns 320a and 320b, a third pattern 330, and second patterns 340 and 341. For example, one or more first patterns 320a and 320b, the third pattern 330, and the second patterns 340 and 341 may be arranged on different layers.

[0158] One or more first patterns 320a and 320b may be formed during the process of forming the first gate electrode GE1, but the embodiments of the present disclosure are not limited thereto. One or more first patterns 320a and 320b may include the same material as the first gate electrode GE1, but the embodiments of the present disclosure are not limited thereto. For example, one or more of the first patterns 320a and 320b may be formed of a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof, but the present disclosure is not limited thereto.

[0159] One or more first patterns 320a and 320b may be disposed spaced apart from each other on the first insulating layer 115. Thus, there may be a space between the first patterns 320a and 320b. The first patterns 320a and 320b may be covered by the second insulating layer 117. For example, the second insulating layer 117 may be disposed on the first patterns 320a and 320b.

[0160] The third pattern 330 may be formed during the process of forming the metal pattern TM, but the embodiments of the present disclosure are not limited thereto. The third pattern 330 may comprise the same material as the metal pattern TM, but the embodiments of the present disclosure are not limited thereto. The third pattern 330 may be disposed on the second insulating layer 117. The third pattern 330 may be arranged so as not to overlap with the first pattern 320a or 320b. For example, the third pattern 330 may be disposed in the space between the first patterns 320a and 320b, which are spaced apart from each other. The third pattern 330 may be covered by the protective layer 119. The protective layer 119 may be disposed on the third pattern 330. The protective layer 119 may include a first groove G1. For example, the protective layer 119 may include a first groove G1 formed by a step caused by the space between the first patterns 320a and 320b disposed thereunder. The first groove G1 may be disposed on both sides of the third pattern 330. For example, the first groove G1 may have a shape similar to the letter "W," but the embodiments of the present disclosure are not limited thereto.

[0161] The second patterns 340 and 341 may be formed during the process of forming the second gate electrode GE2, but the embodiments of the present disclosure are not limited thereto. The second patterns 340 and 341 may include the same material as the second gate electrode GE2, but the embodiments of the present disclosure are not limited thereto. For example, the second pattern 340 may be formed of a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof, but the present disclosure is not limited thereto.

[0162] The second patterns 340 and 341 may be disposed on the third insulating layer 121. The third insulating layer 121 may include a first groove G1 and a second groove G2. The third insulating layer 121 may include a second groove G2 that overlaps the first groove G1. For example, the third insulating layer 121 may include a second groove G2 that overlaps the first groove G1 in a vertical direction (or in a vertical direction). The second patterns 340 and 341 may fill the second groove G2. Thus, the second patterns 340 and 341 and the third insulating layer 121 may have an uneven shape (or a concave-convex shape), but the embodiments of the present disclosure are not limited thereto. For example, the second patterns 340 and 341 and the third insulating layer 121 may have an uneven shape (or a concave-convex shape) in a cross-sectional view, but the embodiments of the present disclosure are not limited thereto. For example, the uneven shape (or concave-convex shape) may have the shape of the letter "W", but the embodiments of the present disclosure are not limited thereto. The second patterns 340 and 341 may overlap the first patterns 320a and 320b and the third pattern 330. For example, the second patterns 340 and 341 may overlap the first patterns 320 a and 320 b and the third pattern 330 in a vertical direction (or in an up-and-down direction).

[0163] The second patterns 340 and 341 may be formed in the same process as the second gate electrode GE2, but the embodiments of the present disclosure are not limited thereto. The second patterns 340 and 341 may include a 2-1 pattern 340 and a 2-2 pattern 341. For example, the second patterns 340 and 341 may include a structure provided with a 2-1 pattern 340 and a 2-2 pattern 341, but the embodiment of the present disclosure is not limited thereto. For example, the second patterns 340 and 341 may include a single-layer pattern, but the embodiments of the present disclosure are not limited thereto. The 2-1 pattern 340 may be a gate pattern or a gate metal pattern, but the embodiments of the present disclosure are not limited thereto. The 2-2 pattern 341 may be a gate pattern or a gate metal pattern, but the embodiments of the present disclosure are not limited thereto.

[0164] Since the one or more first patterns 320a and 320b are arranged on different layers from the third pattern 330 and are staggered without overlapping each other, the first groove G1 and the second groove G2 can be arranged to overlap with the dam portion DM. For example, the first groove G1 and the second groove G2 can be arranged to overlap with the dam portion DM in the vertical direction (or in the up and down direction). The first groove G1 and the second groove G2 can prevent the crack CR from extending toward the display area AA, or delay the crack extension time by increasing the length of the crack extension path. For example, Figure 7 As shown by the arrows in FIG, the expansion path of the crack CR occurring in the fourth insulating layer 123 including the inorganic insulating material can be blocked by the second patterns 340 and 341 including the material filling the second groove G2. The material filling the second groove G2 may be a metal material, but the embodiments of the present disclosure are not limited thereto.

[0165] Furthermore, since the length of the crack CR's extension path increases along the uneven shape (or concavo-convex shape) of the third insulating layer 121, the time for the crack CR to extend toward the display area AA can be delayed. Therefore, dark spot defects or line defects can be prevented from occurring, thereby improving the reliability of the display device.

[0166] The first structure body CPTa may be changed (or varied) according to the shapes of the first pattern, the third pattern, and / or the second pattern.

[0167] Figure 8 Another embodiment according to the present disclosure is shown Figure 6 Another modified example of the structure in region 8 in . Figure 9 Another embodiment according to the present disclosure is shown Figure 6 Another modified example of the structure in region 9 in . Figure 10 Another embodiment according to the present disclosure is shown Figure 6 Another modified example of the structure in region 10 in FIG. Figures 8 to 10 Except for the shape of the structure, it is basically the same Figure 7Since the same reference numerals are shown, repeated descriptions thereof may be omitted or briefly described.

[0168] refer to Figure 8 , the second structure body CPTb may be arranged to overlap with the dam portion DM. For example, the second structure body CPTb may be arranged to overlap with the dam portion DM in the vertical direction (or in the up and down direction). For example, the second structure body CPTb may be arranged below the first layer 310a of the dam portion DM. The second structure body CPTb may include a first pattern 320a, a third pattern 330, and second patterns 340 and 341. The second structure body CPTb may be a structure provided with a first pattern 320a, a third pattern 330, and second patterns 340 and 341. The first pattern 320a, the third pattern 330, and the second pattern 340 and 341 may be arranged on different layers, but the embodiments of the present disclosure are not limited thereto.

[0169] The first pattern 320a may be disposed on the first insulating layer 115. The first pattern 320a may be covered by the second insulating layer 117. The third pattern 330 may be disposed on the second insulating layer 117. The third pattern 330 may be disposed so as not to overlap with the first pattern 320a. For example, the third pattern 330 may be disposed so as not to overlap with the first pattern 320a in a vertical direction (or in a vertical direction). For example, the third pattern 330 may be disposed so as to intersect with the first pattern 320a on the second insulating layer 117.

[0170] The third pattern 330 may be disposed below the protective layer 119. The third pattern 330 may be covered by the protective layer 119. The protective layer 119 may include a first groove G1 formed by a step caused by the first pattern 320a disposed thereunder. The first groove G1 may be disposed on at least one side of the third pattern 330. For example, the first groove G1 may be disposed between the first patterns 320a located below at least one side of the third pattern 330.

[0171] The third insulating layer 121 may be disposed on the protective layer 119. The second patterns 340 and 341 may be disposed on the third insulating layer 121. The third insulating layer 121 may include a first groove G1 and a second groove G2. For example, the second groove G2 may overlap the first groove G1. The third insulating layer 121 may include a second groove G2 that overlaps the first groove G1. For example, the third insulating layer 121 may include a second groove G2 that overlaps the first groove G1 in a vertical direction (or in a vertical direction). The second patterns 340 and 341 may be disposed to overlap the first pattern 320a and the third pattern 330. For example, the second patterns 340 and 341 may be disposed to overlap the first pattern 320a and the third pattern 330 in a vertical direction (or in a vertical direction). Therefore, the second patterns 340 and 341 and the third insulating layer 121 may have an uneven shape (or a concave-convex shape), but embodiments of the present disclosure are not limited thereto. For example, the second patterns 340 and 341 and the third insulating layer 121 may have an uneven shape (or a concave-convex shape) in a cross-sectional view, but the embodiments of the present disclosure are not limited thereto. For example, the uneven shape (or concave-convex shape) may have a shape of the letter "V", but the embodiments of the present disclosure are not limited thereto.

[0172] According to an embodiment of the present disclosure, the first pattern 320a and the third pattern 330 may be arranged at staggered positions on different layers so that the first groove G1 and the second groove G2 overlap each other. For example, the first pattern 320a and the third pattern 330 may be arranged at staggered positions on different layers so that the first groove G1 and the second groove G2 overlap each other in the vertical direction (or in the up-down direction).

[0173] The first groove G1 and the second groove G2 can prevent the crack CR from extending toward the display area AA or delay the extension time of the crack CR. For example, when the crack CR extends in the horizontal direction of the fourth insulating layer 123, as shown in FIG. Figure 8 As shown by the arrows in FIG, the crack propagation time can be blocked by the second patterns 340 and 341 containing the material filling the second groove G2. For example, the material filling the second groove G2 can be a metal material, but the embodiments of the present disclosure are not limited thereto. In addition, the uneven shape (or concave-convex shape) formed by the first groove G1 and the second groove G2 can delay the crack CR propagation time.

[0174] refer to Figure 9, the third structure CPTc can be set to overlap with the dam portion DM. For example, the third structure CPTc can be set to overlap with the dam portion DM in the vertical direction (or in the up and down direction). For example, the third structure CPTc can be set below the first layer 310a of the dam portion DM. The third structure CPTc may include one or more third patterns 330a, 330b and 330c, and second patterns 340 and 341. The one or more third patterns 330a, 330b and 330c and the second patterns 340 and 341 may be set on different layers, but the embodiments of the present disclosure are not limited thereto. The third structure CPTc may be a structure provided with or stacked with one or more third patterns 330a, 330b and 330c and second patterns 340 and 341, but the embodiments of the present disclosure are not limited thereto.

[0175] One or more third patterns 330a, 330b, and 330c may be disposed on the second insulating layer 117. The one or more third patterns 330a, 330b, and 330c may include a 3-1 pattern 330a, a 3-2 pattern 330b, and a 3-3 pattern 330c. The one or more third patterns 330a, 330b, and 330c may be made of the same material as the metal pattern TM in the same process, but the embodiments of the present disclosure are not limited thereto.

[0176] The 3-1 pattern 330a, the 3-2 pattern 330b, and the 3-3 pattern 330c may be spaced apart from each other. Thus, there may be a gap (or separation gap) between the 3-1 pattern 330a and the 3-2 pattern 330b, and between the 3-2 pattern 330b and the 3-3 pattern 330c. The 3-1 pattern to the 3-3 pattern 330a, 330b, and 330c may be covered by the protective layer 119.

[0177] The protective layer 119 may include a first groove G1. The first groove G1 may be disposed in a space (separation space) between the 3-1 pattern 330a, 330b, and 330c. The first groove G1 may be disposed on both sides of the 3-2 pattern 330b. The third insulating layer 121 may be disposed on the protective layer 119.

[0178] The second patterns 340 and 341 may be disposed on the third insulating layer 121. The second patterns 340 and 341 may be formed of the same material as the second gate electrode GE2 in the same process, but the embodiments of the present disclosure are not limited thereto. The third insulating layer 121 may include a second groove G2 that overlaps with the first groove G1. For example, the third insulating layer 121 may include a second groove G2 that overlaps with the first groove G1 in a vertical direction (or in a vertical direction).

[0179] The second patterns 340 and 341 may fill the second groove G2. Thus, the second patterns 340 and 341 and the third insulating layer 121 may have an uneven shape (or concave-convex shape) of the letter "W", but the embodiments of the present disclosure are not limited thereto. For example, the second patterns 340 and 341 and the third insulating layer 121 may have an uneven shape of the letter "W", but the embodiments of the present disclosure are not limited thereto. The second patterns 340 and 341 may overlap with one or more third patterns 330a, 330b, and 330c. For example, the second patterns 340 and 341 may overlap with one or more third patterns 330a, 330b, and 330c in a vertical direction (or in an up-down direction).

[0180] According to an embodiment of the present disclosure, the third structure CPTc disposed overlapping with the dam portion DM can prevent the crack CR from expanding as indicated by the first and second grooves G1 and G2. Furthermore, the uneven shape (or concave-convex shape) formed by the first and second grooves G1 and G2 can delay the expansion time of the crack CR.

[0181] refer to Figure 10 The fourth structure body CPTd may include one or more first patterns 320a and 320b, and second patterns 340 and 341. The fourth structure body CPTd may include one or more first patterns 320a and 320b, and second patterns 340 and 341. The plurality of fourth structure bodies CPTd may be a structure in which one or more first patterns 320a and 320b and second patterns 340 and 341 are stacked or provided, but the embodiments of the present disclosure are not limited thereto. The one or more first patterns 320a and 320b and the one or more second patterns 340 and 341 may be provided on different layers, but the embodiments of the present disclosure are not limited thereto.

[0182] The one or more first patterns 320a and 320b may include a first pattern 320a and a second pattern 320b. The first pattern 320a and the second pattern 320b may be disposed on the first insulating layer 115 and spaced apart from each other. Thus, there may be a space between the first pattern 320a and the second pattern 320b. The first pattern 320a and the second pattern 320b may be covered by the second insulating layer 117. The second insulating layer 117 may be disposed on the first pattern 320a and the second pattern 320b.

[0183] The second insulating layer 117 may be covered by a protective layer 119. The protective layer 119 may be disposed on the second insulating layer 117. The protective layer 119 may include a first groove G1 formed by the space between the first patterns 320a and 320b. The third insulating layer 121 may be disposed on the protective layer 119 including the first groove G1. The third insulating layer 121 may include a second groove G2 that overlaps with the first groove G1. For example, the third insulating layer 121 may include a second groove G2 that overlaps with the first groove G1 in a vertical direction (or in an up-down direction).

[0184] The second patterns 340 and 341 may be disposed on the third insulating layer 121. The second patterns 340 and 341 may fill the second groove G2. The second patterns 340 and 341 may be disposed to overlap with one or more first patterns 320a and 320b. For example, the second patterns 340 and 341 may be disposed to overlap with one or more first patterns 320a and 320b in a vertical direction (or in an up-down direction). Therefore, the second patterns 340 and 341 and the third insulating layer 121, the protective layer 119, and the second insulating layer 117 disposed below the second patterns 340 and 341 may have an uneven shape (or a concave-convex shape), but the embodiments of the present disclosure are not limited thereto. For example, the second patterns 340 and 341 and the third insulating layer 121, the protective layer 119, and the second insulating layer 117 disposed below the second patterns 340 and 341 may have an uneven shape (or a concave-convex shape) in a cross-sectional view, but the embodiments of the present disclosure are not limited thereto. For example, the uneven shape (or concavo-convex shape) may have a shape of letter 'V', but embodiments of the present disclosure are not limited thereto.

[0185] According to an embodiment of the present disclosure, the fourth structure body CPTd disposed overlapping with the dam portion DM can block the crack CR from extending toward the display area AA through the first and second grooves G1 and G2. In addition, since the uneven shape (or concave-convex shape) formed by the first and second grooves G1 and G2 increases the length of the crack extension path, the extension time of the crack CR can be delayed.

[0186] Figure 11 Another embodiment according to the present disclosure is shown. Figure 4 A cross-sectional view taken along line II-II'. Figure 12 Another embodiment according to the present disclosure is shown Figure 11 An enlarged cross-sectional view of region 12 in FIG. Figure 13 Another embodiment according to the present disclosure is shown Figure 11 Another modified example of the structure in region 13 in . Figure 14 According to another embodiment of the present disclosure Figure 11 Another modified example of the structure in region 14 in . Figure 15 Another embodiment according to the present disclosure is shown Figure 11 Another modified example of the structure in region 15 in FIG. Figures 11 to 15 Basically with Figure 10 The same reference numerals are shown, and repeated descriptions thereof are omitted or briefly described.

[0187] refer to Figure 11 and Figure 12 , a plurality of first structural bodies CPTa may be arranged in a first area of ​​the second area MA where a plurality of first barrier patterns OPT are arranged. For example, one first structural body CPTa may be arranged to overlap with at least one first barrier pattern OPT. For example, one first structural body CPTa may be arranged to overlap with at least one first barrier pattern OPT in a vertical direction (or in an up-down direction). The first structural body CPTa may be arranged below an even-numbered first barrier pattern OPT among the plurality of first barrier patterns OPT, but is not limited thereto. In another example, the first structural body CPTa may be arranged below an odd-numbered first barrier pattern OPT.

[0188] The first structure body CPTa may be disposed below the lower structure 210a of the first barrier pattern OPT. The first structure body CPTa may include one or more first patterns 320a and 320b, a third pattern 330, and second patterns 340 and 341. The one or more first patterns 320a and 320b, the third pattern 330, and the second patterns 340 and 341 may be disposed on different layers, but the embodiments of the present disclosure are not limited thereto.

[0189] Each of the one or more first patterns 320 a and 320 b , the third pattern 330 , and the second patterns 340 and 341 disposed on different layers may be insulated (or isolated) from one another in the second insulating layer 117 , the protective layer 119 , or the third insulating layer 121 .

[0190] The protective layer 119 may include a first groove G1. The first groove G1 may be formed by a step caused by the spacing (or separation) between the first pattern 320a and the second pattern 320b. The first groove G1 may be provided on both sides of the third pattern 330. The third insulating layer 121 may include a second groove G2 that overlaps with the first groove G1. For example, the third insulating layer 121 may include a second groove G2 that overlaps with the first groove G1 in a vertical direction (or in a vertical direction). The second patterns 340 and 341 may fill the second groove G2. The second patterns 340 and 341, the third insulating layer 121, and the protective layer 119 may have an uneven shape (or a concave-convex shape), but the embodiments of the present disclosure are not limited thereto. The second patterns 340 and 341, the third insulating layer 121, and the protective layer 119 may have an uneven shape (or a concave-convex shape) in a cross-sectional view, but the embodiments of the present disclosure are not limited thereto. For example, the uneven shape (or concave-convex shape) may have the shape of the letter "W", but the embodiments of the present disclosure are not limited thereto. The second patterns 340 and 341 may overlap with the first patterns 320a and 320b and the third pattern 330. For example, the second patterns 340 and 341 may overlap with the first pattern 320a, the second pattern 320b, and the third pattern 330 in a vertical direction (or in an up-down direction). The first pattern 320a, the second pattern 320b, and the third pattern 330 may be arranged in a staggered structure that does not overlap with each other. For example, the third pattern 330 may be arranged at a position corresponding to the interval (separation interval) between the first pattern 320a and the second pattern 320b. The second patterns 340 and 341 may be covered by the fourth insulating layer 123. The fourth insulating layer 123 may be arranged on the second patterns 340 and 341. The lower structure 210a of the first barrier pattern OPT may be arranged on the fourth insulating layer 123.

[0191] The first groove G1 and the second groove G2 of the first structural body CPTa can prevent cracks from extending toward the display area AA or delay crack propagation by increasing the length of the crack propagation path. Therefore, dark spot defects or line defects caused by cracks can be prevented, thereby improving the reliability of the display device.

[0192] refer to Figure 13, the second structure body CPTb may be arranged to overlap with the first barrier pattern OPT. For example, the second structure body CPTb may be arranged to overlap with the first barrier pattern OPT in a vertical direction (or in an up-down direction). For example, the second structure body CPTb may be arranged below the lower structure 210a of the first barrier pattern OPT. The second structure body CPTb may include a first pattern 320a, a third pattern 330, and second patterns 340 and 341. The first pattern 320a, the third pattern 330, and the second patterns 340 and 341 may be arranged on different layers, but the embodiments of the present disclosure are not limited thereto.

[0193] The first pattern 320a may be disposed on the first insulating layer 115. The exposed surface of the first pattern 320a may be covered by the second insulating layer 117. The third pattern 330 may be disposed on the second insulating layer 117. The third pattern 330 may be disposed so as not to overlap with the first pattern 320a. For example, the third pattern 330 may be disposed so as not to overlap with the first pattern 320a in a vertical direction (or in a vertical direction). The third pattern 330 may be disposed in a staggered structure with the first pattern 320a.

[0194] The third pattern 330 may be disposed under the protective layer 119. The third pattern 330 may be covered by the protective layer 119. The protective layer 119 may include a first groove G1. The first groove G1 may be disposed on at least one side of the third pattern 330. For example, the first groove G1 may be disposed between the first patterns 320a located below at least one side of the third pattern 330.

[0195] The third insulating layer 121 may be disposed on the protective layer 119. The second patterns 340 and 341 may be disposed on the third insulating layer 121. The third insulating layer 121 may include a second groove G2 that overlaps with the first groove G1. For example, the third insulating layer 121 may include a second groove G2 that overlaps with the first groove G1 in a vertical direction (or in a vertical direction). The second patterns 340 and 341 may be disposed to overlap with the first pattern 320a and the third pattern 330. For example, the second patterns 340 and 341 may be disposed to overlap with the first pattern 320a and the third pattern 330 in a vertical direction (or in a vertical direction). Therefore, the second patterns 340 and 341 and the third insulating layer 121 may have an uneven shape (or a concave-convex shape), but the embodiments of the present disclosure are not limited thereto. For example, the second patterns 340 and 341 and the third insulating layer 121 may have an uneven shape (or a concave-convex shape) in a cross-sectional view, but the embodiments of the present disclosure are not limited thereto. For example, the uneven shape (or concavo-convex shape) may have a shape of letter 'V', but embodiments of the present disclosure are not limited thereto.

[0196] refer to Figure 14, the third structure body CPTc may be arranged to overlap with the first barrier pattern OPT. The third structure body CPTc may be arranged to overlap with the first barrier pattern OPT in a vertical direction (or in an up-down direction). For example, the third structure body CPTc may be arranged below the lower structure 210a of the first barrier pattern OPT. The third structure body CPTc may include one or more third patterns 330a, 330b, and 330c, and second patterns 340 and 341. The one or more third patterns 330a, 330b, and 330c and the second patterns 340 and 341 may be arranged on different layers, but the embodiments of the present disclosure are not limited thereto.

[0197] The one or more third patterns 330a, 330b, and 330c may include a 3-1 pattern 330a, a 3-2 pattern 330b, and a 3-3 pattern 330c. The 3-1 pattern 330a, the 3-2 pattern 330b, and the 3-3 pattern 330c may be disposed on the second insulating layer 117. For example, each of the 3-1 pattern 330a, the 3-2 pattern 330b, and the 3-3 pattern 330c may be disposed on the second insulating layer 117 with a gap (or a separation gap). A protective layer 119 may be disposed on the 3-1 pattern to the 3-3 pattern 330a, 330b, and 330c. The 3-1 pattern to the 3-3 pattern 330a, 330b, and 330c may be covered by the protective layer 119.

[0198] The protective layer 119 may include a first groove G1 . The first groove G1 may be provided on both sides of the 3-2 pattern 330 b . The third insulating layer 121 may be provided on the protective layer 119 .

[0199] The second patterns 340 and 341 may be disposed on the third insulating layer 121. The third insulating layer 121 may include a second groove G2 overlapping the first groove G1. For example, the third insulating layer 121 may include a second groove G2 vertically (or vertically) overlapping the first groove G1.

[0200] The second patterns 340 and 341 may fill the second groove G2. Thus, the second patterns 340 and 341 and the third insulating layer 121 may have an uneven shape (or concave-convex shape) of the letter "W", but the embodiments of the present disclosure are not limited thereto. For example, the second patterns 340 and 341 and the third insulating layer 121 may have an uneven shape (or concave-convex shape) of the letter "W", but the embodiments of the present disclosure are not limited thereto. The second patterns 340 and 341 may overlap with one or more third patterns 330a, 330b, and 330c. For example, the second patterns 340 and 341 may overlap with one or more third patterns 330a, 330b, and 330c in a vertical direction (or in an up-down direction).

[0201] refer to Figure 15 The fourth structure body CPTd may include one or more first patterns 320a and 320b, and second patterns 340 and 341. The one or more first patterns 320a and 320b and the one or more second patterns 340 and 341 may be provided on different layers, but the embodiments of the present disclosure are not limited thereto.

[0202] One or more first patterns 320a and second patterns 320b may be disposed spaced apart from each other on the first insulating layer 115. Thus, a space may exist between one or more first patterns 320a and second patterns 320b. The first patterns 320a and second patterns 320b may be covered by the second insulating layer 117. The second insulating layer 117 may be disposed on the first patterns 320a and second patterns 320b.

[0203] The second insulating layer 117 may be covered by a protective layer 119. The protective layer 119 may be disposed on the second insulating layer 117. The protective layer 119 may include a first groove G1. The first groove G1 may be formed by the spacing between the first pattern 320a and the second pattern 320b. The third insulating layer 121 may be disposed on the protective layer 119 including the first groove G1. The third insulating layer 121 may include a second groove G2 that overlaps with the first groove G1. For example, the third insulating layer 121 may include a second groove G2 that overlaps with the first groove G1 in a vertical direction (or in a vertical direction).

[0204] The second patterns 340 and 341 may be disposed on the third insulating layer 121. The second patterns 340 and 341 may fill the second groove G2. The second patterns 340 and 341 may be disposed to overlap with the first pattern 320a and the second pattern 320b. For example, the second patterns 340 and 341 may be disposed to overlap with the first pattern 320a and the second pattern 320b in the vertical direction (or in the up-down direction). Therefore, the second patterns 340 and 341 and the third insulating layer 121, the protective layer 119, and the second insulating layer 117 disposed below the second patterns 340 and 341 may have an uneven shape (or a concave-convex shape), but the embodiments of the present disclosure are not limited thereto. For example, the second patterns 340 and 341 and the third insulating layer 121, the protective layer 119, and the second insulating layer 117 disposed below the second patterns 340 and 341 may have an uneven shape (or a concave-convex shape) in a cross-sectional view, but the embodiments of the present disclosure are not limited thereto. For example, the uneven shape (or concavo-convex shape) may have a shape of letter 'V', but embodiments of the present disclosure are not limited thereto.

[0205] According to an embodiment of the present disclosure, each of the structures CPTa, CPTb, CPTc, and CPTd includes a configuration disposed below the dam portion DM or below the first barrier pattern OPT, but the present invention is not limited thereto. For example, each of the structures CPTa, CPTb, CPTc, and CPTd may be disposed both below the dam portion DM and below the first barrier pattern OPT. In this case, the effectiveness of blocking crack propagation paths can be further enhanced. Furthermore, since the crack propagation paths are increased, the crack propagation time can be further delayed.

[0206] The display device according to various embodiments of the present disclosure can be described as follows.

[0207] According to various embodiments of the present disclosure, a display device may include: a display area, which is arranged on a substrate and includes a plurality of light-emitting elements and a plurality of transistors; a non-display area, which surrounds the display area; a first area, which is located within the display area and includes a hole; and a second area, which is located between the first area and the display area and includes a structure.

[0208] According to various embodiments of the present disclosure, the second region may include a dam disposed between the hole and the display region, a plurality of first barrier patterns between the hole and the dam, and a plurality of second barrier patterns between the dam and the display region.

[0209] According to various embodiments of the present disclosure, the structure may be disposed to overlap with at least one of the dam and the plurality of first barrier patterns.

[0210] According to various embodiments of the present disclosure, the structure may be disposed to overlap one of odd-numbered first barrier patterns and even-numbered first barrier patterns among the plurality of first barrier patterns.

[0211] According to various embodiments of the present disclosure, a structure may include one or more first patterns arranged at intervals, a second pattern overlapping with the one or more first patterns, a first insulating layer located between the first pattern and the second pattern and including a first groove arranged to correspond to the interval, and a second insulating layer including a second groove overlapping with the first groove.

[0212] According to various embodiments of the present disclosure, the display device may further include a third pattern that does not overlap with the first pattern and is arranged to correspond to the interval of one or more first patterns. The third pattern may be arranged on a different layer from the first pattern and the second pattern.

[0213] According to various embodiments of the present disclosure, one of the first groove and the second groove may be provided on at least one side of the third pattern.

[0214] According to various embodiments of the present disclosure, one of the first groove and the second groove may include an uneven shape.

[0215] According to various embodiments of the present disclosure, a structure may include one or more third patterns arranged at intervals, a second pattern overlapping with the one or more third patterns, a first insulating layer arranged between the third pattern and the second pattern and including a first groove arranged to correspond to the interval, and a second insulating layer including a second groove overlapping with the first groove.

[0216] According to various embodiments of the present disclosure, the one or more third patterns may include a 3-1 pattern, a 3-2 pattern, and a 3-3 pattern. One of the first groove and the second groove may be provided on both sides of the 3-2 pattern.

[0217] According to various embodiments of the present disclosure, each of the plurality of light emitting elements may include a first electrode, a second electrode, and a light emitting layer between the first electrode and the second electrode.

[0218] According to various embodiments of the present disclosure, each of the first and second barrier patterns may include a lower structure and an upper structure on the lower structure. The light emitting layer may be disposed along a surface of an upper surface of the upper structure excluding sidewalls of the lower structure.

[0219] According to various embodiments of the present disclosure, the light emitting layer may be disconnected at an end portion of an upper structure of one of the first and second barrier patterns.

[0220] According to various embodiments of the present disclosure, the first barrier pattern may be spaced apart from the hole and surround the hole, and the second barrier pattern may be spaced apart from the dam and surround the dam.

[0221] According to various embodiments of the present disclosure, the first barrier pattern, the second barrier pattern, the dam, and the structure body may include a closed curve shape.

[0222] According to various embodiments of the present disclosure, the width of the structure may be smaller than the width of the dam.

[0223] According to various embodiments of the present disclosure, a plurality of transistors may be configured as one of an oxide semiconductor layer and a low-temperature polysilicon semiconductor layer, or a combination thereof.

[0224] The display device according to various embodiments of the present disclosure may further include an encapsulation portion on the light emitting element, and a touch portion on the encapsulation portion.

[0225] According to various embodiments of the present disclosure, at least one or more of a camera, a proximity sensor, a gesture sensor, a color sensor, a biometric sensor, and an infrared sensor may be disposed in the hole.

[0226] The display device according to various embodiments of the present disclosure can be applied to mobile devices, video phones, smart watches, phone watches, wearable devices, foldable devices, scrollable devices, bendable devices, flexible devices, bending devices, sliding devices, variable devices, electronic notepads, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbook computers, workstations, navigation systems, vehicle display devices, cinema display devices, televisions, wallpaper devices, signage devices, gaming devices, laptops, monitors, cameras, camcorders, home appliances, etc.

[0227] It is obvious to those skilled in the art that various modifications and variations can be made in the present disclosure without departing from the scope of the present disclosure. Therefore, the present disclosure is intended to cover modifications and variations of the present disclosure that fall within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: a display area located on the substrate and including a plurality of light-emitting elements and a plurality of transistors; a non-display area, the non-display area surrounding the display area; a first area located in the display area and including a hole; and A second region is located between the first region and the display region and includes a structure.

2. The display device according to claim 1, wherein The second area includes: a dam portion, located between the hole and the display area; a plurality of first barrier patterns located between the hole and the dam; and A plurality of second barrier patterns are located between the dam portion and the display area.

3. The display device according to claim 2, wherein: The structure is disposed to overlap at least one of the dam and the plurality of first barrier patterns.

4. The display device according to claim 2, wherein The structure is disposed to overlap one of odd-numbered first barrier patterns and even-numbered first barrier patterns among the plurality of first barrier patterns.

5. The display device according to claim 1, wherein The structure includes: one or more first patterns arranged at intervals; a second pattern overlapping the one or more first patterns; a first insulating layer located between the first pattern and the second pattern and including a first groove provided to correspond to the interval; and A second insulating layer includes a second groove overlapping the first groove.

6. The display device according to claim 5, further comprising a third pattern that does not overlap with the first pattern and is arranged to correspond to the interval of the one or more first patterns, in, The third pattern is disposed on a different layer from the first pattern and the second pattern.

7. The display device according to claim 6, wherein: One of the first groove and the second groove is disposed on at least one side of the third pattern.

8. The display device according to claim 5, wherein One of the first groove and the second groove includes an uneven shape.

9. The display device according to claim 1, wherein The structure includes: one or more third patterns arranged at intervals; a second pattern overlapping the one or more third patterns; a first insulating layer disposed between the one or more third patterns and the second pattern and including a first groove disposed to correspond to the interval; and A second insulating layer includes a second groove overlapping the first groove.

10. The display device according to claim 9, wherein The one or more third patterns include a 3-1 pattern, a 3-2 pattern, and a 3-3 pattern, and Wherein, one of the first groove and the second groove is arranged on both sides of the 3-2 pattern.

11. The display device according to claim 1, wherein Each of the plurality of light emitting elements includes a first electrode, a second electrode, and a light emitting layer located between the first electrode and the second electrode.

12. The display device according to claim 11, wherein Each of the first barrier pattern and the second barrier pattern includes a lower structure and an upper structure located on the lower structure, and The light emitting layer is provided along the upper surface of the upper structure except for the sidewalls of the lower structure.

13. The display device according to claim 12, wherein: The light emitting layer is disconnected at an end portion of the upper structure of one of the first barrier pattern and the second barrier pattern.

14. The display device according to claim 2, wherein: The first barrier pattern is spaced apart from the hole and surrounds the hole, and the second barrier pattern is spaced apart from the dam and surrounds the dam.

15. The display device according to claim 2, wherein: The first barrier pattern, the second barrier pattern, the dam, and the structure include a closed curve shape.

16. The display device according to claim 2, wherein: The width of the structure is smaller than the width of the dam.

17. The display device according to claim 1, wherein The plurality of transistors are configured as one of an oxide semiconductor layer and a low-temperature polysilicon semiconductor layer, or a combination thereof.

18. The display device according to claim 1, further comprising: a packaging portion located on the light-emitting element; as well as A touch portion is located on the packaging portion.

19. The display device according to claim 1, wherein At least one or more of a camera, a proximity sensor, a gesture sensor, a color sensor, a biosensor and an infrared sensor is disposed in the hole.

20. A display device comprising: a substrate comprising a display area and a non-display area surrounding the display area; a transistor array layer, on the substrate, wherein the transistor array layer has a plurality of transistors formed therein; as well as a light emitting element array layer, on the transistor array layer, The display area includes a plurality of light-emitting elements and a plurality of transistors for driving the plurality of light-emitting elements. The display area includes a first area with a hole formed therein and a second area surrounding the first area, and Wherein, a crack prevention structure is formed in the second area of ​​the display area.

21. The display device according to claim 20, wherein The transistor array layer includes a plurality of insulating layers, and Wherein, the anti-crack structure includes a plurality of patterns respectively arranged on different insulating layers.

22. The display device according to claim 21, wherein The patterns arranged on different insulating layers are staggered in the vertical direction.

23. The display device according to claim 21, wherein The plurality of insulating layers include a first insulating layer and a second insulating layer, wherein the plurality of patterns include a first-first pattern and a first-second pattern spaced apart from each other on the first insulating layer, and a second pattern on the second insulating layer, The second pattern is located at a position corresponding to the interval between the first-first pattern and the first-second pattern.

24. The display device according to claim 23, wherein The second pattern is spaced apart from the first-first pattern and the first-second pattern in a plan view.

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