Display device

Abstract

A display device includes: a substrate having a main region in which a plurality of pixel electrodes spaced apart from each other are positioned and a sub-region on one side of the main region and including a bending region; a plurality of color filters overlapping the pixel electrode on the substrate; a first color pattern on the substrate and partially overlapping the bending region in the sub-region; a first color dam and a second color dam, the first color dam being spaced apart from the first color pattern and in the sub-region, the second color dam being spaced apart from the first color dam; and an overcoat layer on a color filter from among the plurality of color filters and in the main region and the sub-region, where the overcoat layer covers the main region and is inside the second color dam in the sub-region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0024383 filed on February 20, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] An aspect of some embodiments of the present disclosure relates to a display device. Background Art

[0004] As the information-oriented society progresses, more and more demands are being placed on display devices for displaying images in various ways. For example, display devices can be used in various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart televisions. Display devices can be flat panel display devices such as liquid crystal display devices, field emission display devices, and organic light-emitting display devices. Among flat panel display devices, in light-emitting display devices, because each pixel of the display panel includes a light-emitting element that can emit light by itself, it is possible to display images without a backlight unit that provides light to the display panel.

[0005] The above information disclosed in this Background section is only for enhancement of understanding of the background and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the Invention

[0006] Aspects of some embodiments of the present disclosure include a display device including an overcoat layer formed by an inkjet printing process and a dam formed of the same layer as a color filter.

[0007] Aspects of some embodiments of the present disclosure include a display device having a structure with a shortened manufacturing process.

[0008] However, aspects of the embodiments according to the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0009] According to some embodiments of the present disclosure, a display device includes: a substrate having a main area and a sub-area, a plurality of pixel electrodes spaced apart from each other are positioned in the main area, the sub-area is on one side of the main area and includes a bending area; a plurality of color filters overlapping with the pixel electrodes on the substrate; a first color pattern partially overlapping with the bending area on the substrate and in the sub-area; a first color dam and a second color dam, the first color dam being spaced apart from the first color pattern and the first color dam being in the sub-area, the second color dam being spaced apart from the first color dam; and an outer coating on a color filter from among the plurality of color filters and in the main area and the sub-area, wherein the outer coating covers the main area and is inside the second color dam in the sub-area.

[0010] According to some embodiments, each of the first color pattern, the first color dam, and the second color dam includes the same material as the color filter.

[0011] According to some embodiments, a portion of the first color pattern is between the bending regions of the main region and the sub-region, and the first color dam is spaced apart from the first color pattern outside the bending region.

[0012] According to some embodiments, the overcoat layer overlaps the first color pattern in the subregion, or the overcoat layer fills a first valley portion formed between the first color dam and the first color pattern and on an inner portion of the first color dam.

[0013] According to some embodiments, the display device may further include: a bending protection layer on the outer coating layer and overlapping the bending region.

[0014] According to some embodiments, the display device may further include: a bending structure including a plurality of via layers in a bending region and wiring layers between the via layers, wherein at least a portion of the first color pattern covers the bending structure.

[0015] According to some embodiments, the first color pattern completely covers the bending structure.

[0016] According to some embodiments, the overcoat fills a first valley portion formed between the first color dam and the first color pattern and on an inner portion of the first color dam.

[0017] According to some embodiments, a portion of the first color pattern is outside the bending area of ​​the sub-region, the first color dam is between the bending area and the main region, and the second color dam is between the first color dam and the bending area.

[0018] According to some embodiments, the outer coating does not overlap the first color pattern.

[0019] According to some embodiments, the outer coating is on the interior of the first color dam.

[0020] According to some embodiments, each of the first and second color dams has a width in the range of 30 μm to 60 μm, and a valley portion formed between the first and second color dams has a width in the range of 30 μm to 60 μm.

[0021] According to some embodiments, the display device does not include a polarizing plate.

[0022] According to some embodiments, the display device may further include a light blocking layer in the main region and including a plurality of holes overlapping the plurality of pixel electrodes, wherein the plurality of color filters respectively overlap the plurality of holes of the light blocking layer.

[0023] According to some embodiments, a plurality of color filters overlap each other on the light blocking layer.

[0024] According to some embodiments, among the plurality of color filters, different color filters adjacent to each other overlap each other, and the display device further includes a plurality of color light blocking layers in regions where the different color filters overlap.

[0025] According to some embodiments of the present disclosure, a display device includes: a main area and a sub-area, a plurality of pixel electrodes arranged in a first direction and a second direction are positioned in the main area, the sub-area is on one side of the main area in the first direction and a bending area is formed in the sub-area; a light blocking layer, including a plurality of holes overlapping with the plurality of pixel electrodes in the main area; a plurality of color filters on the light blocking layer and corresponding to the plurality of holes, respectively; a first color pattern, in the sub-area and at least partially overlapping with the bending area; a first color dam and a second color dam, the first color dam is in the sub-area and spaced apart from the first color pattern, and the second color dam is spaced apart from the first color dam; and an outer coating covering a portion of the sub-area and the main area, wherein each of the first color pattern, the first color dam, and the second color dam is on the same layer as one of the color filters, and the outer coating is inside at least one of the first color dam and the second color dam in the sub-area.

[0026] According to some embodiments, a portion of the first color pattern is between the bending region of the main region and the sub-region, and the first color dam is outside the bending region.

[0027] According to some embodiments, a portion of the first color pattern is outside the bending area of ​​the sub-region, the first color dam is between the bending area and the main region, and the second color dam is between the first color dam and the bending area.

[0028] According to some embodiments, the light blocking layer includes at least one groove formed on an outer side of the hole and penetrating the light blocking layer.

[0029] In a display device according to some embodiments, an overcoat layer can be formed by an inkjet printing process, and a dam that prevents or reduces overcoat layer overflow can be formed of the same material as the color filter. Therefore, by reducing the number of mask processes used to form the dam and overcoat layer, the display device can have a relatively shortened manufacturing process.

[0030] However, the effects according to the embodiments of the present disclosure are not limited to the above-described effects, and various other effects are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects and features according to embodiments of the present disclosure will become more apparent by describing aspects of some embodiments of the present disclosure in more detail with reference to the accompanying drawings, in which:

[0032] Figure 1 is a schematic perspective view of an electronic device according to some embodiments;

[0033] Figure 2 is a perspective view illustrating a display device included in an electronic device according to some embodiments;

[0034] Figure 3 yes Figure 2 a cross-sectional view of a display device viewed from the side;

[0035] Figure 4 yes Figure 2 A plan view of a display device;

[0036] Figure 5 is a plan view illustrating an arrangement of holes of a light blocking layer and pixel electrodes in a display area of ​​a display device according to some embodiments;

[0037] Figure 6 is a plan view showing the arrangement of color filters and pixel electrodes in a display area of ​​a display device according to some embodiments;

[0038] Figure 7 is a cross-sectional view of a display device according to some embodiments;

[0039] Figure 8 is a plan view illustrating an arrangement of a color filter layer in a single cell unit of a display device according to some embodiments;

[0040] Figure 9 It is along Figure 8 A cross-sectional view taken along line XX';

[0041] Figure 10 is a cross-sectional view illustrating a bending region of a display device according to some embodiments;

[0042] Figure 11is a plan view showing an arrangement of a color filter layer in a single unit of a display device according to some embodiments;

[0043] Figure 12 It is along Figure 11 A cross-sectional view taken along line X1-X1';

[0044] Figure 13 is a plan view showing an arrangement of a color filter layer in a single unit of a display device according to some embodiments;

[0045] Figure 14 It is along Figure 13 A cross-sectional view taken along line X2-X2';

[0046] Figure 15 is a plan view illustrating an opening in a light blocking layer of a display device according to some embodiments;

[0047] Figures 16 to 18 is a cross-sectional view of a display device according to some embodiments; and

[0048] Figure 19 is a plan view illustrating the arrangement of openings of a pixel defining layer and color filters in a display area of ​​a display device according to some embodiments. DETAILED DESCRIPTION

[0049] Aspects of some embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, which illustrate aspects of some embodiments of the present disclosure. However, the present invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art.

[0050] It will also be understood that when a layer or substrate is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Throughout the specification, like reference numerals refer to like components.

[0051] Hereinafter, aspects of some embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0052] Figure 1 is a schematic perspective view of an electronic device according to some embodiments.

[0053] Reference Figure 1, the electronic device 1 displays a moving image (e.g., a video image) or a still image (e.g., a static image). The electronic device 1 may refer to any electronic device that provides a display screen. Examples of the electronic device 1 may include a television set including a display screen, a laptop computer, a monitor, a billboard, an IoT device, a mobile phone, a smartphone, a tablet personal computer (PC), an electronic watch, a smartwatch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, a game console, a digital camera, a video camera, and the like.

[0054] The electronic device 1 may include Figure 2 A display device 10 is provided for providing a display screen. Examples of the display device 10 may include an inorganic light-emitting diode display device, an organic light-emitting display device, a quantum dot light-emitting display device, a plasma display device, and a field emission display device. In the following description, an organic light-emitting diode display device is used as the display device 10. However, the embodiments of the present disclosure are not limited thereto, and other display devices may be applied within the scope of the same technical spirit.

[0055] The shape of the electronic device 1 can be modified in various ways. For example, the electronic device 1 can have a planar shape such as a horizontally elongated rectangle, a vertically elongated rectangle, a square, a quadrilateral with rounded corners (vertices), other polygonal shapes, and a circular shape. The shape of the display area DA of the electronic device 1 can also be similar to the overall shape of the electronic device 1. Figure 1 The electronic device 1 is shown having a rectangular shape elongated in the second direction DR2 .

[0056] The electronic device 1 may include a display area DA and a non-display area NDA. The display area DA is an area where images can be displayed, and the non-display area NDA is an area where images are not displayed. The display area DA may also be referred to as an active area, and the non-display area NDA may also be referred to as a non-active area. The display area DA may substantially occupy the center of the electronic device 1.

[0057] The display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3. The second display area DA2 and the third display area DA3 are areas where components for adding various functions to the electronic device 1 are located, and the second display area DA2 and the third display area DA3 may correspond to component areas.

[0058] Figure 2 is a perspective view illustrating a display device included in an electronic device according to some embodiments.

[0059] Reference Figure 2, according to some embodiments of the electronic device 1 (see Figure 1 ) may include a display device 10. The display device 10 may provide a screen displayed by the electronic device 1. The display device 10 may have a planar shape similar to the planar shape of the electronic device 1. For example, the display device 10 may have a planar shape similar to a rectangular shape having short sides in the first direction DR1 and long sides in the second direction DR2. The edge where the short sides in the first direction DR1 and the long sides in the second direction DR2 meet may be rounded to have a curvature, but is not limited thereto, and may be formed at a right angle. The planar shape of the display device 10 is not limited to a quadrilateral shape, and may be formed in a shape similar to another polygonal shape, a circular shape, or an elliptical shape.

[0060] The display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , and a touch driver 400 .

[0061] The display panel 100 (or the display device 10 ) may include a main area MA and a sub-area SBA.

[0062] The main area MA may include a display area DA and a non-display area NDA. The display area DA includes pixels PX displaying an image (see FIG. Figure 4 ), the non-display area NDA is arranged around the display area DA. The display area DA can be positioned at the center of the main area MA, and the non-display area NDA can surround the display area DA (for example, at the periphery of the display area DA or outside the occupied area of ​​the display area DA). The display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3. The display area DA may emit light from a plurality of emission areas or a plurality of opening areas. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining an emission area or an opening area, and a self-luminous element.

[0063] For example, the self-luminous element may include at least one of an organic light-emitting diode (LED) including an organic light-emitting layer, a quantum dot LED including a quantum dot light-emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but the embodiments of the present disclosure are not limited thereto.

[0064] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a gate driver that supplies gate signals to gate lines and a fan-out line that connects the display driver 200 to the display area DA.

[0065] The sub-area SBA may be an area extending from one side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded, or curled. For example, when the sub-area SBA is bent, the sub-area SBA may overlap with the main area MA in the thickness direction (third direction DR3). The sub-area SBA may include a display driver 200 and a pad portion connected to the circuit board 300. According to some embodiments, the sub-area SBA may be omitted, and the display driver 200 and the pad portion may be arranged in the non-display area NDA.

[0066] The display driver 200 can output signals and voltages for driving the display panel 100. The display driver 200 can supply data voltages to the data lines. The display driver 200 can supply power voltages to the power lines and can supply gate control signals to the gate driver. The display driver 200 can be formed as an integrated circuit (IC) and mounted on the display panel 100 by a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic bonding method. For example, the display driver 200 can be positioned in the sub-area SBA and can overlap with the main area MA in the thickness direction by bending the sub-area SBA. For another example, the display driver 200 can be mounted on the circuit board 300.

[0067] The circuit board 300 may be attached to the pad portion of the display panel 100 using an anisotropic conductive film (ACF). Leads of the circuit board 300 may be electrically connected to the pad portion of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0068] The touch driver 400 may be mounted on the circuit board 300. The touch driver 400 may be connected to the touch sensing unit of the display panel 100. The touch driver 400 may supply a touch drive signal to the multiple touch electrodes of the touch sensing unit and may sense the change in capacitance between the multiple touch electrodes. For example, the touch drive signal may be a pulse signal having a frequency (e.g., a set frequency or a predetermined frequency). The touch driver 400 may calculate whether an input has been made and the input coordinates based on the change in capacitance between the multiple touch electrodes. The touch driver 400 may be formed as an integrated circuit (IC).

[0069] Figure 3 yes Figure 2 sectional view of a display device viewed from the side. Figure 3 Shown in folded state Figure 2 The sub-area SBA of the display panel 100 in the display device 10 is shown.

[0070] Reference Figure 3The display panel 100 may include a display layer DU, a touch sensing layer TSU, a color filter layer CFL, and a cover window WU. The display layer DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL.

[0071] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or rolled. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but embodiments of the present disclosure are not limited thereto. According to some embodiments, the substrate SUB may include a glass material or a metal material.

[0072] The thin film transistor layer TFTL may be positioned on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors constituting pixel circuits of the pixels. The thin film transistor layer TFTL may also include gate lines, data lines, power lines, gate control lines, fan-out lines connecting the display driver 200 to the data lines, and leads connecting the display driver 200 to the pad portion. Each thin film transistor may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when a gate driver is formed on one side of the non-display area NDA of the display panel 100, the gate driver may include a thin film transistor.

[0073] The thin film transistor layer TFTL may be positioned in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistors, gate lines, data lines, and power lines of each pixel of the thin film transistor layer TFTL may be positioned in the display area DA. The gate control lines and fan-out lines of the thin film transistor layer TFTL may be positioned in the non-display area NDA. Lead lines of the thin film transistor layer TFTL may be positioned in the sub-area SBA.

[0074] The light-emitting element layer (EML) may be positioned on the thin film transistor layer (TFTL). The light-emitting element layer (EML) may include a plurality of light-emitting elements, each including a first electrode, a second electrode, and a light-emitting layer for emitting light, and a pixel-defining layer defining pixels. The plurality of light-emitting elements of the light-emitting element layer (EML) may be positioned in the display area (DA).

[0075] According to some embodiments, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the first electrode receives a voltage through the thin film transistor of the thin film transistor layer TFTL and the second electrode receives a cathode voltage, holes and electrons may be respectively transferred to the organic light-emitting layer through the hole transport layer and the electron transport layer, and may be combined with each other to emit light in the organic light-emitting layer.

[0076] According to some embodiments, the light emitting element may include a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, or a micro light emitting diode.

[0077] The encapsulation layer TFEL may cover the top and side surfaces of the light emitting element layer EML and may protect the light emitting element layer EML. The encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer for encapsulating the light emitting element layer EML.

[0078] The touch sensing layer TSU may be positioned on the encapsulation layer TFEL. The touch sensing layer TSU may include a plurality of touch electrodes for capacitively sensing a user's touch, and touch lines connecting the plurality of touch electrodes to the touch driver 400. For example, the touch sensing layer TSU may sense a user's touch using a mutual capacitance method or a self-capacitance method.

[0079] According to some embodiments, the touch sensing layer TSU may be positioned on a separate substrate located on the display layer DU. In this case, the substrate supporting the touch sensing layer TSU may be a base member encapsulating the display layer DU.

[0080] The plurality of touch electrodes of the touch sensing layer TSU may be positioned in a touch sensor area overlapping the display area DA, and the touch lines of the touch sensing layer TSU may be positioned in a touch peripheral area overlapping the non-display area NDA.

[0081] The color filter layer CFL may be positioned on the touch sensing layer TSU. The color filter layer CFL may include a plurality of color filters corresponding to the plurality of emission areas, respectively. Each of the color filters may selectively transmit light of a specific wavelength and may block or absorb light of different wavelengths. The color filter layer CFL may absorb a portion of the light from outside the display device 10 to reduce reflected light due to external light. Therefore, the color filter layer CFL may prevent or reduce color distortion caused by reflection of external light. In some embodiments, the display device 10 may not form a polarizing plate on the front surface of the display panel 100, and a pixel defining layer PDL (see FIG. 1 ) of the display panel 100, which will be described later, may be formed with a black organic material. Figure 7 ), and a color filter layer CFL may be formed over the pixel defining layer PDL, so that although external light enters the inside, it is possible to prevent or reduce the situation where the external light is reflected from the electrode, etc. to be transmitted to the user.

[0082] Since the color filter layer CFL is directly positioned on the touch sensing layer TSU, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 may be relatively small.

[0083] In some embodiments, the display device 10 may further include an optical device 500. The optical device 500 may be positioned in the second display area DA2 or the third display area DA3. The optical device 500 may transmit or receive light in the infrared band, the ultraviolet band, and the visible light band. For example, the optical device 500 may be an optical sensor that detects light incident on the display device 10, such as a proximity sensor, an illumination sensor, a camera sensor, or an image sensor.

[0084] The cover window WU may be positioned on the color filter layer CFL. The cover window WU may include a window WIN and an anti-reflection layer ARL.

[0085] The window WIN may be positioned on the light blocking layer and the color filter layer CFL and may be attached to the light blocking layer and the color filter layer CFL using a transparent adhesive. The window WIN may be used to protect the display panel 100. The window WIN may be made of a transparent material. The window WIN may be made of, for example, glass or plastic.

[0086] When the window WIN is glass, the glass may be ultra-thin glass (UTG) or thin glass. Ultra-thin glass can be strengthened to have a predetermined stress profile therein. Strengthened ultra-thin glass effectively prevents or reduces crack initiation, crack propagation, and breakage caused by external impacts compared to pre-strengthened ultra-thin glass. Ultra-thin glass strengthened through a strengthening process can have different stress levels in each zone.

[0087] When the glass is ultrathin glass or thin glass, the glass may have flexible properties so that it can be bent, curved, folded or curled. The thickness of the glass may be, for example, in the range of 10 micrometers (μm) to 300 μm, in particular, in the range of 10 μm to 100 μm, or about 50 μm. The glass of the window WIN may include soda-lime glass, alkali-aluminosilicate glass, borosilicate glass or lithium-aluminosilicate glass. The glass of the window WIN may include chemically strengthened glass or heat-strengthened glass to have strong rigidity. Chemical strengthening can be achieved by an ion exchange process in an alkaline salt. The ion exchange process can be performed two or more times. In addition, the window WIN can be obtained by coating a glass film on both surfaces of a polymer film.

[0088] The anti-reflection layer ARL may be located in front of the window WIN, and the anti-reflection layer ARL may be attached to the front surface of the window WIN in the form of an optical film.

[0089] An anti-reflection layer ARL may be positioned on the window WIN. The anti-reflection layer ARL may protect the window WIN and reduce reflection of external light.

[0090] The anti-reflection layer (ARL) may include a hard coating layer and a low-refractive layer. These two layers may be formed so that the two layers, having different refractive indices, cause loss of external light or destructive interference at the boundary surface, thereby preventing or reducing the reflection of external light. The low-refractive layer may include particles dispersed in a transparent resin. In some embodiments, a high-refractive layer may also be included, and the high-refractive layer may be located between the hard coating layer and the low-refractive layer.

[0091] The hard coating layer, the low-refractive layer, and / or the high-refractive layer that may be included in the anti-reflection layer ARL may have the following characteristics.

[0092] The hard coating layer may reduce a warping or lifting phenomenon of the anti-reflection layer ARL under severe conditions such as high temperature and high humidity, and thus may improve reliability issues.

[0093] The hard coating layer may include an organic layer. The organic layer may include at least one of acrylate compounds, polyurethane compounds, polyimide, polycarbonate, polyethersulfone, polyethylene naphthalate, polyphenylene sulfide, liquid crystal polymer (LCP), polymethyl methacrylate, and epoxy polymers, or a combination thereof.

[0094] According to some embodiments, the hard coating layer may include an organic layer and an organic-inorganic composite layer. In this case, the organic layer may include an acrylate compound. For example, the organic layer may be formed to include urethane acrylate. The organic layer may serve as a stress buffer layer.

[0095] The organic material in the organic-inorganic composite layer may be formed from at least one of an acrylate compound, a polyurethane compound, and an epoxy polymer, or a combination thereof. For example, the organic material may include urethane acrylate. The inorganic material in the organic-inorganic composite layer may be at least one selected from the group consisting of silicon oxide (SiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), niobium oxide (Nb2O5 or NbO2), and glass beads.

[0096] The inorganic material can be provided in the form of a single type of inorganic oxide listed above or a mixture thereof. In addition, the inorganic material can be provided in various forms to form an organic-inorganic composite layer. For example, silicon oxide can be provided in the form of particles, sols, or hollow shapes.

[0097] In the organic-inorganic composite layer, an acrylate compound and inorganic particles as organic materials can be provided by mixing them in a weight ratio of 5: 5 to 8: 2. By including both the acrylate compound and the inorganic particles, the organic-inorganic composite layer can improve surface hardness and have impact absorption against external impact, and thus can form a hard coating layer that is not easily damaged.

[0098] According to some embodiments, the hard coating layer may include an acrylate compound and a polyurethane compound. The acrylate compound and the polyurethane compound may be mixed and polymerized in monomer form. The acrylate compound may increase the hardness and abrasion resistance of the anti-reflection layer (ARL) by increasing the hardness of the low-refractive layer. The polyurethane compound may increase the elasticity of the anti-reflection layer (ARL) by providing flexibility to the low-refractive layer. In this case, the weight ratio of the acrylate compound in the hard coating layer may be 70% to 99.9%, and the weight ratio of the polyurethane compound may be 0.1% to 30%. For example, the weight ratio of the acrylate compound to the polyurethane compound may be 7:3 or greater, and the weight ratio of the acrylate compound may be further increased. For example, in the weight ratio of the acrylate compound to the polyurethane compound, the weight ratio of the acrylate compound may be further increased, such as 7:3, 8:2, or 9:1.

[0099] According to some embodiments, the hard coating layer may include an acrylate compound. In this case, the acrylate compound may be an acrylic resin. That is, the hard coating layer may improve the hardness and wear resistance of the anti-reflection layer (ARL) by including the acrylic resin.

[0100] The hard coating layer may have a thickness of 2 μm to 10 μm. The hard coating layer may be configured in the above-mentioned thickness range, and thus a warping or lifting phenomenon may be reduced, so that reliability issues may be improved.

[0101] The hard coating layer may have a refractive index of 1.48 to 1.53. The hard coating layer may be configured in the above refractive index range and thus have a refractive index difference at the interface with the low-refractive layer, which will be described in more detail later, and may refract light emitted from the light-emitting element layer upward to improve light emission efficiency and reduce reflection of external light.

[0102] The low-refractive layer may be positioned on the hard coating layer. The low-refractive layer may refract light emitted from the light-emitting element layer upward to improve light emission efficiency and reduce reflection of external light.

[0103] The low-refractive layer may include particles dispersed in a transparent resin.

[0104] The resin may include one or more selected from the group consisting of acrylic, polysiloxane, polyurethane, polyurethane acrylate, polyimide, polymethylsilsesquioxane (PMSQ), and polymethyl methacrylate (PMMA).

[0105] The particles may be hollow particles. For example, the particles may include one or more selected from the group consisting of silicon dioxide (SiO2), magnesium fluoride (MgF2), and iron oxide (Fe3O4). In addition, the particles may include a shell made of one or more of the above materials and a hollow space in the shell. According to some embodiments, the particles may have a diameter of 10 nm to 200 nm, and the diameter of the particle may determine the thickness of the shell and the diameter of the hollow space.

[0106] The particles may be included in the low-refractive layer at a weight ratio of 10% to 50% relative to the resin. When the weight ratio of the particles to the resin is 10% or greater, the refractive index of the low-refractive layer can be reduced. When the weight ratio of the particles to the resin is 50% or less, adhesion to adjacent layers and degradation can be prevented or reduced. The low-refractive layer can be formed by applying and curing a solution containing a solvent in which the resin and particles are dispersed.

[0107] The thickness of the low-refractive layer may be 10 nm to 200 nm. The low-refractive layer may be configured in the above-mentioned thickness range, and thus may include sufficient particles to lower the refractive index and improve the adhesive strength with the lower layer.

[0108] The refractive index of the low-refractive layer can be less than the refractive index of the hard coating layer. For example, the refractive index of the low-refractive layer can be at least 0.05 less than the refractive index of the hard coating layer. When the difference between the refractive index of the low-refractive layer and the refractive index of the hard coating layer is 0.05 or greater, the total reflection of external light at the interface between the low-refractive layer and the hard coating layer can increase, which can cause destructive interference with the light reflected from the surface of the low-refractive layer. Therefore, the reflectivity of external light of the anti-reflection layer ARL can be reduced. The refractive index of the low-refractive layer can be in the range of 1.3 to 1.43. However, the embodiments according to the present disclosure are not limited thereto, and the low-refractive layer can use a lower refractive index within a range smaller than the refractive index of the hard coating layer.

[0109] Meanwhile, the high-refractive layer may include an inorganic material, an organic material, or an inorganic material and an organic material. Therefore, the high-refractive layer may be formed of an inorganic layer, an organic layer, or an organic layer containing inorganic particles.

[0110] The inorganic material contained in the high refractive layer may be one or more selected from the group consisting of zinc oxide, titanium oxide, zirconium oxide, niobium oxide, tantalum oxide, tin oxide, nickel oxide, silicon oxide, silicon nitride, indium nitride, and gallium nitride.

[0111] The organic material contained in the high refractive layer may be selected from poly (3,4-ethylenedioxythiophene) (PEDOT), 4,4'-bis [N- (3-methylphenyl) -N-phenylamino] biphenyl (TPD), 4,4',4"-tris [(3-methylphenyl) phenylamino] triphenylamine (m-MTDATA), 1,3,5-tris [N,N-bis (2-methylphenyl) -amino] -benzene (o-MTDAB), 1,3,5-tris [N,N-bis (3-methylphenyl) -amino] -benzene (m-MTDAB), 1,3,5-tris [N,N-bis (4- One or more of the group consisting of 1,2-diphenyl-2-nitropropene (1,2,4-dimethylphenyl)-1,2,4-triphenylamine (1,3,5-benzenetriyl)-tris[1-phenyl-1H-benzimidazole] (TPBI) and 3-(4-biphenyl)-4-phenyl-5-tert-butylphenyl-1,2,4-triazole (TAZ).

[0112] The refractive index of the high refractive layer may be greater than that of the low refractive layer to reduce reflection of external light. For example, the refractive index of the high refractive layer may be at least 0.05 greater than that of the low refractive layer. The refractive index of the high refractive layer may be in the range of 1.53 to 1.7. However, the embodiments of the present disclosure are not limited thereto, and the low refractive layer may have a larger refractive index within a range greater than that of the low refractive layer.

[0113] The high refractive layer may have a thickness of 50 to 200 nanometers. The high refractive layer may be configured in the above thickness range, and thus may form a flat interface with the low refractive layer and prevent or reduce a decrease in bonding strength with the hard coating layer.

[0114] The anti-reflection layer ARL further including a high-refractive layer may further reduce reflection of external light by increasing a difference in refractive index at an interface with the low-refractive layer.

[0115] According to some embodiments, the front surface of the window WIN may include another optical film in addition to the anti-reflection layer (ARL), and may also include an anti-fingerprint layer. However, a polarizing plate may not be included, as the light-blocking layer and color filter layer (CFL), described later, can reduce the reflectivity of external light and make it less visible to the user. Therefore, according to some embodiments, the anti-reflection layer (ARL) may not be included on the front surface of the window WIN.

[0116] Figure 4 yes Figure 2 A plan view of a display device. Figure 4The display device 10 is shown in an unbent and unfolded state.

[0117] Reference Figure 4 The display device 10 may include a main area MA and a sub-area SBA. The main area MA may include a display area DA and a non-display area NDA, and the sub-area SBA may include a bank area BNKA, a driving circuit mounting area ICA, and a pad area PA.

[0118] The display area DA may be an area where a plurality of pixels PX are located. The pixels PX and wirings (or some of the wirings) connected to the pixels PX may be located in the display area DA.

[0119] The pixel PX may be provided on the thin film transistor layer TFTL (see FIG. Figure 3 ) and the light emitting element layer EML (see Figure 3 As an example, each of the pixels PX may include a pixel circuit including circuit elements positioned in the thin film transistor layer TFTL and a light emitting element (eg, Figure 7 The light-emitting element ED in the device).

[0120] The pixel PX may include at least two color emission areas EA that emit light of different colors. For example, the pixel PX may include a first color emission area that emits light of a first color (e.g., red light), a second color emission area that emits light of a second color (e.g., green light), and a third color emission area that emits light of a third color (e.g., blue light).

[0121] At least one first color emission area, at least one second color emission area, and at least one third color emission area adjacent to each other may constitute a unit pixel PX (i.e., pixel PX). For example, one first color emission area, two second color emission areas, and one third color emission area adjacent to each other may constitute a unit pixel PX. Each unit pixel PX may emit light of various colors (including white light) by mixing the colors of the light emitted from the emission areas EA constituting the unit pixel PX. According to some embodiments, the first color emission areas and the third color emission areas may be alternately arranged in the first direction DR1 and / or the second direction DR2, and the second color emission areas may be arranged continuously and / or sequentially in the first direction DR1. The type, shape, and / or arrangement structure of the emission area EA may vary depending on the embodiment. In addition, the type, number, ratio, and / or arrangement structure of the emission areas EA constituting each of the unit pixels PX may also vary depending on the embodiment.

[0122] Encapsulation layer TFEL (see Figure 3) may be positioned on the pixel PX. For example, the encapsulation layer TFEL may be provided at least in the display area DA to cover the pixel PX, and a portion of the encapsulation layer TFEL may extend into the non-display area NDA.

[0123] A plurality of wirings may be provided in the thin film transistor layer TFTL and may be located in the display area DA and the non-display area NDA. Furthermore, the wirings may also be located in the sub-area SBA. For example, the wirings may extend from the sub-area SBA through the non-display area NDA to the display area DA.

[0124] The non-display area NDA may be positioned around the display area DA. For example, the non-display area NDA may be an edge area of ​​the main area MA located outside the display area DA.

[0125] The non-display area NDA may include a dam area DAMA spaced apart from the display area DA, a first non-display area NA1 between the display area DA and the dam area DAMA, and a second non-display area NA2 outside the dam area DAMA. The dam area DAMA may be an area where a dam surrounding the display area DA is located. The second non-display area NA2 may include an inorganic encapsulation area IEA (also referred to as a "bonding area") where the inorganic encapsulation layers of the encapsulation layer TFEL are bonded to each other.

[0126] The sub-area SBA may include a bank area BNKA, a drive circuit mounting area ICA, and a pad area PA sequentially arranged on one side of the main area MA. Wiring (or a portion of the wiring), the bank, and the pad PD may be positioned in the sub-area SBA. At least some of the wiring may extend into the main area MA and connect to the pixel PX.

[0127] The bank area BNKA may be an area in which at least one bank is positioned. According to some embodiments, the bank area BNKA may overlap with the bending area BA. For example, the bank area BNKA may include a bending area BA spaced apart from the main area MA, and a first edge area BEA1 and a second edge area BEA2 located on both sides of the bending area BA in the second direction DR2. Banks may be provided in the bending area BA and peripheral areas of the bending area BA (e.g., the first edge area BEA1 and the second edge area BEA2 of the bank area BNKA) to cover wiring passing through the bending area BA. The display device 10 may be bent in the bending area BA so that a portion of the sub-area SBA may be located behind the main area MA. The display device 10 according to some embodiments may include a first color pattern CFP1 (see Figure 8 ), the first color pattern CFP1 is positioned in the bank area BNKA and is aligned with the color filter layer CFL (see Figure 3) includes the same material. In the display device 10, the color filter is positioned in the bank area BNKA and prevents or reduces the overcoat layer OC (see Figure 7 ) overflow can be positioned on the same layer as the color filter. The display device 10 can form the first color pattern CFP1 used as a bank in the process of forming the color filter, and the manufacturing process can be shortened. The first color pattern CFP1 positioned in the sub-area SBA will be described in more detail later.

[0128] The driving circuit mounting area ICA may be an area in which the display driver 200 is positioned. Pads for connecting at least some of the wirings to the display driver 200 may be positioned in the driving circuit mounting area ICA. For example, input pads for connecting the display driver 200 to specific pads (e.g., data input pads) of the pad area PA and output pads for connecting the display driver 200 to the pixels PX may be positioned in the driving circuit mounting area ICA.

[0129] According to some embodiments, the display driver 200 may not be positioned on the display device 10. In this case, the display device 10 may not include the driving circuit mounting area ICA, and only wirings may be positioned in the area between the bank area BNKA and the pad area PA.

[0130] The pad area PA may be located to connect the display device 10 and / or the display driver 200 to the circuit board 300 (see FIG. Figure 3 ) etc. The circuit board 300 may be arranged or bonded on the pad area PA.

[0131] A plurality of pads PD including power pads and signal pads connected to the pixels PX, the display driver 200, and / or the embedded circuits may be positioned in the pad area PA. Power voltages for driving the pixels PX, the display driver 200, and / or the embedded circuits, etc. may be supplied to the power pads. Drive signals and / or image data for driving the pixels PX, the display driver 200, and / or the embedded circuits, etc. may be supplied to the signal pads. The type, position, arrangement order, and / or number of the pads PD may be variously changed according to the embodiment.

[0132] Figure 5 is a plan view illustrating an arrangement of holes of a light blocking layer and pixel electrodes in a display region of a display device according to some embodiments. Figure 6 is a plan view illustrating the arrangement of color filters and pixel electrodes in a display area of ​​a display device according to some embodiments. Figure 5 and Figure 6 The pixel electrodes AE1, AE2, and AE3 and the light blocking layer BM (see FIG. 1 ) positioned in the first display area DA1 are shown. Figure 7 )The arrangement of holes OPT1, OPT2 and OPT3 in.

[0133] Reference Figure 5 and Figure 6 The display device 10 may include a display area DA (see Figure 4 ) (eg, a plurality of pixel electrodes AE1, AE2, and AE3 in the first display area DA1). The plurality of pixel electrodes AE1, AE2, and AE3 may be arranged in a manner Type (e.g., diamond For example, the plurality of pixel electrodes AE1, AE2, and AE3 may be arranged in a fourth direction DR4 and a fifth direction DR5, where the fourth direction DR4 and the fifth direction DR5 are diagonal directions between the first direction DR1 and the second direction DR2. The first pixel electrode AE1 and the second pixel electrode AE2 may be positioned adjacent to each other in the fifth direction DR5, and the second pixel electrode AE2 and the third pixel electrode AE3 may be positioned adjacent to each other in the fourth direction DR4. The first pixel electrode AE1 and the second pixel electrode AE3 may be arranged to be spaced apart from each other in the second direction DR2. In the arrangement of the pixel electrodes AE1, AE2, and AE3, in the first row R1 and the third row R3, the first pixel electrode AE1 and the third pixel electrode AE3 may be alternately arranged in the first direction DR1. In the first column C1 and the third column C3, the first pixel electrode AE1 and the third pixel electrode AE3 may be alternately arranged in the second direction DR2. In the second row R2 and the fourth row R4 , the second pixel electrodes AE2 may be repeatedly arranged in the first direction DR1 , and in the second column C2 and the fourth column C4 , the second pixel electrodes AE2 may be repeatedly arranged in the second direction DR2 .

[0134] The plurality of pixel electrodes AE1, AE2 and AE3 may span the entire display area DA. Figure 5 A pixel PX (see Figure 4 ) may include one first pixel electrode AE1, two second pixel electrodes AE2, and one third pixel electrode AE3. However, the embodiments of the present disclosure are not limited thereto. The number of pixel electrodes AE1, AE2, and AE3 positioned in the pixel PX may vary.

[0135] Each of the pixel electrodes AE1, AE2, and AE3 may be an anode electrode of a light emitting element included in the pixel PX. One pixel PX may include one or more light emitting elements ED (see Figure 7), and the light-emitting element ED may be a light-emitting element ED that emits light of different colors. For example, a light-emitting element including a first pixel electrode AE1 may emit a red first light. A light-emitting element including a second pixel electrode AE2 may emit a green second light, and a light-emitting element including a third pixel electrode AE3 may emit a blue third light. However, the embodiments according to the present disclosure are not limited thereto. One first pixel electrode AE1, two second pixel electrodes AE2, and one third pixel electrode AE3 may form one pixel PX, and may emit different colors and represent a grayscale of white. However, the embodiments according to the present disclosure are not limited thereto, and the combination of pixel electrodes AE1, AE2, and AE3 constituting one pixel PX may be modified in various ways depending on the arrangement of the pixel electrodes AE1, AE2, and AE3 and the color of the light emitted by the pixel electrodes AE1, AE2, and AE3.

[0136] Each of the pixel electrodes AE1, AE2, and AE3 may form an emission region in each pixel PX. For example, the first pixel electrode AE1 may form a first emission region that emits light of a first color, the second pixel electrode AE2 may form a second emission region that emits light of a second color, and the third pixel electrode AE3 may form a third emission region that emits light of a third color. According to some embodiments, the emission region of the display device 10 may be a region overlapping with the pixel electrodes AE1, AE2, and AE3, and for example, Figure 7 The pixel definition layer PDL shown in Figure 7 ) may correspond to the emission regions. For example, each of the emission regions may be formed by a light emitting element layer EML (see FIG. 1 ) which will be described in more detail later. Figure 7 ) of the pixel definition layer PDL (see Figure 7 ). The first emission region may be defined by a first opening in the pixel defining layer PDL that overlaps with the first pixel electrode AE1, the second emission region may be defined by a second opening in the pixel defining layer PDL that overlaps with the second pixel electrode AE2, and the third emission region may be defined by a third opening in the pixel defining layer PDL that overlaps with the third pixel electrode AE3.

[0137] According to some embodiments, the areas or sizes of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be different from each other. Figure 5In the embodiment of the present invention, the area of ​​the third pixel electrode AE3 may be larger than the area of ​​the first pixel electrode AE1 and the area of ​​the second pixel electrode AE2, and the area of ​​the first pixel electrode AE1 may be larger than the area of ​​the second pixel electrode AE2. The intensity of the light to be emitted may vary depending on the area of ​​the emission region overlapping with the pixel electrodes AE1, AE2, and AE3, and the area of ​​the emission region may be adjusted to control the display device 10 or the electronic device 1 (see Figure 1 ) is the color of the screen displayed in Figure 5 In the embodiment, the third pixel electrode AE3 has the largest area, but is not limited thereto. The sizes of the pixel electrodes AE1, AE2, and AE3 and the areas of the emission regions can be freely adjusted according to the desired color of the display device 10 and the electronic device 1. In addition, the areas of the pixel electrodes AE1, AE2, and AE3 may be related to the light efficiency and lifespan of the light-emitting element ED, and may have a trade-off relationship with the reflection of external light. Taking these factors into consideration, the areas of the pixel electrodes AE1, AE2, and AE3 may be adjusted.

[0138] The display device 10 may include a light blocking layer BM positioned on the pixel electrodes AE1 , AE2 , and AE3 , and a plurality of color filters CF1 , CF2 , and CF3 .

[0139] The light blocking layer BM may be arranged throughout the entire display area DA. The light blocking layer BM may include a plurality of holes OPT1, OPT2, and OPT3 arranged to correspond to the plurality of pixel electrodes AE1, AE2, and AE3, respectively. Each of the holes OPT1, OPT2, and OPT3 of the light blocking layer BM may be arranged to correspond to the pixel defining layer PDL (see FIG. Figure 7 ). In the display area DA, the light blocking layer BM may cover other areas of the display area DA except for the areas where the positioning holes OPT1, OPT2, and OPT3 are positioned. The holes OPT1, OPT2, and OPT3 of the light blocking layer BM may be areas where light emitted from the light emitting element including the pixel electrodes AE1, AE2, and AE3 is emitted.

[0140] The plurality of holes OPT1, OPT2, and OPT3 may include a first hole OPT1 overlapping the first pixel electrode AE1, a second hole OPT2 overlapping the second pixel electrode AE2, and a third hole OPT3 overlapping the third pixel electrode AE3. Within an area occupied by one pixel PX, one first hole OPT1, two second holes OPT2, and one third hole OPT3 may be formed in the light blocking layer BM.

[0141] Each of the plurality of apertures OPT1, OPT2, and OPT3 may have a larger area in plan view than each of the pixel electrodes AE1, AE2, and AE3. For example, the first aperture OPT1 may have a larger area in plan view than the first pixel electrode AE1. The second aperture OPT2 and the third aperture OPT3 may also have larger areas in plan view than the second pixel electrode AE2 and the third pixel electrode AE3, respectively. Furthermore, each of the apertures OPT1, OPT2, and OPT3 in the light blocking layer BM may have a different area in plan view. As described above, the areas of the plurality of pixel electrodes AE1, AE2, and AE3 may differ from one another, and therefore, the sizes of the apertures OPT1, OPT2, and OPT3 in the light blocking layer BM may also differ from one another. For example, the diameter or size of the third aperture OPT3 may be larger than the diameters or sizes of the first aperture OPT1 and the second aperture OPT2, and the diameter or size of the first aperture OPT1 may be larger than the diameter or size of the second aperture OPT2. However, embodiments according to the present disclosure are not limited thereto.

[0142] The plurality of color filters CF1, CF2, and CF3 may be arranged to correspond to the pixel electrodes AE1, AE2, and AE3, respectively. For example, the color filters CF1, CF2, and CF3 may be positioned on the light blocking layer BM and may be arranged to correspond to the plurality of holes OPT1, OPT2, and OPT3 of the light blocking layer BM. The holes OPT1, OPT2, and OPT3 of the light blocking layer BM may be formed to correspond to the pixel defining layer PDL (see FIG. Figure 7 ) overlap with the opening of the light blocking layer BM and can form a light exit area through which light emitted from the emission area is emitted. The color filters CF1, CF2, and CF3 can have an area larger than the area of ​​the holes OPT1, OPT2, and OPT3 of the light blocking layer BM, and the color filters CF1, CF2, and CF3 can completely cover the light exit area formed by the holes OPT1, OPT2, and OPT3. The color filters CF1, CF2, and CF3 can completely cover the holes OPT1, OPT2, and OPT3 of the light blocking layer BM, and a portion of the color filters CF1, CF2, and CF3 can be directly positioned on the light blocking layer BM. However, in some embodiments, the color filters CF1, CF2, and CF3 can be omitted.

[0143] The color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3 arranged to correspond to different pixel electrodes AE1, AE2, and AE3, respectively. The color filters CF1, CF2, and CF3 may include a colorant such as a dye or pigment that absorbs light of a wavelength band different from the specific wavelength band, and may be arranged to correspond to the color of light emitted by the light-emitting element including the pixel electrodes AE1, AE2, and AE3. For example, the first color filter CF1 may be a red color filter arranged to overlap with the first pixel electrode AE1 and transmit only red first light. The second color filter CF2 may be a green color filter arranged to overlap with the second pixel electrode AE2 and transmit only green second light, and the third color filter CF3 may be a blue color filter arranged to overlap with the third pixel electrode AE3 and transmit only blue third light.

[0144] Similar to the arrangement of the pixel electrodes AE1, AE2 and AE3, the color filters CF1, CF2 and CF3 may be arranged as Type of arrangement, such as diamonds Type of arrangement. For example, the first color filter CF1 and the third color filter CF3 may be alternately arranged in the first direction DR1 and the second direction DR2. The second color filter CF2 and another adjacent second color filter CF2 may be repeatedly arranged in the first direction DR1 and the second direction DR2, and the second color filter CF2, the adjacent first color filter CF1, and the adjacent third color filter CF3 may be alternately arranged in the fourth direction DR4 or the fifth direction DR5. A plurality of second color filters CF2 may be repeatedly arranged along the first direction DR1 and the second direction DR2, and the second color filter CF2 and the first color filter CF1 or the second color filter CF2 and the third color filter CF3 may be alternately arranged along the fourth direction DR4 or the fifth direction DR5.

[0145] According to some embodiments, the plurality of color filters CF1, CF2, and CF3 may have different areas in a plan view. As described above, the areas of the plurality of pixel electrodes AE1, AE2, and AE3 may differ from one another, and therefore, the sizes of the apertures OPT1, OPT2, and OPT3 of the light blocking layer BM and the areas of the color filters CF1, CF2, and CF3 in a plan view may also differ from one another. For example, the area of ​​the first color filter CF1, which is a red color filter, may be larger than the area of ​​the second color filter CF2, which is a green color filter, and the area of ​​the third color filter CF3, which is a blue color filter. Furthermore, the area of ​​the third color filter CF3 may be larger than the area of ​​the second color filter CF2.

[0146] The color filters CF1, CF2, and CF3 may have a square shape, a rectangular shape, or a diamond shape including sides extending in the fourth direction DR4 and the fifth direction DR5 in a plan view. The first color filter CF1 and the third color filter CF3 may have sides of the same length extending in the fourth direction DR4 and the fifth direction DR5, and may have a square shape or a diamond shape in a plan view. The area of ​​the first color filter CF1 may be larger than the area of ​​the third color filter CF3 in a plan view, and the second color filter CF2 adjacent to the first color filter CF1 and the third color filter CF3 may have sides of different lengths extending in the fourth direction DR4 and the fifth direction DR5 and have a rectangular shape in a plan view. In other words, the extended sides of the first color filter CF1 and the third color filter CF3 have the same length and may therefore have a shape that is not affected by position, while the extended sides of the second color filter CF2 have different lengths and may therefore have different extending directions of the long sides depending on the position. In describing Figure 6 In the case of the shape of the second color filter CF2 shown in , for example, the second color filter CF2 positioned in the second column C2 of the second row R2 may have a shape in which the long side extends in the fourth direction DR4, and the second color filter CF2 positioned in the fourth column C4 of the second row R2 may have a shape in which the long side extends in the fifth direction DR5.

[0147] However, the embodiments of the present disclosure are not limited thereto. In some embodiments, in a plan view, the shapes of the color filters CF1, CF2, and CF3 may be circular shapes similar to the shapes of the pixel electrodes AE1, AE2, and AE3. The display device 10 according to some embodiments may be designed so that the planar shapes and areas of the color filters CF1, CF2, and CF3 allow external light of the display device 10 to have a specific color.

[0148] According to some embodiments, the area ratio of the first color filter CF1 to the second color filter CF2 may be in the range of about 1:0.3 to 1:0.7, and the area ratio of the first color filter CF1 to the third color filter CF3 may be in the range of about 1:0.4 to 1:1. For example, the area ratio of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be 1:0.59:0.52 or 1:0.59:1. However, the area ratio of the color filters CF1, CF2, and CF3 is not limited to the above area ratios, and the planar areas of the color filters CF1, CF2, and CF3 may be designed differently so that the reflected light in the display device 10 of the electronic device 1 has the desired color coordinates.

[0149] The display device 10 may include a display layer DU (see Figure 3) on the color filters CF1, CF2 and CF3 to reduce the intensity of the reflected light caused by external light. In addition, the color of the reflected light caused by external light can be controlled by adjusting the arrangement, shape and area of ​​the color filters CF1, CF2 and CF3 in the plan view.

[0150] The touch electrode TL may be positioned between the pixel electrodes AE1, AE2, and AE3. The touch electrode TL may be arranged to extend in the fourth direction DR4 and the fifth direction DR5 and may be spaced apart from the pixel electrodes AE1, AE2, and AE3. The touch electrode TL may be arranged to extend in the fourth direction DR4 and the fifth direction DR5 and may be spaced apart from the pixel electrodes AE1, AE2, and AE3. Figure 7 ) overlaps with the light blocking layer BM. Although the touch electrode TL is briefly shown in the drawings, the touch electrode TL may include a touch driving electrode and a sensing electrode.

[0151] Figure 7 is a cross-sectional view of a display device according to some embodiments. Figure 7 A pixel PX is shown (see Figure 4 ) is a cross section spanning the first pixel electrode AE1, the second pixel electrode AE2 and the third pixel electrode AE3. Figure 7 It is along Figure 5 A cross-sectional view taken along line Y-Y'.

[0152] Will refer to Figure 7 Description of the display device 10 (see Figure 5 ) cross-sectional structure. The display device 10 may include a display layer DU, a touch sensing layer TSU, a light blocking layer BM, a color filter layer CFL, and an overcoat layer OC. The display layer DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL. The light blocking layer BM may be positioned on the display panel 100 (see FIG. Figure 3 ) on the touch sensing layer TSU, and the color filters CF1, CF2, and CF3 of the color filter layer CFL may be positioned on the light blocking layer BM. An overcoat layer OC may be positioned on the color filter layer CFL and the light blocking layer BM.

[0153] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or rolled. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. For another example, the substrate SUB may include a glass material or a metal material.

[0154] The thin film transistor layer TFTL may include a first buffer layer BF1, a lower metal layer BML, a second buffer layer BF2, a thin film transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0155] The first buffer layer BF1 may be positioned on the substrate SUB. The first buffer layer BF1 may include an inorganic layer capable of preventing or reducing the penetration of air or moisture. For example, the first buffer layer BF1 may include a plurality of inorganic layers alternately stacked.

[0156] The lower metal layer BML may be positioned on the first buffer layer BF1. For example, the lower metal layer BML may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof.

[0157] The second buffer layer BF2 may cover the first buffer layer BF1 and the lower metal layer BML. The second buffer layer BF2 may include an inorganic layer capable of preventing or reducing the penetration of pollutants such as air or moisture. For example, the second buffer layer BF2 may include a plurality of inorganic layers alternately stacked.

[0158] The thin film transistor TFT may be positioned on the second buffer layer BF2 and may constitute a pixel circuit of each of the plurality of pixels PX. For example, the thin film transistor TFT may be a switching transistor or a driving transistor of the pixel circuit. The thin film transistor TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0159] The semiconductor layer ACT may be positioned on the second buffer layer BF2. The semiconductor layer ACT may overlap with the lower metal layer BML and the gate electrode GE in the thickness direction and may be insulated from the gate electrode GE by the gate insulating layer GI. A portion of the semiconductor layer ACT may be made of a conductor to form a source electrode SE and a drain electrode DE.

[0160] The gate electrode GE may be positioned on the gate insulating layer GI. The gate electrode GE may overlap the semiconductor layer ACT with the gate insulating layer GI interposed therebetween.

[0161] The gate insulating layer GI may be positioned on the semiconductor layer ACT. For example, the gate insulating layer GI may cover the semiconductor layer ACT and the second buffer layer BF2 to insulate the gate electrode GE from the semiconductor layer ACT. The gate insulating layer GI may include a contact hole through which the first connection electrode CNE1 passes.

[0162] The first interlayer insulating layer ILD1 may cover the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer insulating layer ILD1 may be connected to the contact hole of the gate insulating layer GI and the contact hole of the second interlayer insulating layer ILD2.

[0163] The capacitor electrode CPE may be positioned on the first interlayer insulating layer ILD1 , overlap the gate electrode GE in a thickness direction, and form a capacitor with the gate electrode GE.

[0164] The second interlayer insulating layer ILD2 may cover the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second interlayer insulating layer ILD2 may be connected to the contact hole of the first interlayer insulating layer ILD1 and the contact hole of the gate insulating layer GI.

[0165] The first connection electrode CNE1 may be positioned on the second interlayer insulating layer ILD2. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 may be inserted into a contact hole provided in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the drain electrode DE of the thin film transistor TFT.

[0166] The first passivation layer PAS1 may cover the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first passivation layer PAS1 may protect the thin film transistor TFT. The first passivation layer PAS1 may include a contact hole through which the second connection electrode CNE2 passes.

[0167] The second connection electrode CNE2 may be positioned on the first passivation layer PAS1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 to the pixel electrode AE1, AE2, or AE3 of the light emitting element ED. The second connection electrode CNE2 may be inserted into a contact hole formed in the first passivation layer PAS1 to contact the first connection electrode CNE1.

[0168] The second passivation layer PAS2 may cover the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 may include a contact hole through which the pixel electrode AE1, AE2, or AE3 of the light emitting element ED passes.

[0169] The light emitting element layer EML may be positioned on the thin film transistor layer TFTL. The light emitting element layer EML may include a light emitting element ED and a pixel defining layer PDL. The light emitting element ED may include pixel electrodes AE1, AE2, and AE3, a light emitting layer EL, and a common electrode CE.

[0170] The pixel electrodes AE1, AE2, and AE3 may be positioned on the second passivation layer PAS2. Each of the different pixel electrodes AE1, AE2, and AE3 may be arranged to overlap one of the different openings of the pixel defining layer PDL. The pixel electrodes AE1, AE2, and AE3 may be electrically connected to the drain electrode DE of the thin film transistor TFT via a first connection electrode CNE1 and a second connection electrode CNE2.

[0171] The light-emitting layer EL may be positioned on the pixel electrodes AE1, AE2, and AE3. For example, the light-emitting layer EL may be an organic light-emitting layer made of an organic material, but is not limited thereto. When an organic light-emitting layer is used as the light-emitting layer EL, the thin film transistor TFT applies a predetermined voltage to the pixel electrodes AE1, AE2, and AE3 of the light-emitting element ED. When the common electrode CE of the light-emitting element ED receives a common voltage or a cathode voltage, holes and electrons may move to the light-emitting layer EL through the hole transport layer and the electron transport layer and recombine to generate light to be emitted by the light-emitting layer EL.

[0172] According to some embodiments, the light-emitting layers EL positioned on different pixel electrodes AE1, AE2, and AE3 may emit light of different colors. For example, the light-emitting layer EL positioned on the first pixel electrode AE1 may emit red light of a first color, the light-emitting layer EL positioned on the second pixel electrode AE2 may emit green light of a second color, and the light-emitting layer EL positioned on the third pixel electrode AE3 may emit blue light of a third color. However, the embodiments of the present disclosure are not limited thereto. According to some embodiments, the light-emitting layer EL may be positioned as a common layer on the different pixel electrodes AE1, AE2, and AE3 and the pixel defining layer PDL, or the light-emitting layers EL positioned on the different pixel electrodes AE1, AE2, and AE3 may emit light of the same color. In this case, the display device 10 may further include a color adjustment layer positioned on the light-emitting element ED.

[0173] The common electrode CE may be disposed on the light-emitting layer EL. For example, the common electrode CE may be formed as an electrode common to all pixels rather than as an electrode specific to each pixel. The common electrode CE may be positioned on the light-emitting layer EL in the region of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3, and may be positioned on the pixel-defining layer PDL in the region other than the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3.

[0174] The common electrode CE can receive a common voltage or a low potential voltage. When the pixel electrode AE1, AE2, or AE3 receives a voltage corresponding to the data voltage and the common electrode CE receives a low potential voltage, a potential difference is formed between the pixel electrodes AE1, AE2, and AE3 and the common electrode CE, so that the light emitting layer EL can emit light.

[0175] The pixel defining layer PDL may include a plurality of openings and may be positioned on a portion of the pixel electrodes AE1, AE2, and AE3 and the second passivation layer PAS2. Each opening of the pixel defining layer PDL may expose a portion of the pixel electrodes AE1, AE2, and AE3. As described above, the corresponding openings of the pixel defining layer PDL may define the first emission area to the third emission area, and the areas or sizes of the first emission area to the third emission area may be different from each other. The pixel defining layer PDL may separate and insulate the pixel electrodes AE1, AE2, and AE3 of each of the plurality of light-emitting elements ED. The pixel defining layer PDL may include a light absorbing material to prevent or reduce light reflection. For example, the pixel defining layer PDL may include a polyimide (PI)-based adhesive and a pigment in which red, green, and blue are mixed. Alternatively, the pixel defining layer PDL may include a cardo-based adhesive resin and a mixture of a lactam black pigment and a blue pigment. Alternatively, the pixel defining layer PDL may include carbon black.

[0176] The encapsulation layer TFEL may be positioned on the common electrode CE to cover the plurality of light-emitting elements ED. The encapsulation layer TFEL may include at least one inorganic layer to prevent or reduce the penetration of contaminants such as oxygen or moisture into the light-emitting element layer EML. The encapsulation layer TFEL may include at least one organic layer to protect the light-emitting element layer EML from foreign matter such as dust.

[0177] According to some embodiments, the encapsulation layer TFEL may include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3. The first encapsulation layer TFE1 and the third encapsulation layer TFE3 may be inorganic encapsulation layers, and the second encapsulation layer TFE2 positioned between the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may be an organic encapsulation layer.

[0178] Each of the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may include one or more inorganic insulating materials. The inorganic insulating materials may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide (ZnO x , which may be ZnO or ZnO2), silicon oxide, silicon nitride and / or silicon oxynitride.

[0179] The second encapsulation layer TFE2 may include a polymer material. Examples of polymer materials include acrylic resin, epoxy resin, polyimide, and polyethylene. For example, the second encapsulation layer TFE2 may include an acrylic resin, such as polymethyl methacrylate or polyacrylic acid. The second encapsulation layer TFE2 may be formed by curing a monomer or applying a polymer.

[0180] The touch sensing layer TSU may be positioned on the encapsulation layer TFEL. The touch sensing layer TSU may include a first touch insulating layer SIL1, a second touch insulating layer SIL2, touch electrodes TL, and a third touch insulating layer SIL3.

[0181] The first touch insulating layer SIL1 may be positioned on the encapsulation layer TFEL. The first touch insulating layer SIL1 may have an insulating function and an optical function. The first touch insulating layer SIL1 may include at least one inorganic layer. Optionally, the first touch insulating layer SIL1 may be omitted.

[0182] The second touch insulating layer SIL2 may cover the first touch insulating layer SIL1. According to some embodiments, touch electrodes of another layer may be further positioned on the first touch insulating layer SIL1, and the second touch insulating layer SIL2 may cover the touch electrodes of the other layer. The second touch insulating layer SIL2 may have both insulating and optical functions. For example, the second touch insulating layer SIL2 may be an inorganic layer including at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0183] A portion of the touch electrode TL may be positioned on the second touch insulating layer SIL2. The touch electrode TL may not overlap with the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3. The touch electrode TL may be formed of a single layer including molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or indium tin oxide (ITO), or may be formed to have a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an Ag-Pd-Cu (APC) alloy, or a stacked structure of an APC alloy and ITO (ITO / APC / ITO).

[0184] The touch electrodes TL of the touch sensing layer TSU can have a constant line width and can be arranged to overlap with the light blocking layer BM, which will be described later. The light blocking layer BM can have a width sufficient to completely cover the touch electrodes TL and can define a gap between the edges of the light blocking layer BM and the touch electrodes TL. According to some embodiments, the line width of the touch electrodes TL can be in the range of 4 μm to 6 μm, and the gap between the touch electrodes TL and the edges of the light blocking layer BM can be in the range of 5 μm to 7 μm. The touch electrodes TL can be arranged so that the center of the touch electrodes TL is substantially aligned with the center of the light blocking layer BM, and the gaps from both sides of the touch electrodes TL to the edges of the light blocking layer BM can be substantially constant.

[0185] The third touch insulating layer SIL3 may cover the touch electrode TL and the second touch insulating layer SIL2. The third touch insulating layer SIL3 may have an insulating function and an optical function. The third touch insulating layer SIL3 may be made of the material described in association with the second touch insulating layer SIL2.

[0186] The light-blocking layer BM may be positioned on the third touch insulating layer SIL3 of the touch sensing layer TSU. The light-blocking layer BM may be arranged to cover the conductive lines of the touch electrodes TL while including a plurality of apertures OPT1, OPT2, and OPT3 that overlap with the pixel electrodes AE1, AE2, and AE3. For example, the first aperture OPT1 may be arranged to overlap with the first pixel electrode AE1. The second aperture OPT2 may be arranged to overlap with the second pixel electrode AE2, and the third aperture OPT3 may be arranged to overlap with the third pixel electrode AE3. The area or size of the apertures OPT1, OPT2, and OPT3 may be larger than the area or size of the pixel electrodes AE1, AE2, and AE3. Furthermore, the area or size of each of the apertures OPT1, OPT2, and OPT3 may be larger than the area or size of the corresponding opening of the pixel defining layer PDL, so that the light emitted from the light-emitting element ED can be visually recognized by the user not only from the front of the display device 10 but also from the side of the display device 10.

[0187] The light-blocking layer BM may include a light-absorbing material. For example, the light-blocking layer BM may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, pentadiene black, and aniline black, but they are not limited thereto. The light-blocking layer BM may prevent or reduce visible light penetration and color mixing between the holes OPT1, OPT2, and OPT3, thereby improving the color reproducibility of the display device 10. According to some embodiments, the light-blocking layer BM may have a thickness of 1 μm to 3 μm, or approximately 1.5 μm.

[0188] The color filters CF1, CF2, and CF3 of the color filter layer CFL may be positioned on the light blocking layer BM. Different color filters CF1, CF2, and CF3 may be arranged to correspond to different pixel electrodes AE1, AE2, and AE3 and the holes OPT1, OPT2, and OPT3 of the light blocking layer BM, respectively. For example, the first color filter CF1 may be arranged to correspond to the first pixel electrode AE1, the second color filter CF2 may be arranged to correspond to the second pixel electrode AE2, and the third color filter CF3 may be arranged to correspond to the third pixel electrode AE3. In the pixel PX (see Figure 4 ), the first color filter CF1 may be positioned in the first hole OPT1 of the light blocking layer BM, the second color filter CF2 may be positioned in the second hole OPT2 of the light blocking layer BM, and the third color filter CF3 may be positioned in the third hole OPT3 of the light blocking layer BM. Each of the color filters CF1, CF2, and CF3 may be arranged to have a larger area than the holes OPT1, OPT2, and OPT3 of the light blocking layer BM in a plan view, and some color filters may be positioned directly on the light blocking layer BM.

[0189] The areas of the plurality of color filters CF1, CF2, and CF3 may vary depending on the sizes of the holes OPT1, OPT2, and OPT3 of the light blocking layer BM. For example, the first color filter CF1 may have a larger area than the second color filter CF2 in a plan view, but may have a smaller area than the third color filter CF3 in a plan view.

[0190] The overcoat layer OC may be positioned on the light blocking layer BM and the color filter layer CFL. The overcoat layer OC may extend over the entire display area DA (see FIG. Figure 4 ) is arranged to flatten the top surface of the display device 10. The overcoat layer OC may be a colorless light-transmitting layer having no color in the visible light band. For example, the overcoat layer OC may include a colorless light-transmitting organic material such as an acrylic resin.

[0191] According to some embodiments, the display device 10 may not include a polarizing plate on the overcoat layer OC. In other words, the polarizing plate can be used to prevent or reduce degradation in display quality when external light is incident and reflected by the sidewalls of the opening of the pixel electrode AE1, AE2, or AE3 or the pixel defining layer PDL, thereby becoming visible to the user. However, the polarizing plate has the disadvantage that, because it not only reduces the reflection of external light but also reduces the light emitted from the light-emitting element layer EML, more power is consumed to display a certain brightness. To reduce power consumption, the light-emitting display device according to some embodiments may not include a polarizing plate.

[0192] Furthermore, the display device 10 includes a structure for preventing or reducing degradation of display quality due to reflection. In this structure, the side surface of the pixel electrode AE1, AE2, or AE3 is covered with a pixel defining layer PDL to reduce the degree of light reflection from the pixel electrode AE1, AE2, or AE3, and a light blocking layer BM is formed to reduce the degree of light incidence. Therefore, there is no need to separately form a polarizing plate on the front surface of the display panel 100.

[0193] According to some embodiments, the overcoat layer (OC) may be formed in the display device 10 using an inkjet printing process. Compared to a patterning process using a photoresist, this has the advantage of eliminating one masking process and shortening the manufacturing process of the display device 10. For example, the overcoat layer (OC) may have a thickness ranging from 10 μm to 20 μm, a viscosity ranging from 10 cp to 20 cp, and a refractive index of approximately 1.5. The overcoat layer (OC) may be formed using an inkjet printing process and may include a material that can improve the optical characteristics of the display device 10.

[0194] In addition, in the display device 10, a non-display area NDA (see FIG. Figure 3 ) or sub-area SBA (see Figure 3 ) can be replaced by layers made of the same material as the configuration of other layers positioned in the display area DA, and the manufacturing process can be further shortened.

[0195] Figure 8 is a plan view illustrating an arrangement of color filter layers in a single cell unit of a display device according to some embodiments. Figure 9 It is along Figure 8 A cross-sectional view taken along line XX'. Figure 9 The display device 10 (see Figure 8 ) in the sub-area SBA in the first direction DR1 through the bending area BA.

[0196] Reference Figure 8 and Figure 9 , the display device 10 can be manufactured from a mother substrate of a single unit CL and can be cut into Figure 4 The outer coating layer OC may be formed in the shape shown in FIG. The outer coating layer OC may be formed to overlap with the display device 10 based on the mother substrate of the single cell CL. The outer coating layer OC may be formed to fill the outer coating valley portion OCL surrounding a portion of the display device 10 in the mother substrate of the single cell CL. The outer coating valley portion OCL may surround a portion of the main area MA and the sub-area SBA of the display device 10. The outer coating valley portion OCL may be formed to pass through the upper side of the display driver 200 in the sub-area SBA of the display device 10.

[0197] The dam structure forming the outer valley portion OCL may be formed in the mother substrate of the single cell CL. Among the outer valley portion OCL, the outer valley portion OCL passing through the sub-area SBA of the display device 10 may be formed by the dam structure positioned in the sub-area SBA.

[0198] According to some embodiments, the display device 10 may include a plurality of color dams CFD1 and CFD2, and a first color pattern CFP1. The plurality of color dams CFD1 and CFD2 form dams or valleys that define an area in which the overcoat layer OC is positioned. The first color pattern CFP1 and the color dams CFD1 and CFD2 are positioned on the same layer and cover a portion of the bend area BA. The first color pattern CFP1 and the color dams CFD1 and CFD2 positioned in a sub-area SBA of the display device 10 may be positioned on the same layer and may include the same material as the color filters of the color filter layer CFL of the display area DA. Because the first color pattern CFP1 and the color dams CFD1 and CFD2 are formed simultaneously with the color filters in the same manner as the overcoat layer OC is formed using an inkjet printing process, masking processes during the manufacturing process may be reduced.

[0199] The bending area BA may include bending structures PSV1, PSV2, SDL and SPC. The bending structures PSV1, PSV2, SDL and SPC include the display layer DU (see FIG. 1 ) positioned in the display area DA. Figure 3 ) are made of the same material. The bending structures PSV1, PSV2, SDL and SPC may include a first via layer PSV1, a wiring layer SDL, a second via layer PSV2 and a spacer SPC. Figure 7 , the first through-hole layer PSV1 and the second through-hole layer PSV2 can be positioned on the same layer as the first passivation layer PAS1 and the second passivation layer PAS2 of the thin film transistor layer TFTL, respectively, and the wiring layer SDL can be positioned on the same layer as the first connection electrode CNE1. The spacer SPC can be positioned on the second through-hole layer PSV2. The wiring layer SDL in the bending structure PSV1, PSV2, SDL, SPC can be a layer that connects the wiring positioned inside the bending area BA and the wiring positioned outside the bending area BA, and the first passivation layer PAS1, the second passivation layer PAS2 and the spacer SPC can prevent or reduce the wiring layer SDL from being exposed to the outside. The wiring layer SDL can be connected to any one of the wirings of the backplane layer TFL positioned inside and outside the bending area BA. Similar to the thin film transistor layer TFTL, the backplane layer TFL can have a structure in which multiple conductive layers and insulating layers are stacked.

[0200] The first color pattern CFP1 may be positioned adjacent to the main area MA in the sub-area SBA. The first color pattern CFP1 may be arranged to cover a portion of the bending area BA. The first color pattern CFP1 may cover a portion of the bending structures PSV1, PSV2, SDL, and SPC, and may form an opening area CFO exposing another portion of the bending structures PSV1, PSV2, SDL, and SPC. The first color pattern CFP1 may protect the bending structures PSV1, PSV2, SDL, and SPC positioned in the bending area BA, and may compensate for the modulus characteristics of the bending area BA when folded. In addition, the display device 10 may include a bending protection layer BPL positioned on the overcoat layer OC in the bending area BA, and similar to the first color pattern CFP1, the bending protection layer BPL may also compensate for the modulus characteristics and protect the wiring layer SDL.

[0201] The plurality of color dams CFD1 and CFD2 may include a first color dam CFD1 and a second color dam CFD2. The first color dam CFD1 is positioned outside the bending area BA in the sub-area SBA, and the second color dam CFD2 is spaced apart from the first color dam CFD1 and adjacent to the pad PD. The first color dam CFD1 may be spaced apart from the first color pattern CFP1 to form a first valley portion CFV1, and the second color dam CFD2 may be spaced apart from the first color dam CFD1 to form a second valley portion CFV2. The first and second valley portions CFV1 and CFV2, as well as the first and second color dams CFD1 and CFD2, can prevent or reduce overflow of an overcoat layer OC formed during the inkjet printing process from the sub-area SBA onto the pad PD. For example, the overcoat layer OC may not exceed the second color dam CFD2 (i.e., the overcoat layer OC is within the second color dam CFD2), may fill the first valley portion CFV1, and may overlap a portion of the first color dam CFD1 (i.e., the overcoat layer OC is on the interior of the first color dam CFD2). The overcoat layer OC may cover the bending structures PSV1 , PSV2 , SDL and SPC and the first color pattern CFP1 .

[0202] According to some embodiments, the first and second color dams CFD1 and CFD2 may have widths ranging from 30 μm to 60 μm, and the first and second valley portions CFV1 and CFV2 may also have widths ranging from 30 μm to 60 μm. Furthermore, each of the first and second color dams CFD1 and CFD2 may have a thickness ranging from 1 μm to 3 μm and a side surface taper angle ranging from 60° to 90°. The color dams CFD1 and CFD2 and the valley portions CFV1 and CFV2 may be formed so that the overcoat layer OC does not extend beyond the overcoat valley portion OCL, and the pads PD of the sub-area SBA may not be covered by the overcoat layer OC.

[0203] In addition, the second color dam CFD2 may not cover the portion of the sub-area SBA where the display driver 200 is located. The second color dam CFD2 may include a first opening pattern COA1 formed to overlap the display driver 200.

[0204] Combine Figure 7 In the display device 10, the color dams CFD1 and CFD2 and the first color pattern CFP1 may be located on the same layer as the color filter layer CFL or the light blocking layer BM in the display area DA and may include the same material. A portion of the touch insulation layer SIL of the touch sensing layer TSU may be located in the sub-area SBA, and the color dams CFD1 and CFD2 and the first color pattern CFP1 may be located directly on the touch insulation layer SIL. As an example, the color dams CFD1 and CFD2 and the first color pattern CFP1 may include the same material as the light blocking layer BM or any of the first, second, and third color filters CF1, CF2, and CF3, and may be formed simultaneously. According to some embodiments, the color dams CFD1 and CFD2 and the first color pattern CFP1 may include the same material as the second color filter CF2 and may be formed together with the second color filter CF2. The first color pattern CFP1, including the same material as the second color filter CF2, may be advantageous in compensating for modulus characteristics when folded in the bending area BA.

[0205] In addition, according to some embodiments, the second color pattern CFP2 arranged around the display device 10 can be formed on the mother substrate of the single cell CL. The second color pattern CFP2 can be positioned outside the display device 10 in the mother substrate of the single cell CL. The second color pattern CFP2 can also form an outer valley portion OCL together with the color dams CFD1 and CFD2, and can prevent the outer coating OC from completely covering the sub-area SBA. Because the outer valley portion OCL is formed to surround the outside of the main area MA of the display device 10, when the outer coating OC is formed by an inkjet printing process, edge unevenness caused by humps formed when ink portions gather at the edge of the display device 10 can also be improved.

[0206] The mother substrate in a single cell CL may be formed with a key for alignment with process equipment. The key may be formed outside the display device 10, and the second color pattern CFP2 may include a plurality of second opening patterns COA2 that overlap with the key so as not to cover the key. Thus, the second color pattern CFP2 can expose the key, which helps identify the alignment of the process equipment with the mother substrate of the single cell CL, while preventing or reducing overflow of the overcoat layer OC.

[0207] The display device 10 according to some embodiments can reduce a mask process when forming the overcoat layer OC through an inkjet printing process, and further, since the color dams CFD1 and CFD2 for preventing or reducing overflow of the overcoat layer OC in the sub-area SBA are formed simultaneously with the color filter layer CFL or the light blocking layer BM, there is an advantage that the manufacturing process can be further shortened.

[0208] Figure 10 is a cross-sectional view illustrating a bending region of a display device according to some embodiments.

[0209] Reference Figure 10 , the display device 10 (see Figure 8 ) can omit the bending protection layer BPL (see Figure 9 ). Since the display device 10 can compensate for the modulus characteristics of the bending area BA by covering a portion of the bending area BA with the first color pattern CFP1, the bending protection layer BPL can be omitted. Figure 9 The embodiment of the present invention is different in that the bending protection layer BPL is omitted. Since the bending protection layer BPL is omitted, the display device 10 can reduce useless space by minimizing the bending area BA.

[0210] Figure 11 is a plan view illustrating an arrangement of color filter layers in a single unit of a display device according to some embodiments. Figure 12 It is along Figure 11 A cross-sectional view taken along line X1-X1'.

[0211] Reference Figure 11 and Figure 12 In the display device 10 according to some embodiments, the first color pattern CFP1 can completely cover the bending area BA. The first color pattern CFP1 can completely cover the spacer SPC in the bending structures PSV1, PSV2, SDL, and SPC without forming an opening area CFO. Depending on the material, the first color pattern CFP1 can have excellent modulus characteristics and avoid damage or warping when the bending area BA is folded. In this case, the first color pattern CFP1 can completely cover the bending structures PSV1, PSV2, SDL, and SPC without forming an opening area CFO. Therefore, the display device 10 can further enhance the modulus characteristics of the bending area BA.

[0212] Figure 13 is a plan view illustrating an arrangement of color filter layers in a single unit of a display device according to some embodiments. Figure 14 It is along Figure 13 A cross-sectional view taken along line X2-X2'.

[0213] Reference Figure 13 and Figure 14 In the display device 10 according to some embodiments, the plurality of color dams CFD1 and CFD2 may be positioned closer to the main area MA than the first color pattern CFP1. The first color pattern CFP1 may cover the bending structures PSV1, PSV2, SDL, and SPC, and may be positioned within and outside the bending area BA in the sub-area SBA. The first and second color dams CFD1 and CFD2 may be spaced apart from each other and may be positioned within the bending area BA. The first and second color dams CFD1 and CFD2, as well as the first color pattern CFP1, may be spaced apart from each other to form a plurality of valleys CFV1 and CFV2, and the overcoat layer OC may not extend beyond at least the second color dam CFD2. The overcoat layer OC may not fill the first valley CFV1 and partially overlap the first color dam CFD1. The overcoat layer OC may not overlap the first color pattern CFP1.

[0214] Figure 15 is a plan view illustrating an opening in a light blocking layer of a display device according to some embodiments. Figure 15 The display area DA is shown (see Figure 4 )'s pixel electrode AE ​​and the hole OPT of the light blocking layer BM are arranged in relative planes.

[0215] Reference Figure 15 , in the display device 10 (see Figure 5 ), the light blocking layer BM positioned in the display area DA may further include a groove TRC protruding from the outside of the hole OPT. The hole OPT of the light blocking layer BM may have a generally circular shape, but the groove TRC may be formed with an outer side protruding from the outside of the hole OPT of the light blocking layer BM in a plan view. The groove TRC may be formed to penetrate the light blocking layer BM in the same manner as the hole OPT. Figure 15 In the embodiment, four trenches TRC are formed at regular intervals in one hole OPT, but the present disclosure is not limited thereto. According to some embodiments, the width of the trench TRC may be in the size of 1 μm to 2 μm.

[0216] Combine Figure 7Since the overcoat layer OC is formed using an inkjet printing process, an area that cannot be partially filled may be formed due to a stepped portion formed by the light blocking layer BM and the color filter layer CFL positioned below the overcoat layer OC. In the light blocking layer BM, since the groove TRC formed on the outer side of the hole OPT is formed to penetrate the light blocking layer BM, the color filters CF1, CF2, and CF3 can be formed to fill the groove TRC in addition to the hole OPT. Therefore, the stepped portion caused by the color filters CF1, CF2, and CF3 can be reduced, and it can be advantageous for the overcoat layer OC positioned on the color filters CF1, CF2, and CF3 to be formed so as to completely fill the gap between the color filter layer CFL and the light blocking layer BM.

[0217] Figures 16 to 18 is a cross-sectional view of a display device according to some embodiments.

[0218] Reference Figure 16 , in the display device 10 according to some embodiments (see Figure 5 ), the color filters CF1, CF2, and CF3 may be arranged to partially overlap with each other. A plurality of color filters CF1, CF2, and CF3 may overlap with different color filters adjacent to each other on the light blocking layer BM. For example, the second color filter CF2 may overlap with each of the adjacent first color filter CF1 and third color filter CF3 on the light blocking layer BM. According to some embodiments, the first color filter CF1 may overlap with the third color filter CF3 on the light blocking layer BM, and in some embodiments, the first color filter CF1, the second color filter CF2, and the third color filter CF3 may all overlap.

[0219] Reference Figure 17 According to some embodiments of the display device 10 (see Figure 5 ) The light blocking layer BM can be omitted (see Figure 16 ), and may include color light blocking layers CFB1 and CFB2, the color light blocking layers CFB1 and CFB2 including the same material as the color filters CF1, CF2, and CF3. The color filters CF1, CF2, and CF3 and the color light blocking layers CFB1 and CFB2 may be located in adjacent emission areas EA (see FIG. Figure 4 ) overlap with each other and can play the same role as the light blocking layer BM.

[0220] For example, the first color filter CF1 may overlap the first pixel electrode AE1 and may be arranged to cover the peripheral area of ​​the first pixel electrode AE1. The first color light blocking layer CFB1 including the same material as the first color filter CF1 may be positioned at a boundary between the emission area overlapping the second pixel electrode AE2 and the emission area overlapping the third pixel electrode AE3.

[0221] The third color filter CF3 may overlap the third pixel electrode AE3 and may be arranged to cover the peripheral area of ​​the third pixel electrode AE3. A portion of the third color filter CF3 may be positioned on the first color filter CF1 and the first color light blocking layer CFB1. The first color filter CF1 may extend to the boundary between the emission region overlapping with the first pixel electrode AE1 and the emission region overlapping with the second pixel electrode AE2, and the second color light blocking layer CFB2 including the same material as the third color filter CF3 may be positioned on the first color filter CF1 so that the second color light blocking layer CFB2 may be positioned at the boundary between the emission region overlapping with the first pixel electrode AE1 and the emission region overlapping with the second pixel electrode AE2.

[0222] The second color filter CF2 may overlap the second pixel electrode AE2 and may be arranged to cover a peripheral area of ​​the second pixel electrode AE2. A portion of the second color filter CF2 may be positioned on the first and second color light blocking layers CFB1 and CFB2.

[0223] Color filters CF1, CF2, and CF3, or color light blocking layers CFB1 and CFB2, each containing different colorants, may overlap at the boundaries between emission regions that overlap with corresponding pixel electrodes AE1, AE2, and AE3. Thus, color filters CF1, CF2, and CF3, or color light blocking layers CFB1 and CFB2, each containing different colorants, may function similarly to light blocking layer BM and block light transmission. Apertures OPT1, OPT2, and OPT3 may be formed in regions of color filters CF1, CF2, and CF3 that do not overlap with color light blocking layers CFB1 and CFB2, or color filters CF1, CF2, and CF3.

[0224] Reference Figure 18 , in the display device 10 (see Figure 5 ), the color light blocking layers CFB1 and CFB2 and the color filters CF1, CF2, and CF3 may partially overlap. For example, the second color filter CF2 may not completely overlap with the first color filter CF1, the first color light blocking layer CFB1, and the second color light blocking layer CFB2, but may partially overlap with the first color filter CF1, the first color light blocking layer CFB1, and the second color light blocking layer CFB2. The third color filter CF3 may overlap with the first color filter CF1 and the first color light blocking layer CFB1. Figure 17 In the embodiment of the present invention, the three different color filters CF1, CF2 and CF3 or the color light blocking layers CFB1 and CFB2 may overlap each other at the boundaries of the adjacent holes OPT1, OPT2 and OPT3, but Figure 18In an embodiment, the color filters CF1 , CF2 , and CF3 of two different colors or the color light blocking layers CFB1 and CFB2 may overlap each other at boundaries of adjacent apertures OPT1 , OPT2 , and OPT3 .

[0225] In the above description, Figure 17 In the embodiment, the three different color filters CF1, CF2 and CF3 or the color light blocking layers CFB1 and CFB2 can overlap with each other, which means that the area where the three different color filters CF1, CF2 and CF3 or the color light blocking layers CFB1 and CFB2 can overlap with each other is larger than the area where the two different color filters CF1, CF2 and CF3 or the color light blocking layers CFB1 and CFB2 can overlap with each other. Similarly, in the above description, Figure 18 In the embodiment, two different color filters CF1, CF2 and CF3 or color light blocking layers CFB1 and CFB2 may overlap with each other meaning that an area in which two different color filters CF1, CF2 and CF3 or color light blocking layers CFB1 and CFB2 may overlap with each other is larger than an area in which three different color filters CF1, CF2 and CF3 or color light blocking layers CFB1 and CFB2 may overlap with each other.

[0226] Figure 19 is a plan view illustrating the arrangement of openings of a pixel defining layer and color filters in a display area of ​​a display device according to some embodiments.

[0227] Reference Figure 19 In the display device 10 according to some embodiments, the openings Opr, Opg, and Opb of the pixel defining layer PDL and the light blocking layer BM (see Figure 7 ) may have an elliptical shape. The major axes of the elliptical openings Opr, Opg, and Opb of the pixel defining layer PDL and the major axes of the elliptical openings OPT1, OPT2, and OPT3 of the light blocking layer BM may have different directions from each other. According to some embodiments, similar to the openings Opr, Opg, and Opb of the pixel defining layer PDL, the pixel electrodes AE1, AE2, and AE3 (see Figure 7 ) can also have an oval shape.

[0228] In the display device 10, the openings Opr, Opg, and Opb of the plurality of pixel defining layers and the holes OPT1, OPT2, and OPT3 of the light blocking layer BM may each have a planar shape of an ellipse having the same eccentricity. That is, the first opening Opr, the second opening Opg, and the third opening Opb may all be ellipses having the same eccentricity, and the first hole OPT1, the second hole OPT2, and the third hole OPT3 may also all be ellipses having the same eccentricity. Here, the eccentricity of the openings Opr, Opg, and Opb and the holes OPT1, OPT2, and OPT3 may have a value greater than or equal to 0 and less than or equal to 0.85.

[0229] Here, an ellipse can have two foci, can have a shape connecting points where the sum of the distances to the two foci is constant, and can have a major axis and a minor axis. Meanwhile, the eccentricity of an ellipse is a value obtained by dividing the distance between the two foci by the length of the major axis. When the eccentricity is 0, it is a circle, and when the eccentricity is 1, it forms a parabola, so an ellipse has a value greater than 0 and less than 1 as its eccentricity value.

[0230] One opening Opr, Opg, or Opb may overlap with one hole OPT1, OPT2, or OPT3, and may have a certain horizontal gap between them. Here, the horizontal gap or separation distance between the openings Opr, Opg, and Opb and the corresponding holes OPT1, OPT2, and OPT3 may be greater than 0 μm and less than or equal to 20 μm, and the horizontal gap may vary depending on the thickness of the layer (e.g., encapsulation layer) located between the two in the cross-sectional view. In addition, according to some embodiments, the direction of the long axis of the openings Opr, Opg, and Opb and the direction of the long axis of the holes OPT1, OPT2, and OPT3 may form a certain angle due to process errors, etc., and may have an angle greater than or equal to 0 degrees and less than or equal to 20 degrees.

[0231] exist Figure 19 In an embodiment, the angle formed by each long axis of the multiple openings Opr, Opg and Opb or each long axis of the multiple holes OPT1, OPT2 and OPT3 can have four or more angles, and the angles formed by the long axes can be positioned at intervals of 45 degrees or less.

[0232] As an example, the following description focuses on an embodiment having five angles to describe specific angle relationships. In the embodiment having five angles, the angles of the major axis are formed at intervals of 36 degrees, so that one major axis has angles of 0 degrees, 36 degrees, 72 degrees, 108 degrees, and 144 degrees relative to the first direction DR1, resulting in a total of five angles. In other words, with respect to the five angles, the intervals between the major axis angles can be checked by dividing an angle of 180 degrees by 5 (the number of directions). This is because two angles of 180 degrees out of 360 degrees have substantially the same major axis direction of the ellipse, and this may mean that the intervals between the major axis angles are calculated by dividing 180 degrees by the number of directions.

[0233] As described above, the angles formed by the major axes of the openings Opr, Opg, and Opb with the major axes of the apertures OPT1, OPT2, and OPT3 may be positioned at equal intervals of a specific angle of 45 degrees or less. However, according to some embodiments, the angles formed by the major axes of each opening may be arranged at irregular intervals of one of 45 degrees or less. In embodiments where the major axes of the openings are arranged at unequal intervals, the major axes may be intentionally arranged to reduce diffraction patterns, or may be arranged at unequal intervals due to process errors.

[0234] In order to make the unit pixel including the openings Opr, Opg and Opb of red, green and blue and the holes OPT1, OPT2 and OPT3 have a square structure, the angle of the long axis is obtained by dividing the square of the integer (for example, 2 2 , 3 2 , 4 2 or 5 2 Here, the unit pixel may include openings Opr, Opg, and Opb from red, green, and blue, and each of holes OPT1, OPT2, and OPT3, and holes OPT1, OPT2, or OPT3 of one color among them (for example, hole OPT2 of green) may be formed in plural.

[0235] At the end of the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the disclosed embodiments without departing substantially from the spirit and scope of the embodiments disclosed herein. Therefore, the disclosed embodiments of the present invention are used in a generic and descriptive sense only and not for the purpose of limitation.

Claims

1. A display device, wherein: The display device includes: A substrate having a main region and a sub-region, wherein a plurality of pixel electrodes spaced apart from each other are positioned on the main region, and the sub-region is on one side of the main region and includes a bending region; a plurality of color filters overlapping the pixel electrodes on the substrate; a first color pattern on the substrate and partially overlapping the bending region in the sub-region; a first color dam and a second color dam, the first color dam being spaced apart from the first color pattern and located in the sub-region, the second color dam being spaced apart from the first color dam; and an overcoat layer on a color filter from among the plurality of color filters and in the main region and the sub-region, The outer coating layer covers the main area and is inside the second color dam in the sub-area.

2. The display device according to claim 1, wherein Each of the first color pattern, the first color dam, and the second color dam includes the same material as the color filter.

3. The display device according to claim 1, wherein A portion of the first color pattern is between the main area and the bending area of ​​the sub-area, and The first color dam is spaced apart from the first color pattern outside the bending region.

4. The display device according to claim 3, wherein The outer coating overlaps the first color pattern in the sub-area, or The overcoat layer fills a first valley portion formed between the first color dam and the first color pattern and is on an inner portion of the first color dam.

5. The display device according to claim 3, wherein The display device further includes a bending protection layer, which is on the outer coating layer and overlaps with the bending area. The display device according to claim 3 , wherein: The display device further includes a bending structure, wherein the bending structure includes a plurality of through-hole layers in the bending region and wiring layers between the through-hole layers. Wherein, at least a portion of the first color pattern covers the bending structure.

7. The display device according to claim 1, wherein A portion of the first color pattern is outside the bending area of ​​the sub-region, The first color dam is between the bending area and the main area, and The second color dam is between the first color dam and the bending region.

8. The display device according to claim 7, wherein: The outer coating does not overlap the first color pattern, or Wherein, the outer coating is on the interior of the first color dam.

9. The display device according to claim 1, wherein The display device further includes a light blocking layer in the main area and including a plurality of holes overlapping the plurality of pixel electrodes, The plurality of color filters respectively overlap with the plurality of holes of the light blocking layer.

10. The display device according to claim 1, wherein Among the plurality of color filters, different color filters adjacent to each other overlap each other, The display device further includes a plurality of color light blocking layers in regions where the different color filters overlap.

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