Semiconductor device

Abstract

A semiconductor device (1) is rectangular in plan view with a side length in a first direction being equal to or greater than a side length in a second direction, has 2n+1 long circular first source pads (111) of first vertical MOS transistors (10) arranged in a strip shape and extending in the second direction at a position included in a first region (A1), has 2n+1 long circular second source pads (121) of second vertical MOS transistors (20) arranged in a strip shape and extending in the second direction at a position included in a second region (A2), a first source pad (111a) closest to a boundary line (90) between the first region (A1) and the second region (A2) among the 2n+1 first source pads (111) is longer than the other first source pads (111), and a second source pad (121a) closest to the boundary line (90) among the 2n+1 second source pads (121) is longer than the other second source pads (121).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device. BACKGROUND

[0002] Conventionally, a semiconductor device that is mounted to a mounting substrate and switches an on state and an off state of a current path in the mounting substrate is known (for example, refer to Patent Literature 1).

[0003] PRIOR ART DOCUMENTS

[0004] PATENT LITERATURE

[0005] Patent Literature 1: International Publication No. 2020 / 129786 SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] Generally, a current path through which a large current flows in a mounting substrate is designed to reduce an on resistance. Therefore, for a semiconductor device that is mounted to a mounting substrate and switches an on state and an off state of a current path through which a large current flows, it is desirable to have a feature that is suitable for reducing an on resistance of a current path in the mounting substrate.

[0008] On the other hand, a semiconductor device configured by laminating a semiconductor layer and a metal layer in order to reduce an on resistance of the semiconductor device is known.

[0009] In a case where such a semiconductor device configured by laminating a semiconductor layer and a metal layer is mounted face down to a mounting substrate in a high temperature environment such as reflow of solder, under the high temperature environment, sometimes, the semiconductor device is warped due to a difference in physical parameters such as a coefficient of thermal expansion and a Young's modulus between the semiconductor layer and the metal layer.

[0010] And, due to the warping, sometimes, mounting failures such as overflow of solder, generation of a solder deficient portion, and the like occur.

[0011] Therefore, an object of the present disclosure is to provide a semiconductor device that has a feature suitable for reducing an on resistance of a current path in a mounting substrate to which the semiconductor device is mounted, and that is capable of suppressing occurrence of a mounting failure at the time of mounting the semiconductor device to the mounting substrate.

[0012] MEANS FOR SOLVING THE PROBLEMS

[0013] A semiconductor device according to an embodiment of the present disclosure is a chip size package type semiconductor device capable of face-down mounting, and includes a semiconductor layer, a metal layer formed in contact with a back surface of the semiconductor layer, a first vertical MOS transistor formed in a first region of the semiconductor layer, a second vertical MOS transistor formed in a second region of the semiconductor layer adjacent to the first region when the semiconductor device is viewed from above, 2n+1 first source pads of the first vertical MOS transistor and a first gate pad of the first vertical MOS transistor formed at a position included in the first region when viewed from above on an upper surface of the semiconductor device, n being an integer of 1 or more, and 2n+1 second source pads of the second vertical MOS transistor and a second gate pad of the second vertical MOS transistor formed at a position included in the second region when viewed from above on the upper surface of the semiconductor device, the semiconductor layer having a semiconductor substrate on the back surface side, the semiconductor substrate being a common drain region of the first vertical MOS transistor and the second vertical MOS transistor, the semiconductor layer being rectangular having a first side and a second side and a third side and a fourth side when viewed from above, the first side and the second side extending in a first direction and having lengths equal to each other, the third side and the fourth side extending in a second direction orthogonal to the first direction and having lengths equal to each other, the third side and the fourth side having lengths shorter than the lengths of the first side and the second side, the first region and the second region being one side and the other side that bisect the semiconductor layer in area, the third side being included in a periphery of the first region, the fourth side being included in a periphery of the second region, a boundary line between the first region and the second region being crank-shaped and being connected in order of a full length of a third line segment, a full length of a first line segment, a full length of a fourth line segment, a full length of a second line segment, and a full length of a fifth line segment from an end of one side of the boundary line toward an end of the other side of the boundary line when viewed from above, the first line segment and the second line segment being equal in length, the third line segment and the fifth line segment being equal in length, the end of the one side being located on the first side, the end of the other side being located on the second side, the fourth line segment being located on an imaginary center line of the semiconductor layer bisecting the semiconductor layer in area when viewed from above, the center line extending in a straight line in the second direction, the first gate pad being circular, a center of the first gate pad being located on the center line, and no other pad being present between the first gate pad and the second side.The second gate pad is a circle having the same diameter as the first gate pad, a center of the second gate pad is located on the center line, there is no other pad between the second gate pad and the first side, the 2n+1 first source pads and the 2n+1 second source pads are oblong circles having the second direction as a long side direction, widths of the 2n+1 first source pads and the 2n+1 second source pads in a short side direction are equal, the 2n+1 first source pads include a first closest source pad closest to the fourth line segment and 2n first non-closest source pads which are not closest to the fourth line segment, the first closest source pad is configured such that a line symmetry axis extending in the long side direction coincides with a first closest equally-spaced line closest to the fourth line segment among n+1 first equally-spaced lines which are imaginary first equally-spaced lines extending in the second direction in the first region and are arranged equally-spaced in the first direction, the 2n first non-closest source pads are configured such that line symmetry axes extending in the long side direction of two first non-closest source pads among the 2n first non-closest source pads coincide with corresponding first non-closest equally-spaced lines among n first non-closest equally-spaced lines other than the first closest equally-spaced line among the n+1 first equally-spaced lines, the 2n+1 second source pads include a second closest source pad closest to the fourth line segment and 2n second non-closest source pads which are not closest to the fourth line segment, the second closest source pad is configured such that a line symmetry axis extending in the long side direction coincides with a second closest equally-spaced line closest to the fourth line segment among n+1 second equally-spaced lines which are imaginary second equally-spaced lines extending in the second direction in the second region and are arranged equally-spaced in the first direction, the 2n second non-closest source pads are configured such that line symmetry axes extending in the long side direction of two second non-closest source pads among the 2n second non-closest source pads coincide with corresponding second non-closest equally-spaced lines among n second non-closest equally-spaced lines other than the second closest equally-spaced line among the n+1 second equally-spaced lines, and the 2n+1 first source pads and the 2n+1 second source pads are line symmetric with the center line as a line symmetry axis.

[0014] Effects of Invention

[0015] According to the semiconductor device of one aspect of the present disclosure, there is provided a semiconductor device having a feature suitable for reducing an on-resistance of a current path in a mounting substrate on which the semiconductor device is mounted, and capable of suppressing occurrence of mounting failure when the semiconductor device is mounted to the mounting substrate. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1is a plan view showing one example of a configuration of a semiconductor device of an embodiment.

[0017] Figure 2 is a sectional view showing one example of a configuration of a semiconductor device of an embodiment.

[0018] Figure 3 is a circuit diagram of a semiconductor device of an embodiment.

[0019] Figure 4 is a plan view showing another example of a configuration of a semiconductor device of an embodiment.

[0020] Figure 5A is a sectional view schematically showing a case where current flows in a first current path of a semiconductor device of an embodiment.

[0021] Figure 5B is a sectional view schematically showing a case where current flows in a second current path of a semiconductor device of an embodiment.

[0022] Figure 6 is a circuit diagram of a charge / discharge circuit of an embodiment.

[0023] Figure 7 is an enlarged plan view of a mounting substrate of an embodiment.

[0024] Figure 8 is a schematic view showing a case where an orientation of a semiconductor device of an embodiment is reversed. DETAILED DESCRIPTION

[0025] (Process of obtaining one aspect of the present disclosure)

[0026] It is known that, in the case where a semiconductor device configured by laminating a semiconductor layer and a metal layer is mounted face down on a mounting substrate in a high-temperature environment such as reflow of solder, when warping occurs in the semiconductor device, the direction of the warping becomes a direction in which curvature occurs along the long-side direction of the semiconductor device in plan view.

[0027] Therefore, in the semiconductor device of the above-described configuration, in order to ensure the flowability of solder at the time of reflow and suppress occurrence of mounting failure due to the above-described warping, it is considered to be one of effective countermeasures to adopt a countermeasure in which the shapes of a plurality of relatively large pads formed on the surface of the semiconductor device are set to oblong shapes with the long-side direction of the semiconductor layer as the long-side direction.

[0028] In view of the foregoing, the inventors have found, through development of the semiconductor device having the above-described structure, that in the case where the semiconductor device having the above-described structure satisfies a certain condition such as a case where a difference between a length in a long side direction and a length in a short side direction when viewed from above is small, for example, occurrence of mounting failure due to warping of the semiconductor device does not become a serious problem.

[0029] Further, the inventors have found that, in such a case, in order to suppress occurrence of mounting failure, necessity of setting the long side direction of the semiconductor device and the long side direction of the pad in the oblong shape to be in the same direction when viewed from above the semiconductor device becomes lower.

[0030] In addition, the inventors have found that, in the case where a plurality of pads in the oblong shape are formed on the surface of the semiconductor device, if the shapes of the semiconductor devices are the same, compared to the case where the long side direction of the semiconductor device and the long side direction of the pad in the oblong shape are set to be in the same direction when viewed from above the semiconductor device, setting the long side direction of the semiconductor device and the long side direction of the pad in the oblong shape to be in directions orthogonal to each other when viewed from above the semiconductor device can increase an area occupancy ratio of the plurality of pads in the oblong shape, that is, can reduce an on-resistance of a current path in the semiconductor device.

[0031] Further, the inventors have found that, in such a case, in order to suppress occurrence of mounting failure, necessity of setting the long side direction of the semiconductor device and the long side direction of the pad in the oblong shape to be in the same direction when viewed from above the semiconductor device becomes lower.

[0032] A semiconductor device of the present disclosure is a chip size package type semiconductor device capable of face-down mounting, and includes: a semiconductor layer; a metal layer formed in contact with a back surface of the semiconductor layer; a first vertical MOS transistor formed in a first region of the semiconductor layer; a second vertical MOS transistor formed in a second region of the semiconductor layer adjacent to the first region when the semiconductor device is viewed from above; 2n+1 first source pads of the first vertical MOS transistor and a first gate pad of the first vertical MOS transistor formed at a position included in the first region when viewed from above on an upper surface of the semiconductor device, n being an integer of 1 or more; and 2n+1 second source pads of the second vertical MOS transistor and a second gate pad of the second vertical MOS transistor formed at a position included in the second region when viewed from above on the upper surface of the semiconductor device; the semiconductor layer having a semiconductor substrate on the back surface side, the semiconductor substrate being a common drain region of the first vertical MOS transistor and the second vertical MOS transistor, the semiconductor layer being a rectangle having a first side and a second side and a third side and a fourth side when viewed from above, the first side and the second side extending in a first direction and having lengths equal to each other, the third side and the fourth side extending in a second direction orthogonal to the first direction and having lengths equal to each other, the third side and the fourth side having lengths shorter than the lengths of the first side and the second side, the first region and the second region being one side and the other side that bisect the semiconductor layer in area, the third side being included in a circumference of the first region, the fourth side being included in a circumference of the second region, a boundary line between the first region and the second region being crank-shaped, being connected in order of a full length of a third line segment, a full length of a first line segment, a full length of a fourth line segment, a full length of a second line segment, and a full length of a fifth line segment from an end of one side of the boundary line toward an end of the other side of the boundary line, and monotonously changing in the first direction and the second direction from the end of the one side toward the end of the other side, a length of the first line segment being equal to a length of the second line segment, a length of the third line segment being equal to a length of the fifth line segment, the end of the one side being located on the first side, the end of the other side being located on the second side, the fourth line segment being located on an imaginary center line of the semiconductor layer bisecting the semiconductor layer in area when viewed from above, and the center line extending in a straight line in the second direction, the first gate pad being circular, a center of the first gate pad being located on the center line, and no other pad being present between the first gate pad and the second side,The second gate pad is a circle having the same diameter as the first gate pad, a center of the second gate pad is located on the center line, there is no other pad between the second gate pad and the first side, the 2n+1 first source pads and the 2n+1 second source pads are oblong circles having the second direction as a long side direction, widths of the 2n+1 first source pads and the 2n+1 second source pads in a short side direction are equal, the 2n+1 first source pads include a first closest source pad closest to the fourth line segment and 2n first non-closest source pads which are not closest to the fourth line segment, the first closest source pad is arranged such that a line symmetry axis extending in the long side direction coincides with a first closest equally-spaced line closest to the fourth line segment among n+1 first equally-spaced lines which are imaginary first equally-spaced lines extending in the second direction in the first region and are arranged equally-spaced in the first direction, the 2n first non-closest source pads are arranged such that line symmetry axes extending in the long side direction of two first non-closest source pads among the 2n first non-closest source pads coincide with corresponding first non-closest equally-spaced lines among n first non-closest equally-spaced lines other than the first closest equally-spaced line among the n+1 first equally-spaced lines, the 2n+1 second source pads include a second closest source pad closest to the fourth line segment and 2n second non-closest source pads which are not closest to the fourth line segment, the second closest source pad is arranged such that a line symmetry axis extending in the long side direction coincides with a second closest equally-spaced line closest to the fourth line segment among n+1 second equally-spaced lines which are imaginary second equally-spaced lines extending in the second direction in the second region and are arranged equally-spaced in the first direction, the 2n second non-closest source pads are arranged such that line symmetry axes extending in the long side direction of two second non-closest source pads among the 2n second non-closest source pads coincide with corresponding second non-closest equally-spaced lines among n second non-closest equally-spaced lines other than the second closest equally-spaced line among the n+1 second equally-spaced lines, and the 2n+1 first source pads and the 2n+1 second source pads are line symmetric with respect to the center line as a line symmetry axis.

[0033] According to the semiconductor device described above, when the semiconductor device is viewed from above, the long side direction of the semiconductor device and the long side directions of the 2n+1 first source pads and the 2n+1 second source pads become directions orthogonal to each other.

[0034] Therefore, according to the semiconductor device having the above structure, compared with a structure in which the long side direction of the semiconductor device coincides with the long side direction of the 2n+1 first source pads and the 2n+1 second source pads when the semiconductor device is viewed from above, the area occupancy ratio of the 2n+1 first source pads and the area occupancy ratio of the 2n+1 second source pads can be increased.

[0035] Therefore, according to the semiconductor device having the above structure, compared with a structure in which the long side direction of the semiconductor device coincides with the long side direction of the 2n+1 first source pads and the 2n+1 second source pads when the semiconductor device is viewed from above, the area occupancy ratio of the 2n+1 first source pads and the area occupancy ratio of the 2n+1 second source pads can be increased.

[0036] In addition, the semiconductor device having the above structure generally has a metal layer having a lower resistivity than the semiconductor layer, and the metal layer becomes a part of the current path of the current flowing between the first vertical MOS transistor and the second vertical MOS transistor.

[0037] Therefore, according to the semiconductor device having the above structure, compared with a structure in which the long side direction of the semiconductor device coincides with the long side direction of the 2n+1 first source pads and the 2n+1 second source pads when the semiconductor device is viewed from above, the area occupancy ratio of the 2n+1 first source pads and the area occupancy ratio of the 2n+1 second source pads can be increased.

[0038] In addition, according to the semiconductor device having the above structure, at the position of the center of the semiconductor device in the first direction of the second side when the semiconductor device is viewed from above, the first gate pad can be brought close to the position closest to the second side according to design rules, and further, at the position of the center of the semiconductor device in the first direction of the first side, the second gate pad can be brought close to the position closest to the first side according to design rules.

[0039] Therefore, according to the semiconductor device having the above structure, compared with a structure in which the long side direction of the semiconductor device coincides with the long side direction of the 2n+1 first source pads and the 2n+1 second source pads when the semiconductor device is viewed from above, the area occupancy ratio of the 2n+1 first source pads and the area occupancy ratio of the 2n+1 second source pads can be increased.

[0040] Therefore, according to the semiconductor device having the above structure, compared with a structure in which the long side direction of the semiconductor device coincides with the long side direction of the 2n+1 first source pads and the 2n+1 second source pads when the semiconductor device is viewed from above, the area occupancy ratio of the 2n+1 first source pads and the area occupancy ratio of the 2n+1 second source pads can be increased.

[0041] In addition, in the present specification, the center when viewed from above, for example, for a configuration having a rectangular shape when viewed from above such as a semiconductor device, means the intersection of the diagonals of the rectangle, for example, for a configuration having a circular shape when viewed from above such as a gate pad, means the center of the circle, for example, for a configuration having an oblong shape when viewed from above such as a source pad, means the intersection of the line of symmetry extending in the long side direction of the oblong and the line of symmetry extending in the short side direction of the oblong, and for a configuration having an elliptical shape when viewed from above, means the intersection of the major axis and the minor axis of the ellipse.

[0042] Further, according to the semiconductor device described above, two first non-closest source pads are arranged on each first non-closest equal-interval line, and two second non-closest source pads are arranged on each second non-closest equal-interval line, in a plan view of the semiconductor device.

[0043] Therefore, according to the semiconductor device described above, compared with a structure in which one first non-closest source pad is arranged on each first non-closest equal-interval line, and one second non-closest source pad is arranged on each second non-closest equal-interval line, in a plan view of the semiconductor device, occurrence of mounting failure caused by warping of the semiconductor device can be suppressed. This is because the shorter the length of each of the first non-closest source pads in the longitudinal direction, the lower the frequency of occurrence of mounting failure, and the shorter the length of each of the second non-closest source pads in the longitudinal direction, the lower the frequency of occurrence of mounting failure.

[0044] Thus, according to the semiconductor device described above, a semiconductor device having a feature of reducing the on-resistance of a current path in a mounting substrate for mounting, and capable of suppressing occurrence of mounting failure when the semiconductor device is mounted on the mounting substrate, is provided.

[0045] Further, it can also be that, in the plan view, the length of the first closest source pad in the longitudinal direction is longer than the length of each of the 2n first non-closest source pads in the longitudinal direction, and the length of the second closest source pad in the longitudinal direction is longer than the length of each of the 2n second non-closest source pads in the longitudinal direction.

[0046] Thus, according to the semiconductor device described above, in a plan view of the semiconductor device, the first closest source pad, which is the largest of the 2n+1 first source pads, and the second closest source pad, which is the largest of the 2n+1 second source pads, are arranged closest to the fourth line segment, which is the line segment with the highest current density in the current path of the current flowing between the first vertical MOS transistor and the second vertical MOS transistor.

[0047] Therefore, according to the semiconductor device described above, the on-resistance of the current path of the current flowing between the 2n+1 first source pads and the 2n+1 second source pads can be reduced.

[0048] In addition, it can also be that, in the plan view, the closest distance between the 2 first non-closest source pads coinciding with the line symmetry axis extending in the long side direction in the plan view and the corresponding first non-closest equally-spaced line of the n first non-closest equally-spaced lines, and the closest distance between the 2 second non-closest source pads coinciding with the line symmetry axis extending in the long side direction in the plan view and the corresponding second non-closest equally-spaced line of the n second non-closest equally-spaced lines, is less than the diameter of the first gate pad and the diameter of the second gate pad.

[0049] Thus, when the semiconductor device is viewed in plan, reduction in the area occupancy of the 2n first non-closest source pads due to the two first non-closest source pads being arranged with a gap on each first non-closest equally-spaced line, and reduction in the area occupancy of the 2n second non-closest source pads due to the two second non-closest source pads being arranged with a gap on each second non-closest equally-spaced line, can be suppressed.

[0050] In addition, it can also be that, in the plan view, the closest distance between the 2 first non-closest source pads coinciding with the line symmetry axis extending in the long side direction in the plan view and the corresponding first non-closest equally-spaced line of the n first non-closest equally-spaced lines, and the closest distance between the 2 second non-closest source pads coinciding with the line symmetry axis extending in the long side direction in the plan view and the corresponding second non-closest equally-spaced line of the n second non-closest equally-spaced lines, is less than the diameter of the first gate pad and the diameter of the second gate pad.

[0051] In addition, it can also be that, in the plan view, a closest distance between the first non-closest source pad closer to the first edge of the 2 first non-closest source pads coinciding with the line symmetry axis extending in the long edge direction in the plan view and the first edge is shorter than a closest distance between the first closest source pad and the first edge, a closest distance between the first non-closest source pad closer to the second edge of the 2 first non-closest source pads coinciding with the line symmetry axis extending in the long edge direction in the plan view and the second edge is shorter than a closest distance between the first closest source pad and the second edge, a closest distance between the second non-closest source pad closer to the first edge of the 2 second non-closest source pads coinciding with the line symmetry axis extending in the long edge direction in the plan view and the first edge is shorter than a closest distance between the second closest source pad and the first edge, and a closest distance between the second non-closest source pad closer to the second edge of the 2 second non-closest source pads coinciding with the line symmetry axis extending in the long edge direction in the plan view and the second edge is shorter than a closest distance between the second closest source pad and the second edge.

[0052] Thus, reduction in the area occupancy of the 2n first non-closest source pads and reduction in the area occupancy of the 2n second non-closest source pads can be suppressed.

[0053] In addition, in the plan view, a distance between a center of a first non-closest source pad of the 2 first non-closest source pads that coincides with the line symmetry axis extending in the long side direction in the plan view and a corresponding first non-closest equal-interval line of the n first non-closest equal-interval lines and the first edge can be longer than a closest distance between the first closest source pad and the first edge, and a distance between a center of a second non-closest source pad of the 2 second non-closest source pads that coincides with the line symmetry axis extending in the long side direction in the plan view and a corresponding second non-closest equal-interval line of the n second non-closest equal-interval lines and the second edge can be longer than a closest distance between the second closest source pad and the second edge.

[0054] In addition, in the plan view, a closest distance between the first closest source pad and the fourth line segment can be shorter than a closest distance in the first direction between 2 first source pads of the 2n+1 first source pads that are adjacent to each other in the first direction, and a closest distance between the second closest source pad and the fourth line segment can be shorter than a closest distance in the first direction between 2 second source pads of the 2n+1 second source pads that are adjacent to each other in the first direction.

[0055] In addition, in the plan view, if a first length of the semiconductor layer in the first direction is set as Lx, a second length of the semiconductor layer in the second direction is set as Ly, and a diameter of the first gate pad and the second gate pad is set as d, Ly≤14×d and Lx≤Ly+2×d can be satisfied.

[0056] Thus, when the semiconductor device is viewed from above, the shape of the semiconductor device becomes a rectangle that is relatively close to a square. Therefore, the degree of warping of the semiconductor device in a high-temperature environment is relatively small.

[0057] According to the semiconductor device having the above structure, it is possible to suppress occurrence of mounting failure when mounting the semiconductor device on a mounting substrate.

[0058] In addition, n can be 3, and the widths of the 2n+1 first source pads and the 2n+1 second source pads can be smaller than the diameters of the first gate pad and the second gate pad in the plan view.

[0059] Hereinafter, a specific example of a semiconductor device according to an embodiment of the present disclosure will be described with reference to the drawings. The embodiments shown in the drawings each represent one specific example of the present disclosure. Therefore, the numerical values, shapes, constituent elements, arrangement and connection modes of the constituent elements, and steps (procedures) and orders of the steps shown in the following embodiments are one example, and are not intended to limit the present disclosure. In addition, each drawing is a schematic view, and is not necessarily strictly mapped. In each drawing, the same reference signs are attached to substantially identical structures, and overlapping descriptions are omitted or simplified.

[0060] (Embodiment)

[0061] Hereinafter, a semiconductor device according to an embodiment will be described. The semiconductor device is a chip size package type semiconductor device capable of face-down mounting, which has two longitudinal MOS (Metal Oxide Semiconductor) transistors.

[0062] <Configuration of Semiconductor Device>

[0063] Figure 1 is a plan view showing one example of the configuration of the semiconductor device 1 according to the embodiment. As shown in Figure 1 , the semiconductor device 1 is rectangular when viewed from above, has a first side 71 and a second side 72 each of which has a length equal to each other and extends in a first direction (X-axis direction in Figure 1 ), and has a third side 73 and a fourth side 74 each of which has a length equal to each other and extends in a second direction (Y-axis direction in Figure 1 ) orthogonal to the first direction, and the lengths of the third side 73 and the fourth side 74 are shorter than the lengths of the first side 71 and the second side 72.

[0064] In addition, in Figure 1 , the outer periphery of a portion 13 (described later) of the first source electrode 11 (not shown in Figure 1 , described later) when viewed from above the semiconductor device 1, and the outer periphery of a portion 23 (described later) of the second source electrode 21 (not shown in Figure 1 , described later) when viewed from above the semiconductor device 1 are illustrated by broken lines as if they can be visually recognized, but in fact they cannot be visually recognized directly from the outside of the semiconductor device 1.

[0065] Figure 2 is a sectional view showing one example of the configuration of the semiconductor device 1, and is a sectional view showing a section of the boundary line 90 at II-II of Figure 1

[0066] Figure 3 is a circuit diagram of the semiconductor device 1.

[0067] As shown in Figures 1-3 , the semiconductor device 1 includes a semiconductor layer 40, a metal layer 30, an interlayer insulating layer 34, a passivation layer 35, a first vertical MOS transistor 10 formed in a first region Al of the semiconductor layer 40, and a second vertical MOS transistor 20 formed in a second region A2 of the semiconductor layer 40 which is adjacent to the first region Al when the semiconductor device 1 is viewed in plan.

[0068] Here, the first region Al and the second region A2 are one side and the other side which bisect the semiconductor layer 40 in area when the semiconductor device 1 is viewed in plan, the third edge 73 is included in the outer periphery of the first region Al, and the fourth edge 74 is included in the outer periphery of the second region A2.

[0069] The boundary line 90 of the first region Al and the second region A2 is crank-shaped when the semiconductor device 1 is viewed in plan, is formed by connecting a first line segment 91 and a second line segment 92 which extend in a straight line in the first direction, and a third line segment 93, a fourth line segment 94, and a fifth line segment 95 which extend in a straight line in the second direction from one end 61 of the boundary line 90 toward the other end 62 of the boundary line 90 in the order of the entire length of the third line segment 93, the entire length of the first line segment 91, the entire length of the fourth line segment 94, the entire length of the second line segment 92, and the entire length of the fifth line segment 95, and monotonically changes in the first direction and the second direction from the one end 61 of the boundary line 90 toward the other end 62 of the boundary line 90.

[0070] In the present specification, the boundary line being crank-shaped means that the boundary line is a shape in which line segments which extend in a straight line in the first direction and line segments which extend in a straight line in the second direction are alternately connected in a manner of monotonically changing in the first direction and the second direction.

[0071] In addition, in the present specification, monotonically changing means a function which monotonically increases in a broad sense or a function which monotonically decreases in a broad sense. That is, the function which monotonically increases in a broad sense means a function f(x) which becomes f(xl) < f(x2) in the case of xl < x2, and the function which monotonically decreases in a broad sense means a function f(x) which becomes f(xl) > f(x2) in the case of xl < x2.

[0072] ​Here, when viewed from above the semiconductor device 1, (1) the length of the first line segment 91 is equal to the length of the second line segment 92, (2) the length of the third line segment 93 is equal to the length of the fifth line segment 95, (3) the end 61 of one side is located on the first side 71, (4) the end 62 of the other side is located on the second side 72, and (5) when viewed from above the semiconductor device 1, the fourth line segment 94 is located on the imaginary center line 80 of the semiconductor layer 40 that divides the semiconductor layer 40 into two equal parts in area, that is, the center line 80 that extends in a straight line in the second direction.

[0073] Furthermore, the semiconductor device 1 includes a first vertical MOS transistor 10 with 2n (n is an integer greater than or equal to 1) formed in a position included in the first region A1 when viewed from above. Figure 1 In the middle, n is 3) + 1 first source pad 111 (corresponding to Figure 1 The first source pads 111a to 111g are included in the first source pad 111. Hereinafter, without explicitly distinguishing each individual component, the first source pads 111a to 111g will also be simply referred to as "first source pads 111". The first gate pad 119 of the first vertical MOS transistor 10 is also included, and the second vertical MOS transistor 20 has 2n+1 second source pads 121 (corresponding to...) formed in the second region A2 when viewed from above. Figure 1 The second source pads 121a to 121g are described below. Hereinafter, without explicitly distinguishing each individual component, the second source pads 121a to 121g will also be referred to simply as "second source pads 121". The second gate pad 129 of the second vertical MOS transistor 20 is also mentioned.

[0074] When viewed from above, (1) the first gate pad 119 is circular, (2) the center of the first gate pad 119 is located on the center line 80, (3) there are no other pads between the first gate pad 119 and the second side 72, (4) the second gate pad 129 is a circle with the same diameter as the first gate pad 119, (5) the center of the second gate pad 129 is located on the center line 80, and (6) there are no other pads between the second gate pad 129 and the first side 71.

[0075] When the semiconductor device 1 is viewed in plan, (1) the 2n+l first source pads 111 and the 2n+l second source pads 121 are long circular shapes with the second direction as the long side direction, (2) the widths of the 2n+l first source pads 111 and the 2n+l second source pads 121 in the short side direction are equal, (3) the 2n+l first source pads 111 include a first closest source pad 111a closest to the fourth line segment 94 and 2n first non-closest source pads 111b to 111g (hereinafter, the first non-closest source pads 111b to 111g are also simply referred to as "first non-closest source pads 111bg" in cases where it is not necessary to explicitly distinguish each individual from one another) that are not closest to the fourth line segment 94, and (4) the 2n+l second source pads 121 include a second closest source pad 121a closest to the fourth line segment 94 and 2n second non-closest source pads 121b to 121g (hereinafter, the second non-closest source pads 121b to 121g are also simply referred to as "second non-closest source pads 121bg" in cases where it is not necessary to explicitly distinguish each individual from one another) that are not closest to the fourth line segment 94.

[0076] Here, when the semiconductor device 1 is viewed in plan, (1) the first closest source pad 111a is arranged so that a line symmetry axis extending in the long side direction coincides with a first closest equally-spaced line 81a closest to the fourth line segment 94 among n+1 first equally-spaced lines 81a to 81d extending in the second direction in the first region Al and arranged at equal intervals in the first direction, and (2) the 2n first non-closest source pads 111bg are arranged so that line symmetry axes extending in the long side direction of two first non-closest source pads 111bg each coincide with a first non-closest equally-spaced line 81bd among the n first non-closest equally-spaced lines 81b to 81d (hereinafter, the first non-closest equally-spaced lines 81b to 81d are also simply referred to as "first non-closest equally-spaced lines 81bd" in cases where it is not necessary to explicitly distinguish each individual from one another) other than the first closest equally-spaced line 81a among the n+1 first equally-spaced lines 81a to 81d. That is, when the semiconductor device 1 is viewed in plan, the first source pads 111 are arranged in a strip-like arrangement.

[0077] In addition, when viewed from above the semiconductor device 1, (1) the second closest source pad 121a is arranged so that a line symmetry axis extending in the longitudinal direction coincides with the second closest second equally spaced line 82a among the n+1 second equally spaced lines 82a to 82d extending in the second direction and arranged at equal intervals in the first direction in the second region A2, and (2) the 2n second non-closest source pads 121bg are arranged so that line symmetry axes extending in the longitudinal direction of two of the second non-closest source pads 121bg coincide with the second non-closest equally spaced line 82bd among the n second non-closest equally spaced lines 82b to 82d (hereinafter, the second non-closest equally spaced lines 82b to 82d are also simply referred to as "second non-closest equally spaced lines 82bd" in cases where it is not necessary to explicitly distinguish between the individual lines from each other). That is, when viewed from above the semiconductor device 1, the second source pads 121 are arranged in a strip shape.

[0078] Here, it can also be that, when viewed from above the semiconductor device 1, (1) the length of the first closest source pad 111a in the longitudinal direction is longer than the length of each of the 2n first non-closest source pads 111bg in the longitudinal direction, and (2) the length of the second closest source pad 121a in the longitudinal direction is longer than the length of each of the 2n second non-closest source pads 121bg in the longitudinal direction.

[0079] Thus, when viewed from above the semiconductor device 1, the largest of the 2n+1 first source pads 111, that is, the first closest source pad 111a, and the largest of the 2n+1 second source pads 121, that is, the second closest source pad 121a, are arranged closest to the fourth line segment 94 having the highest current density among the current paths of the current flowing between the first vertical MOS transistor 10 and the second vertical MOS transistor 20.

[0080] Therefore, it is possible to reduce the on-resistance of the current paths of the current flowing between the 2n+1 first source pads 111 and the 2n+1 second source pads 121.

[0081] In addition, when viewed from above the semiconductor device 1, the 2n+1 first source pads 111 and the 2n+1 second source pads 121 are line-symmetric with the center line 80 as a line symmetry axis.

[0082] Furthermore, as Figure 1As shown, the closest distance between the two first non-closest source pads 111bg whose outer peripheries coincide with the corresponding first non-closest equal-interval lines 81bd of the n first non-closest equal-interval lines 81bd extending in the long-side direction when the semiconductor device 1 is viewed from above and the line symmetry axis extending in the long-side direction when the semiconductor device 1 is viewed from above, and the closest distance between the two second non-closest source pads 121bg whose outer peripheries coincide with the corresponding second non-closest equal-interval lines 82bd of the n second non-closest equal-interval lines 82bd extending in the long-side direction when the semiconductor device 1 is viewed from above and the line symmetry axis extending in the long-side direction when the semiconductor device 1 is viewed from above, can be smaller than the diameter of the first gate pad 119 and the diameter of the second gate pad 129.

[0083] Thus, the reduction in the area occupancy of the 2n first non-closest source pads 111bg due to the two first non-closest source pads 111bg being arranged with a gap on each first non-closest equal-interval line 81bd when the semiconductor device 1 is viewed from above, and the reduction in the area occupancy of the 2n second non-closest source pads 121bg due to the two second non-closest source pads 121bg being arranged with a gap on each second non-closest equal-interval line 82bd when the semiconductor device 1 is viewed from above, can be suppressed.

[0084] In addition, as shown, Figure 1 As shown, the closest distance between the two first non-closest source pads 111bg whose outer peripheries coincide with the corresponding first non-closest equal-interval lines 81bd of the n first non-closest equal-interval lines 81bd extending in the long-side direction when the semiconductor device 1 is viewed from above and the line symmetry axis extending in the long-side direction when the semiconductor device 1 is viewed from above, and the closest distance between the two second non-closest source pads 121bg whose outer peripheries coincide with the corresponding second non-closest equal-interval lines 82bd of the n second non-closest equal-interval lines 82bd extending in the long-side direction when the semiconductor device 1 is viewed from above and the line symmetry axis extending in the long-side direction when the semiconductor device 1 is viewed from above, can be smaller than the diameter of the first gate pad 119 and the diameter of the second gate pad 129.

[0085] In addition, as shown, Figure 1As shown, the closest distance between the first non-closest source pad 111bg closer to the first edge 71 among the two first non-closest source pads 111bg coinciding with the corresponding first non-closest equal-interval line 81bd of the n first non-closest equal-interval lines 81bd and the first edge 71 can be shorter than the closest distance between the first closest source pad 111a and the first edge 71 when the semiconductor device 1 is viewed in plan, and the closest distance between the first non-closest source pad 111bg closer to the second edge 72 among the two first non-closest source pads 111bg coinciding with the corresponding first non-closest equal-interval line 81bd of the n first non-closest equal-interval lines 81bd and the second edge 72 can be shorter than the closest distance between the first closest source pad 111a and the second edge 72 when the semiconductor device 1 is viewed in plan, and the closest distance between the second non-closest source pad 121bg closer to the first edge 71 among the two second non-closest source pads 121bg coinciding with the corresponding second non-closest equal-interval line 82bd of the n second non-closest equal-interval lines 82bd and the first edge 71 can be shorter than the closest distance between the second closest source pad 121a and the first edge 71 when the semiconductor device 1 is viewed in plan, and the closest distance between the second non-closest source pad 121bg closer to the second edge 72 among the two second non-closest source pads 121bg coinciding with the corresponding second non-closest equal-interval line 82bd of the n second non-closest equal-interval lines 82bd and the second edge 72 can be shorter than the closest distance between the second closest source pad 121a and the second edge 72 when the semiconductor device 1 is viewed in plan.

[0086] Thus, the reduction in the area occupancy ratio of the 2n first non-closest source pads 111bg and the reduction in the area occupancy ratio of the 2n second non-closest source pads 121bg can be suppressed.

[0087] Further, the reason why the first non-closest source pad 111bg coinciding with the corresponding first non-closest equal-interval line 81bd of each first non-closest equal-interval line 81bd is provided in two instead of one and the reason why the second non-closest source pad 121bg coinciding with the corresponding second non-closest equal-interval line 82bd of each second non-closest equal-interval line 82bd is provided in two instead of one is that the longer the length in the long-side direction of each of the first non-closest source pad 111bg and the second non-closest source pad 121bg, the higher the frequency of occurrence of mounting failure.

[0088] Additionally, the position of the midpoint of the imaginary line segment connecting the closest points on the outer peripheries of the two first non-closest source pads 111bg that coincide with the first non-closest equidistant line 81bd along the long side direction when viewed from above the semiconductor device 1, and the position of the midpoint of the imaginary line segment coinciding with the corresponding first non-closest equidistant line 82bd along the long side direction when viewed from above the semiconductor device 1, and the position of the midpoint of the imaginary line segment connecting the closest points on the outer peripheries of the two first non-closest source pads 111bg that coincide with the corresponding first non-closest equidistant line 82bd along the long side direction when viewed from above the semiconductor device 1, and the position of the midpoint of the imaginary line segment connecting the closest points on the outer peripheries of the two first non-closest source pads 111bg along the long side direction when viewed from above the semiconductor device 1, and the position of the midpoint of the imaginary line segment coinciding with the corresponding second non-closest equidistant line 82bd .... The reason why the midpoint of the imaginary line segment connecting the closest points on the outer periphery of the second non-closest source pad 121bg to each other in the second direction is consistent with the position of the center 111a1 of the first closest source pad 111a and the center 121a1 of the second closest source pad 121a in the second direction is that, in this way, the first non-closest source pad 111bg and the second non-closest source pad 121bg can be formed near the first side 71 or the second side 72.

[0089] In addition, such as Figure 1 As shown, it can also be that, when viewed from above the semiconductor device 1, (1) the center of the first non-closest source pad 111bg closest to the first side 71 among the two first non-closest source pads 111bg whose axis of symmetry along the long side direction when viewed from above the semiconductor device 1 coincides with the first non-closest equidistant line 81bd among the n first non-closest equidistant lines 81bd. Figure 1 The distance between the center 111c1, center 111e1 or center 111g1) and the first side 71 is longer than the closest distance between the first closest source pad 111a and the first side 71. (2) When viewed from above, the center of the first non-closest source pad 111bg that is closer to the second side 72 is the center of the first non-closest source pad 111bg that is the same as the first non-closest equidistant line 81bd in the n first non-closest equidistant lines 81bd when the line symmetry axis extends along the long side direction and is consistent with the first non-closest equidistant line 81bd. Figure 1 The distance between the center 111b1, center 111d1 or center 111f1) and the second side 72 is longer than the closest distance between the first closest source pad 111a and the second side 72. (3) When viewed from above, the center of the second non-closest source pad 121bg that is closer to the first side 71 is the center of the second non-closest source pad 121bg that is consistent with the second non-closest equidistant line 82bd in the line symmetry axis extending along the long side direction of the semiconductor device 1 and the second non-closest equidistant line 82bd. Figure 1the distance between the center 121b1, the center 121d1, or the center 121f1 in the second most close source pad 121a and the second edge 72 is longer than the closest distance between the second most close source pad 121a and the second edge 72. Figure 1 the distance between the center 121b1, the center 121d1, or the center 121f1 in the second most close source pad 121a and the second edge 72 is longer than the closest distance between the second most close source pad 121a and the second edge 72.

[0090] In addition, as shown in FIG. 1, it can also be that, when the semiconductor device 1 is viewed from above, (1) the closest distance between the first most close source pad 111a and the fourth line segment 94 is shorter than the closest distance in the first direction between two first source pads 111 that are adjacent to each other in the first direction among the 2n+1 first source pads 111, and (2) the closest distance between the second most close source pad 121a and the fourth line segment 94 is shorter than the closest distance in the first direction between two second source pads 121 that are adjacent to each other in the first direction among the 2n+1 second source pads 121. Figure 1

[0091] In addition, it can also be that, when the semiconductor device 1 is viewed from above, if a first length of the semiconductor layer 40 in the first direction is set as Lx, a second length of the semiconductor layer 40 in the second direction is set as Ly, and a diameter of the first gate pad 119 and the second gate pad 129 is set as d, then

[0092] Ly≤14×d

[0093] Lx≤Ly+2×d

[0094] is satisfied.

[0095] Thus, when the semiconductor device 1 is viewed from above, the shape of the semiconductor device 1 becomes a rectangle that is relatively close to a square. Therefore, the degree of warping of the semiconductor device 1 in a high-temperature environment is relatively small.

[0096] Therefore, according to the semiconductor device 1 having the above structure, it is possible to suppress the occurrence of mounting failure when the semiconductor device 1 is mounted to a mounting substrate.

[0097] ​Further, in this case, as a typical shape of the semiconductor device 1 in the case where d is 0.20 [mm], a shape in which, for example, Ly is 2.0 [mm] and Lx is 2.0 [mm] to 2.4 [mm], or a shape in which, for example, Ly is 2.5 [mm] and Lx is 2.5 [mm] to 2.9 [mm], or the like can be considered.

[0098] Further, in this case, as a typical shape of the semiconductor device 1 in the case where d is 0.20 [mm], a shape in which, for example, Ly is 2.0 [mm] and Lx is 2.0 [mm] to 2.4 [mm], or a shape in which, for example, Ly is 2.5 [mm] and Lx is 2.5 [mm] to 2.9 [mm], or the like can be considered.

[0099] Further, the reason why Ly is 14xd or less is that, as a result of experiments, simulations, and the like performed in advance by the inventors, it was confirmed that if the length in the long side direction of the first closest source pad 111a and the second closest source pad 121a is 8 times or less the diameter of the first gate pad 119 and the second gate pad 129, mounting failure can be suppressed from occurring, and further, the closest distance in the second direction between the first gate pad 119 and the second edge 72, the shortest distance in the second direction between the first gate pad 119 and the first closest source pad 111a, the closest distance in the second direction between the second gate pad 129 and the first edge 71, and the shortest distance in the second direction between the second gate pad 129 and the second closest source pad 121a are each observed with the diameter of the first gate pad 119 and the second gate pad 129.

[0100] Further, the reason why Lx is Ly+2d or less is that, as a result of experiments, simulations, and the like performed in advance by the inventors, it was confirmed that if Lx is within a range in which Ly is extended by at most 2 diameters of the first gate pad 119 and the second gate pad 129, the degree of warping of the semiconductor device 1 is within a range that does not have a serious influence on the occurrence of mounting failure.

[0101] Further, as shown in FIG. 1, the semiconductor device 1 can also be such that n is 3, and the width of the 2n+1 first source pads 111 and the 2n+1 second source pads 121 is smaller than the diameter of the first gate pad 119 and the second gate pad 129 when the semiconductor device 1 is viewed in plan. Figure 4

[0102] However, n can be an integer of 2 or more, and need not be limited to 3, and for example, n can be an integer of 2 or more.

[0103] Figures 1-3 ​is a plan view showing one example of the configuration of the semiconductor device 1 in the case where n is 2.

[0104] Returning again Figure 2 to the description of the configuration of the semiconductor device 1.

[0105] The semiconductor layer 40 is configured by laminating the semiconductor substrate 32 and the low-concentration impurity layer 33.

[0106] The semiconductor substrate 32 is disposed on the back surface side of the semiconductor layer 40, and is composed of silicon of the first conductivity type containing impurities of a first concentration.

[0107] The low-concentration impurity layer 33 is disposed on the surface side of the semiconductor layer 40, and is formed in contact with the semiconductor substrate 32, and is composed of silicon of the first conductivity type containing impurities of a second concentration lower than the first concentration. The low-concentration impurity layer 33 can be formed on the semiconductor substrate 32, for example, by epitaxial growth.

[0108] Generally, there are two types of conductivities, P-type and N-type, for semiconductors. The first conductivity type can be either P-type or N-type. Here, the first conductivity type is assumed to be N-type, and the second conductivity type described later is assumed to be P-type. However, the first conductivity type can also be assumed to be P-type, and the second conductivity type can be assumed to be N-type.

[0109] In the first region Al of the low-concentration impurity layer 33, a first body region 18 containing impurities of a second conductivity type different from the first conductivity type is formed in a range from the upper surface of the semiconductor layer 40 to a first prescribed depth.

[0110] In the first body region 18, a first source region 14 containing the first conductivity type of impurities is formed in a range from the upper surface of the semiconductor layer 40 to a second prescribed depth that does not pass through the first body region 18.

[0111] Further, in the first region Al of the low-concentration impurity layer 33, a plurality of gate trenches 17 extending in the second direction are formed in a range from the upper surface of the semiconductor layer 40 to a third prescribed depth that passes through the first source region 14 and the first body region 18 up to a portion of the low-concentration impurity layer 33.

[0112] Further, in the first region Al of the low-concentration impurity layer 33, a plurality of gate trenches 17 extending in the second direction are formed in a range from the upper surface of the semiconductor layer 40 to a third prescribed depth that passes through the first source region 14 and the first body region 18 up to a portion of the low-concentration impurity layer 33.

[0113] The first gate conductor 15 is electrically connected to the first gate electrode 19.

[0114] As one example, the first gate conductor 15 can be polycrystalline silicon containing impurities.

[0115] In the second region A2 of the low-concentration impurity layer 33, a second body region 28 containing an impurity of the second conductivity type is formed in a range from the upper surface of the semiconductor layer 40 to a second prescribed depth that does not penetrate the second body region 28.

[0116] In the second body region 28, a second source region 24 containing an impurity of the first conductivity type is formed in a range from the upper surface of the semiconductor layer 40 to a third prescribed depth that penetrates the second source region 24 and the second body region 28 up to a portion of the low-concentration impurity layer 33.

[0117] Further, in the second region A2 of the low-concentration impurity layer 33, a plurality of gate trenches 27 extending in the second direction are formed in a range from the upper surface of the semiconductor layer 40 to the third prescribed depth that penetrates the second source region 24 and the second body region 28 up to a portion of the low-concentration impurity layer 33.

[0118] Further, in the second region A2 of the low-concentration impurity layer 33, a plurality of gate trenches 27 extending in the second direction are formed in a range from the upper surface of the semiconductor layer 40 to the third prescribed depth that penetrates the second source region 24 and the second body region 28 up to a portion of the low-concentration impurity layer 33.

[0119] The second gate conductor 25 is electrically connected to the second gate electrode 29.

[0120] As a non-limiting example, the second gate conductor 25 can be polysilicon containing an impurity.

[0121] By the above-described structure of the first vertical MOS transistor 10 and the second vertical MOS transistor 20, the semiconductor substrate 32 functions as a common drain region in which a first drain region of the first vertical MOS transistor 10 and a second drain region of the second vertical MOS transistor 20 are common.

[0122] The metal layer 30 is formed in contact with the back surface of the semiconductor layer 40, and is composed of silver or copper as a non-limiting example. In addition, the metal layer 30 can contain an element other than metal that is mixed as an impurity in the manufacturing process of the semiconductor device 1 in a trace amount.

[0123] The interlayer insulating layer 34 is disposed on the upper surface of the semiconductor layer 40, and is formed in contact with the low-concentration impurity layer 33.

[0124] The passivation layer 35 is a protective film that covers the upper surface of the first vertical MOS transistor 10 and the upper surface of the second vertical MOS transistor 20, and has 2n+1 opening portions that expose the 2n+1 first source pads 111 to the outside of the semiconductor device 1, respectively, an opening portion that exposes the first gate pad 119 to the outside of the semiconductor device 1, 2n+1 opening portions that expose the 2n+1 second source pads 121 to the outside of the semiconductor device 1, respectively, and an opening portion that exposes the second gate pad 129 to the outside of the semiconductor device 1.

[0125] Here, the fact that the passivation layer 35 covers the upper surface of the first longitudinal MOS transistor 10 and the upper surface of the second longitudinal MOS transistor 20 means that the passivation layer 35 is formed on substantially the entire surface of the semiconductor device 1 except for the opening portion when the semiconductor device 1 is viewed from above. Here, the substantially entire surface of the semiconductor device 1 means the entire surface of the semiconductor device 1 in a region of the wafer secured as a margin when the semiconductor device 1 is cut from the wafer, except for a peripheral region of the semiconductor device 1 slightly remaining on four sides of the semiconductor device 1 after cutting. Therefore, in this peripheral region, the interlayer insulating layer 34 is exposed on the upper surface of the semiconductor device 1, except for this.

[0126] In addition, the opening portion of the passivation layer 35 in the present disclosure means a shape in which the entire length of the outer periphery of the opening portion is closed by the passivation layer 35 when the semiconductor device 1 is viewed from above. Therefore, a shape in which a part of the outer periphery overlaps with the peripheral region of the semiconductor device 1 in which the interlayer insulating layer 34 is exposed on the upper surface of the semiconductor device 1, except for this, when the semiconductor device 1 is viewed from above, does not correspond to the opening portion of the passivation layer 35 in the present disclosure.

[0127] In addition, in the semiconductor device 1, a position included in the first region Al when the semiconductor device 1 is viewed from above is provided with the first source electrode 11 functioning as a source electrode of the first longitudinal MOS transistor 10 and the first gate electrode 19 (not illustrated in the Figure 2 ) functioning as a gate electrode of the first longitudinal MOS transistor 10, and a position included in the second region A2 when the semiconductor device 1 is viewed from above is provided with the second source electrode 21 functioning as a source electrode of the second longitudinal MOS transistor 20 and the second gate electrode 29 (not illustrated in the Figure 5A ) functioning as a gate electrode of the second longitudinal MOS transistor 20. Figure 2 Figure 5A

[0128] The first source electrode 11 is composed of a portion 12 and a portion 13, and the portion 12 is connected to the first source region 14 and the first body region 18 via the portion 13.

[0129] The portion 12 is a layer that is joined with solder at the time of reflow in face-down mounting, and can be composed of a metal material including any one or more of nickel, titanium, tungsten, and palladium, for example. A plating layer of gold or the like can be applied to the surface of the portion 12.

[0130] The portion 13 of the first source electrode 11 is a layer that connects the portion 12 to the semiconductor layer 40, and can be composed of a metal material including any one or more of aluminum, copper, gold, and silver, for example.

[0131] ​​The surface of the portion 12 is exposed on the surface of the semiconductor device 1 via the opening portion of the passivation layer 35. Also, the surface of the portion 12 exposed on the surface of the semiconductor device 1 via the opening portion of the passivation layer 35 becomes the first source pad 111.

[0132] That is, the first source pad 111 is a portion of the first source electrode 11 exposed on the surface of the semiconductor device 1 via the opening portion of the passivation layer 35.

[0133] As a non-limiting example, the first gate electrode 19 can be composed of a metal material including any one or more of aluminum, copper, gold, and silver.

[0134] The surface of the first gate electrode 19 is exposed on the surface of the semiconductor device 1 via the opening portion of the passivation layer 35. Also, the surface of the first gate electrode 19 exposed on the surface of the semiconductor device 1 via the opening portion of the passivation layer 35 becomes the first gate pad 119.

[0135] That is, the first gate pad 119 is a portion of the first gate electrode 19 exposed on the surface of the semiconductor device 1 via the opening portion of the passivation layer 35.

[0136] The second source electrode 21 is composed of a portion 22 and a portion 23, and the portion 22 is connected to the second source region 24 and the second body region 28 via the portion 23.

[0137] The portion 22 is a layer that is joined with solder at the time of reflow in face-down mounting, and as a non-limiting example, can be composed of a metal material including any one or more of nickel, titanium, tungsten, and palladium. A plating layer of gold or the like can be applied to the surface of the portion 22.

[0138] The portion 23 of the second source electrode 21 is a layer that connects the portion 22 to the semiconductor layer 40, and as a non-limiting example, can be composed of a metal material including any one or more of aluminum, copper, gold, and silver.

[0139] The surface of the portion 22 is exposed on the surface of the semiconductor device 1 via the opening portion of the passivation layer 35. Also, the surface of the portion 22 exposed on the surface of the semiconductor device 1 via the opening portion of the passivation layer 35 becomes the second source pad 121.

[0140] That is, the second source pad 121 is a portion of the surface of the second source electrode 21 exposed on the surface of the semiconductor device 1 via the opening portion of the passivation layer 35.

[0141] As a non-limiting example, the second gate electrode 29 can be composed of a metal material including any one or more of aluminum, copper, gold, and silver.

[0142] The surface of the second gate electrode 29 is exposed on the surface of the semiconductor device 1 via the opening portion of the passivation layer 35. Also, the surface of the second gate electrode 29 exposed on the surface of the semiconductor device 1 via the opening portion of the passivation layer 35 becomes the second gate pad 129.

[0143] That is, the second gate pad 129 is the portion of the second gate electrode 29 exposed on the surface of the semiconductor device 1 via the opening portion of the passivation layer 35.

[0144] <Operation of Semiconductor Device>

[0145] Next, the operation of the semiconductor device 1 having the above-described structure will be described.

[0146] In the semiconductor device 1, current flows from one of the first source pad 111 and the second source pad 121 as an inlet, via the common drain region and the metal layer 30, and the other of the first source pad 111 and the second source pad 121 as an outlet.

[0147] Here, the path in which current flows with the first source pad 111 as the inlet and the second source pad 121 as the outlet will be referred to as a first current path, and the path in which current flows with the second source pad 121 as the inlet and the first source pad 111 as the outlet will be referred to as a second current path.

[0148] Next, the first current path and the second current path will be described using Figure 5B , Figure 5A

[0149] Figure 5B is a cross-sectional view schematically showing the case where current flows in the first current path.

[0150] The first current path is formed as follows.

[0151] First, in the semiconductor device 1, a higher voltage than the second source electrode 21 is applied to the first source electrode 11.

[0152] Next, a voltage higher than the threshold value of the second vertical MOS transistor 20 is applied to the second gate electrode 29 with the voltage of the second source electrode 21 as a reference.

[0153] Thus, a conduction channel is formed in the vicinity of the second gate insulating film 26 in the second body region 28.

[0154] ​Thus, a first current path through which current flows in the order of the first source electrode 11 - the first body region 18 - the low-concentration impurity layer 33 - the semiconductor substrate 32 - the metal layer 30 - the semiconductor substrate 32 - the low-concentration impurity layer 33 - the conduction channel formed in the second body region 28 - the second source region 24 - the second source electrode 21 is formed.

[0155] At this time, although the amount is relatively small, current also flows in a path that flows from the first region Al to the second region A2 in the semiconductor substrate 32 without passing through the metal layer 30, and in a path that flows from the first region Al to the second region A2 in the low-concentration impurity layer 33 without passing through the semiconductor substrate 32 and the metal layer 30.

[0156] Therefore, here, it is assumed that these paths are also included in the first current path and the description is made.

[0157] Here, the description is made assuming that a path in which current flows forward through a PN junction (body diode) at the contact surface between the first body region 18 and the low-concentration impurity layer 33 in the first vertical MOS transistor 10 constitutes the first current path.

[0158] In contrast to this, in a case where a conduction channel is formed in the vicinity of the first gate insulating film 16 in the first body region 18 by applying a voltage above the threshold voltage of the first vertical MOS transistor 10 to the first gate electrode 19, a path in which current flows through the conduction channel also constitutes the first current path.

[0159] In a case where current flows through the conduction channel, in the first current path, current flows in the order of the first source electrode 11 - the first source region 14 - the conduction channel formed in the first body region 18 - the low-concentration impurity layer 33 - the semiconductor substrate 32 - the metal layer 30 - the semiconductor substrate 32 - the low-concentration impurity layer 33 - the conduction channel formed in the second body region 28 - the second source region 24 - the second source electrode 21.

[0160] Figure 6 is a cross-sectional view schematically showing a case where current flows in a second current path.

[0161] The second current path is formed as follows.

[0162] First, in the semiconductor device 1, a higher voltage than the first source electrode 11 is applied to the second source electrode 21.

[0163] Next, a voltage above the threshold of the first vertical MOS transistor 10 is applied to the first gate electrode 19 with the voltage of the first source electrode 11 as a reference.

[0164] Thus, a conduction channel is formed in the vicinity of the first gate insulating film 16 in the first body region 18.

[0165] Thus, a second current path in which current flows in the order of the second source electrode 21 - the second body region 28 - the low-concentration impurity layer 33 - the semiconductor substrate 32 - the metal layer 30 - the semiconductor substrate 32 - the low-concentration impurity layer 33 - the conduction channel formed in the first body region 18 - the first source region 14 - the first source electrode 11 is formed.

[0166] At this time, although the amount is small, current also flows in a path in which it flows from the second region A2 to the first region Al in the semiconductor substrate 32 without passing through the metal layer 30, and in a path in which it flows from the second region A2 to the first region Al in the low-concentration impurity layer 33 without passing through the semiconductor substrate 32 and the metal layer 30.

[0167] Therefore, here, it is assumed that these paths are also included in the second current path and a description will be given.

[0168] Here, it is assumed that a path in which current flows forward through a PN junction (body diode) at the contact surface between the second body region 28 and the low-concentration impurity layer 33 in the second vertical MOS transistor 20 constitutes the second current path and a description will be given.

[0169] In contrast, in a case in which a conduction channel is formed in the vicinity of the second gate insulating film 26 in the second body region 28 by applying a voltage above the threshold voltage of the second vertical MOS transistor 20 to the second gate electrode 29, a path in which current flows through the conduction channel also constitutes the second current path.

[0170] In a case in which current flows through the conduction channel, in the second current path, current flows in the order of the second source electrode 21 - the second source region 24 - the conduction channel formed in the second body region 28 - the low-concentration impurity layer 33 - the semiconductor substrate 32 - the metal layer 30 - the semiconductor substrate 32 - the low-concentration impurity layer 33 - the conduction channel formed in the first body region 18 - the first source region 14 - the first source electrode 11.

[0171] <Example of mounting of semiconductor device>

[0172] As one example, the semiconductor device 1 of the above-described structure is mounted on a mounting substrate in a face-down manner, and is used as a switching element that switches the conduction state and the non-conduction state of a current path in the mounting substrate.

[0173] Figure 6 is a circuit diagram of a circuit, i.e., a charge / discharge circuit 5, in which the semiconductor device 1 is mounted on a mounting substrate in a face-down manner and is used as a switching element.

[0174] As shown in Figure 7 , the charge-discharge circuit 5 is provided with the semiconductor device 1, the control IC 2, the storage battery 3, and the load 4.

[0175] The charge-discharge circuit 5 is a circuit that realizes discharging from the storage battery 3 to the load 4 and charging from the load 4 to the storage battery 3 by using the semiconductor device 1 as a switching element.

[0176] The control IC 2 is connected to the semiconductor device 1, and controls the discharging operation from the storage battery 3 to the load 4 and the charging operation from the load 4 to the storage battery 3 by controlling the voltage of the first gate electrode 19 and the voltage of the second gate electrode 29.

[0177] The semiconductor device 1 is switched to one of (1) a first state in which the first current path is in an on state, (2) a second state in which the second current path is in an on state, and (3) a third state in which the first current path and the second current path are in an off state, by the control IC 2 controlling the voltage of the first gate electrode 19 and the voltage of the second gate electrode 29. Further, it is required that the voltage of the first source electrode 11 be higher than the voltage of the second source electrode 21 in the first state, and that the voltage of the second source electrode 21 be higher than the voltage of the first source electrode 11 in the second state.

[0178] That is, in the charge-discharge circuit 5, the semiconductor device 1 functions as a switching element that is switched (1) to an on state of the charge-discharge circuit 5 in which a current path through which current flows from the storage battery 3 to the load 4 or a current path through which current flows from the load 4 to the storage battery 3 becomes in an on state according to a difference in level between the voltage of the first source electrode 11 and the voltage of the second source electrode 21, or (2) to an off state of the charge-discharge circuit 5 in which both the current path through which current flows from the storage battery 3 to the load 4 and the current path through which current flows from the load 4 to the storage battery 3 become in an off state, by the control IC 2 controlling the voltage of the first gate electrode 19 and the voltage of the second gate electrode 29.

[0179] Figure 8 is an enlarged plan view that enlarges a portion in which the semiconductor device 1 is mounted in the mounting substrate 6 in which the semiconductor device 1 is mounted face down in the charge-discharge circuit 5, Figure 8 is a diagram that shows a case in which the orientation of the semiconductor device 1 is reversed in such a manner that the surface of the semiconductor device 1 faces the surface of the mounting substrate 6 when the semiconductor device 1 is mounted face down in the mounting substrate 6, that is, Figure 1 is a diagram that shows a case in which the semiconductor device 1 is rotated 180 degrees with an axis orthogonal to the Z-axis as a rotation axis in such a manner that the Z-axis direction is reversed as shown in Figure 8 Figure 7 is a diagram that shows a case in which the semiconductor device 1 is rotated 180 degrees with the X-axis as a rotation axis in the case shown in​

[0180] Further, in Figure 7 , the outline of the semiconductor device 1 that is not actually mounted and the boundary line 90 in the semiconductor device 1 are illustrated as if the semiconductor device 1 is mounted on the mounting substrate 6 by a broken line.

[0181] Further, in Figure 8 and Figure 7 , FET1 refers to the first vertical MOS transistor 10, and FET2 refers to the second vertical MOS transistor 20.

[0182] As Figure 7 illustrated, the mounting substrate 6 includes a wiring pattern 51, a wiring pattern 52a, a wiring pattern 52b, a wiring pattern 53, 2n+1 first mounting source pads 511 (corresponding to the first mounting source pads 511a to the first mounting source pads 511g in Figure 7 ), a first mounting gate pad 519, 2n+1 second mounting source pads 521 (corresponding to the second mounting source pads 521a to the second mounting source pads 521g in Figure 7 ), a second mounting gate pad 529, and a gap 54.

[0183] The wiring pattern 51 is a wiring pattern formed on the upper surface of the mounting substrate 6 and is electrically connected to the battery 3.

[0184] The wiring pattern 53 is a wiring pattern formed on the upper surface of the mounting substrate 6 and is electrically connected to the load 4.

[0185] The wiring pattern 52a is a wiring pattern formed on the upper surface of the mounting substrate 6 and is electrically connected to the control IC 2.

[0186] The wiring pattern 52b is a wiring pattern formed on the upper surface of the mounting substrate 6 and is electrically connected to the control IC 2.

[0187] The gap 54 is a region that electrically and physically separates the wiring pattern 51 and the wiring pattern 53.

[0188] The first mounting source pads 511a to the first mounting source pads 511g are pads formed by electrically and physically connecting the upper surface of the wiring pattern 51 to the wiring pattern 51 and are pads for being joined to the first source pads 111a to the first source pads 111g, respectively, via a joining material such as solder when the semiconductor device 1 is mounted on the mounting substrate 6 with the semiconductor device 1 facing downward.

[0189] The first mounting gate pad 519 is a pad formed by electrical and physical connection between the upper surface of the wiring pattern 52a and the wiring pattern 52a. It is a pad used to bond with the first gate pad 119 by bonding materials such as solder when the semiconductor device 1 is mounted face down on the mounting substrate 6.

[0190] The second mounting source pads 521a to 521g are pads formed by electrical and physical connection between the wiring pattern 53 and the upper surface of the wiring pattern 53. They are pads used to bond to the second source pads 121a to 121g respectively by solder or other bonding materials when the semiconductor device 1 is mounted face down on the mounting substrate 6.

[0191] The second mounting gate pad 529 is a pad formed by electrical and physical connection between the upper surface of the wiring pattern 52b and the wiring pattern 52b. It is a pad used to bond with the second gate pad 129 by bonding materials such as solder when the semiconductor device 1 is mounted face down on the mounting substrate 6.

[0192] like Figure 7 As shown, when viewed from above, the semiconductor device 1 is mounted face down at a position where wiring patterns 51 and 53, which are opposite each other and separated by a gap 54, are spanned.

[0193] More specifically, the semiconductor device 1 is mounted face down on the mounting substrate 6 such that: the first source pads 111a to 111g are respectively bonded to the first mounting source pads 511a to 511g via solder or other bonding materials; the first gate pad 119 is bonded to the first mounting gate pad 519 via solder or other bonding materials; the second source pads 121a to 121g are respectively bonded to the second mounting source pads 521a to 521g via solder or other bonding materials; and the second gate pad 129 is bonded to the second mounting gate pad 529 via solder or other bonding materials.

[0194] As described above, when viewed from above, the center of the first gate pad 119 is located on the centerline 80, and no other pads are sandwiched between the first gate pad 119 and the second side 72. Therefore, when viewed from above, the position of the center of the semiconductor device 1 in the first direction of the second side 72 can be such that the first gate pad 119 is brought close to the position closest to the second side 72 according to design rules.

[0195] In addition, as described above, when the semiconductor device 1 is viewed in plan, the center of the second gate pad 129 is located on the center line 80, and no other pad is interposed between the second gate pad 129 and the first side 71. Therefore, when the semiconductor device 1 is viewed in plan, the position of the center of the semiconductor device 1 in the first direction of the first side 71 can be designed so that the second gate pad 129 is located closest to the first side 71.

[0196] Therefore, as ​ indicated, when the mounting substrate 6 is viewed in plan, the first mounting gate pad 519 to which the first gate pad 119 is bonded, the wiring pattern 52a connected to the first mounting gate pad 519, the second mounting gate pad 529 to which the second gate pad 129 is bonded, and the wiring pattern 52b connected to the second mounting gate pad 529 can be arranged at appropriate positions that do not disturb the flow of current in the discharge-time current path through which current flows from the wiring pattern 51 to the wiring pattern 53 when the secondary battery 3 discharges to the load 4, and the charge-time current path through which current flows from the wiring pattern 53 to the wiring pattern 51 when the load 4 charges the secondary battery 3.

[0197] <Investigation>

[0198] According to the semiconductor device 1 having the above-described structure, when the semiconductor device 1 is viewed in plan, the long side direction of the semiconductor device 1 and the long side direction of the 2n+1 first source pads 111 and the 2n+1 second source pads 121 are orthogonal to each other.

[0199] Therefore, when the semiconductor device 1 is viewed in plan, the area occupancy ratio of the 2n+1 first source pads 111 and the area occupancy ratio of the 2n+1 second source pads 121 can be increased compared to a structure in which the long side direction of the semiconductor device 1 and the long side direction of the 2n+1 first source pads 111 and the 2n+1 second source pads 121 are coincident with each other.

[0200] Therefore, according to the semiconductor device 1 having the above-described structure, the on-resistance of the current path through which current flows between the 2n+1 first source pads 111 and the 2n+1 second source pads 121 can be reduced compared to a structure in which, when the semiconductor device 1 is viewed in plan, the long side direction of the semiconductor device 1 and the long side direction of the 2n+1 first source pads 111 and the 2n+1 second source pads 121 are coincident with each other.

[0201] Further, according to the semiconductor device 1 of the above structure, the largest first source pad 111 among the 2n+l first source pads 111, that is, the first closest source pad 111a, and the largest second source pad 121 among the 2n+l second source pads 121, that is, the second closest source pad 121a, are disposed in the closest position to the fourth line segment 94 having the highest current density among the current paths of the current flowing between the first longitudinal MOS transistor 10 and the second longitudinal MOS transistor 20 when the semiconductor device 1 is viewed from above.

[0202] Therefore, according to the semiconductor device 1 of the above structure, the on-resistance of the current paths of the current flowing between the 2n+l first source pads 111 and the 2n+l second source pads 121 can be reduced.

[0203] Further, according to the semiconductor device 1 of the above structure, the metal layer 30 having a lower resistivity than the semiconductor layer 40 is generally provided, and the metal layer 30 becomes a part of the current paths of the current flowing between the first longitudinal MOS transistor 10 and the second longitudinal MOS transistor 20.

[0204] Therefore, according to the semiconductor device 1 of the above structure, the on-resistance of the current paths of the current flowing between the 2n+l first source pads 111 and the 2n+l second source pads 121 can be reduced.

[0205] Further, according to the semiconductor device 1 of the above structure, the first gate pad 119 can be disposed in the closest position to the second side 72 at the position of the center of the semiconductor device 1 in the first direction of the second side 72 according to the design rule, and further, the second gate pad 129 can be disposed in the closest position to the first side 71 at the position of the center of the semiconductor device 1 in the first direction of the first side 71 according to the design rule when the semiconductor device 1 is viewed from above.

[0206] Thus, the first gate pad 119 and the second gate pad 129 can be prevented from interfering with the current paths of the current flowing between the 2n+l first source pads 111 and the 2n+l second source pads 121.

[0207] Therefore, according to the semiconductor device 1 of the above structure, the on-resistance of the current paths of the current flowing between the 2n+l first source pads 111 and the 2n+l second source pads 121 can be reduced.

[0208] Further, according to the semiconductor device 1 of the above structure, two first non-closest source pads 111bg are disposed on each first non-closest equidistant line 81bd, and two second non-closest source pads 121bg are disposed on each second non-closest equidistant line 82bd when the semiconductor device 1 is viewed from above.

[0209] Thus, according to the semiconductor device 1 of the above structure, as compared with a structure in which one first non-closest source pad 111bg is arranged on each first non-closest equal-interval line 81bd and one second non-closest source pad 121bg is arranged on each second non-closest equal-interval line 82bd, it is possible to suppress occurrence of mounting failure caused by warping of the semiconductor device. This is because the shorter the length of each of the first non-closest source pads 111bg in the longitudinal direction, the lower the frequency of occurrence of mounting failure, and the shorter the length of each of the second non-closest source pads 121bg in the longitudinal direction, the lower the frequency of occurrence of mounting failure.

[0210] Thus, according to the semiconductor device 1 of the above structure, a semiconductor device 1 having a feature of being suitable for reducing the on-resistance of a current path in a mounting substrate 6 for mounting, and being capable of suppressing occurrence of mounting failure when mounted on the mounting substrate 6 is provided.

[0211] (SUPPLEMENT)

[0212] The semiconductor device of one aspect of the present disclosure has been described above on the basis of the embodiments, but the present disclosure is not limited to the embodiments. As long as the spirit of the present disclosure is not deviated from, aspects obtained by various modifications conceivable to those skilled in the art to the embodiments can also be included in the range of one or more aspects of the present disclosure.

[0213] INDUSTRIAL UTILITY

[0214] The present disclosure can be widely used for semiconductor devices and the like mounted on a mounting substrate.

[0215] EXPLANATION OF REFERENCE NUMERALS

[0216] 1 semiconductor device

[0217] 2 control IC

[0218] 3 storage battery

[0219] 4 load

[0220] 5 charge-discharge circuit

[0221] 6 mounting substrate

[0222] 10 first longitudinal MOS transistor

[0223] 11 first source electrode

[0224] 12, 13, 22, 23 portions

[0225] 14 first source region

[0226] 15 first gate conductor

[0227] 16 first gate insulating film

[0228] 17, 27 gate trench

[0229] 18 first body region

[0230] 19 first gate electrode

[0231] 20 second longitudinal MOS transistor

[0232] 21 second source electrode

[0233] 24 second source region

[0234] 25 second gate conductor

[0235] 26 second gate insulating film

[0236] 28 second body region

[0237] 29 second gate electrode

[0238] 30 metal layer

[0239] 32 semiconductor substrate

[0240] 33 low-concentration impurity layer

[0241] 34 interlayer insulating layer

[0242] 35 passivation layer

[0243] 40 semiconductor layer

[0244] 51, 52a, 52b, 53 wiring pattern

[0245] 54 gap

[0246] 61 one end portion

[0247] 62 other end portion

[0248] 71 first side

[0249] 72 second side

[0250] 73 third side

[0251] 74 fourth side

[0252] 80 center line

[0253] 81a first equidistant line, first closest equidistant line

[0254] 81b, 81c, 81d first equidistant line, first non-closest equidistant line

[0255] 81bd first non-closest equidistant line

[0256] 82a second equally spaced line, second closest equally spaced line

[0257] 82b, 82c, 82d second equally spaced line, second non-closest equally spaced line

[0258] 82bd second non-closest equally spaced line

[0259] 90 boundary line

[0260] 91 first line segment

[0261] 92 second line segment

[0262] 93 third line segment

[0263] 94 fourth line segment

[0264] 95 fifth line segment

[0265] 111 first source pad

[0266] 111a first source pad, first closest source pad

[0267] 111b, 111c, 111d, 111e, 111f, 111g first source pad, first non-closest source pad

[0268] 111bg first non-closest source pad

[0269] 111a1, 111b1, 111c1, 111d1, 111e1, 111f1, 111g1, 121a1, 121b1, 121c1, 121d1, 121e1, 121f1, f21g1 center

[0270] 119 first gate pad

[0271] 121 second source pad

[0272] 121a second source pad, second closest source pad

[0273] 121b, 121c, 121d, 121e, 121f, 121g second source pad, second non-closest source pad

[0274] 121bg second non-closest source pad

[0275] 129 second gate pad

[0276] 511a, 511b, 511c, 511d, 511e, 511f, 511g first mounting source pad

[0277] 519 first mounting gate pad

[0278] 521a, 521b, 521c, 521d, 521e, 521f, 521g second mounting source pad

[0279] 529 second mounting gate pad

[0280] A1 first region

[0281] A2 second region

Claims

1. A semiconductor device which is a chip size package type semiconductor device capable of face-down mounting, characterized by comprising: a semiconductor layer; a metal layer formed in contact with a back surface of the semiconductor layer; a first longitudinal MOS transistor formed in a first region of the semiconductor layer; a second longitudinal MOS transistor formed in a second region of the semiconductor layer which is adjacent to the first region when the semiconductor device is viewed in plan; 2n+1 first source pads of the first longitudinal MOS transistor and a first gate pad of the first longitudinal MOS transistor formed at positions of the semiconductor device which include the first region in plan, n being an integer of 1 or more; and 2n+1 second source pads of the second longitudinal MOS transistor and a second gate pad of the second longitudinal MOS transistor formed at positions of the semiconductor device which include the second region in plan; the semiconductor layer having a semiconductor substrate on the back surface side, the semiconductor substrate being a common drain region of the first longitudinal MOS transistor and the second longitudinal MOS transistor, in the plan, the semiconductor layer being rectangular having a first side and a second side which extend in a first direction and are equal in length to each other, and a third side and a fourth side which extend in a second direction orthogonal to the first direction and are equal in length to each other, the third side and the fourth side being shorter in length than the first side and the second side, the first region and the second region being one and the other which bisect the semiconductor layer in area, the third side being included in the outer periphery of the first region, the fourth side being included in the outer periphery of the second region, a boundary line between the first region and the second region being crank-shaped, being connected in order of the full length of a third line segment which extends in a straight line in the second direction, the full length of a first line segment and the full length of a second line segment which extend in a straight line in the first direction, the full length of a fourth line segment and the full length of a fifth line segment which extend in a straight line in the second direction, from an end portion of one side of the boundary line toward an end portion of the other side of the boundary line, and monotonously varying in the first direction and the second direction from the end portion of the one side toward the end portion of the other side, the length of the first line segment being equal to the length of the second line segment, the length of the third line segment being equal to the length of the fifth line segment, the end portion of the one side being located on the first side, the end portion of the other side being located on the second side, the fourth line segment being located on an imaginary center line of the semiconductor layer which bisects the semiconductor layer in area in plan, and the center line extending in a straight line in the second direction, the first gate pad being circular, the center of the first gate pad being located on the center line, and no other pad being present between the first gate pad and the second side.

2. The semiconductor device according to claim 1, wherein the first line segment and the second line segment are located on the first side, and the third line segment and the fifth line segment are located on the second side.

3. The semiconductor device according to claim 1, wherein the first line segment and the second line segment are located on the third side, and the third line segment and the fifth line segment are located on the fourth side.

4. The semiconductor device according to claim 1, wherein the first line segment and the second line segment are located on the third side, and the fourth line segment is located on the fourth side.

5. The semiconductor device according to claim 1, wherein the first line segment and the second line segment are located on the third side, and the fourth line segment is located on the second side.

6. The semiconductor device according to claim 1, wherein the first line segment and the second line segment are located on the fourth side, and the third line segment and the fifth line segment are located on the third side.

7. The semiconductor device according to claim 1, wherein the first line segment and the second line segment are located on the fourth side, and the fourth line segment is located on the third side.

8. The semiconductor device according to claim 1, wherein the first line segment and the second line segment are located on the fourth side, and the fourth line segment is located on the second side.

9. The semiconductor device according to claim 1, wherein the first line segment and the second line segment are located on the second side, and the third line segment and the fifth line segment are located on the first side.

10. The semiconductor device according to claim 1, wherein the first line segment and the second line segment are located on the second side, and the fourth line segment is located on the first side.

11. The semiconductor device according to claim 1, wherein the first line segment and the second line segment are located on the second side, and the fourth line segment is located on the third side.

12. The semiconductor device according to claim 1, wherein the first line segment and the second line segment are located on the second side, and the fourth line segment is located on the fourth side.

13. The semiconductor device according to claim 1, wherein the first line segment and the second line segment are located on the first side, and the third line segment and the fifth line segment are located on the second side.

14. The semiconductor device according to claim 1, wherein the first line segment and the second line segment are located on the first side, and the fourth line segment is located on the second side.

15. The semiconductor device according to claim 1, wherein the first line segment and the second line segment are located on the first side, and the fourth line segment is located on the third side.

16. The semiconductor device according to claim 1, wherein the first line segment and the second line segment are located on the first side, and the fourth line segment is located on the fourth side.

17. The semiconductor device according to claim 1, wherein the first line segment and the second line segment are located on the third side, and the third line segment and the fifth line segment are located on the fourth side.

18. The semiconductor device according to claim 1, wherein the first line segment and the second line segment are located on the third side, and the fourth line segment is located on the second side.

19. The semiconductor device according to claim 1, wherein the first line segment and the second line segment are located on the third side, and the fourth line segment is located on the first side.

20. The semiconductor device according to claim 1, wherein the first line segment and the second line segment are located on the third side, and the fourth line segment is located on the fourth side. the second gate pad is a circle having the same diameter as the first gate pad, a center of the second gate pad is on the center line, and there is no other pad between the second gate pad and the first side, the 2n+1 first source pads and the 2n+1 second source pads are oblongs having the second direction as a long side direction, and widths in a short side direction of the 2n+1 first source pads and the 2n+1 second source pads are equal, the 2n+1 first source pads are composed of a first closest source pad closest to the fourth line segment and 2n first non-closest source pads not closest to the fourth line segment, the first closest source pad is arranged so that a line symmetry axis extending in a long side direction coincides with a first closest equally-spaced line closest to the fourth line segment among n+1 first equally-spaced lines that are imaginary first equally-spaced lines extending in the second direction in the first region and arranged equally-spaced in the first direction, the 2n first non-closest source pads are arranged so that line symmetry axes extending in a long side direction of two first non-closest source pads among the 2n first non-closest source pads coincide with corresponding first non-closest equally-spaced lines among n first non-closest equally-spaced lines other than the first closest equally-spaced line among the n+1 first equally-spaced lines, the 2n+1 second source pads are composed of a second closest source pad closest to the fourth line segment and 2n second non-closest source pads not closest to the fourth line segment, the second closest source pad is arranged so that a line symmetry axis extending in a long side direction coincides with a second closest equally-spaced line closest to the fourth line segment among n+1 second equally-spaced lines that are imaginary second equally-spaced lines extending in the second direction in the second region and arranged equally-spaced in the first direction, the 2n second non-closest source pads are arranged so that line symmetry axes extending in a long side direction of two second non-closest source pads among the 2n second non-closest source pads coincide with corresponding second non-closest equally-spaced lines among n second non-closest equally-spaced lines other than the second closest equally-spaced line among the n+1 second equally-spaced lines, the 2n+1 first source pads and the 2n+1 second source pads are line-symmetric with the center line as a line symmetry axis.

2. The semiconductor device according to claim 1, wherein in the plan view, a length in the long side direction of the first closest source pad is longer than lengths in the long side direction of the 2n first non-closest source pads, a length in the long side direction of the second closest source pad is longer than lengths in the long side direction of the 2n second non-closest source pads.

3. The semiconductor device according to claim 2, wherein In the plan view, a closest distance between the 2 first non-closest source pads coinciding with a corresponding one of the n first non-closest equally-spaced lines and a line symmetry axis extending in the longitudinal direction in the plan view, and a closest distance between the 2 second non-closest source pads coinciding with a corresponding one of the n second non-closest equally-spaced lines and the line symmetry axis extending in the longitudinal direction in the plan view, are shorter than the diameter of the first gate pad and the diameter of the second gate pad.

4. The semiconductor device according to claim 2, wherein In the plan view, a midpoint of an imaginary line segment joining closest points of outer peripheries of the 2 first non-closest source pads coinciding with a corresponding one of the n first non-closest equally-spaced lines and a line symmetry axis extending in the longitudinal direction in the plan view to each other, a midpoint of an imaginary line segment joining closest points of outer peripheries of the 2 second non-closest source pads coinciding with a corresponding one of the n second non-closest equally-spaced lines and the line symmetry axis extending in the longitudinal direction in the plan view to each other, a center of the first closest source pad, and a center of the second closest source pad are located on one straight line extending in the first direction.

5. The semiconductor device according to claim 4, wherein In the plan view, In the plan view, a closest distance between a first non-closest source pad closer to the first side among the 2 first non-closest source pads coinciding with a corresponding one of the n first non-closest equally-spaced lines and the line symmetry axis extending in the longitudinal direction in the plan view and the first side is shorter than a closest distance between the first closest source pad and the first side, In the plan view, a closest distance between a first non-closest source pad closer to the second side among the 2 first non-closest source pads coinciding with a corresponding one of the n first non-closest equally-spaced lines and the line symmetry axis extending in the longitudinal direction in the plan view and the second side is shorter than a closest distance between the first closest source pad and the second side, In the plan view, a closest distance between a second non-closest source pad closer to the first side among the 2 second non-closest source pads coinciding with a corresponding one of the n second non-closest equally-spaced lines and the line symmetry axis extending in the longitudinal direction in the plan view and the first side is shorter than a closest distance between the second closest source pad and the first side, In the plan view, a closest distance between a second non-closest source pad closer to the second side among the 2 second non-closest source pads coinciding with a corresponding one of the n second non-closest equally-spaced lines and the line symmetry axis extending in the longitudinal direction in the plan view and the second side is shorter than a closest distance between the second closest source pad and the second side.

6. The semiconductor device according to claim 4, wherein in the plan view, a distance between a center of a first non-closest source pad of the 2 first non-closest source pads coinciding with the linear symmetry axis extending in the long side direction and a corresponding first non-closest equally-spaced line of the n first non-closest equally-spaced lines and a first edge is longer than a closest distance between the first closest source pad and the first edge, a distance between a center of a first non-closest source pad of the 2 first non-closest source pads coinciding with the linear symmetry axis extending in the long side direction and a corresponding first non-closest equally-spaced line of the n first non-closest equally-spaced lines and a second edge is longer than a closest distance between the first closest source pad and the second edge, a distance between a center of a second non-closest source pad of the 2 second non-closest source pads coinciding with the linear symmetry axis extending in the long side direction and a corresponding second non-closest equally-spaced line of the n second non-closest equally-spaced lines and the first edge is longer than a closest distance between the second closest source pad and the first edge, and a distance between a center of a second non-closest source pad of the 2 second non-closest source pads coinciding with the linear symmetry axis extending in the long side direction and a corresponding second non-closest equally-spaced line of the n second non-closest equally-spaced lines and the second edge is longer than a closest distance between the second closest source pad and the second edge.

7. The semiconductor device according to claim 4, wherein in the plan view, a closest distance between the first closest source pad and the fourth line segment is shorter than a closest distance in the first direction between 2 first source pads of the 2n+1 first source pads adjacent to each other in the first direction, a closest distance between the second closest source pad and the fourth line segment is shorter than a closest distance in the first direction between 2 second source pads of the 2n+1 second source pads adjacent to each other in the first direction.

8. The semiconductor device according to claim 4, wherein in the plan view, if a first length of the semiconductor layer in the first direction is set as Lx, a second length of the semiconductor layer in the second direction is set as Ly, and a diameter of the first gate pad and the second gate pad is set as d, the following holds Ly < 14 x d Lx < Ly + 2 x d.

9. The semiconductor device according to claim 4, wherein n is 3, in the plan view, the width of the 2n+1 first source pads and the 2n+1 second source pads is smaller than the diameter of the first gate pad and the second gate pad.

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