Equipment anti-disassembly detection device and detection method
Through the combination of mechanical trigger module and chip control, the use of flying wire short connection to the GPIO pin and redundant detection module, the singularity and cost problems of anti-tamping detection in the existing technology are solved, and efficient and low-cost multi-dimensional anti-tamping detection is achieved, which is suitable for consumer electronics and industrial equipment.
Patent Information
- Application Number
- CN202510504799.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-22
- Publication Date
- 2025-08-26
AI Technical Summary
In the anti-tamping detection, the existing technology has problems such as single detection methods, insufficient intelligence, poor environmental adaptability and imbalance in cost and performance, and cannot effectively prevent the precision disassembly of high-value equipment and core data leakage.
The combination of mechanical trigger module and chip control is adopted, and a closed circuit is formed by shorting the GPIO pin by flying wire, combined with the redundant detection module to monitor the level state changes in real time, and send verification signals through the RS-485 differential bus to achieve multi-dimensional detection and dynamic encryption protection.
It realizes accurate identification and prevention of illegal disassembly, reduces hardware costs, and improves detection reliability and environmental adaptability, and is suitable for consumer electronics and industrial equipment.
Smart Images
Figure CN120539629A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of electronic equipment safety protection, and in particular to an equipment anti-disassembly detection device and a detection method. Background Art
[0002] In industrial manufacturing, medical equipment, and precision machining, plasma power supplies, as core power modules, carry critical data. Their physical security is directly linked to intellectual property protection and equipment operational compliance. Current mainstream anti-tampering solutions present significant security risks. A certain brand of industrial power supplies (such as the XX-3000) employs purely mechanical anti-tampering measures, though equipped with a multi-point snap-on housing, can be opened without damage by professionals using a micro-hydraulic ejector within 90 seconds, potentially exposing critical data such as voltage waveform characteristics and process recipes stored in memory chips. Furthermore, the conductive rubber strips of the YY series medical plasma equipment, which utilize microswitch detection, have a false triggering rate of 23% in humid environments. These frequent false alarms force maintenance personnel to disable the anti-tampering feature, creating an opportunity for the illegal installation of power amplifier modules. More seriously, after a semiconductor company's Zeta-9 plasma power supply was intentionally modified, attackers obtained proprietary parameters for the wafer etching process through reverse engineering, directly leaking core technology. These cases reveal that traditional anti-dismantling technology is unable to meet the triple protection needs of high-value equipment - it lacks the real-time perception capability of precise disassembly behavior, cannot implement dynamic encryption protection for key data, and lacks a device integrity verification mechanism. These are precisely the industry pain points that this patented technology strives to solve.
[0003] The existing technology has the following defects: the detection means are single, relying only on physical locks or single sensors, and cannot cope with precise disassembly behaviors. It is not intelligent enough, lacking multi-channel redundant verification and dynamic encryption protection mechanisms. The environmental adaptability is poor, and electronic sensors are easily affected by temperature, humidity, and electromagnetic interference. There is an imbalance between cost and performance, and high-performance solutions are expensive and difficult to apply on a large scale. In response to these problems, this patent proposes a mechanical plus chip-controlled anti-dismantling detection method, which realizes multi-dimensional detection by combining mechanical structure and chip-controlled intelligent detection technology: using mechanical structure to provide physical protection, while monitoring the device status in real time through the chip-controlled sensor network to improve detection accuracy and reliability. The combination of mechanical and electronic solutions reduces implementation costs while ensuring high performance, is suitable for large-scale applications, and meets the high requirements of modern electronic equipment for anti-dismantling technology. Summary of the Invention
[0004] In order to solve the technical problems existing in the background technology, the present invention proposes an equipment anti-disassembly detection device and a detection method.
[0005] The present invention proposes a device anti-disassembly detection method, comprising:
[0006] The mechanical trigger module includes at least one set of flying leads arranged inside the device housing and short-circuited between at least one pair of GPIO pins on the circuit board to form a closed circuit. When the device is illegally disassembled, the flying leads break due to mechanical damage, causing the closed circuit to be disconnected, causing the level state of the GPIO pin to jump from a first level to a second level.
[0007] A control module is connected to the GPIO pin and is configured to monitor the level state of the GPIO pin in real time, perform de-jitter processing and verification on the jump signal, and send the verified disassembly signal to the main control device through the RS-485 differential bus transceiver;
[0008] The redundancy detection module is composed of a plurality of short-circuited GPIO pins, and each pair of short-circuited GPIO pins is independently connected to the control module for confirming illegal disassembly events.
[0009] Preferably, in the redundant detection module, multiple pairs of GPIO pins are short-circuited in pairs, and each pair of short-circuited pins is independently connected to an input port of the control module; when the flying wire between any pair of short-circuited pins is broken, the level state of the corresponding input port jumps from the first level to the second level.
[0010] Preferably, the control module is configured as follows: when a level jump is detected at any input port, a timer is started and the number of level jumps of all input ports is counted within a preset time window; only when level jumps are detected at more than a preset number of input ports, it is determined to be an illegal disassembly event and a disassembly signal is sent.
[0011] Preferably, in the redundancy detection module, at least one GPIO pin is short-circuited with multiple other GPIO pins at the same time to form a star topology; when all flying wires short-circuited to the same GPIO pin are broken, the control module determines it as an illegal disassembly event.
[0012] Preferably, the control module is configured to generate a disassembly event identifier when multiple short-circuit pairs of the same input port detect level jumps, and send the identifier to the main control device via the RS-485 bus.
[0013] Preferably, the redundancy detection module includes at least three pairs of GPIO pins short-circuited; the control module is configured to: when a level jump is detected in more than half of the short-circuited pairs, it is determined to be an illegal disassembly event.
[0014] Preferably, the data frame sent by the RS-485 differential bus transceiver includes a device ID, a timestamp, and an event type field, and the control module and the main control device perform full-duplex communication via the RS-485 protocol.
[0015] The present invention provides a device anti-disassembly detection method, which is applied to any of the above-mentioned device anti-disassembly detection devices, and includes:
[0016] S1. Arrange a flying wire inside the device housing and short-circuit the flying wire between at least one pair of GPIO pins on the circuit board to form a closed circuit.
[0017] S2. When the device is illegally disassembled, the flying wire breaks, causing the closed circuit to be disconnected, triggering the GPIO pin level to jump from the first level to the second level;
[0018] S3. Monitor the level status of the GPIO pin in real time through the control module and de-jitter the jump signal;
[0019] S4. Verify the consistency of multi-channel level transitions through a redundancy detection module;
[0020] S5. If the verification is successful, a disassembly event identifier is generated and sent to the master control device via the RS-485 bus.
[0021] Preferably, the de-jittering process includes: sampling the level status multiple times within a preset time window, and determining it as a valid signal only when the same level jump is detected multiple times in succession.
[0022] Preferably, verifying the consistency of multi-channel level transitions specifically includes: checking whether the level transition duration exceeds a threshold or verifying whether the level transitions of multiple pairs of GPIO pins are consistent through detection.
[0023] The device and method proposed in this invention utilizes a broken flying lead to trigger a level change, combined with multi-channel redundant verification, to accurately identify unauthorized disassembly. Upon detection, the device shuts down or performs an encrypted data erase, preventing the leakage of core parameters. This eliminates the need for additional sensors and directly shorts the GPIO pins with flying leads, reducing hardware costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 This is a schematic diagram of the device architecture of a device anti-disassembly detection device proposed by the present invention;
[0025] Figure 2 This is a circuit structure diagram of Example 1 of a device anti-disassembly detection device proposed by the present invention;
[0026] Figure 3 This is a circuit diagram of a second embodiment of a device anti-disassembly detection device according to the present invention;
[0027] Figure 4 This is a schematic structural diagram of the anti-disassembly work flow of the main control device of the device anti-disassembly detection device proposed by the present invention;
[0028] Figure 5 This is a schematic diagram of the workflow structure of a device anti-disassembly detection method proposed by the present invention. DETAILED DESCRIPTION
[0029] Reference Figure 1-5 The present invention proposes a device for detecting anti-disassembly of equipment, comprising:
[0030] The mechanical trigger module includes at least one set of flying leads, which are arranged inside the device casing and short-circuited between at least one pair of GPIO pins on the circuit board to form a closed circuit. When the device is illegally disassembled, the flying leads break due to mechanical damage, causing the closed circuit to be disconnected, causing the level state of the GPIO pin to jump from a first level to a second level.
[0031] The control module is connected to the GPIO pin and is configured to monitor the level status of the GPIO pin in real time, de-jitter and verify the jump signal, and send the verified disassembly signal to the main control device through the RS-485 differential bus transceiver.
[0032] Specifically, through the combination of mechanical structure and chip level detection, Figure 1 This is a module diagram of the anti-tampering machine detection control circuit of the present invention, as shown in FIG. Figure 1 As shown, the device employs a "destructive trigger" design, employing a clever mechanical structure. By short-circuiting flying leads, unauthorized device disassembly inevitably causes the leads to break, thereby changing the power level. The control module (MCU) monitors GPIO level changes in real time. If the level at the monitoring point changes, the data sent to the host computer is modified. Upon power-up, the host computer suspends operation when it detects disassembly data.
[0033] In this embodiment, the solution does not require sensors, and the control module MCU uses the STM32C0 series with a main frequency of 48MHZ and low cost. The invention has high reliability, fast response through the IO port, low false alarm rate (<1%) and strong environmental adaptability. It is suitable for consumer electronics, industrial equipment and other fields, effectively preventing the equipment from being illegally disassembled or tampered with, while significantly reducing costs and maintenance difficulties.
[0034] The redundancy detection module is composed of multiple GPIO pins short-circuited, and each pair of short-circuited GPIO pins is independently connected to the control module to confirm illegal disassembly events.
[0035] Example 1:
[0036] In this embodiment, multiple pairs of GPIO pins are short-circuited in pairs, and each pair of short-circuited pins is independently connected to an input port of the control module; when the flying wire between any pair of short-circuited pins is broken, the level state of the corresponding input port jumps from the first level to the second level.
[0037] In this embodiment, when a level jump is detected at any input port, a timer is started and the number of level jumps of all input ports is counted within a preset time window; only when level jumps are detected at more than a preset number of input ports, it is determined to be an illegal disassembly event and a disassembly signal is sent.
[0038] In this embodiment, the redundancy detection module includes at least three pairs of GPIO pins short-circuited; the control module is configured to: when a level jump is detected in more than half of the short-circuited pairs, it is determined to be an illegal disassembly event.
[0039] Specifically, if Figure 2 As shown, PA1 and PA6, PA2 and PA5, PA3 and PA4 are connected through flying wires respectively. If the flying wires are broken, the IO port level will jump, and the data sent to the main control through 485 will change. When the host reads the disassembly data during power-on, the operation will be suspended.
[0040] Example 2:
[0041] In the redundancy detection module, at least one GPIO pin is short-circuited with multiple other GPIO pins at the same time, forming a star topology. When all the flying wires short-circuited to the same GPIO pin are broken, the control module determines it as an illegal disassembly event.
[0042] In this embodiment, the control module is configured to generate a disassembly event identifier when multiple short-circuit pairs of the same input port all detect level jumps, and send the identifier to the main control device via the RS-485 bus.
[0043] Specifically, the data frame sent by the RS-485 differential bus transceiver includes a device ID, a timestamp, and an event type field, and the control module and the master device perform full-duplex communication via the RS-485 protocol.
[0044] In this embodiment, if Figure 3 As shown in the figure, if multiple flying wires are connected to the PA1 end, if all the flying wires on the PA1 end are broken, the IO port level will jump, and the data sent to the main control through 485 will change. When the host reads the disassembly data during power-on, it will suspend operation, realizing an efficient and low-cost anti-disassembly detection method.
[0045] It should be noted that if Figure 4 As shown, when the master device is powered on, it first reads the EEPROM history to see if there is a disassembly event identifier transmitted by the anti-tampering device through the RS-485 bus. If not, it directly reads the anti-tampering device to see if there is a disassembly event identifier. If there is no event identifier, it runs normally. If it detects that the device has been disassembled, the master program will lock itself and cannot start.
[0046] Reference Figure 1-5The present invention proposes a device anti-disassembly detection method, which is applied to any of the above-mentioned device anti-disassembly detection devices, comprising:
[0047] S1. Arrange a flying wire inside the device housing and short-circuit the flying wire between at least one pair of GPIO pins on the circuit board to form a closed circuit.
[0048] S2. When the device is illegally disassembled, the flying wire breaks, causing the closed circuit to be disconnected, triggering the level of the GPIO pin to jump from the first level to the second level.
[0049] S3. Monitor the level status of the GPIO pin in real time through the control module, and de-jitter the jump signal.
[0050] In this embodiment, the de-jittering process includes: sampling the level status multiple times within a preset time window, and determining it as a valid signal only when the same level jump is detected multiple times in succession.
[0051] S4. Verify the consistency of multi-channel level transitions through a redundancy detection module.
[0052] In this embodiment, verifying the consistency of multi-channel level transitions specifically includes: checking whether the level transition duration exceeds a threshold or verifying whether the level transitions of multiple pairs of GPIO pins are consistent through detection.
[0053] S5. If the verification is successful, a disassembly event identifier is generated and sent to the master control device via the RS-485 bus.
[0054] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the technical field, within the technical scope disclosed by the present invention, who makes equivalent replacements or changes based on the technical solution and inventive concept of the present invention, should be covered by the scope of protection of the present invention.
Claims
1. A device for detecting anti-disassembly of equipment, characterized in that: include: The mechanical trigger module includes at least one set of flying leads arranged inside the device housing and short-circuited between at least one pair of GPIO pins on the circuit board to form a closed circuit. When the device is illegally disassembled, the flying leads break due to mechanical damage, causing the closed circuit to be disconnected, causing the level state of the GPIO pin to jump from a first level to a second level. A control module is connected to the GPIO pin and is configured to monitor the level state of the GPIO pin in real time, perform de-jitter processing and verification on the jump signal, and send the verified disassembly signal to the main control device through the RS-485 differential bus transceiver; The redundancy detection module is composed of a plurality of short-circuited GPIO pins, and each pair of short-circuited GPIO pins is independently connected to the control module for confirming illegal disassembly events.
2. The device for detecting anti-disassembly of equipment according to claim 1, characterized in that: In the redundancy detection module, multiple pairs of GPIO pins are short-circuited in pairs, and each pair of short-circuited pins is independently connected to an input port of the control module; when the flying wire between any pair of short-circuited pins is broken, the level state of the corresponding input port jumps from the first level to the second level.
3. The device for detecting anti-disassembly of equipment according to claim 2, characterized in that: The control module is configured to: when a level jump of any input port is detected, start a timer and count the number of level jumps of all input ports within a preset time window; Only when more than a preset number of input ports detect level jumps, it is determined to be an illegal disassembly event and a disassembly signal is sent.
4. The device for detecting anti-disassembly of equipment according to claim 1, characterized in that: In the redundancy detection module, at least one GPIO pin is short-circuited with multiple other GPIO pins at the same time to form a star topology; when all flying wires short-circuited to the same GPIO pin are broken, the control module determines it as an illegal disassembly event.
5. The device for detecting anti-disassembly of equipment according to claim 4, characterized in that: The control module is configured to generate a disassembly event identifier when multiple short-circuit pairs of the same input port detect level jumps, and send the identifier to the main control device via the RS-485 bus.
6. The device for detecting anti-disassembly of equipment according to claim 3, characterized in that: The redundancy detection module includes at least three pairs of GPIO pins short-circuited; the control module is configured to: when more than half of the short-circuited pairs detect a level jump, determine it as an illegal disassembly event.
7. The device for detecting anti-disassembly of equipment according to claim 1, characterized in that: The data frame sent by the RS-485 differential bus transceiver includes a device ID, a timestamp, and an event type field, and the control module and the main control device perform full-duplex communication via the RS-485 protocol.
8. A device anti-disassembly detection method, applied to the device anti-disassembly detection device according to any one of claims 1 to 7, characterized in that: include: S1. Arrange a flying wire inside the device housing and short-circuit the flying wire between at least one pair of GPIO pins on the circuit board to form a closed circuit. S2. When the device is illegally disassembled, the flying wire breaks, causing the closed circuit to be disconnected, triggering the GPIO pin level to jump from the first level to the second level; S3. Monitor the level status of the GPIO pin in real time through the control module and de-jitter the jump signal; S4. Verify the consistency of multi-channel level transitions through a redundancy detection module; S5. If the verification is successful, a disassembly event identifier is generated and sent to the master control device via the RS-485 bus.
9. The device anti-disassembly detection method according to claim 8, characterized in that: The de-jittering process includes: sampling the level state multiple times within a preset time window, and determining it as a valid signal only when the same level jump is detected multiple times in succession.
10. The device anti-disassembly detection method according to claim 8, characterized in that: Verifying the consistency of multi-channel level transitions specifically includes: checking whether the level transition duration exceeds a threshold or verifying whether the level transitions of multiple pairs of GPIO pins are consistent through detection.