A high power supply rejection ratio strong drive reference source integrated circuit

Abstract

The present invention proposes a high power supply rejection ratio and strong drive reference source integrated circuit. By setting circuit modules such as drive enhancement and power supply ripple resistance, the reference source integrated circuit has a high power supply rejection ratio and a strong load driving capability, thereby meeting the requirements of a weak electric signal acquisition system for a reference voltage source. The present invention comprises a drive enhancement circuit and a voltage-stabilizing output circuit. The drive enhancement circuit improves the load driving capability of the voltage-stabilizing output circuit by reducing the output impedance of the system, and introduces a negative feedback loop to enable the voltage-stabilizing output circuit to drive a load with small impedance and large capacitance without causing stability problems. The voltage-stabilizing output circuit generates a reference voltage with a high power supply rejection ratio and outputs it through a port.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a high power supply rejection ratio strong drive reference source integrated circuit. Background Art

[0002] Weak electrical signal acquisition systems typically include circuit modules with low impedance and high capacitance, requiring the reference source circuit module to possess strong load-driving capabilities. Traditional reference source integrated circuit modules typically output high common-mode noise, which is amplified by subsequent amplifier circuits, exacerbating the interference the reference source integrated circuit module causes to the signal acquisition system. Therefore, in weak electrical signal acquisition systems subject to strong power frequency interference, it is particularly important for the reference source integrated circuit module to possess a high power supply rejection ratio and strong load-driving capabilities. Summary of the Invention

[0003] The problem solved by the present invention is to propose a high power supply rejection ratio and strong drive reference source integrated circuit. By setting up circuit modules such as drive enhancement and power supply ripple resistance, the reference source integrated circuit has a high power supply rejection ratio and a strong load driving capability, thereby meeting the requirements of weak electrical signal acquisition systems for reference voltage sources.

[0004] To solve the above problems, the present invention provides a high power supply rejection ratio strong drive reference source integrated circuit comprising a drive enhancement circuit and a voltage stabilization output circuit.

[0005] The drive enhancement circuit is connected to the regulated output circuit. It improves the load-driving capability of the regulated output circuit by reducing the system's output impedance. By introducing a negative feedback loop, the regulated output circuit can drive low-impedance, high-capacitance loads without causing stability issues. The regulated output circuit generates a reference voltage with a high power supply rejection ratio and outputs it through a port.

[0006] The drive enhancement circuit 1 includes terminals VJND, VGCP, VLS1, VFSO, and VEFK.

[0007] The voltage regulated output circuit 2 includes ports VJOU, VGUT, VLS2, VFIN and VREF.

[0008] Port VJDN is connected to port VJOU for transmitting feedback voltage Vj4. Port VGCP is connected to port VGUT for transmitting feedback voltage Vg4. Port VLS1 is connected to port VLS2 for transmitting bias voltage Vb1. Port VFSO is connected to port VFIN for transmitting voltage Vs. Port VEFK is connected to port VREF for transmitting voltage Vref.

[0009] The driving enhancement circuit includes a subthreshold bias circuit and an output driving circuit.

[0010] The subthreshold bias circuit is connected to the output driver circuit. It outputs two bias voltages that are unaffected by power supply ripple and are fed to the output driver circuit and the regulated output circuit, respectively. The output driver circuit's circuit connection structure ensures a low output impedance, enabling stable driving of loads with large input capacitance.

[0011] The voltage stabilizing output circuit includes an anti-ripple circuit and a reference output circuit.

[0012] The anti-ripple circuit is connected to the reference output circuit. By introducing two negative feedback loops, the anti-ripple circuit significantly improves the power supply rejection ratio of the reference output circuit. The reference output circuit stably outputs the reference voltage and has strong load driving capability.

[0013] Compared with the prior art, the present invention offers the following advantages: It provides a high-PSRR, strong-drive reference integrated circuit, comprising a drive enhancement circuit and a voltage-regulated output circuit. The drive enhancement circuit improves the load-driving capability of the voltage-regulated output circuit by reducing the system's output impedance. Furthermore, by introducing a negative feedback loop, the voltage-regulated output circuit can drive low-impedance, high-capacitance loads without stability issues. The voltage-regulated output circuit generates a reference voltage with a high PSRR and outputs it through a port. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 Schematic diagram of the system structure of the present invention;

[0015] Figure 2 Schematic diagram of the principle structure of the driving enhancement circuit of the present invention;

[0016] Figure 3 It is a schematic diagram of the principle structure of the voltage-stabilizing output circuit of the present invention.

[0017] Description of reference numerals:

[0018] 1-Drive enhancement circuit; 2-Voltage regulated output circuit; 11-Subthreshold bias circuit; 12-Output drive circuit; 21-Anti-ripple circuit; 22-Reference output circuit. DETAILED DESCRIPTION

[0019] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0020] like Figure 1 As shown, a high power supply rejection ratio strong drive reference source integrated circuit includes a drive enhancement circuit 1 and a voltage stabilization output circuit 2.

[0021] Drive enhancement circuit 1 is connected to voltage-regulated output circuit 2. It improves the load-driving capability of voltage-regulated output circuit 2 by reducing the system's output impedance. By introducing a negative feedback loop, voltage-regulated output circuit 2 can drive low-impedance, high-capacitance loads without causing stability issues. Voltage-regulated output circuit 2 generates a reference voltage with a high power supply rejection ratio and outputs it through a port.

[0022] The drive enhancement circuit 1 includes terminals VJND, VGCP, VLS1, VFSO, and VEFK.

[0023] The voltage regulated output circuit 2 includes ports VJOU, VGUT, VLS2, VFIN and VREF.

[0024] The port VJDN is connected to the port VJOU and is used to transmit the feedback voltage Vj4.

[0025] The port VGCP is connected to the port VGUT and is used to transmit the feedback voltage Vg4.

[0026] The port VLS1 is connected to the port VLS2 and is used to transmit the bias voltage Vb1.

[0027] The port VFSO is connected to the port VFIN for transmitting the voltage Vs.

[0028] The port VEFK is connected to the port VREF and is used to transmit the voltage Vref.

[0029] like Figure 1 As shown, the driving enhancement circuit 1 includes a subthreshold bias circuit 11 and an output driving circuit 12 .

[0030] Subthreshold bias circuit 11 is connected to output driver circuit 12. Subthreshold bias circuit 11 outputs two bias voltages that are unaffected by power supply ripple, one to output driver circuit 12 and the other to voltage-regulated output circuit 2. The output driver circuit 12, based on its circuit connection structure, provides a low output impedance for stable driving of loads with large input capacitance.

[0031] like Figure 1 As shown, the voltage stabilization output circuit 2 includes an anti-ripple circuit 21 and a reference output circuit 22 .

[0032] The anti-ripple circuit 21 is connected to the reference output circuit 22. By introducing two negative feedback loops, the anti-ripple circuit 21 significantly improves the power supply rejection ratio of the reference output circuit 22. The reference output circuit 22 stably outputs the reference voltage and has a strong load driving capability.

[0033] like Figure 2 As shown, the subthreshold bias circuit 11 includes a self-bias circuit 111 and a bias voltage circuit 112 .

[0034] Self-bias circuit 111 is connected to bias voltage circuit 112. Self-bias circuit 111 generates a bias current that is unaffected by power supply voltage ripple and outputs it to bias voltage circuit 112, providing bias conditions for the normal operation of the main MOS transistors in bias voltage circuit 112. Bias voltage circuit 112 generates a bias voltage that is unaffected by power supply voltage ripple and inputs it to output driver circuit 12 and regulated output circuit 2.

[0035] The self-bias circuit 111 includes a MOS transistor M1 , a MOS transistor M2 , a MOS transistor M3 , a MOS transistor M4 , a MOS transistor M5 , a MOS transistor M6 , and a MOS transistor M7 .

[0036] The source of MOS transistor M1 is connected to the power supply VDD, the gate of MOS transistor M1 is connected to the gate of MOS transistor M5, and the drain of MOS transistor M1 is connected to the drain of MOS transistor M2. The drain of MOS transistor M2 is connected to the gate of MOS transistor M1, the gate of MOS transistor M2 is connected to the gate of MOS transistor M6, and the source of MOS transistor M2 is connected to the drain of MOS transistor M3. The drain of MOS transistor M3 is connected to the source of MOS transistor M2, the gate of MOS transistor M3 is connected to the gate of MOS transistor M7, and the source of MOS transistor M3 is grounded.

[0037] The source of MOS transistor M4 is connected to the source of MOS transistor M1, the gate of MOS transistor M4 is connected to the drain of MOS transistor M4, and the drain of MOS transistor M4 is connected to the source of MOS transistor M5. The source of MOS transistor M5 is connected to the gate of MOS transistor M4, the gate of MOS transistor M5 is connected to the drain of MOS transistor M1, and the drain of MOS transistor M5 is connected to the drain of MOS transistor M6. The drain of MOS transistor M6 is connected to the gate of MOS transistor M6, the gate of MOS transistor M6 is connected to the gate of MOS transistor M3, and the source of MOS transistor M6 is connected to the drain of MOS transistor M7. The drain of MOS transistor M7 is connected to the source of MOS transistor M6, the gate of MOS transistor M7 is connected to the gate of MOS transistor M2, and the source of MOS transistor M7 is grounded.

[0038] Power supply voltage ripple can cause changes in the bias circuit output voltage, which in turn affects the reference voltage output by the reference source. Due to its circuit connection structure, the subthreshold bias circuit 11 outputs a bias voltage that is not affected by power supply ripple, thereby improving the power supply rejection ratio of the entire circuit system.

[0039] MOS transistors M1 through M7 all operate in the subthreshold region. Due to the circuit connection structures of MOS transistors M1, M4, and M5, the operating voltage and current required by MOS transistors M1 through M7 are extremely low. The drain-source voltage of MOS transistor M4 is equal to the difference between the gate-source voltage of MOS transistor M1 and the gate-source voltage of MOS transistor M5. The expression for the bias current Ib1 generated in the drain-source branch of MOS transistor M5 is shown below.

[0040] ;

[0041] In the formula, Vgs1 is the gate-source voltage of the MOS tube M1, Vgs5 is the gate-source voltage of the MOS tube M5, Rm4 is the on-resistance of the MOS tube M4, ga is the subthreshold slope factor of the MOS tube, Kb is the Boltzmann constant, T is the temperature, W5 is the conductive channel width of the MOS tube M5, L5 is the conductive channel length of the MOS tube M5, W1 is the conductive channel width of the MOS tube M1, L1 is the conductive channel length of the MOS tube M1, and q is the unit charge.

[0042] It can be seen from the expression of the bias current Ib1 that the bias current Ib1 is not affected by the power supply voltage ripple.

[0043] The bias voltage circuit 112 includes a MOS transistor M8 , a MOS transistor M9 , a MOS transistor M10 , a MOS transistor M11 , a MOS transistor M12 , a MOS transistor M13 , a MOS transistor M14 , a MOS transistor M15 , a port VEFK and a port VLS1 .

[0044] The drain of MOS transistor M8 is connected to the power supply VDD, the gate of MOS transistor M8 is connected to the port VEFK, and the source of MOS transistor M8 is connected to the drain of MOS transistor M9. The drain of MOS transistor M9 is connected to the source of MOS transistor M8, the gate of MOS transistor M9 is connected to the drain of MOS transistor M9, and the source of MOS transistor M9 is connected to the drain of MOS transistor M10. The drain of MOS transistor M10 is connected to the port VLS1, the gate of MOS transistor M10 is connected to the drain of MOS transistor M6, and the source of MOS transistor M10 is connected to the drain of MOS transistor M11. The drain of MOS transistor M11 is connected to the source of MOS transistor M10, the gate of MOS transistor M11 is connected to the gate of MOS transistor M10, and the source of MOS transistor M11 is grounded.

[0045] The drain of MOS transistor M12 is connected to the drain of MOS transistor M8, the gate of MOS transistor M12 is connected to the gate of MOS transistor M8, and the source of MOS transistor M12 is connected to the drain of MOS transistor M13. The drain of MOS transistor M13 is connected to the source of MOS transistor M12, the gate of MOS transistor M13 is connected to the drain of MOS transistor M13, and the source of MOS transistor M13 is connected to the drain of MOS transistor M14. The drain of MOS transistor M14 is connected to the source of MOS transistor M13, the gate of MOS transistor M14 is connected to the gate of MOS transistor M10, and the source of MOS transistor M14 is connected to the drain of MOS transistor M15. The drain of MOS transistor M15 is connected to the source of MOS transistor M14, the gate of MOS transistor M15 is connected to the gate of MOS transistor M14, and the source of MOS transistor M15 is grounded.

[0046] MOS transistors M10 and M11 are connected to their gates, as well as to the gates of MOS transistors M6 and M7. The interconnection of MOS transistors M6, M7, M10, and M11 forms a pair of split-type NMOS current mirrors, directing bias current Ib1 into the drain-source branch of MOS transistor M10. The gates of MOS transistors M8 and M12 are connected to the reference source output port VREF via port VEFK to generate feedback voltage Vref. The source of MOS transistor M9 is connected to port VLS1, through which it outputs bias voltage Vb1 to output voltage regulator circuit 2. The expression for voltage Vb1 is shown below.

[0047] ;

[0048] In the formula, Vref is the reference voltage output by the system, ga is the subthreshold slope factor of the MOS tube, Kb is the Boltzmann constant, T is the temperature, q is the unit charge, Ic is the reverse saturation current, W8 is the conductive channel width of the MOS tube M8, and L8 is the conductive channel length of the MOS tube M8.

[0049] It can be seen from the expression of the bias voltage Vb1 that the voltage Vb1 is not affected by the power supply voltage ripple.

[0050] MOS transistors M14, M15, M6, and M7 are interconnected, also forming a split current mirror structure. The collector of MOS transistor M14 is connected to the gate of MOS transistor M17. The voltage Vb2 at the connection node between the drain of MOS transistor M14 and the source of MOS transistor M13 serves as the bias voltage for MOS transistor M17. The expression for bias voltage Vb2 is shown below.

[0051] ;

[0052] In the formula, Vref is the reference voltage output by the system, ga is the subthreshold slope factor of the MOS tube, Kb is the Boltzmann constant, T is the temperature, q is the unit charge, Ic is the reverse saturation current, W12 is the conductive channel width of the MOS tube M12, and L12 is the conductive channel length of the MOS tube M12.

[0053] As can be seen from the formula, the bias voltage Vb2 is generated based on the same principle as the bias voltage Vb1, and the bias voltage Vb2 is also not affected by the power supply voltage ripple, thereby effectively improving the power supply rejection ratio of the output drive circuit.

[0054] like Figure 2 As shown, the output drive circuit 12 includes MOS transistors M16, M17, M18, M19, transistors Q1, Q2, resistors R1, R2, R3, capacitor C1, port VJDN, port VGCP, and port VFSO.

[0055] The source of MOS transistor M16 is connected to power supply VDD, the gate of MOS transistor M16 is connected to the gate of MOS transistor M18, and the drain of MOS transistor M16 is connected to the collector of transistor Q1. The collector of transistor Q1 is connected to the gate of MOS transistor M17, the base of transistor Q1 is connected to port VJDN, and the emitter of transistor Q1 is connected to the upper end of resistor R1. The drain of MOS transistor M17 is connected to the lower end of resistor R1, the gate of MOS transistor M17 is connected to the source of MOS transistor M13, and the source of MOS transistor M17 is grounded.

[0056] The source of MOS transistor M18 is connected to the source of MOS transistor M16. The gate of MOS transistor M18 is connected to the drain of MOS transistor M16. The drain of MOS transistor M18 is connected to the collector of transistor Q2. The collector of transistor Q2 is connected to the drain of MOS transistor M18. The base of transistor Q2 is connected to port VGCP. The emitter of transistor Q2 is connected to the upper end of resistor R2, and the lower end of resistor R2 is grounded. The upper end of resistor R3 is connected to the drain of MOS transistor M18. The lower end of resistor R3 is connected to the upper end of capacitor C1, and the lower end of capacitor C1 is connected to port VFSO. The source of MOS transistor M19 is connected to the source of MOS transistor M18. The gate of MOS transistor M19 is connected to the upper end of resistor R3. The drain of MOS transistor M19 is connected to port VFSO.

[0057] MOS transistors M16, M17, M18, and M19 all operate in the subthreshold region. Furthermore, the drain of MOS transistor M18 is connected to the gate of MOS transistor M19, and the drain voltage of MOS transistor M18 biases MOS transistor M19, causing it to operate in the subthreshold region without the need for an additional bias circuit. Transistor Q1 is connected to transistor Q4 in the voltage-regulated output circuit 2 via port VJND, and transistor Q2 is connected to transistor Q3 in the voltage-regulated output circuit 2 via port VGCP. The circuit connection structure of transistors Q1 to Q4 significantly reduces circuit mismatch and balances the current in the branches containing transistors Q3 and Q4, making the currents in the two branches equal. Transistors Q1 and Q2 have high transconductance, and based on the circuit connection structure of transistors Q1 and Q2, the power consumption of the output drive circuit 12 is effectively reduced.

[0058] Resistor R3 and capacitor C1 are connected in series and are connected to the gate and drain of MOS transistor M19, respectively. Based on their associated circuit connection structure, resistor R3 and capacitor C1 perform Miller compensation on the output drive circuit 12, improving the system's phase margin and thus enhancing system stability. The output drive circuit 12 is designed using a two-stage amplifier circuit. Due to its negative feedback position and connection structure within the entire circuit system, the output impedance of the entire circuit system is significantly reduced, enabling the system to drive load circuits with large capacitance without causing stability issues.

[0059] like Figure 3 As shown, the anti-ripple circuit 21 includes a gain negative feedback circuit 211 and a proportional negative feedback circuit 212 .

[0060] Gain negative feedback circuit 211 is connected to proportional negative feedback circuit 212. Gain negative feedback circuit 211 employs a symmetrical circuit structure with proportional negative feedback circuit 212, jointly eliminating the common-mode interference voltage in anti-ripple circuit 21. Based on the negative feedback circuit structure, gain negative feedback circuit 211 and proportional negative feedback circuit 212 eliminate the effects of power supply voltage ripple on the system, significantly improving the power supply rejection ratio of voltage-regulated output circuit 2.

[0061] The gain negative feedback circuit 211 includes a MOS transistor M22 , a MOS transistor M23 , a MOS transistor M24 , a MOS transistor M25 , a MOS transistor M26 , a MOS transistor M32 , and a port VLS2 .

[0062] The source of MOS transistor M22 is connected to power supply VDD, the gate of MOS transistor M22 is connected to the gate of MOS transistor M25, and the drain of MOS transistor M22 is connected to the drain of MOS transistor M23. The drain of MOS transistor M23 is connected to the gate of MOS transistor M22, the gate of MOS transistor M23 is connected to the collector of transistor Q4, and the source of MOS transistor M23 is connected to the drain of MOS transistor M24. The drain of MOS transistor M24 is connected to the source of MOS transistor M23, the gate of MOS transistor M24 is connected to port VLS2, and the source of MOS transistor M24 is grounded.

[0063] The source of MOS transistor M25 is connected to the source of MOS transistor M22, the gate of MOS transistor M25 is connected to the drain of MOS transistor M22, and the drain of MOS transistor M25 is connected to the drain of MOS transistor M29. The drain of MOS transistor M26 is connected to the drain of MOS transistor M23, the gate of MOS transistor M26 is connected to the collector of transistor Q3, and the source of MOS transistor M26 is connected to the source of MOS transistor M23. The source of MOS transistor M32 is connected to power supply VDD, the gate of MOS transistor M32 is connected to the drain of MOS transistor M22, and the drain of MOS transistor M32 is connected to the drain of MOS transistor M33.

[0064] The drain of MOS transistor M32 is connected to the gate of MOS transistor M20, forming an equivalent inverting amplifier circuit structure. The drain of MOS transistor M20 is connected to the gate of MOS transistor M32 via resistor R6, forming a negative feedback closed loop. The gate of MOS transistor M23 is connected to the collector of transistor Q4, forming a common-emitter amplifier circuit structure and determining the negative feedback gain of gain negative feedback circuit 211.

[0065] The proportional negative feedback circuit 212 includes a MOS transistor M27 , a MOS transistor M28 , a MOS transistor M29 , a MOS transistor M30 , a MOS transistor M31 , and a MOS transistor M33 .

[0066] The source of MOS transistor M27 is connected to the power supply VDD, the gate of MOS transistor M27 is connected to the gate of MOS transistor M28, and the drain of MOS transistor M27 is connected to the drain of MOS transistor M22. The source of MOS transistor M28 is connected to the source of MOS transistor M27, the gate of MOS transistor M28 is connected to the drain of MOS transistor M28, and the drain of MOS transistor M28 is connected to the drain of MOS transistor M29. The drain of MOS transistor M29 is connected to the drain of MOS transistor M25, the gate of MOS transistor M29 is connected to port VREF, and the source of MOS transistor M29 is connected to the source of MOS transistor M26. The source of MOS transistor M30 is connected to the source of MOS transistor M28, the gate of MOS transistor M30 is connected to the drain of MOS transistor M28, and the drain of MOS transistor M30 is connected to the drain of MOS transistor M31. The drain of MOS transistor M31 is connected to the drain of MOS transistor M30, the gate of MOS transistor M31 is connected to the gate of MOS transistor M33, and the source of MOS transistor M31 is grounded. The drain of MOS transistor M33 is connected to the gate of MOS transistor M20, the gate of MOS transistor M33 is connected to the drain of MOS transistor M31, and the source of MOS transistor M33 is grounded.

[0067] The gate of MOS transistor M29 is connected to the gates of transistors Q3 and Q4, and the equivalent resistance of the collector circuit node of transistor Q3 is greater than the equivalent resistance of the collector circuit node of transistor Q4. Based on the ratio of branch resistor R4 to resistor R6, the feedback loop formed by proportional negative feedback circuit 212 and transistor Q3 is negative feedback.

[0068] The anti-ripple circuit 21 is configured based on its two negative feedback circuit structures, which effectively eliminates the influence of power supply voltage ripple on the voltage stabilizing output circuit 2 .

[0069] The expression for the equivalent resistance Rj3 of the collector circuit node of transistor Q3 is shown below.

[0070] ;

[0071] In the formula, A1 is the negative feedback gain of the proportional negative feedback circuit 212, and gm3 is the transconductance of the transistor Q3.

[0072] The expression of the equivalent resistance Rj4 of the collector circuit node of transistor Q4 is shown below.

[0073] ;

[0074] In the formula, A2 is the negative feedback gain of the gain negative feedback circuit 211, and gm4 is the transconductance of the transistor Q4.

[0075] Based on the relevant circuit structures of the gain negative feedback circuit 211 and the proportional negative feedback circuit 212 , the expression of the power supply rejection ratio PSRR of the voltage regulated output circuit 2 is as follows.

[0076] ;

[0077] ; ;

[0078] In the formula, n1 and n2 represent the branch impedance proportional coefficients, A1 represents the negative feedback gain of proportional negative feedback circuit 212, A2 represents the negative feedback gain of gain negative feedback circuit 211, r4 represents the resistance of resistor R4, and r6 represents the resistance of resistor R6. As can be seen from the expression for the power supply rejection ratio of the voltage-regulated output circuit 2, the anti-ripple circuit 21 incorporates the gains of the two negative feedback loops as a product term into the denominator to eliminate the interference of power supply voltage ripple on the system, thereby improving the system's power supply rejection ratio.

[0079] like Figure 3 As shown, the reference output circuit 22 includes a MOS transistor M20, a MOS transistor M21, a resistor R4, a resistor R5, a resistor R6, a transistor Q3, a transistor Q4, a capacitor C2, a capacitor C3, a port VJOU, a port VGUT, a port VFIN, and a port VREF.

[0080] The source of MOS transistor M20 is connected to power supply VDD, the gate of MOS transistor M20 is connected to the drain of MOS transistor M32, and the drain of MOS transistor M20 is connected to the upper end of resistor R4. The collector of transistor Q3 is connected to the lower end of resistor R4 and to port VGUT. The base of transistor Q3 is connected to the base of transistor Q4 and to port VFIN. The emitter of transistor Q3 is connected to the upper end of resistor R5. The drain of MOS transistor M21 is connected to the lower end of resistor R5, the gate of MOS transistor M21 is connected to the drain of MOS transistor M21, and the source of MOS transistor M21 is grounded. The upper end of resistor R6 is connected to the upper end of resistor R4, and the lower end of resistor R6 is connected to port VJOU. The collector of transistor Q4 is connected to the lower end of resistor R6, the base of transistor Q4 is connected to port VREF, and the emitter of transistor Q4 is connected to the lower end of resistor R5. The upper end of capacitor C2 is connected to the gate of MOS transistor M20, and the lower end of capacitor C2 is connected to the gate of MOS transistor M26. The upper end of capacitor C3 is connected to the upper end of capacitor C2, and the lower end of capacitor C3 is connected to the gate of MOS transistor M23.

[0081] The collectors of transistors Q3 and Q4 are connected to output drive circuit 12 via ports VGUT and VJOU, respectively, enabling transistors Q3 and Q4 to operate stably in the amplification region. The gate and drain of MOS transistor M20 are connected to relevant nodes of anti-ripple circuit 21, enabling MOS transistor M20 to operate stably in the saturation region.

[0082] Capacitor C2 is connected to the gate of MOS transistor M20 and the collector of transistor Q3. Capacitor C3 is connected to the gate of MOS transistor M20 and the collector of transistor Q4. Transistors Q3 and Q4 introduce a 90Hz zero Zn1 into the system through a feedforward path, ensuring sufficient phase margin for the circuit system. The expression for zero Zn1 is shown below.

[0083] ;

[0084] In the formula, c2 is the capacitance value of capacitor C2, c3 is the capacitance value of capacitor C3, A2 is the negative feedback gain of the gain negative feedback circuit 211, and Rd20 is the equivalent impedance of the drain circuit node of the MOS tube M20.

[0085] Transistors Q3 and Q4 have the same bias current. Because resistor R5 is connected to the source of transistor Q3, the source degradation effect of the circuit structure associated with transistor Q3 is significantly greater than that of the circuit structure associated with transistor Q4. Consequently, the common-emitter amplifier gain of the circuit structure associated with transistor Q3 is smaller than that of the circuit structure associated with transistor Q4. This means that the negative feedback gain formed by transistor Q4 and the anti-ripple circuit 21 is greater than the positive feedback gain formed by transistor Q3 and the output driver circuit 12, ensuring the stability of the entire circuit system. The voltage across resistor R5 is the difference between the base and emitter voltages of transistor Q4. The gate of transistor Q4 is connected to port VREF, through which a reference voltage Vref is output. The expression for reference voltage Vref is shown below.

[0086] ;

[0087] In the formula, Vbe4 is the base-emitter voltage of transistor Q4, Vbe3 is the base-emitter voltage of transistor Q3, r5 is the resistance of resistor R5, Rm21 is the on-resistance of MOS transistor M21, Kb is the Boltzmann constant, T is the temperature, N is the emitter area ratio of transistor Q3 to transistor Q4, and q is the unit charge. By adjusting Rm21, the reference voltage Vref can achieve the optimal temperature coefficient.

Claims

1. A high power supply rejection ratio strong drive reference source integrated circuit, characterized in that: It includes a driving enhancement circuit (1) and a voltage stabilization output circuit (2); The driving enhancement circuit (1) is connected to the voltage stabilizing output circuit (2). The driving enhancement circuit (1) improves the load driving capability of the voltage stabilizing output circuit (2) by reducing the output impedance of the system, and enables the voltage stabilizing output circuit (2) to drive a load with small impedance and large capacitance without causing stability problems by introducing a negative feedback loop. The voltage stabilization output circuit (2) generates a reference voltage with a high power supply rejection ratio and outputs it through a port; The driving enhancement circuit (1) includes a subthreshold bias circuit (11) and an output driving circuit (12); The subthreshold bias circuit (11) is connected to the output drive circuit (12), and the subthreshold bias circuit (11) outputs two bias voltages that are not affected by power supply ripple, and outputs them to the output drive circuit (12) and the voltage stabilization output circuit (2) respectively; The output drive circuit (12) enables the system to have a small output impedance based on its circuit connection structure, so as to stably drive a load with a large input capacitance; The voltage stabilizing output circuit (2) includes an anti-ripple circuit (21) and a reference output circuit (22); The anti-ripple circuit (21) is connected to the reference output circuit (22), and the anti-ripple circuit (21) significantly improves the power supply rejection ratio of the reference output circuit (22) by introducing two negative feedback loops; The reference output circuit (22) stably outputs the reference voltage and has a strong load driving capability; The subthreshold bias circuit (11) includes a self-bias circuit (111) and a bias voltage circuit (112); The self-bias circuit (111) is connected to the bias voltage circuit (112), and the self-bias circuit (111) generates a bias current that is not affected by the power supply voltage ripple and outputs it to the bias voltage circuit (112), thereby providing a bias condition for the normal operation of the main MOS tube in the bias voltage circuit (112); The bias voltage circuit (112) generates a bias voltage that is not affected by the power supply voltage ripple and inputs the bias voltage into the output drive circuit (12) and the voltage stabilization output circuit (2); The anti-ripple circuit (21) includes a gain negative feedback circuit (211) and a proportional negative feedback circuit (212); The gain negative feedback circuit (211) is connected to the proportional negative feedback circuit (212), and the gain negative feedback circuit (211) adopts a circuit structure symmetrical with the proportional negative feedback circuit (212) to jointly eliminate the common-mode interference voltage in the anti-ripple circuit (21); The gain negative feedback circuit (211) and the proportional negative feedback circuit (212) are based on a negative feedback circuit structure, eliminating the influence of power supply voltage ripple on the system and significantly improving the power supply rejection ratio of the voltage stabilizing output circuit (2).

Images