Data processing method, electronic equipment, medium and product

Abstract

The invention provides a data processing method, electronic equipment, a medium and a product, and relates to the technical field of computers, by exchanging storage positions of target user data and first target check bit data under the condition that first performance quality is greater than a first quality threshold value and second performance quality is smaller than a second quality threshold value, the storage positions of the target user data and the first target check bit data are exchanged; the storage position between the check bit data in the strip and the user data is flexibly adjusted, abrasion of the solid state disk at the original storage position of the first target check bit data is reduced, and better load balancing is achieved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to data processing methods, electronic devices, media, and products. Background Art

[0002] A solid-state drive includes multiple storage units, each of which is used to store data. User data is distributed across different storage units and parity bits are added to improve data security.

[0003] In related technologies, in order to maintain data consistency and the accuracy of check bit information, each time data is written to a storage unit, the data of the corresponding storage unit needs to be updated, and the corresponding check bit data needs to be updated at the same time. This data processing method may lead to low performance of the solid-state drive. Summary of the Invention

[0004] The present application provides a data processing method, electronic device, medium and product to at least solve the problem of low performance of solid-state drives in related technologies.

[0005] The present application provides a data processing method applied to a solid-state drive. The solid-state drive stores multiple stripes, each of the multiple stripes includes multiple pages of data, and the multiple pages of data include: multiple user data and check bit data. The method includes:

[0006] In the case where a target operation is detected, target user data in a target stripe to be operated by the target operation is determined, where the target stripe is a stripe among the multiple stripes, and the target user data is one of the multiple user data included in the target stripe;

[0007] Determining a first performance quality of a first target storage unit where target user data is located;

[0008] Determine a second performance quality of a second target storage unit where the first target parity bit data included in the target stripe is located;

[0009] When the first performance quality is greater than a first quality threshold and the second performance quality is less than a second quality threshold, storage locations of the target user data and the first target check bit data are exchanged.

[0010] The present application also provides a data processing device, which is applied to a solid-state hard disk. The solid-state hard disk stores multiple stripes, each of the multiple stripes includes multiple pages of data, and the multiple pages of data include: multiple user data and check bit data. The device includes:

[0011] A first determining module is configured to, when a target operation is detected, determine target user data in a target stripe to be operated on by the target operation, where the target stripe is a stripe among the multiple stripes, and the target user data is one of the multiple user data included in the target stripe;

[0012] a second determining module, configured to determine a first performance quality of a first target storage unit where the target user data is located;

[0013] A third determining module is configured to determine a second performance quality of a second target storage unit where the first target parity bit data included in the target stripe is located;

[0014] The exchange module is used to exchange the storage locations of the target user data and the first target check bit data when the first performance quality is greater than the first quality threshold and the second performance quality is less than the second quality threshold.

[0015] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of the above-mentioned data processing method when executing the computer program.

[0016] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned data processing method are implemented.

[0017] The present application also provides a computer program product, comprising a computer program, which implements the steps of the above-mentioned data processing method when executed by a processor.

[0018] In an embodiment of the present application, by exchanging the storage positions of the target user data and the first target check bit data when the first performance quality is greater than the first quality threshold and the second performance quality is less than the second quality threshold, flexible adjustment of the storage positions between the check bit data and the user data within the stripe is achieved, reducing the wear on the solid-state hard disk at the original storage position of the first target check bit data, and achieving better load balancing. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0020] Figure 1 A schematic diagram of a data processing method provided for related technology;

[0021] Figure 2A schematic diagram of another data processing method provided for related technology;

[0022] Figure 3 An application scenario diagram of a data processing method provided in an embodiment of the present application;

[0023] Figure 4 A flowchart of a data processing method provided in an embodiment of the present application;

[0024] Figure 5 A schematic diagram of a data exchange storage location provided in an embodiment of the present application Figure 1 ;

[0025] Figure 6 A schematic diagram of a data exchange storage location provided in an embodiment of the present application Figure 2 ;

[0026] Figure 7 A schematic diagram of a flow chart of an evaluation model for estimating exchange results provided in an embodiment of the present application;

[0027] Figure 8 A schematic diagram of the structure of a data processing device provided in an embodiment of the present application;

[0028] Figure 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0030] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0031] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use, processing, transmission, provision, disclosure and application of the relevant data comply with the relevant laws, regulations and standards of the relevant countries and regions, take necessary confidentiality measures, do not violate public order and good morals, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0032] Flash-based solid-state drives (SSDs), with their advantages of low power consumption, portability, and fast random access, have gradually replaced traditional mechanical hard drives and become the mainstream storage device. As the demand for data storage continues to grow, the importance of high-density SSDs is becoming increasingly prominent. However, the increasing density of flash memory cells also leads to more serious problems such as read and write interference. In this context, traditional error correction code technology is unable to effectively address these read and write interference issues.

[0033] To improve data reliability, RAID-5 (Redundant Array of Independent Disks Level 5) solid-state drive technology is used. This technology distributes user data across different flash memory chips and calculates parity information. This mechanism effectively prevents data loss caused by a single flash memory chip failure, thereby enhancing data security. However, RAID-5 requires that each time user data is written, the system must not only update the user data being written, but also the corresponding parity bit data to ensure data consistency.

[0034] Among them, the traditional RAID-5 parity bit update mechanism has the following problems:

[0035] (1) Load imbalance, that is, only considering reducing additional read requests without considering the real-time load of each channel inside the SSD, resulting in some channels being highly congested while other channels are idle, and the high concurrency performance advantage of the SSD cannot be fully utilized.

[0036] (2) Write position restriction: To ensure the validity of the tape, updated user data and check bit data must be written back to the original storage unit. This causes a serious imbalance in the workload between the channels corresponding to each storage unit, limiting the parallel processing capability of the solid-state drive.

[0037] Furthermore, RAID-5 technology implements its functionality through a striped data storage mechanism. Each stripe consists of multiple user data and one parity bit. The parity bit is the result of an exclusive OR (XOR) operation on the multiple user data. If one piece of user data is erroneous or missing, the erroneous or missing user data is retrieved by reading the remaining user data in the same stripe and the parity bit data and performing an XOR operation on them.

[0038] To ensure effective data recovery when user data errors occur, the parity bit data within the same stripe must be updated simultaneously with the user data update. Parity bit data can be updated using either a ReadModifyWrite (RMW) or a ReconstructWrite (RCW) method. Both methods require sending additional read requests to obtain the updated user data and parity bit data in the stripe.

[0039] For example, refer to Figure 1 When the user data to be updated is less than 1 / 2 of the data contained in the stripe, you can choose to update the parity data in RMW mode. When the user data to be updated is greater than or equal to 1 / 2 of the data contained in the stripe, you can choose to update the parity data in RMW mode. Figure 1 , stripe T1 includes data a0 to data a4, and parity data P. When data a0 is updated to data a0′, the parity data P is updated to parity data P′ using RMW. Figure 2 When data a0 is updated to data a0′, data a1 is updated to data a1′, and data a2 is updated to data a2′, the check bit data P1 is updated to P′′ using the RCW method.

[0040] It is understandable that both of the above-mentioned methods of updating the check bit data will lead to frequent updates of the check bit data, which will in turn trigger a large number of additional write operations, which will have multiple adverse effects on the operation of the SSD: First, the surge in write operations will directly extend the I / O (Input / Output) response time, resulting in a decline in the overall performance of the SSD; second, frequent write operations will intensify the data migration and garbage collection activities within the SSD, thereby accelerating the wear and aging of the SSD and significantly shortening the service life of the SSD; finally, since the SSD requires that the updated user data and the corresponding check bits must be written back to the original storage unit, this mandatory write strategy further worsens the load imbalance between the channels of the SSD, restricting the parallel processing capabilities of the SSD.

[0041] Based on the above problems, the present application can exchange the storage positions of the target user data and the first target check bit data when the first performance quality is greater than the first quality threshold and the second performance quality is less than the second quality threshold, thereby achieving flexible adjustment of the storage positions between the check bit data and the user data within the stripe, reducing the wear on the solid-state hard disk at the original storage position of the first target check bit data, and achieving better load balancing.

[0042] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0043] In conjunction with the specific application environment architecture or specific hardware architecture on which the execution of the data processing method depends, the specific application environment architecture or specific hardware architecture is described here. Figure 3 , Figure 3 This is an example diagram of the application scenario of the data processing method. Figure 3 A schematic diagram of the structure of a solid-state drive is shown. The solid-state drive includes flash memory, which includes multiple storage modules, such as storage module b0, storage module b1, ... storage module b2. Each storage module stores a stripe, and each storage module includes multiple storage units. For example, storage module bi includes storage units bi0 to bi5, where i ranges from 0 to 2. Each stripe includes multiple user data and one parity bit data, and each storage unit stores one user data or one parity bit data. For example, the multiple stripes include stripes D0 to D2, where stripe D0 is stored in storage module b0, stripe D1 is stored in storage module b1, and stripe D2 is stored in storage module b2. Furthermore, stripe Dr includes user data Dr0 to Dr4 and parity bit data Pr, where n can range from 0 to 2. User data Drj is stored in corresponding storage unit brj, where j ranges from 0 to 4, and parity bit data Pr is stored in storage unit br5. For each storage module, the storage units of the storage module correspond to the channels one by one. For example, the storage unit bij corresponds to the channel ct, where the channel ct is used to transmit the user data or check bit data stored in the storage unit bij.

[0044] In an embodiment of the present application, the amount of user data included in different stripes may be the same or different, and the multiple channels corresponding to different storage modules may be the same or not completely the same. For example, 10 channels are included, namely channel c0 to channel c9, storage units b00 to storage units b05 correspond to channels c0 to channel c5 respectively, and storage units b10 to storage units b15 correspond to channels c3 to channel c8 respectively. This application does not limit this.

[0045] Figure 4A flow chart of the steps of a data processing method is shown, and the data processing method specifically includes the following steps:

[0046] S401 : When a target operation is detected, determine target user data in a target stripe to be operated by the target operation.

[0047] The solid-state drive stores multiple stripes, each of which includes multiple pages of data. The multiple pages of data include: multiple user data and check bit data. It can be understood that one user data is one page of data, and one check bit data is also one page of data.

[0048] For example, refer to Figure 3 , the solid-state drive stores three stripes, namely stripe D0, stripe D1 and stripe D2. Stripes D0 to D2 each include 6 pages of data. Among the 6 pages of data included in stripe Dr, 5 are user data, namely user data Dr0 to user data Dr4, and 1 is check bit data Pr.

[0049] It can be understood that the parity bit data in each stripe is calculated based on the user data in the stripe, and the specific calculation method can be an exclusive OR calculation.

[0050] In the embodiment of the present application, the target stripe is a stripe among the multiple stripes, and the target user data is one of the multiple user data included in the target stripe.

[0051] For example, the target action is for Figure 1 If the stripe D0 in the target stripe is user data D00, then the stripe D0 is the target stripe and the user data D00 is the target user data.

[0052] In the embodiment of the present application, the target operation is a write operation or a recycle operation, wherein the write operation is to update the target user data.

[0053] S402: Determine a first performance quality of a first target storage unit where target user data is located.

[0054] Among them, reference Figure 3 , if the target user data is user data D00, the first target storage unit is storage unit b00.

[0055] In some embodiments, determining a first performance quality of a first target storage unit where target user data is located includes: determining a first degree of wear of the first target storage unit; determining a first degree of load of a first target channel corresponding to the first target storage unit; determining a first performance quality based on the first degree of wear and / or the first degree of load, the first degree of wear being negatively correlated with the first performance quality, and the first degree of load being negatively correlated with the first performance quality.

[0056] The first wear degree may be determined based on the total number of historical write operations of the first target storage unit. The total number of historical write operations is positively correlated with the first wear degree, that is, the greater the total number of historical write operations, the more severe the first wear degree.

[0057] For example, the first wear degree can be divided into level 1, level 2, level 3 and level 4, and the higher the level, the heavier the first wear degree. Among them, the first number threshold, the second number threshold and the third number threshold are set, and the first number threshold is less than the second number threshold and less than the third number threshold. If the total number of historical write operations is less than the first number threshold, the first wear degree is level 1. If the total number of historical write operations is greater than or equal to the first number threshold and less than the second number threshold, the first wear degree is level 2. If the total number of historical write operations is greater than or equal to the second number threshold and less than the third number threshold, the first wear degree is level 3. If the total number of historical operations is greater than or equal to the third number threshold, the first wear degree is level 4.

[0058] In an embodiment of the present application, for example, the first target storage unit is storage unit b00, then the first target channel is channel c0, wherein the first load degree of channel c0 can be determined according to the amount of data currently transmitted by channel c0, wherein the more data transmitted by channel c0, the more severe the first load degree.

[0059] In some embodiments, the first load level can be divided into level 1, level 2, level 3 and level 4, and the higher the level, the more severe the first load level. Among them, a first quantity threshold, a second quantity threshold and a third quantity threshold are set, and the first quantity threshold is less than the second quantity threshold and less than the third quantity threshold. If the amount of data transmitted by the first target channel is less than the first quantity threshold, the first load level is level 1. If the amount of data transmitted by the first target channel is greater than or equal to the first quantity threshold and less than the second quantity threshold, the first load level is level 2. If the amount of data transmitted by the first target channel is greater than or equal to the second quantity threshold and less than the third quantity threshold, the first load level is level 3. If the amount of data transmitted by the first target channel is greater than or equal to the third quantity threshold, the first load level is level 4.

[0060] For example, refer to Figure 3, memory cells b00, b10, and b20 all use channel c0 to transmit data. If channel c0 currently does not need to transmit data, the first load level is level 1. If data transmission is required only from one of the memory cells (for example, reading data D00 or writing data to memory cell b00), the first load level is level 2. If data transmission is required for two of the memory cells, the first load level is 3. If data transmission is required for three memory cells, the first load level is level 4.

[0061] In an embodiment of the present application, the first performance quality of the first target storage unit can be determined based on the first wear degree and / or the first load degree. The higher the first performance quality of the first target storage unit (the lower the corresponding first wear degree and / or the lower the first load degree), the more efficient the read and write operations can be performed on the data stored in the first target storage unit. The lower the first performance quality of the first target storage unit (the higher the corresponding first wear degree and / or the higher the first load degree), the lower the efficiency of the read and write operations on the data stored in the first target storage unit, which in turn affects the use of the solid-state drive.

[0062] In some embodiments, the first performance quality of the first target storage unit can be determined according to the first wear degree and / or the first load degree by a preset calculation method. For example, the first performance quality can be expressed as 1 / s1, where s1 is the level of the first wear degree. For example, if s1=4, the first performance quality is 1 / 4, indicating that the first performance quality is relatively low. The first performance quality can also be expressed as 1 / s2, where s2 is the level of the first load degree. For example, if s2=1, the first performance quality is 1, indicating that the first performance quality is relatively high. For example, the first performance quality can be expressed as f / s1+g / s2, for example, s1=4, s2=2, f and g are preset coefficients, f and g are both [0,1], f+g=1, for example, if f is 0.5, g=0.5, then the first performance quality is 3 / 8.

[0063] In the embodiment of the present application, the first performance quality may also be determined by other methods, which are not limited here.

[0064] S403: Determine a second performance quality of a second target storage unit where the first target parity bit data included in the target stripe is located.

[0065] For example, refer to Figure 3 , the target stripe is stripe D0, the target parity bit data is P0, and the second target storage unit is storage unit b05.

[0066] In some embodiments, determining the second performance quality of the second target storage unit where the first target check bit data included in the target stripe is located includes: determining a second degree of wear of the second target storage unit; determining a second degree of load of the second target channel corresponding to the second target storage unit; determining the second performance quality based on the second degree of wear and / or the second degree of load, the second degree of wear being negatively correlated with the second performance quality, and the second degree of load being negatively correlated with the second performance quality.

[0067] In the embodiment of the present application, the method for determining the second performance quality may refer to the first performance quality, which will not be described in detail here.

[0068] S404 : When the first performance quality is greater than a first quality threshold and the second performance quality is less than a second quality threshold, swap storage locations of the target user data and the first target check bit data.

[0069] The first quality threshold is greater than the second quality threshold.

[0070] In some embodiments, the first performance quality can be expressed as [0, 1], and the second performance quality can also be expressed as [0, 1], with larger values ​​indicating higher performance quality. For example, the first quality threshold can be set to 0.7, and the second instruction threshold can be set to 0.3.

[0071] In some embodiments, the first performance quality may also be expressed in other ways, such as a quality level, where a higher quality level indicates a higher first performance quality, and a lower quality level indicates a lower first performance quality, which is not limited in this application.

[0072] It can be understood that the update frequency of the target parity bit data is higher than or equal to that of any user data in the target stripe. Therefore, the storage unit containing the target parity bit data wears out faster, and the channel corresponding to the storage unit containing the target parity bit data is also more likely to experience high load levels. Therefore, when the second performance quality is high, by swapping the storage locations of the target user data and the first target parity bit data, load balancing of the SSD can be achieved, and uneven wear of the storage units can be avoided, which in turn affects the service life of the SSD.

[0073] For example, refer to Figure 3In the initialized solid-state hard drive, the present application stores stripes D0, D1, and D2. For stripe D0, if user data D00 is updated q1 times, user data D01 is updated q2 times, user data D02 is updated q3 times, user data D03 is updated q4 times, and user data D04 is updated q5 times, then the check bit data P0 needs to be updated q1+q2+q3+q4+q5 times. After the check bit data is frequently updated, the degree of wear of the storage unit b05 is high. In this case, the storage position of the check bit data P0 can be exchanged with the user data in the same stripe to avoid failure caused by continued rapid wear of the storage unit b05. In addition, since the update frequency of the check bit data P0 is relatively high, if the channel corresponding to the storage unit b05 is also used to transmit other hot data, it may cause the channel to be seriously loaded. If the channel corresponding to the storage unit b05 is seriously loaded, the check bit data P0 can be exchanged with the user data in the same strip to reduce the load of the storage unit b05 and achieve load balancing of the solid-state hard drive.

[0074] In some embodiments, the target operation is a write operation, and the method further includes: obtaining target write data corresponding to the target user data; updating the first target check bit data according to the target write data and other user data in the target stripe to obtain the second target check bit data.

[0075] Exchanging the storage locations of the target user data and the first target check bit data includes: storing the second target check bit data in the first target storage unit and storing the target write data in the second target storage unit.

[0076] It is understood that the target write data is the updated data of the target user data, and the target write data needs to be rewritten into the target stripe. The second target check bit data is calculated based on the first target check bit data, the target write data and other user data in the target stripe.

[0077] Furthermore, if the storage locations of the exchange target user data and the first target check bit data are determined, during the write operation, the target user data in the first target storage unit is erased, and the first target check bit data in the second target storage unit is erased, and then the second target check bit data is stored in the first target storage unit, and the target write data is stored in the second target storage unit.

[0078] Reference Figure 5 As shown, Figure 5 (1) is the storage status of stripe D0 in storage unit b0 when it is not swapped. Figure 5(2) shows the storage status of stripe D0 in storage unit b0 after the swap. D00 is the target user data, D00′ is the target write data, P0 is the first target parity bit data, and P0′ is the second target parity bit data. After the second target parity bit data P0′ is stored in the first target storage unit, the reading and writing of the second target parity bit data P0′ through the first target storage unit is wear and tear on the first target storage unit, thereby reducing the wear and tear on the second target storage unit. In addition, the reading and writing of the second target parity bit data P0′ through the channel corresponding to the first target storage unit can reduce the load on the channel corresponding to the second target storage unit.

[0079] In summary, the present application can exchange the storage locations of the target user data and the first target check bit data during the write operation, thereby avoiding additional read and write operations caused by exchanging the storage locations, and thus improving data exchange efficiency.

[0080] In some embodiments, the target operation is a recycling operation, the target user data is valid data, and the storage locations of the target user data and the first target check bit data are exchanged, including: determining whether the target user data is valid data; if so, storing the first target check bit data in the first target storage unit; and storing the target user data in the second target storage unit.

[0081] In the embodiment of the present application, a solid state drive stores multiple data blocks, each of which includes multiple pages of data. Figure 3 The user data or check bit data shown. Since the access frequencies of various page data in the same data block are different, for example, some page data have a higher access frequency and some page data have a lower access frequency, the page data with a higher access frequency may be valid page data, and the page data with a lower access frequency may be invalid page data. Furthermore, in order to ensure the security of valid page data during the data block recovery operation, it is usually necessary to migrate the valid page data first.

[0082] Reference Figure 6 As shown, in the recycling operation, Figure 6 (1) is the storage status of stripe D0 in storage unit b0 when it is not swapped. Figure 6(2) shows the storage status of stripe D0 in storage unit b0 after the swap. D00 is the target user data, and P0 is the first target parity bit data. After the first target parity bit data P0 is stored in the first target storage unit, the reading and writing of the first target parity bit data P0 passes through the first target storage unit, which wears out the first target storage unit and reduces the wear on the second target storage unit. In addition, the reading and writing of the first target parity bit data P0 passes through the channel corresponding to the first target storage unit, which can reduce the load of the channel corresponding to the second target storage unit.

[0083] It can be understood that the recycling operation of this application is for the data block containing the target user data. Since the target user data is valid data, the target user data needs to be migrated to avoid the target user data being recycled. Therefore, the target user data needs to be migrated.

[0084] In an embodiment of the present application, the storage locations of the target user data and the first target check bit data can be exchanged when migrating the target user data, so as to avoid additional read and write operations caused by exchanging the storage locations, thereby further enhancing the overall efficiency and response speed of the solid-state drive without affecting the performance of the solid-state drive.

[0085] In some embodiments, when the first performance quality is greater than the first quality threshold and the second performance quality is less than the second quality threshold, the storage locations of the target user data and the first target check bit data are exchanged, including: when the first performance quality is greater than the first quality threshold and the second performance quality is less than the second quality threshold, using a preset evaluation model to evaluate the exchange result, the exchange result is used to indicate whether to exchange the storage locations of the target user data and the first target check bit data; when the exchange result indicates to exchange, exchanging the storage locations of the target user data and the first target check bit data.

[0086] In an embodiment of the present application, an evaluation model may be preset to evaluate whether exchanging the target user data with the first target check digit data will improve the performance of the solid-state drive. If the evaluation model's exchange result indicates that the exchange is to be performed, it can be understood that exchanging the target user data with the first target check digit data will improve the performance of the solid-state drive, and further steps may be performed to exchange the storage locations of the target user data and the first target check digit data.

[0087] In some embodiments, the target operation is a write operation, and the method further includes: when the exchange result indicates that no exchange is to be performed, storing the target write data corresponding to the target user data in the first target storage unit, and storing the second target check bit data in the second target storage unit, the second target check bit data being obtained after updating based on the first target check bit data.

[0088] It is understandable that if the exchange result of the evaluation model indicates not to exchange, it is understandable that exchanging the target user data and the first target check bit data will not improve the performance of the solid state drive, and the exchange step is not performed.

[0089] In some embodiments, the target operation is a write operation, and the method further includes: if the swap result indicates not to perform the swap, storing the target write data in the first target storage unit and storing the second target check bit data in the second target storage unit.

[0090] It is understandable that if no exchange is performed, then according to the relevant RAID-5 update mechanism, the updated target write data is written to the first target storage unit, and the corresponding updated second target parity bit data is written to the second target storage unit.

[0091] In some embodiments, the evaluation model includes a first module and a second module, and the evaluation model is constructed in the following manner: constructing a first module, the first module is used to determine multiple state variables and multiple decision variables based on the objective function, the multiple state variables and the multiple decision variables have a one-to-one correspondence, the multiple state variables and the multiple decision variables are used to minimize the target value of the determined objective function, each state variable represents the state of a page data of a stripe in its corresponding channel, and each decision variable represents the exchange possibility of a page data of a stripe in its corresponding channel; constructing a second module, the second module is used to determine the exchange result based on the state variables corresponding to the target user data and the decision variables corresponding to the target user data.

[0092] In the embodiment of the present application, the evaluation model is constructed based on the total number of accesses to multiple pages of data and the channel load. The specific construction method is as follows:

[0093] (1) Construct the first module:

[0094] First, define multiple state variables C rst , where multiple state variables C rst Used to indicate the status of the solid state drive, C rst The value of is 0 or 1, where C rst Indicates that the sth page data in the rth stripe belongs to the tth channel, where C rst The value of 1 indicates that the sth page data in the rth stripe needs to be exchanged to alleviate wear and / or achieve load balancing. rstA value of 0 indicates that the sth page data in the rth stripe does not need to be swapped. If the SSD stores R+1 stripes, r ranges from 0 to R. The rth stripe contains S+1 pages of data, and s ranges from 0 to S. The sth page data belongs to the tth channel. Therefore, the sth page data is stored in the storage unit corresponding to the tth channel.

[0095] For example, refer to Figure 3 , R is 2, r can be 0, 1, 2, the rth stripe includes: 6 pages of data, s can be 0 to 5.

[0096] In the embodiment of the present application, s can be the same as t or different, and the channels corresponding to the page data in the same stripe are different. In the case where s and t are different, for example, refer to the following Table 1:

[0097] Table 1

[0098]

[0099] In Table 1, the SSD has six channels: channel c0, channel c1, channel c2, channel c3, channel c4, and channel c5. For stripe D0, user data D01 belongs to channel c0, user data D00 belongs to channel c1, parity data P0 belongs to channel c2, user data D03 belongs to channel c3, user data D04 belongs to channel c4, and user data D02 belongs to channel c5. For stripe D1, user data D12 belongs to channel c0, user data D11 belongs to channel c1, user data D10 belongs to channel c2, parity data P1 belongs to channel c3, user data D14 belongs to channel c4, and user data D13 belongs to channel c5. For stripe D2, user data D20 belongs to channel c0, parity data P2 belongs to channel c1, user data D24 belongs to channel c2, user data D22 belongs to channel c3, user data D21 belongs to channel c4, and user data D23 belongs to channel c5.

[0100] It can be understood that based on Table 1, multiple state variables can be obtained, namely C 010 、C 001 、C 052 、C 033 、C 044 、C 025 、C 120 、C 111 、C 102 、C 153 、C 144 、C 135、 C 200 、C 251 、C 242 、C 223 、C214 、C 235 .

[0101] Next, define multiple decision variables X rst , where multiple decision variables X rst The decision variable used to indicate whether to exchange, where X rst The value is 0 or 1, where X rs The value of 1 indicates that the sth page data in the rth stripe needs to be exchanged to alleviate wear and / or achieve load balancing. rs A value of 0 indicates that the sth page data in the rth stripe does not need to be swapped.

[0102] For example, referring to Table 1, we can get multiple decision variables, namely X 010 、X 001 、X 052 、X 033 、X 044 、X 025 、X 120 、X 111 、X 102 、X 153 、X 144 、X 135、 X 200 、X 251 、X 242 、X 223 、X 214 、X 235 .

[0103] In some embodiments, the objective value of the objective function is the sum of a plurality of first difference values, each of which is the absolute value of the difference between one of the state variables and the corresponding decision variable.

[0104] For example, the objective function can be expressed as the following expression (1):

[0105] (1)

[0106] In expression (1), Z is the target value of the objective function, is the first difference. Wherein, the objective function is used to determine multiple state variables C rst and multiple decision variables X rst The value of is chosen so that Z reaches the minimum value.

[0107] In some embodiments, the objective value of the objective function is the sum of a plurality of first products, each of the plurality of first products being the product of one of the state variables and the corresponding decision variable.

[0108] For example, the objective function can be expressed as the following expression (2):

[0109] (2)

[0110] In expression (2), V is the target value of the objective function, is the first product. Among them, the objective function is used to determine multiple state variables C rst and multiple decision variables X rst to minimize V.

[0111] In some embodiments, based on Expression (1) and Expression (2), the objective function includes at least one of the following constraints:

[0112] Constraint 1: The sum of the decision variables corresponding to different pages of data belonging to different channels in the same stripe is 1;

[0113] Constraint 2: The sum of the decision variables and the state variables corresponding to different pages of data in the same channel must be equal;

[0114] Constraint 3: The wear difference of the storage unit to which the data to be exchanged belongs is less than or equal to the wear threshold;

[0115] Constraint 4: The load difference of the channels to which the data to be exchanged belongs must be less than or equal to the load threshold.

[0116] Specifically, constraint 1 is expressed as , where t is 0, 1, ..., N-1, N is the total number of channels, and constraint 1 means that for different pages of data belonging to different channels in the same stripe, the corresponding X rst The sum is 1, for example: for strip D0, X 010 +X 001 +X 052 +X 033 +X 044 +X 025 =1, that is, X 010 、X 001 、X 052 、X 033 、X 044 、X 025 Only one of them has a value of 1, and the others are 0. For strip D1, X 120 +X 111 +X 102 +X 153 +X 144 +X 135 =1, that is, X 111 、X 102 、X 153 、X 144and X 135 Only one of them has a value of 1, and the others are 0. For strip D2, X 200 +X 251 +X 242 +X 223 +X 214 +X 235 =1, that is, X 200 、X 251 、X 242 、X 223 、X 214 、X 235 Only one of them has a value of 1, and the others have a value of 0.

[0117] Constraint 2 is expressed as , s takes 0, 1, ..., S, it can be understood that for the X corresponding to different page data of the same channel rst The sum of C rst The same as .

[0118] Constraint 3 is expressed as ,in, Used to indicate wear differences, Used to represent the wear threshold, in an embodiment of the present application, the i-th channel may be the channel corresponding to the first target storage unit for storing target user data, and the j-th channel may be the channel corresponding to the second target storage unit for storing first target check bit data. is the preset wear balance constraint coefficient, and its value is [0,1]. Indicates the average wear of the storage cells corresponding to N channels.

[0119] in, , I can understand, Indicates the total number of writes to the sth page of the rth stripe, and the total number of reads for each page of each stripe. , determine its relationship with the channel to which it belongs The product of the sum and the ratio of the number of channels N is .

[0120] Constraint 4 is expressed as , Used to indicate load differences, Used to indicate the load threshold. Indicates the total number of reads of the sth page data of the rth stripe belonging to the i-th channel, represents the total number of reads for the sth page of the rth stripe belonging to the jth channel. β is the preset load balancing constraint coefficient, which is in the range [0,1]. Used to indicate the average load of N channels.

[0121] in, , I can understand, Indicates the total number of reads for the sth page of the rth stripe.

[0122] Among the above constraints, constraint 1 and constraint 2 are constraints related to exchange. The constraints are used to ensure that in a stripe, after the page data is exchanged, the channel to which the page data belongs is still the channel corresponding to the stripe of the page data. For example, stripe D0 corresponds to channel c0 to channel c5. Then, after the user data D00 and the first target check bit data P0 are exchanged, the channel to which the first target check bit data P0 belongs after the exchange is included in the channels c0 to channel c5 corresponding to the stripe D0, and the channel to which the user data D00 belongs after the exchange is also included in the channels c0 to channel c5 corresponding to the stripe D0, and any two page data in the same stripe cannot belong to the same channel, that is, they belong to different channels.

[0123] The above constraint (3) is a balance constraint on wear, that is, the wear difference between each storage unit can be made as small as possible, that is, the wear is close to the average value. , where the smaller α is, the greater the constraint is, and wear leveling is achieved.

[0124] The above constraint (4) is a load balance constraint, that is, the load difference between each channel is as small as possible, that is, the load is close to the average value. , to achieve load balancing.

[0125] Through the above expression (1) or expression (2), based on each constraint condition, the first target value X can be obtained uzi and the second target value C uzi , where u represents the stripe to which the target user data belongs, z represents the target user data, and i represents the channel to which the target user data belongs.

[0126] (2) Constructing the second module:

[0127] The second module can use the following expression (3) to determine the exchange result:

[0128] (3)

[0129] in, Indicates the swap result. When the swap result is greater than or equal to the result threshold (such as 0.5), that is, when it approaches 1 or is 1, it is used to indicate the storage location of the swap target user data and the first target check bit data. When the swap result is less than the result threshold, that is, when it approaches 1 or is 0, it is used to indicate that no swap operation is performed.

[0130] In an embodiment of the present application, the evaluation model is used to evaluate whether the wear of the solid-state drive is alleviated and whether the load imbalance problem of the solid-state drive is solved after exchanging the target user data and the first target check bit data.

[0131] Reference Figure 7 , using the preset evaluation model to evaluate the exchange results, specifically including the following steps:

[0132] S701 , obtaining the total number of writes and reads for each page of data in a plurality of stripes.

[0133] Based on Table 1, the total number of writes and reads corresponding to each page data is shown in Table 2:

[0134] Table 2

[0135]

[0136] S702: Obtain a mapping relationship between each page data in a plurality of stripes and a plurality of channels.

[0137] The mapping relationship is used to indicate the channel to which each page data of each stripe belongs.

[0138] In the embodiment of the present application, the mapping relationship is shown in Table 1, which represents the mapping relationship between stripes, page data, and channels.

[0139] S703 , obtaining a first channel to which the target user data belongs and a second channel to which the first target check bit data belongs.

[0140] Referring to Table 1, if the target user data is D01, the first channel is channel c0, the first target check bit data is P0, and the second channel is channel c2. These data are input into the evaluation model. The evaluation model can execute the objective function based on the first module and the second module to execute expression (3) to obtain the exchange result.

[0141] S704: The total number of writes, the total number of reads, the mapping relationship, and the first channel and the second channel are input into an evaluation model for evaluation to obtain an exchange result.

[0142] In the evaluation model, the representation of multiple decision variables and multiple state variables can be determined according to the input mapping relationship. For example, based on Table 1, multiple state variables can be obtained as C 010 、C 001 、C 052 、C 033 、C 044 、C 025 、C 120 、C 111 、C 102 、C 153 、C144 、C 135、 C 200 、C 251 、C 242 、C 223 、C 214 、C 235 . We can get multiple decision variables, namely X 010 、X 001 、X 052 、X 033 、X 044 、X 025 、X 120 、X 111 、X 102 、X 153 、X 144 、X 135、 X 200 、X 251 、X 242 、X 223 、X 214 、X 235 .

[0143] Furthermore, if the objective function is expression (1), then based on expression (1), we can determine:

[0144] .

[0145] If the objective function is expression (2), then based on expression (1), determine:

[0146] .

[0147] Furthermore, based on constraints 1 to 4, the values ​​of each state variable and decision variable are determined when the target value of the objective function is minimized.

[0148] For example, based on constraint 1, for stripe D0 there exists X 010 +X 001 +X 052 +X 033 +X 044 +X 025 =1; for strip D1 there is X 120 +X 111 +X 102 +X 153 +X 144 +X 135 =1; for strip D2 there is X 200 +X 251 +X 242 +X 223 +X 214 +X 235=1.

[0149] Based on constraint 2, refer to Table 1, for channel c0, X 010 +X 120 +X 200 = C 010 +C 120 +C 200 For channel c1, X 001 +X 111 +X 251 = C 001 +C 111 +C 251 For channel c2, X 052 +X 102 +X 242 = C 052 +C 102 +C 241 For channel 3, X 033 +X 153 +X 223 = C 033 +C 153 +C 223 For channel c4, X 044 +X 144 +X 214 = C 044 +C 144 +C 214 For channel c5, X 025 +X 135 +X 235 = C 025 +C 135 +C 235 .

[0150] Based on constraint 3, the target user data is D01, the first target check bit data is P0, based on Table 1, i is 0, j is 2, there exists .

[0151] in,

[0152] .

[0153] Based on constraint 4, we have:

[0154] .

[0155] in,

[0156] .

[0157] Based on the above method, the value of each state variable and decision variable can be determined, and further, the and The value of , and then based on the expression, determine the exchange result .

[0158] In summary, the present application optimizes the physical storage locations of user data and check bit data to achieve a balanced I / O workload of all channels in the solid-state drive. In addition, the present application constructs an evaluation model to analyze and measure the wear of storage units and the balance of I / O workloads. In order to improve load balancing, the storage locations of user data and check bit data in the same stripe are exchanged. The present application can solve the problem of unbalanced I / O workload in RAID-5 solid-state drives. By reallocating the physical storage locations of data, the I / O workload of the entire solid-state drive can be more evenly distributed. In addition, the present application solves the performance problem caused by excessive load on channels carrying too much hot check bit data, maximizes the use of the high parallel processing capabilities of the solid-state drive, and thus improves the performance of the solid-state drive.

[0159] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0160] Figure 8 This is a schematic diagram of the structure of the data processing device provided in the embodiment of the present application. Figure 8 As shown, an embodiment of the present application further provides a data processing device, which may include: a first determination module 81, a second determination module 82, a third determination module 83 and an exchange module 84, wherein:

[0161] A first determining module 81 is configured to, when a target operation is detected, determine target user data in a target stripe to be operated on by the target operation, where the target stripe is a stripe among multiple stripes, and the target user data is one of multiple user data included in the target stripe;

[0162] A second determining module 82 is configured to determine a first performance quality of a first target storage unit where the target user data is located;

[0163] A third determining module 83 is configured to determine a second performance quality of a second target storage unit where the first target parity bit data included in the target stripe is located;

[0164] The exchange module 84 is configured to exchange the storage locations of the target user data and the first target check bit data when the first performance quality is greater than a first quality threshold and the second performance quality is less than a second quality threshold.

[0165] Optionally, the target operation is a write operation, and the apparatus further includes:

[0166] An acquisition module (not shown in the figure), configured to acquire target write data corresponding to target user data;

[0167] An update module (not shown in the figure) is used to update the first target parity bit data according to the target write data and other user data in the target stripe to obtain the second target parity bit data;

[0168] The exchange module 84 is specifically configured to store the second target check bit data in the first target storage unit, and store the target write data in the second target storage unit.

[0169] Optionally, the target operation is a recycling operation, the target user data is valid data, and the exchange module 84 is specifically used to determine whether the target user data is valid data;

[0170] If so, storing the first target check bit data in the first target storage unit;

[0171] The target user data is stored in the second target storage unit.

[0172] Optionally, the exchange module 84 is specifically used to evaluate the exchange result using a preset evaluation model when the first performance quality is greater than the first quality threshold and the second performance quality is less than the second quality threshold, and the exchange result is used to indicate whether to exchange the storage locations of the target user data and the first target check bit data; when the exchange result indicates an exchange, the storage locations of the target user data and the first target check bit data are exchanged.

[0173] Optionally, the evaluation model includes a first module and a second module, and the device further includes a construction module (not shown in the figure) for constructing the evaluation model in the following manner:

[0174] Constructing a first module, the first module is used to determine a plurality of state variables and a plurality of decision variables based on the objective function, the plurality of state variables and the plurality of decision variables having a one-to-one correspondence, the plurality of state variables and the plurality of decision variables being used to minimize a target value of the determined objective function, each state variable representing a state of a page of data of a stripe in a corresponding channel, and each decision variable representing a swap possibility of a page of data of a stripe in a corresponding channel;

[0175] A second module is constructed, and the second module is used to determine an exchange result based on the state variable corresponding to the target user data and the decision variable corresponding to the target user data.

[0176] Optionally, the objective value of the objective function is the sum of multiple first difference values, and each first difference value in the multiple first difference values ​​is the absolute value of the difference between one of the state variables and the corresponding decision variable.

[0177] Optionally, the objective value of the objective function is the sum of multiple first products, and each first product in the multiple first products is the product of one of the state variables and the corresponding decision variable.

[0178] Optionally, the objective function includes at least one of the following constraints:

[0179] The sum of the decision variables corresponding to different page data belonging to different channels in the same stripe is 1;

[0180] The sum of the decision variables corresponding to different pages of data in the same channel is equal to the sum of the state variables;

[0181] The wear difference of the storage unit to which the data to be exchanged belongs is less than or equal to the wear threshold;

[0182] The load difference of the channels to which the data to be exchanged belongs is less than or equal to the load threshold.

[0183] Optionally, when the exchange module 84 uses a preset evaluation model to evaluate the exchange result, it is specifically configured to:

[0184] Get the total number of writes and reads for each page of data in multiple stripes;

[0185] Obtain a mapping relationship between each page data in the multiple stripes and the multiple channels, where the mapping relationship is used to indicate the channel to which each page data in each stripe belongs;

[0186] Obtaining a first channel to which target user data belongs and a second channel to which first target check bit data belongs;

[0187] The total number of writes, the total number of reads, the mapping relationship, and the first channel and the second channel are input into the evaluation model for evaluation to obtain the exchange result.

[0188] Optionally, the second determining module 82 is specifically configured to:

[0189] determining a first wear level of a first target storage unit;

[0190] determining a first load level of a first target channel corresponding to a first target storage unit;

[0191] A first performance quality is determined based on the first degree of wear and / or the first degree of load, the first degree of wear being negatively correlated to the first performance quality, and the first degree of load being negatively correlated to the first performance quality.

[0192] Optionally, the third determining module 83 is specifically configured to:

[0193] determining a second wear level of a second target storage unit;

[0194] determining a second load level of a second target channel corresponding to the second target storage unit;

[0195] A second performance quality is determined based on the second degree of wear and / or the second degree of load, wherein the second degree of wear is negatively correlated with the second performance quality, and the second degree of load is negatively correlated with the second performance quality.

[0196] Optionally, the target operation is a write operation, and the apparatus further includes:

[0197] A storage module (not shown in the figure) is used to store the target write data corresponding to the target user data in the first target storage unit and store the second target check bit data in the second target storage unit when the exchange result indicates that no exchange is to be performed, where the second target check bit data is obtained after updating based on the first target check bit data.

[0198] It should be noted that the data processing device shown in the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principles and beneficial effects are similar, which will not be repeated here.

[0199] Figure 9 This is a schematic diagram of the structure of the electronic device provided in this application. Figure 9 As shown, the electronic device 90 provided in this embodiment includes: at least one processor 91 and a memory 92. Optionally, the electronic device 90 further includes a communication component 93. The processor 91, the memory 92 and the communication component 93 are connected via a bus.

[0200] During the specific implementation process, at least one processor 91 executes the computer execution instructions stored in the memory 92, so that the at least one processor 91 executes the above-mentioned data processing method embodiment.

[0201] The specific implementation process of the processor 91 can be found in the above-mentioned method embodiment. Its implementation principle and technical effects are similar and will not be repeated here in this embodiment.

[0202] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in the application may be directly executed by a hardware processor or by a combination of hardware and software modules within the processor.

[0203] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (NVM), exemplarily at least one disk storage.

[0204] A bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. Buses can be categorized as address buses, data buses, and control buses. For ease of illustration, the buses in the drawings of this application are not limited to just one bus or just one type of bus.

[0205] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above-mentioned data processing method embodiments when run.

[0206] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0207] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above data processing method embodiments are implemented.

[0208] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned data processing method embodiments are implemented.

[0209] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0210] The above is a detailed introduction to a data processing method provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core ideas of the present application. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, several improvements and modifications may be made to the present application, and such improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A data processing method, characterized in that: Applied to a solid-state drive, the solid-state drive stores multiple stripes, each of the multiple stripes includes multiple pages of data, and the multiple pages of data include: multiple user data and check bit data, the method includes: In a case where a target operation is detected, determining target user data in a target stripe to be operated by the target operation, the target stripe being a stripe among the plurality of stripes, and the target user data being one of the plurality of user data included in the target stripe; Determining a first performance quality of a first target storage unit where the target user data is located; Determine a second performance quality of a second target storage unit where the first target parity bit data included in the target stripe is located; When the first performance quality is greater than a first quality threshold and the second performance quality is less than a second quality threshold, the storage locations of the target user data and the first target check bit data are exchanged.

2. The data processing method according to claim 1, wherein: The target operation is a write operation, and the method further includes: Obtaining target write data corresponding to the target user data; updating the first target parity bit data according to the target write data and other user data in the target stripe to obtain second target parity bit data; The exchanging the storage locations of the target user data and the first target check bit data includes: The second target parity bit data is stored in the first target storage unit, and the target write data is stored in the second target storage unit.

3. The data processing method according to claim 1, wherein: The target operation is a recycling operation, the target user data is valid data, and exchanging the storage locations of the target user data and the first target check bit data includes: Determining whether the target user data is valid data; If so, storing the first target check bit data in the first target storage unit; The target user data is stored in the second target storage unit.

4. The data processing method according to any one of claims 1 to 3, characterized in that: The step of swapping the storage locations of the target user data and the first target check bit data when the first performance quality is greater than a first quality threshold and the second performance quality is less than a second quality threshold includes: When the first performance quality is greater than a first quality threshold and the second performance quality is less than a second quality threshold, evaluating an exchange result using a preset evaluation model, the exchange result being used to indicate whether to exchange storage locations of the target user data and the first target check bit data; When the exchange result indicates to perform an exchange, the storage locations of the target user data and the first target check digit data are exchanged.

5. The data processing method according to claim 4, characterized in that: The evaluation model includes a first module and a second module, and is constructed in the following manner: Constructing a first module, the first module being configured to determine a plurality of state variables and a plurality of decision variables based on an objective function, the plurality of state variables and the plurality of decision variables being in one-to-one correspondence, the plurality of state variables and the plurality of decision variables being configured to minimize a target value of the determined objective function, each state variable representing a state of a page of data of a stripe in a corresponding channel, and each decision variable representing a swap probability of a page of data of a stripe in a corresponding channel; A second module is constructed, where the second module is used to determine the exchange result based on the state variable corresponding to the target user data and the decision variable corresponding to the target user data.

6. The data processing method according to claim 5, characterized in that: The objective value of the objective function is the sum of a plurality of first difference values, each of which is the absolute value of a difference between one of the state variables and the corresponding decision variable.

7. The data processing method according to claim 5, characterized in that: The objective value of the objective function is a sum of a plurality of first products, each of which is a product of one of the state variables and a corresponding decision variable.

8. The data processing method according to claim 5, characterized in that: The objective function includes at least one of the following constraints: The sum of the decision variables corresponding to different page data belonging to different channels in the same stripe is 1; The sum of the decision variables corresponding to different pages of data in the same channel is equal to the sum of the state variables; The wear difference of the storage unit to which the data to be exchanged belongs is less than or equal to the wear threshold; The load difference of the channels to which the data to be exchanged belongs is less than or equal to the load threshold.

9. The data processing method according to claim 8, characterized in that: The use of a preset evaluation model to evaluate the exchange result includes: Obtaining a total number of writes and a total number of reads for each page of data in the plurality of stripes; Obtaining a mapping relationship between each page data in the plurality of stripes and a plurality of channels, wherein the mapping relationship is used to indicate the channel to which each page data in each stripe belongs; Acquire a first channel to which the target user data belongs and a second channel to which the first target check bit data belongs; The total number of write times, the total number of read times, the mapping relationship, the first channel, and the second channel are input into the evaluation model for evaluation to obtain the exchange result.

10. The data processing method according to any one of claims 1 to 3, characterized in that: The determining a first performance quality of the first target storage unit where the target user data is located includes: determining a first wear level of the first target storage unit; determining a first load level of a first target channel corresponding to the first target storage unit; The first performance quality is determined according to the first wear degree and / or the first load degree, wherein the first wear degree is negatively correlated with the first performance quality, and the first load degree is negatively correlated with the first performance quality.

11. The data processing method according to any one of claims 1 to 3, characterized in that: The determining the second performance quality of the second target storage unit where the first target parity bit data included in the target stripe is located includes: determining a second wear level of the second target storage unit; determining a second load level of a second target channel corresponding to the second target storage unit; The second performance quality is determined according to the second wear degree and / or the second load degree, the second wear degree is negatively correlated with the second performance quality, and the second load degree is negatively correlated with the second performance quality.

12. The data processing method according to claim 4, characterized in that: The target operation is a write operation, and the method further includes: When the exchange result indicates that no exchange is to be performed, the target write data corresponding to the target user data is stored in the first target storage unit, and the second target check bit data is stored in the second target storage unit, where the second target check bit data is obtained after updating based on the first target check bit data.

13. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the data processing method according to any one of claims 1 to 12 when executing the computer program.

14. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the data processing method according to any one of claims 1 to 12 when executed by a processor.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the data processing method according to any one of claims 1 to 12 are implemented.

Images