Vector interleaving unit, vector processor, high performance processor and device

Abstract

The application provides a vector interleaving unit, a vector processor, a high-performance processor and a device. The vector interleaving unit comprises a decoder of the vector interleaving unit, a plurality of execution modules and a selector. The decoder of the vector interleaving unit is used for decoding an instruction to obtain an execution module identifier. The instruction is sent to an execution module corresponding to the execution module identifier. The execution module is used for executing the instruction based on the execution module identifier. The selector is used for selecting an execution result of the execution module and outputting the selected execution result. The vector interleaving unit provided by the application is no longer limited by a register reference stack, and the instruction execution efficiency can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the computer technical field, and in particular to a vector interleaving unit, a vector processor, a high-performance processor and a device. BACKGROUND

[0002] The processing flow of operation instructions is roughly divided into: fetching, decoding, executing, accessing memory, and writing back.

[0003] Due to the limitation of the register reference stack, currently only 32 bits or 64 bits can be processed at a time during instruction fetching and decoding, which makes the existing instruction execution slow. SUMMARY

[0004] In order to solve one of the above technical defects, the present application provides a vector interleaving unit, a vector processor, a high-performance processor and a device.

[0005] The first aspect of the present application provides a vector interleaving unit, comprising: a decoder of the vector interleaving unit, a plurality of execution modules, and a selector.

[0006] The decoder of the vector interleaving unit is configured to decode an instruction to obtain an execution module identifier, and send the instruction to an execution module corresponding to the execution module identifier.

[0007] The execution module is configured to execute the instruction based on the execution module identifier.

[0008] The selector is configured to select an execution result of the execution module and output the selected execution result.

[0009] Optionally, the decoder of the vector interleaving unit is configured to generate a control signal based on the execution module identifier, and the control signal is used to control the instruction to be sent to the execution module corresponding to the execution module identifier.

[0010] Optionally, the decoder of the vector interleaving unit is configured to send the instruction to a register of the execution module corresponding to the execution module identifier.

[0011] The execution module is configured to read the instruction from the register of the execution module corresponding thereto and execute the instruction.

[0012] Optionally, when the decoder of the vector interleaving unit parses a self-write operation instruction, a bypass is generated.

[0013] The read execution module identifier in the self-write operation instruction is the same as the write execution module identifier.

[0014] The second aspect of the present application provides a vector processor, comprising: a vector program control unit and a vector interleaving unit.

[0015] The vector program control unit is configured to determine whether to execute the instruction after fetching the instruction, and transmit the instruction to the vector interleaving unit based on a determination result.

[0016] The vector interleaving unit comprises a decoder of the vector interleaving unit, a plurality of execution modules, and a selector.

[0017] The decoder of the vector interleaving unit is configured to decode the instruction generated by the vector program control unit to obtain an execution module identifier, and transmit the instruction to an execution module corresponding to the execution module identifier.

[0018] The execution module is configured to execute the instruction based on the execution module identifier.

[0019] The selector is configured to select an execution result of the execution module and output the selected execution result.

[0020] Optionally, the decoder of the vector interleaving unit is configured to generate a control signal based on the execution module identifier, and the control signal is used to control the instruction to be transmitted to the execution module corresponding to the execution module identifier.

[0021] Optionally, the vector processor further comprises a register corresponding to the execution module.

[0022] The decoder of the vector interleaving unit is configured to transmit the instruction to the register of the execution module corresponding to the execution module identifier.

[0023] The execution module is configured to read the instruction from the register of the execution module corresponding to the execution module and execute the instruction.

[0024] Optionally, the decoder of the vector interleaving unit generates a bypass when the self-write operation instruction is parsed.

[0025] In the self-write operation instruction, the read execution module identifier is the same as the write execution module identifier.

[0026] The third aspect of the application provides a high-performance processor, which comprises the vector processor and the scalar processor according to the second aspect.

[0027] The vector program control unit is further configured to receive a start command sent by the scalar processor, start the vector processor, and return an indication signal of whether the vector processor ends to the scalar processor.

[0028] A read first-in-first-out (FIFO) unit and a write FIFO unit are arranged between the vector processor and the scalar processor.

[0029] The vector program control unit and the scalar processor perform read operation on the read FIFO unit and write operation on the write FIFO unit.

[0030] In a fourth aspect, the present application provides an electronic device, comprising: the high-performance processor of the third aspect; or comprising one or more processor clusters, wherein each processor cluster comprises a plurality of high-performance processors of the third aspect.

[0031] The present application provides a vector interleaving unit, a vector processor, a high-performance processor and an electronic device. The vector interleaving unit comprises: a decoder of the vector interleaving unit, a plurality of execution modules, and a selector. The decoder of the vector interleaving unit is configured to decode an instruction to obtain an execution module identifier, and send the instruction to an execution module corresponding to the execution module identifier. The execution module is configured to execute the instruction based on the execution module identifier. The selector is configured to select an execution result of the execution module and output the selected execution result. The vector interleaving unit provided by the present application is no longer limited by the register reference stack, and the instruction execution efficiency can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0032] The accompanying drawings, which are included to provide a further understanding of the present application and constitute a part of this application, illustrate embodiments of the present application and together with the description serve to explain the present application. In the drawings:

[0033] Figure 1 A structure schematic diagram of a vector interleaving unit provided by an embodiment of the present application;

[0034] Figure 2 A processing schematic diagram of a vector interleaving unit provided by an embodiment of the present application;

[0035] Figure 3 An interface schematic diagram of a vector interleaving unit provided by an embodiment of the present application;

[0036] Figure 4 A structure schematic diagram of a vector processor provided by an embodiment of the present application;

[0037] Figure 5 A structure schematic diagram of another vector processor provided by an embodiment of the present application;

[0038] Figure 6 A structure schematic diagram of a high-performance processor provided by an embodiment of the present application;

[0039] Figure 7 A structure schematic diagram of a scalar processor provided by an embodiment of the present application;

[0040] Figure 8 A structure schematic diagram of a synchronization unit of a scalar processor provided by an embodiment of the present application. DETAILED DESCRIPTION

[0041] In order to make the technical solutions and advantages of the embodiments of the present application clearer, the exemplary embodiments of the present application are further described in detail below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0042] In the process of implementing the present application, the inventors found that the processing flow of operation instructions is roughly divided into: fetching, decoding, executing, accessing, and writing back. Due to the limitation of the register reference stack, currently only 32 bits or 64 bits can be processed at a time during fetching and decoding, which makes the existing instruction execution slow.

[0043] To solve the above problems, the present application provides a vector interleaving unit, a vector processor, a high-performance processor, and a device. The vector interleaving unit includes a decoder of the vector interleaving unit, a plurality of execution modules, and a selector. The decoder of the vector interleaving unit is configured to decode an instruction to obtain an execution module identifier. The instruction is sent to an execution module corresponding to the execution module identifier. The execution module is configured to execute the instruction based on the execution module identifier. The selector is configured to select an execution result of the execution module and output the selected execution result. The vector interleaving unit provided by the present application is no longer limited by the limitation of the register reference stack, and the instruction execution efficiency can be improved.

[0044] Referring to Figure 1 The present embodiment provides a vector interleaving unit, which includes a decoder of the vector interleaving unit (SHU Decoder), a plurality of execution modules (Execution Unit), and a selector (Result Mux).

[0045] 1. Decoder of vector interleaving unit (SHU Decoder)

[0046] The decoder of the vector interleaving unit (SHU Decoder) is configured to decode an instruction to obtain an execution module identifier (regID). The instruction is sent to an execution module (Execution Unit) corresponding to the execution module identifier (regID).

[0047] Specifically, the decoder of the vector interleaving unit (SHU Decoder) is configured to generate a control signal based on the execution module identifier (regID). The control signal is used to control the instruction to be sent to the execution module (Execution Unit) corresponding to the execution module identifier (regID).

[0048] For example, the SHU Decoder sends the instruction to the register of the execution unit corresponding to the regID.

[0049] The SHU Decoder decodes the instruction and gets the regID.

[0050] The decoder generates a control signal based on the regID to control the instruction to be sent to the register of the execution unit corresponding to the regID.

[0051] The SHU Vector Register file is a vector register composed of multiple registers of the execution unit.

[0052] When the instruction is sent to the register of the execution unit corresponding to the regID, the execution unit regID reads the instruction from the register and executes the instruction.

[0053] 2、Execution Unit

[0054] The execution unit executes the instruction based on the regID.

[0055] Specifically, the execution unit reads the instruction from the register corresponding to the execution unit and executes the instruction.

[0056] Multiple execution units can execute in parallel.

[0057] 3、Result Mux

[0058] The Result Mux selects the execution result of the execution unit and outputs the selected execution result.

[0059] The Result Mux selects one execution result to output each time.

[0060] In addition, when the SHU Decoder parses the self-write operation instruction, a bypass is generated.

[0061] Wherein, the read execution module identifier (regID) is same as the write execution module identifier (regID) in the self-write operation instruction.

[0062] This kind of processing of the self-write operation provides a calculation path for the vector interleaving unit, and a bypass is generated when the vector interleaving unit resolves to a read regID=write regID.

[0063] If there are multiple vector interleaving units, the write operation of each vector interleaving unit will occupy source0.

[0064] The vector interleaving unit provided in the embodiment is no longer limited by the register reference stack, and can process 512 bits at a time, so that the calculation speed is improved.

[0065] Figure 2 A processing schematic diagram of the vector interleaving unit in a specific application is shown. After the vector program control unit (MFetch) fetches an instruction from a customized SRAM, the instruction is decoded by the decoder (SHU Decoder) of the vector interleaving unit, Figure 2 A processing schematic diagram of three cycles is shown. Ex is a cycle identifier. If Ex0 is the 0th cycle, Ex1 is the 1st cycle, and Ex2 is the 2nd cycle. Figure 2 The SHU in the embodiment is the vector interleaving unit provided in the embodiment.

[0066] In addition, in the specific implementation, the vector interleaving unit can be a functional unit in the vector processor, and there can be multiple vector interleaving units in the vector processor.

[0067] Taking the vector processor with four vector interleaving units (SHU0, SHU1, SHU2, and SHU3) as an example, Figure 3 An interface of each vector interleaving unit is shown. T0-T32 are 32 vector registers of 512 bits. T0-T7 correspond to SHU0, T8-T15 correspond to SHU1, T16-T23 correspond to SHU2, and T24-T31 correspond to SHU3.

[0068] The embodiment provides a vector interleaving unit. The vector interleaving unit comprises a decoder of the vector interleaving unit, a plurality of execution modules, and a selector. The decoder of the vector interleaving unit is configured to decode an instruction to obtain an execution module identifier, and send the instruction to an execution module corresponding to the execution module identifier. The execution module is configured to execute the instruction based on the execution module identifier. The selector is configured to select an execution result of the execution module and output the selected execution result. The vector interleaving unit provided in the embodiment is no longer limited by the register reference stack, and the instruction execution efficiency can be improved.

[0069] Based on the same inventive concept of the vector interleave unit, the embodiment provides a vector processor, which comprises a vector program control unit (MFetch) and a vector interleave unit.

[0070] The vector interleave unit can be as shown in FIG. 1 or 2. Figure 1

[0071] The vector program control unit is configured to, after fetching an instruction, judge whether to execute the instruction, and transmit the instruction to the vector interleave unit based on the judgment result.

[0072] The vector interleave unit comprises a decoder of the vector interleave unit, a plurality of execution modules, and a selector.

[0073] The decoder of the vector interleave unit is configured to decode the instruction from the vector program control unit to obtain an execution module identifier, and transmit the instruction to the execution module corresponding to the execution module identifier.

[0074] The execution module is configured to execute the instruction based on the execution module identifier.

[0075] The selector is configured to select an execution result of the execution module, and output the selected execution result.

[0076] In addition, the decoder of the vector interleave unit is configured to generate a control signal based on the execution module identifier, and the control signal is used to control the instruction to be transmitted to the execution module corresponding to the execution module identifier.

[0077] In addition, the vector processor further comprises a register corresponding to the execution module.

[0078] The decoder of the vector interleave unit is configured to transmit the instruction to the register of the execution module corresponding to the execution module identifier.

[0079] The execution module is configured to read the instruction from the register of the execution module corresponding thereto, and execute the instruction.

[0080] In addition, the decoder of the vector interleave unit generates a bypass when the instruction of the self-write operation is parsed.

[0081] The read execution module identifier in the self-write operation instruction is the same as the write execution module identifier.

[0082] In the specific implementation, the vector interleave unit can be used as a functional unit. For example, Figure 4 The vector processor shown in FIG. 1 or 2 can further comprise other functional units, a register file stack, and scalar register registers in addition to the vector program control unit and the vector interleave unit.

[0083] ​In addition, the vector processor further comprises: private vector registers of the vector interleave unit, private vector registers of the vector access unit.

[0084] 1. A vector program control unit

[0085] The vector program control unit is configured to fetch instructions and issue instructions.

[0086] That is, the vector program control unit is configured to fetch instructions, determine whether to execute the instructions, and issue the instructions to the functional units based on the determination result.

[0087] The vector program control unit is further configured to control the jump of the instructions.

[0088] The vector program control unit has scalar computing capability.

[0089] The vector program control unit interacts with scalar registers.

[0090] In a specific implementation, the vector program control unit is a fetch and issue unit, configured to fetch instructions from a cache according to a PC value, issue the instructions to the functional units according to a wait value (configured by a wait instruction) after determining whether to execute the instructions, control the jump of the instructions, and have partial scalar computing capability.

[0091] In addition, the vector program control unit is further configured to receive a start command sent by another operation processor, and start the vector processor. The vector program control unit returns an indication signal to the other operation processor to indicate whether the vector processor ends.

[0092] Taking the other operation processor as a scalar processor as an example, the vector program control unit receives a start command sent by a synchronization unit of the scalar processor, starts the vector processor to execute, and returns an indication signal to the synchronization unit to indicate whether the vector processor ends.

[0093] 2. A functional unit

[0094] The functional unit is configured to perform functional processing according to instructions.

[0095] For example, the functional unit receives instructions from the vector program control unit, processes data according to the instructions, and outputs the processing result to an address specified in the instructions.

[0096] The functional unit comprises one or more vector operation units, one or more vector interleave units, and one or more vector access units.

[0097] 1) A vector operation unit

[0098] Any vector operation unit is configured to perform vector operation according to instructions.

[0099] Any vector operation unit, comprising: a floating point multiply-add operation subunit, a floating point multiply-accumulate operation subunit, a floating point arithmetic operation subunit, a tensor multiplication subunit and an intermediate result register.

[0100] The floating point multiply-add operation subunit and the floating point arithmetic operation subunit share one emission slot. Therefore, at most 8 instructions of the vector operation unit are emitted per cycle.

[0101] The floating point multiply-accumulate operation subunit and the tensor multiplication subunit share one emission slot.

[0102] The floating point multiply-add operation subunit is executed by a functional unit for executing floating point multiply-add operation subunit related instructions. For example, the floating point multiply-add operation subunit related instructions are instructions for performing integer and floating point vector multiply-accumulate, multiplication, addition, tensor computation, etc.

[0103] 1 vector operation unit has independent intermediate result registers.

[0104] 1 floating point multiply-add operation subunit, 1 floating point multiply-accumulate operation subunit, 1 tensor multiplication subunit and 1 floating point arithmetic operation subunit share intermediate result registers.

[0105] (1) The floating point multiply-add operation subunit and the floating point multiply-accumulate operation subunit can perform integer and floating point vector multiplication, multiply-accumulate, etc. Supported types include but are not limited to int32, fp32, fp64.

[0106] (2) The floating point arithmetic operation subunit can perform integer and floating point vector arithmetic operations, such as comparison, addition, subtraction, bit operation, etc. Supported types include but are not limited to int8, uint8, int16, uint16, int32, uint32, bool, fp16, bf16, fp32, tf32, fp64.

[0107] (3) The tensor multiplication subunit can perform tensor multiplication, multiply-accumulate, etc. Supported types include but are not limited to int8, bf16, fp16, tf32.

[0108] 2) Vector interleaving unit

[0109] The vector interleaving unit can be as shown in FIG. Figure 1 or 2.

[0110] The vector interleaving unit, comprising: a decoder of the vector interleaving unit, a plurality of execution modules, a selector.

[0111] The decoder of the vector interleaving unit is used for decoding instructions generated by the vector program control unit to obtain execution module identifiers. The instructions are emitted to the execution modules corresponding to the execution module identifiers.

[0112] An execution module is configured to execute the instruction based on the execution module identifier.

[0113] A selector is configured to select an execution result of the execution module and output the selected execution result.

[0114] In addition, a decoder of the vector interleaving unit is configured to generate a control signal based on the execution module identifier, and the control signal is configured to control the instruction to be sent to the execution module corresponding to the execution module identifier.

[0115] In addition, the vector processor further comprises a register corresponding to the execution module.

[0116] The decoder of the vector interleaving unit is configured to send the instruction to the register of the execution module corresponding to the execution module identifier.

[0117] The execution module is configured to read the instruction from the register of the execution module corresponding to the execution module and execute the instruction.

[0118] In addition, the decoder of the vector interleaving unit generates a bypass when the self-write operation instruction is parsed.

[0119] The read execution module identifier in the self-write operation instruction is the same as the write execution module identifier.

[0120] 3) Vector access unit

[0121] Any vector access unit is configured to perform multi-mode memory access, address calculation, and scalar calculation according to an instruction.

[0122] The vector access unit is a memory access unit in the vector processor, and is mainly responsible for reading / writing instructions and various scalar calculations.

[0123] The reading / writing instructions support multiple memory access modes, such as row mode, column mode, discrete mode, extended mode, and cumulative mode.

[0124] Meanwhile, multiple parameter configurations are supported, and the maximum reading / writing instruction data bit width can reach 1024 bits. The address calculation, loading / storage, and other instructions are executed.

[0125] All vector access units share a set of private vector registers, so the private vector registers of the vector access unit are shared by multiple vector access units.

[0126] 3, Register file stack

[0127] The register file stack is configured to return data after reading and writing requests. The data is rearranged and returned. The register file stack interacts with the functional unit for reading and writing. The configuration registers of the vector program control unit are configured by the data in the register file stack.

[0128] The register file stack is a general vector register stack, which is a main storage unit in the vector processor, responsible for receiving read and write requests and returning data, and can rearrange the data before returning to the request module in some functions.

[0129] The register file stack interacts with the functional units (such as floating-point multiply-add operation subunits, floating-point arithmetic operation subunits, floating-point multiply-accumulate operation subunits, and tensor multiplication subunits) in the vector processor for reading and writing, and supports configuring the instruction fetch unit configuration register using the data in the register file stack.

[0130] The register file stack is also used to write data to other arithmetic processors. It receives state information from other arithmetic processors to query whether the data is written.

[0131] Taking a scalar processor as an example, the synchronization unit of the scalar processor can write data to the register file stack, and the register file stack can also receive state information from the synchronization unit of the scalar processor to query whether the data is written.

[0132] The depth of the register file stack is configurable.

[0133] Figure 5 A schematic diagram of a vector processor is shown, in which the functional units include four vector operation subunits, four vector interleaving subunits, and four vector access subunits.

[0134] Figure 5 The vector interleaving subunit (SHU) in the vector processor is as shown in FIG. 1 or 2, which includes a decoder of the vector interleaving subunit, a plurality of execution modules, and a selector. Figure 1

[0135] The decoder of the vector interleaving subunit is configured to decode the instruction to obtain an execution module identifier, and send the instruction to the execution module corresponding to the execution module identifier.

[0136] The execution module is configured to execute the instruction based on the execution module identifier.

[0137] The selector is configured to select an execution result of the execution module, and output the selected execution result.

[0138] Optionally, the decoder of the vector interleaving subunit is configured to generate a control signal based on the execution module identifier, and the control signal is used to control the instruction to be sent to the execution module corresponding to the execution module identifier.

[0139] Optionally, the decoder of the vector interleaving subunit is configured to send the instruction to a register of the execution module corresponding to the execution module identifier.

[0140] The execution module is configured to read the instruction from the register of the execution module corresponding to the execution module identifier, and execute the instruction. ​

[0141] Optionally, the decoder of the vector interleaving unit generates a bypass when resolving the self-write operation instruction.

[0142] The read execution module identifier in the self-write operation instruction is the same as the write execution module identifier.

[0143] The vector processor supports a VLIW (Very Long Instruction Word) instruction set, each VLIW can be composed of one or more instructions, and each instruction corresponds to a functional unit.

[0144] In addition, the vector processor and the other operation processor are provided with a read FIFO unit and a write FIFO unit.

[0145] The vector program control unit and the other operation processor perform read operation on the read FIFO unit and write operation on the write FIFO unit.

[0146] The other operation processor performs read operation or write operation on the vector register.

[0147] Taking the other operation processor as a scalar processor as an example, the scalar processor and the vector processor are provided with a read FIFO and a write FIFO unit for transmitting data, and the scalar processor and the vector program control unit can perform read operation or write operation on the read-write FIFO.

[0148] Meanwhile, the synchronization unit of the scalar processor can perform read operation or write operation on the scalar register of the vector processor.

[0149] The embodiment provides a vector processor, and the vector interleaving unit in the vector processor comprises a vector interleaving unit decoder, a plurality of execution modules and a selector.

[0150] Based on the same inventive concept of the vector interleaving unit, the embodiment provides a high-performance processor, and the high-performance processor comprises a scalar processor and a vector processor.

[0151] The connection relationship of the scalar processor and the vector processor can be as shown in the figure. Figure 6

[0152] ​The scalar processor and the vector processor share the memory. The vector processor can only access the memory and can only be executed by the scalar processor.

[0153] A connection is established between the scalar processor and the vector processor. The connection is established between the scalar processor and the vector processor through a dedicated instruction channel.

[0154] In addition, the high-performance processor can further include two registers, one register corresponding to the scalar processor and the other register corresponding to the vector processor. The vector processor can read and write its corresponding register, and the scalar processor can read and write the register corresponding to the vector processor in addition to reading and writing its corresponding register.

[0155] The scalar processor can read and write the register of the vector processor.

[0156] The scalar processor is connected to the global memory.

[0157] (1) Scalar processor

[0158] Referring to Figure 7 The scalar processor can include a fetch unit, a register renaming unit, an operation reservation stack unit, a memory reservation stack unit, a scalar operation unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit, a register file unit, and a special vector register file unit.

[0159] In addition, the scalar processor can further include one or more other units, such as one or more functional modules, one or more instruction caches, one or more data stores, one or more special vector registers, one or more status flag registers, etc.

[0160] 1. Fetch unit

[0161] The fetch unit is used for fetching instructions and dispatching instructions.

[0162] Specifically, the fetch unit is used to generate a fetch request address, output the fetch request address to the instruction cache for fetching, receive instructions from the instruction cache, and store them in the data store. Each cycle reads qualified instructions from the data store in sequence, decodes and checks the read instructions, and dispatches the checked instructions in sequence.

[0163] For example, the instruction fetch unit generates instruction fetch request addresses and outputs them to the instruction cache for instruction fetch, and receives instruction storage data from the instruction cache, sequentially finds one or more instructions from the qualified instructions for decoding and related checks every cycle, and sequentially dispatches the qualified instructions, with a maximum of one program control unit instruction, one synchronization unit instruction, and one or more scalar operation unit instructions and one or more memory access unit instructions every time.

[0164] 2. The register renaming unit

[0165] The register renaming unit is configured to receive the instructions dispatched by the instruction fetch unit and perform register renaming.

[0166] In particular, the register renaming unit is configured to receive the instructions dispatched by the instruction fetch unit and store them, perform special vector register renaming, perform instruction condition decoding, and generate a pipeline stall signal. The register renaming unit is also configured to receive data from one or more of the scalar operation unit, the memory access unit, the program control unit, the synchronization unit, the special vector register, the condition register, and the flag register and write them back. The register renaming unit is further configured to send the instructions to one or more of the operation reservation stack unit, the memory reservation stack unit, the program control unit, and the synchronization unit.

[0167] For example, the register renaming unit is configured to receive the instructions dispatched by the instruction fetch unit and perform register renaming, special vector register renaming, instruction condition decoding, and pipeline stall signal generation. The register renaming unit is also configured to receive data from the write-back registers of the execution units (e.g., the scalar operation unit, the memory access unit, the program control unit, and the synchronization unit), the special vector register, the condition register, and the status flag register and write them back to the corresponding registers.

[0168] The scalar processor supports out-of-order write-back, has high execution efficiency, and distributes the instructions to the operation reservation stack unit, the memory reservation stack unit, the program control unit, or the synchronization unit.

[0169] The register renaming unit has a bandwidth of 6 bits, and multiple (e.g., 4) input instructions can be active at the same time.

[0170] The condition register can be multiple and located in the register renaming unit.

[0171] The instructions of the scalar operation unit and the memory access unit support reading and writing operations of the condition register.

[0172] The instructions of the synchronization unit support reading operations of the condition register.

[0173] The jump and function call instructions of the program control unit support reading operations of the condition register.

[0174] When an instruction enters a condition register, if there is an unexecuted instruction in the condition register, the pipeline is blocked.

[0175] That is, the condition register is not renamed, and when a read-write correlation occurs, the dispatch block is triggered to wait. The condition register read-write rules are as follows:

[0176] • Read rule:

[0177] (1) All instructions of the scalar operation unit, the memory access unit, and the synchronization unit support conditional execution, and need to read the value of the condition register.

[0178] (2) The scalar operation unit also supports reading the condition register instruction operation.

[0179] (3) The jump and function call instructions of the program control unit support reading the condition register operation.

[0180] • Write rule:

[0181] (1) The scalar operation unit supports writing the condition register instruction.

[0182] (2) The scalar operation unit logic class instruction and comparison class instruction support the option of writing the condition register.

[0183] When the actual execution of the condition register writing instruction issued in the front is not yet executed, and an instruction reading or writing the same condition register enters, the pipeline is blocked, a conditional execution block signal is generated, and the front condition register is waited to be written.

[0184] In addition, the register renaming unit includes one or more physical registers and one or more logical registers.

[0185] Any physical register is one of the following: a vector physical register, a condition register, and a flag register.

[0186] Any logical register is one of the following: a read-only register and a vector logical register.

[0187] For example, the register renaming unit includes one or more physical registers, for example, a plurality of 512-bit special vector registers, a plurality of condition registers, and a state flag register.

[0188] Among them, the special vector register is renamed, the condition register is not renamed, and the state flag register is not renamed.

[0189] The number of logical registers is multiple, such as a plurality of logical registers being read-only registers and a plurality of vector logical registers.

[0190] In addition, the mapping relationship between the logical registers and the physical registers is maintained by a register mapping table. The mapping relationship between the vector logical registers and the vector physical registers is maintained by a special vector register mapping table.

[0191] 1) Register mapping table

[0192] Initially, the mapping physical registers of the table entries corresponding to all logical register indexes in the register mapping table are all 0. When an instruction is executed, or when an interrupt arrives, the mapping of the table entry corresponding to the allocated logical register index in the register mapping table is updated to the identifier of the relevant physical register.

[0193] For example, the register mapping table has a depth of 32 and a width of 6 bits, and stores the mapping relationship between all logical registers and all physical registers. Initially, the mapping of the register mapping table is invalid, and the mapping physical registers of all table entries are all 0. When a physical register is allocated to a logical register for use, the table entry corresponding to the logical register index in the register mapping table is changed to the ID of the physical register.

[0194] It should be noted that the register mapping table is updated only when an instruction is actually executed. If a conditional execution instruction is not executed, the register mapping table will not be updated. In addition, the register mapping table will not be updated when a jump arrives, but the interrupt return address must update the register mapping table when an interrupt arrives, to ensure that the interrupt can return normally.

[0195] 2) Special vector register mapping table

[0196] Initially, the mapping vector physical registers of the table entries corresponding to all vector logical register indexes in the special vector register mapping table are all 0. When an instruction is executed, the mapping of the table entry corresponding to the allocated vector logical register index in the special vector register mapping table is updated to the identifier of the relevant vector physical register.

[0197] For example, the special vector register mapping table has a depth of 4 and a width of 3 bits, and stores the mapping relationship between all vector logical registers and all vector physical registers. Initially, the mapping of the special vector register mapping table is invalid, and the mapping vector physical registers of all table entries are all 0. When a vector physical register is allocated to a vector logical register for use, the table entry corresponding to the vector logical register index in the special vector register mapping table is changed to the ID of the vector physical register.

[0198] It should be noted that the special vector register mapping table is updated only when the instruction is indeed executed, and if the conditional execution instruction is not executed, the special vector register mapping table is not updated, and in addition, the special vector register mapping table is not updated when a jump occurs.

[0199] 3. Operation reservation stack unit

[0200] The operation reservation stack unit is the issue queue of the scalar operation units.

[0201] The operation reservation stack unit receives instructions, dispatch and renaming information from the register renaming unit and pushes them into the queue. It pops the ready instructions to the scalar operation units for execution.

[0202] The operation reservation stack unit also decodes the incoming instructions and stores the instruction type information.

[0203] That is, the operation reservation stack unit is the issue queue of the scalar operation units. The operation reservation stack unit receives instructions and related dispatch and renaming information from the register renaming unit and pushes them into the queue, and it pops the ready instructions to the scalar operation units for execution. The operation reservation stack unit decodes the incoming instructions and stores the instruction type information.

[0204] In implementation, the depth of the operation reservation stack unit can be flexibly adjusted, for example, the depth of the operation reservation stack unit is 8. Multiple scalar operation units share one operation reservation stack unit.

[0205] The instruction issue and receive rules of the operation reservation stack unit are as follows:

[0206] (1) The output of the register renaming unit enters the operation reservation stack unit.

[0207] (2) When there is any free scalar operation unit, it takes instructions and operands from the operation reservation stack unit for execution.

[0208] (3) The principle of taking instructions from the operation reservation stack unit for execution is to take executable instructions that can be sent from the operation reservation stack unit in the order from front to back.

[0209] (4) Whether it can be sent is determined according to whether all source registers or special vector registers or condition registers and status flag registers are ready.

[0210] (5) If there are multiple instructions that can be sent, the oldest instruction is sent first according to the instruction order.

[0211] (6) If any scalar operation unit is blocked, it cannot receive new instructions.

[0212] (7) If the instruction sent to any scalar unit before is a divide instruction, then wait until the divide result is ready and the ready En signal is returned before sending a new divide instruction to the scalar unit.

[0213] 4. A memory reservation stack unit

[0214] The memory reservation stack unit is a launch queue for the memory access units.

[0215] The memory reservation stack unit receives instructions and register renaming information from the register renaming unit and pushes them into the queue.

[0216] The memory reservation stack unit also sends a read request to the register renaming unit when the instruction address register is ready and saves the read address operand.

[0217] The register renaming unit also calculates the address and decodes the address and saves the decode information when the instruction gets the address.

[0218] The register renaming unit also detects when the source register for any instruction is ready and the address decoding is complete and then launches it to the memory access unit for execution.

[0219] In a specific implementation, the depth of the memory reservation stack unit can be flexibly adjusted, such as being 16. Multiple memory access units share one memory reservation stack unit. The memory reservation stack unit is a launch queue for the memory access units. The memory reservation stack unit receives instructions and register renaming information from the register renaming unit and pushes them into the queue. When the instruction address register in the memory reservation stack unit is ready, the memory reservation stack unit sends a read request to the register renaming unit and saves the read address operand into the queue. When the instruction in the memory reservation stack unit gets the address, the memory reservation stack unit can calculate the address and decode the address and save the resulting decode information in the queue. When the source register for an instruction in the memory reservation stack unit is ready and the address decoding is complete, the instruction can be launched to the memory access unit for execution after a series of checks, such as address type checking, address comparison checking, and address forward checking.

[0220] The rules for the memory reservation stack unit to send and receive instructions are as follows:

[0221] (1) The output of the register renaming unit enters the memory reservation stack unit.

[0222] (2) When the source operand for calculating the address is ready, the memory access address is calculated and saved in the memory reservation stack unit.

[0223] (3) Address-Independent Instructions: Can be reordered, the reordering rules are: read instruction after read instruction, read instruction after write instruction, write instruction after read instruction can be reordered and sent, write instruction after write instruction needs to be guaranteed in sequence (can not be sent to different memory units at the same time), even if the write instruction after the address-independent write instruction also needs to be guaranteed in sequence.

[0224] (4) Address-Dependent Instructions: Read instruction after write instruction, write instruction after read instruction, write instruction after write instruction, read instruction after read instruction all need to be guaranteed in sequence.

[0225] (5) Address-independent but located in the same storage space as all instructions that have not been successfully sent (i.e., on the way to the destination, including at the memory unit level and at the memory unit output level) can be reordered and sent to the same memory unit, but cannot be sent to two or more memory units.

[0226] (6) Memory instructions located in the same storage space but address-independent can only be sent one at a time, and cannot be sent simultaneously by two or more memory units.

[0227] (7) Address-dependent judgment principle: Whether the address is related is that the address is not related if it is located in different storage spaces, and whether the address is related is determined according to the data granularity if it is located in the same storage space.

[0228] 5. Scalar Operation Unit

[0229] In specific implementation, the scalar operation unit can be one or more.

[0230] If the scalar processor includes two scalar operation units, they are scalar operation unit 0 and scalar operation unit 1.

[0231] The scalar operation unit is configured to receive the instruction and data sent by the operation reservation stack unit, perform operation on the data based on the instruction, and write the operation result back to the register renaming unit.

[0232] The scalar operation unit is the calculation unit of the scalar processor, and can perform various types of fixed-point and floating-point operations, such as addition and subtraction, multiplication, division, logical operation, comparison operation, and shifting. It receives the instruction and data sent by the operation reservation stack unit, performs operation, and writes the result to the register stack unit or special vector register stack unit of the register renaming unit.

[0233] The following exemplary provides several instruction examples, and in specific implementation, it is not limited to the following instructions, nor is it limited to whether all instructions are included.

[0234] The instructions of the execution stage of level one include: fixed-point addition and subtraction, logic class instructions, shift class instructions, fixed-point comparison class instructions, read-write Flag instructions, fixed-point maximum and minimum instructions, ABS instructions, bit reverse order instructions, selection instructions, special vector register distribution instructions, read special vector register instructions, Byte reverse order instructions, Merge instructions, immediate assignment instructions, FirstOne instructions, CRC instructions, floating-point classification instructions, floating-point partial domain extraction and Rounding instructions.

[0235] The instructions of the execution stage of level three include: fixed-point multiplication instructions, fixed-point conversion class instructions, bit screening instructions, Count instructions, floating-point addition and subtraction instructions.

[0236] The instructions supporting Bypass include: selection instructions, fixed-point addition and subtraction instructions, shift class instructions, immediate assignment instructions, ABS instructions, logic class instructions, comparison class instructions, maximum and minimum instructions.

[0237] The execution period of the division instruction is uncertain, and is related to the data of the divisor and the dividend. The instruction execution is completed to generate a DivEn instruction, indicating that the instruction execution is completed and the result is output to the register heap. During the execution of the division instruction, no new division instruction can be input, but other scalar calculation unit instructions can be input. The output port of the first stage pipeline is multiplexed when the output port of the first stage pipeline is not used by other scalar calculation unit instructions. The division outputs its result, and simultaneously outputs the DivEn identifier. The DivEn identifier is output to the operation reservation stack unit, indicating that the Div instruction can be continuously output to the current scalar operation unit.

[0238] 6. Memory access unit

[0239] In the specific implementation, the memory access unit can be one or more.

[0240] If the scalar processor includes two memory access units, they are memory access unit 0 and memory access unit 1.

[0241] The memory access unit is configured to receive the instruction and data and register information sent by the storage reservation stack unit, and read and write the data based on the instruction and the register information.

[0242] The memory access unit is a functional module that executes memory access-related instructions in a scalar processor. The memory access unit receives instructions and data, as well as register-related information, from the memory-reserved stack. It executes the instructions accordingly, interacts with other units for data reading and writing, and writes data back to the register renaming unit for read and write instructions. This includes register-level read and write instructions, including 8-bit, 16-bit, 32-bit, 64-bit, or other bit granularities, as well as vector-level read and write instructions. Vector granularities include 128-bit, 256-bit, 512-bit, or other bit granularities. Different instructions have different processing times.

[0243] In addition, the memory access unit is responsible for providing the number of instructions required by the FENCE, and the memory access unit interacts with the memory reservation stack unit to complete the data storage configuration.

[0244] 7. Program Control Unit

[0245] In practice, there is only one program control unit.

[0246] The program control unit receives instructions and data from the register renaming unit, processes the data based on the instructions, and outputs the processing results.

[0247] The program control unit is a functional module that executes instructions related to the execution order of the scalar processor's control program. The program control unit receives instructions and data from the register renaming unit, processes the data accordingly, and outputs the processing results to other modules of the scalar processor. Different instructions have different processing time cycles.

[0248] The program control unit is responsible for controlling the direction of program execution (such as stopping, interrupting, jumping, and function calling), involving the execution of related instructions and the reading and writing control of configuration information; the program control unit is responsible for the configuration and prefetching operation of the instruction cache, as well as the FENCE operation; the program control unit is responsible for the reading, writing and control of the counter, as well as the reading and writing of some other control information, etc.

[0249] 8. Synchronization Unit

[0250] In practice, there is only one synchronization unit.

[0251] The synchronization unit is used for synchronizing the scalar processor and the vector processor.

[0252] like Figure 8 As shown, the synchronization unit establishes communication connections with the pipeline control unit, register renaming unit, program control unit, and vector processor.

[0253] The instructions for the synchronization unit come from the register renaming unit, and the reading and writing of data in the synchronization unit are all done in interaction with the register renaming unit.

[0254] The synchronization unit is configured to receive the stall signal sent by the pipeline control unit, send an execution stage stall signal generated when communicating with the vector processor to the pipeline control unit, so as to generate an execution stall signal of the scalar processor.

[0255] The synchronization unit is configured to generate an instruction and transmit the instruction to the program control unit.

[0256] That is, the synchronization unit is a unit for synchronizing the scalar processor and the vector processor, which receives an instruction and data sent by the register renaming unit, reads data from the vector processor and writes back to the register file, reads data from the register file unit or the special vector register file unit and sends the data to the functional module of the vector processor, is responsible for starting and state querying of the vector processor, such as querying reading and writing of the read-write FIFO (First Input First Output) in the vector program control unit of the vector processor, configuration of the register file, reading or writing of the scalar register, state querying of the register file, reading of the FIFO depth, reading of the start vector processor instruction counter, and providing the program control unit with synchronization unit instruction information.

[0257] The synchronization unit interacts with the pipeline control unit, the register renaming unit and the program control unit inside the scalar processor, and interacts with the vector processor, the scalar processor and the vector processor transmission queue module. The synchronization unit instruction comes from the register renaming unit, and the reading and writing of data are interacted with the register renaming unit. The blocking signal from the pipeline control unit is received, and the execution stage blocking signal of the synchronization unit itself is generated when communicating with the vector processor, and is sent to the pipeline control unit, which is used to generate the ExeStall signal acting on the entire scalar processor. The synchronization unit generates an instruction to be executed in the next cycle, and transmits the instruction to the program control unit, which is used for the instruction of the counter of the program control unit. The synchronization unit interacts with the vector processor, including but not limited to: configuring the register file with special vector registers or registers, reading and writing the scalar register, querying the write state of the register file. The scalar processor interacts with the scalar processor and the vector processor transmission queue module, including but not limited to: starting the vector processor, querying the state of the vector processor, reading and writing the FIFO data in the instruction fetch unit of the vector processor, reading the FIFO depth, and reading the start vector processor instruction counter.

[0258] Therefore, in the specific implementation, the synchronization unit can have the following functions (it should be noted that the following functions are only examples, and there can be other functions, and the embodiments and subsequent embodiments do not limit the specific functions of the synchronization unit) :

[0259] Start vector processor function, for starting the vector processor to use, including immediate start and register start, like pipeline waiting until start success, or write back the result of start success or failure to the destination register.

[0260] Query vector processor execution status function, supporting optional item B.

[0261] Read-write FIFO function, the FIFO is in the instruction fetch unit of the vector processor, like FIFO bit width 32bit, read-write FIFO like waiting until success, or read-write FIFO success or failure result write back to the register.

[0262] Write register file stack function, including special vector register write or register write.

[0263] Read-write scalar register function, including immediate index or register index read-write.

[0264] Query register file stack write back status function, like waiting until all write register file stack ends, or return the result of write register file stack completion to the register.

[0265] When the relevant operation is not completed, the synchronization unit will generate its own blocking signal, blocking waiting, the signal will be sent to the pipeline control unit to generate the pipeline blocking signal.

[0266] A FIFO (like 32bit depth FIFO) can also be added between the scalar processor and the vector processor, for storing the start vector processor request, moving the read-write FIFO previously located in the vector processor to the scalar processor and vector processor transmission queue module, the scalar processor and vector processor transmission queue module unit implements start vector processor, query vector processor execution status, read-write FIFO function, read FIFO depth function, read start vector processor instruction counter function, the condition for start vector processor success is that start vector processor FIFO is not full, the condition for query vector processor execution status is that the vector processor is stopped, and the condition for vector processor status is that the vector processor is executed and start vector processor FIFO is empty.

[0267] 9. Pipeline control unit

[0268] Pipeline control unit, for generating the pause signal of the pipeline and / or generating the start and stop signal of the scalar processor.

[0269] The pipeline control unit is the flow control unit of the scalar processor, and is connected with each unit inside the scalar processor, responsible for generating the blocking signal of the pipeline, for example, the blocking in normal working mode and the blocking in debugging mode.

[0270] The pipeline control unit also communicates with the communication and synchronization unit to generate signals for starting and stopping the scalar processor.

[0271] In addition, the scalar processor can also perform conditional execution decoding in actual application. For example, when the scalar processor performs conditional execution decoding, the scalar processor performs execution condition judgment on the preset bits of the instruction, and outputs a valid instruction if the condition is met, or outputs a null instruction otherwise. The null instruction represents a null instruction or an invalid instruction.

[0272] If there is a read-write related operation on the condition register, pipeline blocking is triggered, and the read operation is performed after the write operation on the condition register is completed. There is no bypass for the read-write operation on the condition register.

[0273] Taking the condition register as two, condition register 0 and condition register 1, and the preset bits as [29:28] bits as an example, when the scalar processor performs conditional execution decoding, the scalar processor performs execution condition judgment on the input instruction based on the [29:28] bits of the instruction set encoding, and outputs a valid instruction if the condition is met, or outputs a null instruction otherwise.

[0274] Among them, [29:28] bits are 00, indicating that condition register 0 is executed, [29:28] bits are 01, indicating that condition register 1 is executed, [29:28] bits are 10, indicating that! condition register 0 is executed, and [29:28] bits are 11, indicating unconditional execution. If the condition is not met, the instruction is invalid, and a null instruction is output.

[0275] If there is a read-write related operation on the condition register, pipeline blocking is triggered, and the read operation is performed after the write operation on the condition register is completed. There is no bypass for the read-write operation on the condition register.

[0276] (II) Vector processor

[0277] In specific implementation, the vector processor can be as shown in Figure 4 or Figure 5 The implementation details of the vector processor can also be described as in the embodiments shown in Figure 4 or Figure 5 This will not be described here. For example, the vector processor includes a vector program control unit (MFetch) and a vector interleaving unit.

[0278] Among them, the vector interleaving unit can be as shown in Figure 1 or 2.

[0279] The vector program control unit is used to determine whether to execute after fetching the instruction, and transmit the instruction to the vector interleaving unit based on the determination result.

[0280] The vector interleaving unit includes a decoder of the vector interleaving unit, a plurality of execution modules, and a selector.

[0281] A decoder of the vector interleaving unit is configured to decode an instruction generated by the vector program control unit to obtain an execution module identifier.

[0282] An execution module is configured to execute the instruction based on the execution module identifier.

[0283] A selector is configured to select an execution result of the execution module and output the selected execution result.

[0284] In addition, the decoder of the vector interleaving unit is configured to generate a control signal based on the execution module identifier, and the control signal is configured to control the instruction to be sent to the execution module corresponding to the execution module identifier.

[0285] In addition, the vector processor further comprises a register corresponding to the execution module.

[0286] The decoder of the vector interleaving unit is configured to send the instruction to the register of the execution module corresponding to the execution module identifier.

[0287] The execution module is configured to read the instruction from the register of the execution module corresponding thereto and execute the instruction.

[0288] In addition, when the decoder of the vector interleaving unit parses a self-write operation instruction, a bypass is generated.

[0289] The read execution module identifier in the self-write operation instruction is the same as the write execution module identifier.

[0290] In addition, the vector program control unit is further configured to receive a start command sent by the scalar processor to start the vector processor, and return an indication signal of whether the vector processor is ended to the scalar processor.

[0291] A FIFO (First Input First Output) unit and a write FIFO unit are arranged between the vector processor and the scalar processor.

[0292] The vector program control unit and the scalar processor perform read operation on the read FIFO unit and write operation on the write FIFO unit.

[0293] This embodiment provides a high-performance processor. The vector interleaving unit in this high-performance processor includes: a decoder for the vector interleaving unit, multiple execution modules, and a selector. The decoder decodes instructions to obtain execution module identifiers and sends the instructions to the execution modules corresponding to the execution module identifiers. Each execution module executes the instructions based on its identifier. The selector selects the execution result from the chosen execution module and outputs the selected result. The high-performance processor provided in this embodiment is no longer limited by the register base file, thus improving instruction execution efficiency.

[0294] Based on the same inventive concept of vector interleaving units, this embodiment provides an electronic device that includes a high-performance processor, or the electronic device includes one or more processor clusters, wherein each processor cluster includes multiple high-performance processors.

[0295] Among them, high-performance processors can be such as Figure 6 As shown, the implementation details of high-performance processors can also be seen as follows: Figure 6 The embodiments shown are illustrated and will not be repeated here. For example, the high-performance processor includes a scalar processor and a vector processor.

[0296] The vector processor includes a vector programmable control unit (MFetch) and a vector interleaving unit.

[0297] Among them, the vector interleaving unit can be as follows Figure 1 Or as shown in Figure 2.

[0298] The vector program control unit is used to retrieve the instruction, determine whether to execute it, and then send the instruction to the vector interleaving unit based on the determination result.

[0299] The vector interleaving unit includes: a decoder for the vector interleaving unit, multiple execution modules, and a selector.

[0300] The decoder of the vector interleaving unit decodes the instructions generated by the vector program control unit to obtain the execution module identifier. The instructions are then sent to the execution module corresponding to the execution module identifier.

[0301] The execution module is used to execute instructions based on the execution module identifier.

[0302] The selector is used to select the execution result of the module to be executed and output the selected execution result.

[0303] In addition, the decoder of the vector interleaving unit is used to generate control signals based on the execution module identifier. The control signals are used to control the sending of instructions to the execution module corresponding to the execution module identifier.

[0304] In addition, the vector processor also includes registers corresponding to the execution module.

[0305] The decoder of the vector interleaving unit is configured to send the instruction to the execution module corresponding to the execution module identifier in the register.

[0306] The execution module is configured to read the instruction from the register of the execution module corresponding to the execution module identifier and execute the instruction.

[0307] In addition, the decoder of the vector interleaving unit generates a bypass when the self-write operation instruction is parsed.

[0308] The read execution module identifier in the self-write operation instruction is the same as the write execution module identifier.

[0309] In addition, the scalar program control unit is further configured to receive a start command sent by the scalar processor to start the vector processor, and return an indication signal of whether the vector processor is ended to the scalar processor.

[0310] The read first-in-first-out (FIFO) unit and the write FIFO unit are arranged between the vector processor and the scalar processor.

[0311] The vector program control unit and the scalar processor perform read operation on the read FIFO unit and write operation on the write FIFO unit.

[0312] The electronic device provided in the embodiment includes a vector interleaving unit, a vector program control unit, a scalar processor, and a read first-in-first-out (FIFO) unit and a write FIFO unit arranged between the vector processor and the scalar processor.

[0313] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can be in the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can be in the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program code. The solutions in the embodiments of the present application can be implemented in various computer languages, such as object-oriented programming language Java and direct script language JavaScript.

[0314] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flowcharts and / or blocks Figure 1 means for functionally implementing the steps listed in the flowchart block or blocks.

[0315] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart block or blocks. Figure 1 one or more flowcharts and / or blocks Figure 1 means for functionally implementing the steps listed in the flowchart block or blocks.

[0316] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flowcharts and / or blocks ​ means for functionally implementing the steps listed in the flowchart block or blocks.

[0317] While the preferred embodiments of the application have been described, additional variations and modifications can be employed by those skilled in the art. Therefore, the appended claims intend to cover all such modifications and variations as fall within the true spirit and scope of the application.

[0318] Obviously, numerous modifications and variations of the present application are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A vector processor, characterized by The vector processor comprises a vector program control unit and a vector interleaving unit, a vector access unit; The vector program control unit is configured to determine whether to execute an instruction after fetching the instruction, and transmit the instruction to the vector interleaving unit based on a determination result; The vector interleaving unit comprises a decoder of the vector interleaving unit, a plurality of execution modules, and a selector; A plurality of registers of the vector interleaving unit correspond to a plurality of vector interleaving units one by one, and a private vector register of the vector interleaving unit is shared by the plurality of vector interleaving units; and a private vector register of the vector access unit is shared by a plurality of vector access units; The decoder of the vector interleaving unit is configured to decode an instruction generated by the vector program control unit to obtain an execution module identifier, and transmit the instruction to an execution module corresponding to the execution module identifier; The execution module is configured to execute the instruction based on the execution module identifier; The selector is configured to select an execution result of the module and output the selected execution result.

2. The vector processor of claim 1, wherein the decoder of the vector interleaving unit is configured to generate a control signal based on the execution module identifier, and the control signal is used to control the instruction to be transmitted to the execution module corresponding to the execution module identifier.

3. The vector processor of claim 1, wherein, The vector processor further comprises a register corresponding to the execution module; The decoder of the vector interleaving unit is configured to transmit the instruction to the register of the execution module corresponding to the execution module identifier; The execution module is configured to read the instruction from the register corresponding to the execution module and execute the instruction.

4. The vector processor of claim 1, wherein the decoder of the vector interleaving unit generates a bypass when a self-write operation instruction is parsed. wherein The read execution module identifier in the self-write operation instruction is the same as the write execution module identifier.

5. A high performance processor, comprising: The vector processor comprises: The vector processor and the scalar processor of any one of claims 1-4; The vector program control unit is further configured to receive a start command sent by the scalar processor to start the vector processor, and return an indication signal of whether the vector processor ends to the scalar processor; A read first-in-first-out (FIFO) unit and a write FIFO unit are arranged between the vector processor and the scalar processor; The vector program control unit and the scalar processor perform read operation on the read FIFO unit and write operation on the write FIFO unit.

6. An electronic device, comprising: The high-performance processor of claim 5; or one or more processor clusters, wherein each processor cluster comprises a plurality of high-performance processors of claim 5. ​

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