High-performance processors, processor clusters and electronic devices

Abstract

This application provides a high-performance processor, processor cluster, and electronic device. The high-performance processor includes: a scalar processor, a vector processor, and local memory; the scalar processor and the vector processor share the local memory; and the vector processor only accesses the local memory and is executed only by the scalar processor; a connection is established between the scalar processor and the vector processor; the scalar processor establishes a connection with global memory; the scalar processor is used to fetch instructions and parameters from the global memory; after determining that the execution conditions are met, the scalar processor calls the vector processor to execute the parameter-based task. The high-performance processor provided in this application, after the scalar processor fetches instructions and parameters from the global memory, calls the vector processor to execute the task based on the parameters when it determines that the execution conditions are met, thereby coordinating the use of multiple heterogeneous cores to meet different computing needs.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more particularly to a high-performance processor, processor cluster, and electronic device. Background Technology

[0002] In heterogeneous multi-core architectures, the processing cores can be different, potentially with varying architectures, clock frequencies, and power consumption. The goal is to combine different types of cores to enable the processor to better adapt to different types of tasks.

[0003] In heterogeneous multi-core architectures, it is crucial to know how to perform heterogeneous multi-core processing and coordinate the use of multiple heterogeneous cores to meet different computing needs. Summary of the Invention

[0004] To address one of the aforementioned technical deficiencies, this application provides a high-performance processor, processor cluster, and electronic device.

[0005] In a first aspect, this application provides a high-performance processor, which includes: a scalar processor, a vector processor, and local memory;

[0006] Scalar processors and vector processors share local memory; and vector processors only access local memory and are only executed by scalar processors.

[0007] Establish a connection between scalar processors and vector processors;

[0008] The scalar processor establishes a connection with global memory;

[0009] The scalar processor is used to fetch instructions and parameters from global memory; after the scalar processor determines that the execution conditions are met, it calls the vector processor to execute the parameter-based execution task.

[0010] Optionally, the scalar processor is an out-of-order multiple-issue scalar processor;

[0011] The vector processor is a very long instruction word vector processor.

[0012] Optionally, the high-performance processor also includes:

[0013] Instruction First-In-First-Out (FIFO) memory;

[0014] The instruction FIFO memory is 32 bits deep.

[0015] Optionally, the high-performance processor also includes: an instruction FIFO memory and a data FIFO memory;

[0016] Both the instruction FIFO memory and the data FIFO memory have a depth of 32 bits.

[0017] Optionally, execution is performed when the vector processor is not processing a task.

[0018] Optionally, the execution condition is that the instruction FIFO memory is not full;

[0019] Scalar processors are used to store the addresses of instructions and parameters into the instruction FIFO memory;

[0020] Vector processors are used to read instructions and data from the instruction FIFO memory when no task is being processed, and execute instructions based on the data.

[0021] Optionally, the execution condition is that neither the instruction FIFO memory nor the data FIFO memory is full;

[0022] Scalar processors are used to store the memory address of instructions into the instruction FIFO memory and the memory address of parameters into the data FIFO memory.

[0023] A vector processor is used to read instructions from the instruction FIFO memory, read data from the data FIFO memory, and execute instructions based on the data when no task is being processed.

[0024] Optionally, the task may include an identifier of the thread to which it belongs.

[0025] A second aspect of this application provides a processor cluster comprising: a plurality of high-performance processors as described in the first aspect.

[0026] A third aspect of this application provides an electronic device comprising: the high-performance processor described in the first aspect, or comprising the high-performance processor described in the second aspect.

[0027] This application provides a high-performance processor, processor cluster, and electronic device. The high-performance processor includes: a scalar processor, a vector processor, and local memory; the scalar processor and the vector processor share the local memory; and the vector processor only accesses the local memory and is executed only by the scalar processor; a connection is established between the scalar processor and the vector processor; the scalar processor establishes a connection with global memory; the scalar processor is used to fetch instructions and parameters from the global memory; after determining that the execution conditions are met, the scalar processor calls the vector processor to execute the parameter-based task. The high-performance processor provided in this application, after the scalar processor fetches instructions and parameters from the global memory, calls the vector processor to execute the task based on the parameters when it determines that the execution conditions are met, thereby coordinating the use of multiple heterogeneous cores to meet different computing needs. Attached Figure Description

[0028] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0029] Figure 1 This is a schematic diagram of the structure of a high-performance processor provided in an embodiment of this application;

[0030] Figure 2 This is a schematic diagram of another high-performance processor provided in an embodiment of this application;

[0031] Figure 3 This is a schematic diagram illustrating the implementation process of a high-performance processor for execution conditions where a vector processor is not performing task processing, as provided in an embodiment of this application.

[0032] Figure 4 A schematic diagram illustrating the implementation process of a high-performance processor for an execution condition where the instruction FIFO memory is not full, as provided in an embodiment of this application;

[0033] Figure 5 This is a schematic diagram of the structure of a scalar processor provided in an embodiment of this application;

[0034] Figure 6 A schematic diagram of the structure of a synchronization unit for a scalar processor provided in an embodiment of this application;

[0035] Figure 7 A schematic diagram of the architecture of a vector processor provided in an embodiment of this application;

[0036] Figure 8 This is a schematic diagram of the structure of a vector operation unit provided in an embodiment of this application;

[0037] Figure 9 This is a schematic diagram of another vector processor architecture provided in an embodiment of this application. Detailed Implementation

[0038] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0039] In developing this application, the inventors discovered that in a heterogeneous multi-core architecture, the processing cores can be different, potentially possessing different architectures, clock frequencies, and power consumption. The goal is to combine different types of cores to enable the processor to better adapt to various tasks. In a heterogeneous multi-core architecture, how to perform heterogeneous multi-core processing and coordinate the use of multiple heterogeneous cores to meet diverse computational needs is crucial.

[0040] To address the aforementioned issues, this application provides a high-performance processor, processor cluster, and electronic device. The high-performance processor includes a scalar processor, a vector processor, and local memory. The scalar processor and vector processor share the local memory; the vector processor only accesses the local memory and is executed only by the scalar processor. A connection is established between the scalar processor and the vector processor. The scalar processor also establishes a connection with global memory. The scalar processor retrieves instructions and parameters from the global memory. After determining that the execution conditions are met, the scalar processor calls the vector processor to execute a parameter-based task. The high-performance processor provided in this application, after the scalar processor retrieves instructions and parameters from the global memory, calls the vector processor to execute a parameter-based task when the execution conditions are met, thereby coordinating the use of multiple heterogeneous cores to meet different computing needs.

[0041] This embodiment provides a high-performance processor, which is a heterogeneous asynchronous processor composed of a scalar processor and a vector processor.

[0042] See Figure 1 This high-performance processor includes: a scalar processor, a vector processor, and local memory.

[0043] In this configuration, scalar processors and vector processors share local memory. Furthermore, vector processors can only access local memory and are executed solely by scalar processors.

[0044] A connection is established between scalar processors and vector processors. For example, scalar processors and vector processors can be connected via a dedicated instruction channel.

[0045] like Figure 2 As shown, a high-performance processor may also include two registers: one corresponding to the scalar processor and the other to the vector processor. The vector processor can read and write its corresponding register, while the scalar processor can read and write both its corresponding register and the register corresponding to the vector processor.

[0046] Scalar processors can read and write the registers of vector processors.

[0047] The scalar processor establishes a connection with global memory.

[0048] (a) Scalar Processor

[0049] The scalar processor is an out-of-order, multi-issue scalar processor.

[0050] Scalar processors are primarily responsible for data handling, task management / synchronization / switching, and invoking vector processors to perform accelerated computations. For example, they fetch instructions and parameters from global memory. Once the scalar processor determines that the execution conditions are met, it invokes the vector processor to execute the parameter-based task.

[0051] In practical implementation, a scalar processor can be like... Figure 5 As shown, the scalar processor includes: an instruction fetch unit, a register renaming unit, an arithmetic reserved stack unit, a memory reserved stack unit, a scalar arithmetic unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit, a register file unit, and a special vector register file unit.

[0052] In addition, a scalar processor may include one or more other units, such as one or more other functional modules, one or more instruction caches, one or more data stores, one or more special vector registers, one or more status flag registers, etc.

[0053] 1. Instruction Fetch Unit

[0054] The instruction fetch unit is used to fetch and dispatch instructions.

[0055] Specifically, the instruction fetch unit generates an instruction fetch request address, outputs the fetch request address to the instruction cache for instruction fetching, receives instructions from the instruction cache, and stores them in the data storage. Each cycle, it sequentially reads qualified instructions from the data storage, decodes and performs relevant checks on the read instructions, and then dispatches the checked instructions sequentially.

[0056] For example, the instruction fetch unit generates an instruction fetch request address and outputs it to the instruction cache for instruction fetching. It also receives instructions from the instruction cache and stores them in the data storage. In each cycle, it sequentially searches for one or more instructions from the qualified instructions, performs decoding and related checks, and dispatches the qualified instructions in sequence. At most, it dispatches one program control unit instruction and one synchronization unit instruction at a time. In addition, it can dispatch one or more scalar arithmetic unit instructions and one or more memory access unit instructions at a time.

[0057] 2. Register renaming unit

[0058] The register renaming unit is used to receive instructions dispatched by the instruction fetch unit and to rename registers.

[0059] Specifically, the register renaming unit receives and stores instructions dispatched by the instruction fetch unit, renames special vector registers, performs instruction conditional decoding, and generates pipeline congestion signals. It receives data from one or more of the following: the scalar arithmetic unit, memory access unit, program control unit, synchronization unit, special vector registers, condition registers, and flag registers, and writes it back. It sends instructions to the arithmetic reserved stack unit, and stores them in one or more of the following: the program control unit, and the synchronization unit.

[0060] For example, the register renaming unit in a scalar processor is used to receive instructions dispatched by the instruction fetch unit and rename registers and special vector registers, decode instruction conditions, generate pipeline congestion signals, and simultaneously receive data from execution units (such as scalar arithmetic units, memory access units, program control units, and synchronization units) to write back registers, special vector registers, condition registers, and status flag registers and write them back to the corresponding registers.

[0061] Scalar processors support out-of-order write-back, resulting in high execution efficiency. They also distribute instructions to the arithmetic stack, storage stack, program control unit, or synchronization unit.

[0062] The register renaming unit bandwidth can be 6 bits, during which multiple (e.g., 4) input instructions can be valid at the same time.

[0063] There can be multiple condition registers, which are located in the register renaming unit.

[0064] The instructions for the scalar arithmetic unit and memory access unit support reading and writing condition registers.

[0065] The instructions for the synchronization unit support reading the condition register.

[0066] The program control unit's jump and function call instructions support reading the condition register.

[0067] When an instruction enters the condition register, the pipeline will be blocked if there are unexecuted instructions in the condition register.

[0068] In other words, the condition register is not renamed; when a read / write request occurs, a dispatch blocking mechanism is triggered to wait. The conditions register read / write rules are as follows:

[0069] Reading rules:

[0070] (1) All instructions in the scalar arithmetic unit, memory access unit, and synchronization unit support conditional execution and require reading the value of the condition register.

[0071] (2) The scalar arithmetic unit also supports read condition register instruction operations.

[0072] (3) The jump and function call instructions of the program control unit support reading condition register operations.

[0073] Write the rules:

[0074] (1) The scalar arithmetic unit supports write condition register instructions.

[0075] (2) Scalar arithmetic unit logic instructions and comparison instructions support the option to write to the condition register.

[0076] When a previously issued instruction to write to the condition register has not yet finished executing, and another instruction to read or write to the same condition register enters, the pipeline becomes congested, generating a condition execution block signal, and waits for the previous condition register to finish writing.

[0077] In addition, the register renaming unit includes one or more physical registers and one or more logical registers.

[0078] Each of the following physical registers can be one of the following: scalar physical register, vector physical register, condition register, or flag register.

[0079] Any logic register can be one of the following: scalar logic register or vector logic register.

[0080] For example, a register renaming unit contains one or more physical registers, such as multiple 512-bit special vector registers, multiple condition registers, and a status flag register.

[0081] Among them, the special vector register is renamed, while the condition register and status flag register are not renamed.

[0082] There are multiple logic registers, such as scalar logic registers and multiple vector logic registers.

[0083] In addition, the mapping relationship between logical registers and physical registers is maintained by a register mapping table. The mapping relationship between vector logical registers and vector physical registers is maintained by a special vector register mapping table.

[0084] 1) Register Map Table

[0085] Initially, the mapped physical registers for all entries corresponding to logical register indices in the register map are all 0. When an instruction is executed, or when an interrupt occurs, the logical register allocated to the relevant physical register is determined, and the mapping of the entries corresponding to the allocated logical register indices in the register map is updated to the identifier of the relevant physical register.

[0086] For example, a register map table with a depth of 32 bits and a width of 6 bits stores the mapping relationship between all logical registers and all physical registers. Initially, the register map table is invalid, and all entries mapping physical registers are all 0. When a physical register is allocated to a logical register, the entry in the register map table corresponding to the logical register index is changed to the ID of that physical register.

[0087] It should be noted that the register map is only updated when an instruction is actually executed. If the conditional execution instruction is not executed, the register map will not be updated. In addition, the register map will not be updated when a jump occurs. However, when an interrupt occurs, the interrupt return address must update the register map to ensure that the interrupt can return normally.

[0088] 2) Special Vector Register Mapping Table

[0089] Initially, the mapped vector physical registers for all entries corresponding to vector logical register indices in the special vector register map are all 0. When an instruction is executed, the vector logical register allocated to the relevant vector physical register is determined, and the mapping of the entries corresponding to the allocated vector logical register indices in the special vector register map is updated to the identifier of the relevant vector physical register.

[0090] For example, the special vector register map table, with a depth of 4 bits and a width of 3 bits, stores the mapping relationship between all vector logic registers and all vector physical registers. Initially, the special vector register map table is invalid, and all entries mapping to vector physical registers are 0. When a vector physical register is allocated to a vector logic register, the entry in the special vector register map table corresponding to the vector logic register index is changed to the ID of that vector physical register.

[0091] It should be noted that the special vector register mapping table is only updated when the instruction is actually executed. If the conditional execution instruction is not executed, the special vector register mapping table will not be updated. In addition, the special vector register mapping table will not be updated when a jump occurs.

[0092] 3. Operations retain stack units

[0093] The operation-reserved stack unit is the issue queue of scalar operation units.

[0094] The arithmetic stack is used to receive instructions, dispatch and rename information from the register renaming unit and push them into the queue. Ready instructions are popped into the scalar arithmetic unit for execution.

[0095] The stack space is reserved for operations and is also used to decode input instructions and store instruction type information.

[0096] In other words, the arithmetic reserve stack is the dispatch queue of the scalar arithmetic unit. The arithmetic reserve stack receives instructions and related dispatch and renaming information from the register renaming unit and pushes them into the queue. It also pops ready instructions onto the scalar arithmetic unit for execution. The arithmetic reserve stack decodes the input instructions and stores the instruction type information.

[0097] In practice, the depth of the operation reserve stack can be flexibly adjusted, such as a depth of 8. Multiple scalar operation units share one operation reserve stack unit.

[0098] The rules for issuing and receiving instructions that reserve stack space are as follows:

[0099] (1) The output of the register renaming unit enters the operation reserve stack unit.

[0100] (2) When there is any free scalar arithmetic unit, it will fetch instructions and operands from the arithmetic reserve stack and execute them.

[0101] (3) The principle of fetching instructions from the operation reserved stack is to fetch executable instructions that can be sent from the operation reserved stack in the order from front to back.

[0102] (4) Whether it is possible to send a value based on the values ​​of all source registers or special vector registers or condition registers and status flag registers is ready to be determined.

[0103] (5) If there are multiple instructions that can be sent, send the oldest instruction first according to the order of instructions.

[0104] (6) If any scalar arithmetic unit is blocked, it can no longer receive new instructions.

[0105] (7) If the instruction previously sent to any scalar arithmetic unit was a division instruction, a new division instruction can only be sent to it after the division result is calculated and the calculation completion En signal is returned.

[0106] 4. Store and retain stack units

[0107] The storage-reserved stack unit is the issue queue for memory access units.

[0108] The storage reserve stack unit is used to receive instructions and register renaming information from the register renaming unit and push them into the queue.

[0109] The storage reserve stack unit is also used to send a read request to the register renaming unit when the instruction address register is ready, and to save the read address operand.

[0110] The register renaming unit is also used to calculate the address after the instruction has obtained the address, decode the address, and save the decoded information.

[0111] The register renaming unit is also used to detect when the existence source register of any instruction is ready and the address decoding is complete, and then send it to the memory access unit for execution.

[0112] In practice, the depth of the memory reservation stack unit can be flexibly adjusted, such as 16. Multiple memory access units share one memory reservation stack unit. The memory reservation stack unit is the issue queue for memory access units. The memory reservation stack unit receives instructions and register renaming information from the register renaming unit and pushes them into the queue. When the instruction address register in the memory reservation stack unit is ready, a read request is sent to the register renaming unit, and the read address operand is saved to the queue. After the instruction in the memory reservation stack unit obtains the address, it can calculate the address and decode the address, saving the resulting decoding information to the queue. When the source register of an instruction (such as a write instruction) is ready in the memory reservation stack unit and the address decoding is complete, it can be issued to the memory access unit for execution. Before issuance, a series of checks are performed, such as address type checks, address comparison checks, and address forward checks.

[0113] The rules for storing and reserving stack cells for sending and receiving instructions are as follows:

[0114] (1) The output of the register renaming unit enters the memory retention stack unit.

[0115] (2) Once the source operand for the calculated address is ready, calculate the memory access address and store it in the memory reservation stack.

[0116] (3) Address-independent instructions: can be out of order. The out-of-order rules are: read instructions after read instructions, write instructions after read instructions, and read instructions after write instructions can all be sent out of order. Write instructions after write instructions need to be ordered (cannot be sent to different memory access units at the same time). Even if the address-independent write instructions are written after write instructions, the order still needs to be maintained.

[0117] (4) Address-related instructions: The order of reading instructions followed by writing instructions, writing instructions followed by reading instructions, writing instructions followed by writing instructions, and reading instructions followed by reading instructions must be guaranteed.

[0118] (5) When addresses are unrelated but are located in the same memory space as all instructions that have not been successfully sent (i.e. instructions on the way that have not been sent to the destination, including those at the memory access unit level and the memory access unit output level), they can be sent out of order to the same memory access unit, but they cannot be sent to two or more memory access units.

[0119] (6) Only one memory access instruction located in the same memory space but with unrelated addresses can be sent at the same time. Two or more memory access instructions cannot be sent at the same time.

[0120] (7) Address correlation judgment principle: whether addresses are related is: if they are located in different storage spaces, they are not related; if they are located in the same storage space, the address correlation is judged based on the data granularity.

[0121] 5. Scalar Operation Unit

[0122] In a practical implementation, there can be one or more scalar operation units.

[0123] For example, a scalar processor includes two scalar arithmetic units, namely scalar arithmetic unit 0 and scalar arithmetic unit 1.

[0124] The scalar arithmetic unit is used to receive instructions and data sent by the arithmetic storage stack unit, perform operations on the data based on the instructions, and write the operation result back to the register renaming unit.

[0125] The scalar arithmetic unit is the computational unit of the scalar processor. It can perform various types of fixed-point and floating-point operations, such as addition, subtraction, multiplication, division, logical operations, comparison operations, and shifting. It receives instructions and data sent from the arithmetic stack, performs the operations, and writes the results back to the register file of the register renaming unit or the special vector register file.

[0126] The following are some example instructions. In actual implementation, the instructions are not limited to these, nor is it limited to including all of them.

[0127] Instructions at execution level 1 include: fixed-point addition and subtraction, logical instructions, shift instructions, fixed-point and floating-point comparison instructions, read / write Flag instructions, fixed-point and floating-point max / min instructions, ABS instructions, bit reversal instructions, selection instructions, special vector register dispatch instructions, read special vector register instructions, Byte reversal instructions, Merge instructions, immediate assignment instructions, FirstOne instructions, CRC instructions, floating-point classification instructions, floating-point partial field extraction instructions, and Rounding instructions.

[0128] Instructions with an execution level of three include: fixed-point multiplication instructions, fixed-to-floating-point conversion instructions, bit filtering instructions, count instructions, and floating-point addition and subtraction instructions.

[0129] Instructions that support bypass include: selection instructions, fixed-point addition and subtraction instructions, shift instructions, immediate assignment instructions, ABS instructions, logical instructions, comparison instructions, and maximum and minimum instructions.

[0130] The execution cycle of a division instruction is indeterminate and depends on the data of the divisor and dividend. Upon completion, the instruction generates a DivEn instruction, indicating its completion and outputting the result to the register file. No new division instructions can be input during the execution of a division instruction, but other scalar computation unit instructions can be input. The output result of the division is multiplexed with the output port of the first-stage pipeline. When the output port of the first-stage pipeline is not used by other scalar computation unit instructions, the division outputs its result and simultaneously outputs the DivEn flag. This DivEn flag is output to the arithmetic reserve stack, indicating that Div instructions can continue to be output to the current scalar computation unit.

[0131] 6. Memory access unit

[0132] In a practical implementation, there can be one or more memory access units.

[0133] For example, a scalar processor includes two memory access units, namely memory access unit 0 and memory access unit 1.

[0134] The memory access unit is used to receive instructions, data, and register information sent by the memory-reserved stack unit, and to read and write the data based on the instructions and register information.

[0135] The memory access unit is a functional module that executes memory access-related instructions in a scalar processor. The memory access unit receives instructions and data, as well as register-related information, from the memory-reserved stack. It executes the instructions accordingly, interacts with other units for data reading and writing, and writes data back to the register renaming unit for read and write instructions. This includes register-level read and write instructions, including 8-bit, 16-bit, 32-bit, 64-bit, or other bit granularities, as well as vector-level read and write instructions. Vector granularities include 128-bit, 256-bit, 512-bit, or other bit granularities. Different instructions have different processing times.

[0136] In addition, the memory access unit is responsible for providing the number of instructions required by the FENCE, and the memory access unit interacts with the memory reservation stack unit to complete the data storage configuration.

[0137] 7. Program Control Unit

[0138] In practice, there is only one program control unit.

[0139] The program control unit receives instructions and data from the register renaming unit, processes the data based on the instructions, and outputs the processing results.

[0140] The program control unit is a functional module that executes instructions related to the execution order of the scalar processor's control program. The program control unit receives instructions and data from the register renaming unit, processes the data accordingly, and outputs the processing results to other modules of the scalar processor. Different instructions have different processing time cycles.

[0141] The program control unit is responsible for controlling the direction of program execution (such as stopping, interrupting, jumping, and function calling), involving the execution of related instructions and the reading and writing control of configuration information; the program control unit is responsible for the configuration and prefetching operation of the instruction cache, as well as the FENCE operation; the program control unit is responsible for the reading, writing and control of the counter, as well as the reading and writing of some other control information, etc.

[0142] 8. Synchronization Unit

[0143] In practice, there is only one synchronization unit.

[0144] The synchronization unit is used for synchronizing the scalar processor and the vector processor.

[0145] like Figure 6 As shown, the synchronization unit establishes communication connections with the pipeline control unit, register renaming unit, program control unit, and vector processor.

[0146] The instructions for the synchronization unit come from the register renaming unit, and the reading and writing of data in the synchronization unit are all done in interaction with the register renaming unit.

[0147] The synchronization unit is used to receive the pause signal sent by the pipeline control unit and send the execution-level pause signal generated during communication with the vector processor to the pipeline control unit in order to generate the execution pause signal of the scalar processor.

[0148] The synchronization unit is used to generate instructions and transmit them to the program control unit.

[0149] In other words, the synchronization unit is the unit that synchronizes the scalar processor and the vector processor. It receives instructions and data from the register renaming unit, reads data from the vector processor and writes it back to the register file, and reads data from the register file unit or special vector register file unit and sends it to the vector processor. It is responsible for the startup and status query of the vector processor, such as querying the read and write FIFO (First Input First Output) in the vector program control unit of the vector processor, the configuration of the register file, the read or write of scalar registers, the status query of the register file, reading the FIFO depth, reading the startup vector processor instruction counter, etc., and providing synchronization unit instruction information to the program control unit.

[0150] The synchronization unit interacts with the pipeline control unit, register renaming unit, and program control unit within the scalar processor, as well as with the external vector processor, scalar processor, and vector processor transfer queue module. Synchronization unit instructions originate from the register renaming unit, and data reads and writes require interaction with this unit. It receives blocking signals from the pipeline control unit, generates its own execution-level blocking signal when communicating with the vector processor, and sends it to the pipeline control unit to generate the ExeStall signal affecting the entire scalar processor. The synchronization unit generates the instructions to be executed in the next cycle and transmits them to the program control unit for use by the program control unit's counter instructions. The synchronization unit interacts with the vector processor, including but not limited to: configuring the register file using special vector registers or registers, reading and writing scalar registers, and querying the write status of the register file. The scalar processor interacts with the scalar processor and vector processor transfer queue module, including but not limited to: starting the vector processor, querying the vector processor status, reading and writing FIFO data in the vector processor's instruction fetch unit, reading the FIFO depth, and reading the start vector processor instruction counter.

[0151] Therefore, in a specific implementation, the synchronization unit can have the following functions (it should be noted that the following functions are only examples, and other functions may also be available. This embodiment and subsequent embodiments do not limit the specific functions of the synchronization unit):

[0152] The Startup Vector Processor function is used to start the vector processor, including immediate start and register start, such as pipeline waiting until the start is successful, or writing the result of the start success or failure back to the destination register.

[0153] The query vector processor execution status function supports option B.

[0154] The read / write FIFO function is located in the instruction fetch unit of the vector processor. For example, the FIFO has a bit width of 32 bits. Reading / writing the FIFO will wait until success, or the result of reading / writing the FIFO will be written back to the register whether it is successful or not.

[0155] Write register file stack functionality, including special vector register write or register write.

[0156] Read and write scalar register functions, including immediate index or register index read and write.

[0157] The function queries the register file stack write-back status. If necessary, it waits until all writes to the register file stack are complete, or returns the result of whether the write to the register file stack is complete to the register.

[0158] When the relevant operation is not completed, a blocking signal is generated by the synchronization unit itself, and the unit blocks and waits. This signal is then sent to the pipeline control unit to generate a pipeline blocking signal.

[0159] A FIFO (such as a 32-bit deep FIFO) can be added between the scalar processor and the vector processor to store the vector processor start request. The read / write FIFO previously located in the vector processor is moved to the scalar processor and vector processor transfer queue module. The scalar processor and vector processor transfer queue module unit implements the functions of starting the vector processor, querying the vector processor execution status, reading and writing the FIFO, reading the FIFO depth, and reading the start vector processor instruction counter. The conditions for successfully starting the vector processor are that the start vector processor FIFO is not full, and the query of the vector processor execution status is successful. The conditions for the vector processor status to stop are that the vector processor has finished executing and the start vector processor FIFO is empty.

[0160] 9. Production line control unit

[0161] The pipeline control unit is used to generate a pause signal for the pipeline and / or to generate start and stop signals for the scalar processor.

[0162] The pipeline control unit is the pipeline control unit of the scalar processor. It is connected to various units inside the scalar processor and is responsible for generating pipeline blocking signals, such as blocking in normal operation mode and blocking in debug mode.

[0163] The pipeline control unit also communicates with the communication and synchronization unit to generate signals for starting and stopping the scalar processor.

[0164] In addition, scalar processors can also perform conditional execution decoding in practical applications. For example, when performing conditional execution decoding, a scalar processor checks the preset bits of the instruction to determine the execution condition. If the condition is met, a valid instruction is output; otherwise, a null instruction is output. Here, a null instruction represents an empty instruction or an invalid instruction.

[0165] If a read / write operation is active in the condition register, pipeline blocking is triggered, waiting for the condition register write operation to complete before the read operation can proceed. There is no bypass for condition register reads and writes.

[0166] Taking two condition registers, namely condition register 0 and condition register 1, with the preset bits [29:28] as an example, when the scalar processor performs conditional execution decoding, it judges the execution conditions of the input instruction based on the [29:28] bits of the instruction set encoding. If the conditions are met, a valid instruction is output; otherwise, a null instruction is output.

[0167] In this instruction, bits [29:28] being 00 indicates that condition register 0 is 1 and the instruction is executed; bits [29:28] being 01 indicates that condition register 1 is 1 and the instruction is executed; bits [29:28] being 10 indicates that condition register 0 is 0 and the instruction is executed without conditions; and bits [29:28] being 11 indicates that the instruction is executed without conditions. If the conditions are not met, the instruction is invalid and an empty instruction is output.

[0168] If there is a read / write dependency in the condition register, pipeline blocking is triggered, and the read operation is performed only after the condition register has been written. There is no bypass for condition register read / write operations.

[0169] (ii) Vector Processor

[0170] The vector processor is a Very Long Instruction Word (VLIW) vector processor.

[0171] Vector processors can be unbalancedly clustered and can run more than 20 instructions concurrently, with various vector / matrix operation acceleration instructions and loop acceleration methods.

[0172] In practical implementation, a vector processor can be as follows: Figure 7 As shown, the vector processor includes: a vector program control unit, multiple functional units, a register file stack, and scalar registers.

[0173] In addition, the vector processor also includes: a private vector register for the vector interleaving unit and a private vector register for the vector access unit.

[0174] 1. Vector Program Control Unit

[0175] Vector program control unit, used for instruction fetching and instruction issuing.

[0176] That is, the vector program control unit is used to retrieve instructions, determine whether to execute them, and issue instructions to functional units based on the determination result.

[0177] The vector program control unit is also used to control instruction jumps.

[0178] The vector program control unit has scalar computation capabilities.

[0179] The vector program control unit interacts with the scalar register.

[0180] In practical implementation, the vector program control unit is an instruction fetch and instruction issue unit. It fetches instructions from the cache based on the PC value, and after determining whether to execute, issues instructions to each functional unit based on the wait value (configured by the wait instruction). It also controls instruction jumps and has some scalar computation capabilities.

[0181] In addition, the vector program control unit is also used to receive start commands from other processing processors and start the vector processor. It also returns an indication signal to other processing processors indicating whether the vector processor has finished.

[0182] Taking other processing processors as scalar processors as an example, the vector program control unit receives the start command issued by the synchronization unit of the scalar processor, starts the vector processor to execute, and also returns an indication signal to the synchronization unit whether the vector processor execution has ended.

[0183] 2. Functional Units

[0184] Functional units are used to perform functional processing according to instructions.

[0185] For example, a functional unit receives instructions from a vector program control unit, processes the data accordingly, and outputs the processing results at the address specified in the instructions.

[0186] The functional units include: one or more vector operation units, one or more vector interleaving units, and one or more vector access units.

[0187] 1) Vector operation unit

[0188] Any vector operation unit is used to perform vector operations according to instructions.

[0189] like Figure 8 As shown, any vector operation unit includes: a floating-point multiply-add subunit, a floating-point multiply-accumulate subunit, a floating-point arithmetic subunit, a tensor multiplication subunit, and an intermediate result register.

[0190] The floating-point multiply-accumulate subunit and the floating-point arithmetic subunit share one issue slot. Therefore, a maximum of 8 instructions from the vector operation unit can be issued per cycle.

[0191] The floating-point multiplication-accumulation subunit and the tensor multiplication subunit share a single launch slot.

[0192] The floating-point multiply-accumulate subunit is a functional unit that executes instructions related to floating-point multiply-accumulate operations. For example, instructions related to floating-point multiply-accumulate operations include integer and floating-point vector multiplication and accumulation, multiplication, addition, tensor calculation, etc.

[0193] Each vector operation unit has its own intermediate result register.

[0194] One floating-point multiply-accumulate subunit, one floating-point multiply-accumulate subunit, one tensor multiplication subunit, and one floating-point arithmetic subunit share an intermediate result register.

[0195] (1) Floating-point multiply-accumulate and floating-point multiply-accumulate subunits, which can perform integer and floating-point vector multiplication, multiply-accumulate and other operations. Supported types include, but are not limited to, int32, fp32, and fp64.

[0196] (2) The floating-point arithmetic subunit can perform integer and floating-point vector arithmetic operations, such as comparison, addition, subtraction, bitwise operations, etc. Supported types include, but are not limited to, int8, uint8, int16, uint16, int32, uint32, bool, fp16, bf16, fp32, tf32, fp64.

[0197] (3) The tensor multiplication subunit can perform tensor multiplication, multiply-accumulate and other operations. Supported types include, but are not limited to, int8, bf16, fp16 and tf32.

[0198] 2) Vector interleaving unit

[0199] Any vector interleaving unit is used to perform data interleaving and logical processing according to instructions.

[0200] The vector interleaving unit is the control and data processing unit within the vector processor. It is responsible for interleaving data, supporting logical and some fixed-point and floating-point calculations. It also supports numerous customized instructions, including table lookup, horizontal calculation, sparse matrix calculation, precision conversion, and FIFO (First Input First Output) functions. It executes instructions such as data broadcasting, extraction, and internal interleaving.

[0201] Each vector interleaving unit has a set of private vector registers; therefore, the private vector registers of each vector interleaving unit correspond one-to-one with the vector interleaving units.

[0202] 3) Vector Access Unit

[0203] Each vector access unit is used to perform multi-mode memory access, address calculation, and scalar calculation according to instructions.

[0204] The vector access unit is the memory access unit within the vector processor, primarily responsible for reading / writing instructions and various scalar calculations.

[0205] The read / write instructions support multiple memory access modes, such as row mode, column mode, discrete mode, extended mode, and accumulation mode.

[0206] It supports multiple parameter configurations, with a maximum read / write instruction data width of up to 1024 bits. It executes instructions such as address calculation, load / store, etc.

[0207] All vector access units share a set of private vector registers, so the private vector registers of a vector access unit are shared by multiple vector access units.

[0208] 3. Register file stack

[0209] The register file is used to receive and return data after read / write requests. The data is rearranged and then returned. It interacts with functional units for read / write operations. The configuration registers of the vector program control unit are configured using data within the register file.

[0210] The register file stack is a general-purpose vector register stack, which is the main storage unit within the vector processor. It is responsible for receiving read and write requests and returning data. In some functions, it can rearrange the data before returning it to the requesting module.

[0211] The register file stack interacts with functional units within the vector processor (such as the floating-point multiply-accumulate subunit, floating-point arithmetic subunit, floating-point multiply-accumulate subunit, and tensor multiplication subunit), and also supports configuring the instruction fetch unit configuration register using data in the register file stack.

[0212] The register file is also used to write data to other processing units. It receives status messages from other processing units indicating whether the data has been written.

[0213] Taking other processing processors as examples, such as scalar processors, the synchronization unit of a scalar processor can write data to the register file, and the register file can also receive status information from the synchronization unit of the scalar processor to query whether the data has been written.

[0214] The depth of the register file heap is configurable.

[0215] Figure 9 A schematic diagram of a vector processor is shown, comprising four vector operation units, four vector interleaving units, and four vector access units.

[0216] The vector processor provided in this embodiment supports the VLIW (Very Long Instruction Word) instruction set. Each VLIW can consist of one or more instructions, and each instruction corresponds to a functional unit.

[0217] In addition, read FIFO units and write FIFO units are set up between the vector processor and other computing processors.

[0218] The vector program control unit and other arithmetic processors both perform read operations on the read FIFO unit and write operations on the write FIFO unit.

[0219] Other processing units perform read or write operations on the vector register.

[0220] Taking other processing processors as examples, such as scalar processors, there are read FIFO and write FIFO units between the scalar processor and the vector processor for transmitting data. The scalar processor and the vector program control unit can perform read operations or write operations on the read and write FIFOs.

[0221] Meanwhile, the synchronization unit of the scalar processor can perform read or write operations on the scalar registers of the vector processor.

[0222] In addition, a high-performance processor may also include: instruction FIFO (First Input First Output) memory. Alternatively, a high-performance processor may also include: instruction FIFO memory and data FIFO memory.

[0223] The instruction FIFO memory and the data FIFO memory are both 32-bit deep.

[0224] In practice, there can be multiple execution conditions. For example, the execution condition may be that the vector processor is not processing any tasks. Alternatively, the execution condition may be that the instruction FIFO memory is not full (for example, the instruction FIFO memory is 32 bits deep, in which case the instruction FIFO memory forms an asynchronous queue). Or, the execution condition may be that both the instruction FIFO memory and the data FIFO memory are not full (for example, the instruction FIFO memory and the data FIFO memory are both 32 bits deep, in which case the instruction FIFO memory forms an asynchronous queue for instructions, and the data FIFO memory forms an asynchronous queue for parameters).

[0225] Depending on the execution conditions, the specific implementation schemes of high-performance processors also vary, which are explained below:

[0226] The execution condition is that the vector processor has not performed task processing.

[0227] Taking two tasks (task0 and task1) as an example, see [link to example]. Figure 3 ( Figure 3 (White boxes are executed by scalar processors, and gray boxes are executed by vector processors.) The high-performance processor handles this type of execution condition as follows:

[0228] The scalar processor retrieves task0 and its parameters from global memory.

[0229] The scalar processor determines whether the vector processor is currently processing a task. If the vector processor is not processing a task, the scalar processor calls the vector processor to execute task0 based on the parameters of task0.

[0230] The vector processor then executes task0 based on its parameters. Meanwhile, the scalar processor can retrieve task1 and its parameters from global memory again to prepare for the execution of task1.

[0231] The scalar processor synchronizes with the vector processor to confirm whether the vector processor is processing task0. If the vector processor has not finished executing task0 and is currently processing a task, the scalar processor will wait until the vector processor finishes processing task0.

[0232] If the scalar processor determines again that the vector processor has not processed the task, the scalar processor will then call the vector processor to execute task1 based on the parameters of task1.

[0233] In this heterogeneous multi-core processing, the scalar processor needs to synchronize with the vector processor. The scalar processor can only call the vector processor to process the next task after the previous task of the vector processor has been completed.

[0234] The execution condition is that the instruction FIFO memory is not full.

[0235] For this type of execution condition, the process by which a scalar processor in a high-performance processor calls a vector processor to execute a task based on parameters can be as follows: The scalar processor stores the memory addresses of the instructions and parameters into the instruction FIFO memory. When not processing a task, the vector processor reads the instructions and parameters from the instruction FIFO memory and executes the instructions based on the parameters.

[0236] Taking two tasks (task0 and task1) as an example, see [link to example]. Figure 4 ( Figure 4 (The white-background boxes are executed by the scalar processor, and the gray-background boxes are executed by the vector processor.) The high-performance processor implements this execution condition based on an asynchronous queue instruction FIFO memory.

[0237] For example, a scalar processor retrieves task0 and its parameters from global memory.

[0238] The scalar processor determines whether the instruction FIFO memory is full. If not, it packages task0 and its parameters into task packet 0 (e.g., packages task0 and the starting address of its parameters into task packet 0) and stores the task packet in the instruction FIFO memory. When not processing any tasks, the vector processor reads task packet 0 from the instruction FIFO memory and executes task0 based on its parameters.

[0239] During the execution of a task by the vector processor, the scalar processor can retrieve task1 and its parameters from the global memory. Retrieving task1 and its parameters from the global memory prepares for task1 execution. The scalar processor determines if the instruction FIFO memory is full. If not, it packages task1 and its parameters into task packet 1 and stores the task packet in the instruction FIFO memory. In other words, the process of the scalar processor reading tasks and parameters and packaging them into task packets is independent of whether the vector processor is executing a task. As long as the instruction FIFO memory is not full (i.e., the instruction FIFO memory does not contain 32 task packets), the scalar processor can repeatedly retrieve instructions and parameters from the global memory. After determining that the execution conditions are met, the scalar processor calls the vector processor to execute the parameter-based task execution steps, continuously retrieving tasks and parameters, packaging them into task packets, and storing them in the instruction FIFO memory.

[0240] However, whether the vector processor processes a new task is independent of the scalar processor. As long as the vector processor completes the processing of a task (even if it is not currently processing a task), and the instruction FIFO memory is not empty, it can retrieve a task packet from the instruction FIFO memory and execute the task packet. If the vector processor completes the processing of a task (even if it is not currently processing a task), but the instruction FIFO memory is empty, then the execution of the task will be stopped.

[0241] In this heterogeneous multi-core processing, scalar processors and vector processors do not need to be synchronized, and the task reading and distribution of scalar processors are unrelated to the task execution of vector processors.

[0242] The execution condition is that both the instruction FIFO memory and the data FIFO memory are not full.

[0243] For this type of execution condition, the process by which a scalar processor in a high-performance processor calls a vector processor to execute a task based on parameters can be as follows: The scalar processor stores the instruction's memory address in the instruction FIFO memory and the parameter's memory address in the data FIFO memory. When not processing a task, the vector processor reads instructions from the instruction FIFO memory, reads parameters from the data FIFO memory, and executes the instructions based on the parameters.

[0244] Taking a scenario with two tasks (task0 and task1) to be executed as an example, for heterogeneous multi-core processing under such execution conditions, an asynchronous queue instruction FIFO memory and an asynchronous queue data FIFO memory are constructed. Both the instruction FIFO memory and the data FIFO memory are 32 bits deep, meaning that the instruction FIFO memory can store 32 task packets simultaneously, and the data FIFO memory can also store 32 task packets simultaneously. Furthermore, the instructions and parameters stored in the instruction FIFO memory and the data FIFO memory are corresponding (that is, if instruction 2 is stored in the second position of the instruction FIFO memory, the parameters of instruction 2 are also stored in the second position of the data FIFO memory). This ensures that the parameters read by the vector processor from the instruction FIFO memory and the data FIFO memory are the parameters of the instructions read.

[0245] First, the scalar processor retrieves task0 and its parameters from global memory.

[0246] The scalar processor determines whether both the instruction FIFO and data FIFO memories are not full (since the instruction and data FIFO memories are stored correspondingly, if the instruction FIFO memory is not full, the data FIFO memory is also not full; if the instruction FIFO memory is full, the data FIFO memory is also full). If both the instruction and data FIFO memories are not full, the scalar processor stores instruction 0 in the instruction FIFO memory and stores the storage address of the parameters of instruction 0 in the data FIFO memory (e.g., the scalar processor allocates a space on local memory, stores the parameters of instruction 0 in that space, and stores the starting address of that space in the data FIFO memory). When not processing a task, the vector processor reads task0 from the instruction FIFO memory, reads the parameters of task0 from the data FIFO memory, and executes task0 based on the parameters of task0.

[0247] During the execution of a task by the vector processor, the scalar processor can retrieve task1 and its parameters from global memory. Retrieving task1 and its parameters from global memory prepares for task1 execution. The scalar processor determines whether both the instruction FIFO and data FIFO are not full. If not, the scalar processor stores instruction 1 in the instruction FIFO and the storage address of its parameters in the data FIFO (e.g., the scalar processor allocates a space in local memory, stores the parameters of instruction 1 in that space, and stores the starting address of that space in the data FIFO). In other words, the process of the scalar processor reading the task and its parameters and storing them in the instruction FIFO and data FIFO is independent of whether the vector processor is executing a task. As long as both the instruction FIFO and data FIFO are not full (i.e., the instruction FIFO does not contain 32 task packets, and the data FIFO does not contain 32 task packets), the scalar processor can repeatedly retrieve instructions and parameters from global memory. After the scalar processor determines that the execution conditions are met, it calls the vector processor to execute the steps of the parameter-based task execution, continuously acquiring the task and parameters, and storing the task and parameters in the instruction FIFO memory and the data FIFO memory respectively.

[0248] However, whether a vector processor processes a new task is independent of the scalar processor. As long as the vector processor completes the processing of a task (even if it is not currently processing a task), and both the instruction FIFO and data FIFO memories are not empty, it can retrieve the task and parameters from the instruction FIFO and data FIFO memories respectively, and then execute the task based on the parameters. If the vector processor completes the processing of a task (even if it is not currently processing a task), but both the instruction FIFO and data FIFO memories are empty, then the execution of the task will be stopped.

[0249] In this heterogeneous multi-core processing, scalar processors and vector processors do not need to be synchronized. The task reading and dispatching of scalar processors are unrelated to the task execution of vector processors. At the same time, when a vector processor retrieves a task from the instruction FIFO memory, it also retrieves the parameter address from the data FIFO memory, thereby obtaining a list of task parameters. In this way, the task is called and the actual parameters are obtained at the same time.

[0250] Furthermore, in its implementation, the scalar processor includes an identifier of the thread to which the task belongs in each task call. This identifier indicates which thread's task it belongs to. The identifier allows the processor to check whether tasks issued by each thread have finished executing, transforming synchronous execution into asynchronous execution. The instruction FIFO memory serves as the asynchronous execution mechanism.

[0251] This embodiment provides a high-performance processor, which includes: a scalar processor, a vector processor, and local memory; the scalar processor and the vector processor share the local memory; and the vector processor only accesses the local memory and is only invoked and executed by the scalar processor; a connection is established between the scalar processor and the vector processor; the scalar processor establishes a connection with global memory; the scalar processor is used to retrieve instructions and parameters from the global memory; after determining that the execution conditions are met, the scalar processor invokes the vector processor to execute the parameter-based task. The high-performance processor provided in this embodiment, after the scalar processor retrieves instructions and parameters from the global memory, invokes the vector processor to execute the task based on the parameters when it determines that the execution conditions are met, thereby coordinating the use of multiple heterogeneous cores to meet different computing needs.

[0252] Based on the same inventive concept as high-performance processors, this embodiment provides a processor cluster, which includes multiple processors such as... Figure 1 or Figure 2 The high-performance processor shown.

[0253] For example, this high-performance processor includes: a scalar processor, a vector processor, and local memory;

[0254] Scalar processors and vector processors share local memory; and vector processors only access local memory and are only executed by scalar processors.

[0255] Establish a connection between scalar processors and vector processors;

[0256] The scalar processor establishes a connection with global memory;

[0257] The scalar processor is used to fetch instructions and parameters from global memory; after the scalar processor determines that the execution conditions are met, it calls the vector processor to execute the parameter-based execution task.

[0258] Among them, the scalar processor is an out-of-order multiple-issue scalar processor;

[0259] The vector processor is a very long instruction word vector processor.

[0260] Among them, high-performance processors also include:

[0261] Instruction First-In-First-Out (FIFO) memory;

[0262] The instruction FIFO memory is 32 bits deep.

[0263] The high-performance processor also includes: instruction FIFO memory and data FIFO memory;

[0264] Both the instruction FIFO memory and the data FIFO memory have a depth of 32 bits.

[0265] The execution condition is that the vector processor is not processing any tasks.

[0266] The execution condition is that the instruction FIFO memory is not full;

[0267] Scalar processors are used to store the addresses of instructions and parameters into the instruction FIFO memory;

[0268] Vector processors are used to read instructions and data from the instruction FIFO memory when no task is being processed, and execute instructions based on the data.

[0269] The execution condition is that neither the instruction FIFO memory nor the data FIFO memory is full;

[0270] Scalar processors are used to store the memory address of instructions into the instruction FIFO memory and the memory address of parameters into the data FIFO memory.

[0271] A vector processor is used to read instructions from the instruction FIFO memory, read data from the data FIFO memory, and execute instructions based on the data when no task is being processed.

[0272] The task includes the identifier of the thread to which it belongs.

[0273] The processor cluster provided in this embodiment includes a high-performance processor comprising: a scalar processor, a vector processor, and local memory; the scalar processor and the vector processor share the local memory; and the vector processor only accesses the local memory and is only invoked and executed by the scalar processor; a connection is established between the scalar processor and the vector processor; the scalar processor establishes a connection with the global memory; the scalar processor is used to retrieve instructions and parameters from the global memory; after determining that the execution conditions are met, the scalar processor invokes the vector processor to execute the parameter-based execution task, thereby coordinating the use of multiple heterogeneous cores to meet different computing needs.

[0274] Based on the same inventive concept as high-performance processors, this embodiment provides an electronic device, which includes as follows: Figure 1 or Figure 2 The high-performance processor shown, or, comprising one or more processor clusters, wherein each processor cluster includes multiple such processors... Figure 1 or Figure 2 The high-performance processor shown.

[0275] For example, this high-performance processor includes: a scalar processor, a vector processor, and local memory;

[0276] Scalar processors and vector processors share local memory; and vector processors only access local memory and are only executed by scalar processors.

[0277] Establish a connection between scalar processors and vector processors;

[0278] The scalar processor establishes a connection with global memory;

[0279] The scalar processor is used to fetch instructions and parameters from global memory; after the scalar processor determines that the execution conditions are met, it calls the vector processor to execute the parameter-based execution task.

[0280] Among them, the scalar processor is an out-of-order multiple-issue scalar processor;

[0281] The vector processor is a very long instruction word vector processor.

[0282] Among them, high-performance processors also include:

[0283] Instruction First-In-First-Out (FIFO) memory;

[0284] The instruction FIFO memory is 32 bits deep.

[0285] The high-performance processor also includes: instruction FIFO memory and data FIFO memory;

[0286] Both the instruction FIFO memory and the data FIFO memory have a depth of 32 bits.

[0287] The execution condition is that the vector processor is not processing any tasks.

[0288] The execution condition is that the instruction FIFO memory is not full;

[0289] Scalar processors are used to store the addresses of instructions and parameters into the instruction FIFO memory;

[0290] Vector processors are used to read instructions and data from the instruction FIFO memory when no task is being processed, and execute instructions based on the data.

[0291] The execution condition is that neither the instruction FIFO memory nor the data FIFO memory is full;

[0292] Scalar processors are used to store the memory address of instructions into the instruction FIFO memory and the memory address of parameters into the data FIFO memory.

[0293] A vector processor is used to read instructions from the instruction FIFO memory, read data from the data FIFO memory, and execute instructions based on the data when no task is being processed.

[0294] The task includes the identifier of the thread to which it belongs.

[0295] The electronic device provided in this embodiment includes a high-performance processor comprising: a scalar processor, a vector processor, and local memory; the scalar processor and the vector processor share the local memory; and the vector processor only accesses the local memory and is only invoked and executed by the scalar processor; a connection is established between the scalar processor and the vector processor; the scalar processor establishes a connection with the global memory; the scalar processor is used to retrieve instructions and parameters from the global memory; after determining that the execution conditions are met, the scalar processor invokes the vector processor to execute the parameter-based execution task, thereby coordinating the use of multiple heterogeneous cores to meet different computing needs.

[0296] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of this application can be implemented in various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0297] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0298] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0299] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0300] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0301] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A high-performance processor, characterized in that, The high-performance processor includes: a scalar processor, a vector processor, and local memory; The scalar processor and the vector processor share local memory; and the vector processor only accesses the local memory and is only invoked and executed by the scalar processor. A connection is established between the scalar processor and the vector processor; The scalar processor establishes a connection with the global memory; The scalar processor is used to retrieve instructions and parameters from the global memory; after determining that the execution conditions are met, the scalar processor calls the vector processor to execute the task based on the parameters. The high-performance processor also includes: an instruction FIFO memory and a data FIFO memory; Both the instruction FIFO memory and the data FIFO memory are 32 bits deep; the instructions and parameters stored in the instruction FIFO memory and the data FIFO memory are corresponding. The execution condition is that neither the instruction FIFO memory nor the data FIFO memory is full; The scalar processor is used to store the storage address of the instruction into the instruction FIFO memory and store the storage address of the parameter into the data FIFO memory. The vector processor is configured to read instructions from the instruction FIFO memory, read data from the data FIFO memory, and execute the instructions based on the data when no task processing is performed.

2. The high-performance processor according to claim 1, characterized in that, The scalar processor is an out-of-order multiple-issue scalar processor; The vector processor is a Very Long Instruction Word Vector Processor.

3. The high-performance processor according to claim 1, characterized in that, The execution condition is that the vector processor is not processing any tasks.

4. The high-performance processor according to claim 1, characterized in that, The task includes the identifier of the thread to which it belongs.

5. A processor cluster, characterized in that it comprises a plurality of high-performance processors as described in any one of claims 1 to 3.

6. An electronic device, characterized in that, include: The high-performance processor as described in any one of claims 1 to 3, or comprising one or more processor clusters as described in claim 5.

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