Method and apparatus for hardware thread switching

Abstract

This application provides a hardware thread switching method and device. The method includes: sending a PackSave instruction to a control unit; wherein the PackSave instruction is used to trigger saving the context, and the PackSave instruction carries a thread identifier; the processor, based on the PackSave instruction, blocks the pipeline and stops dispatching new instructions into the pipeline; saving relevant context data according to the thread identifier; and restoring the pipeline; wherein the relevant context data includes, but is not limited to: register file information, logical register-physical register mapping table, condition register information, and status register information. The method provided by this application can achieve hardware thread switching with a single PackSave instruction, reducing hardware thread switching time and improving hardware thread switching speed.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a hardware thread switching method and device. Background Technology

[0002] A thread is a single execution flow within a process. Multiple threads can share resources such as code segments, data segments, and open files, but each thread has its own independent set of registers and stack, ensuring that the control flow of a thread is relatively independent. A thread can be considered the basic unit of processor scheduling.

[0003] When switching hardware threads, it is necessary to save and restore the thread's execution context, such as saving information about the thread's relevant registers and counters.

[0004] Traditional hardware thread switching requires multiple instructions to complete, resulting in long switching times and slow speed. Summary of the Invention

[0005] To address one of the aforementioned technical deficiencies, this application provides a hardware thread switching method and device.

[0006] The first aspect of this application provides a hardware thread switching method, the method comprising:

[0007] The program execution direction control unit sends a PackSave command; the PackSave command is used to trigger saving the context, and the PackSave command carries a thread identifier;

[0008] The processor uses the PackSave instruction to block the pipeline, stopping the dispatch of new instructions into the pipeline; saves relevant context data based on thread identifiers; and restores the pipeline.

[0009] The relevant data at the site includes, but is not limited to: register file information, logical register-physical register mapping table, condition register information, and status register information.

[0010] Optionally, relevant on-site data can be saved based on the thread identifier, including:

[0011] By continuously performing M / P cycles, relevant on-site data is saved according to the thread identifier;

[0012] Where M is the total amount of on-site related data for the hardware thread, and P is the amount of data per row in the private storage.

[0013] Optionally, relevant field data is saved based on the thread identifier over M / P consecutive cycles, including:

[0014] Within each cycle, perform the following steps:

[0015] Based on the thread identifier, determine the private storage address for that cycle; the private storage address is used to access private storage, and the private storage address is different for each hardware thread;

[0016] Retrieve the data saved within this period; wherein, the data saved within this period is a part of the relevant field data, and the data saved in each period is different, and the sum of the data saved in M / P periods is all the relevant field data;

[0017] The data saved during this period will be stored in the private storage address of this period.

[0018] Optionally, after saving the relevant data based on the thread identifier, the method further includes:

[0019] The program execution direction control unit sends a PackRestore command; the PackRestore command is used to trigger the restoration of the context; and the PackRestore command carries a thread identifier;

[0020] The processor uses the PackRestore instruction to block the pipeline, stop dispatching new instructions into the pipeline, restore the relevant context data based on the thread identifier, and restore the pipeline.

[0021] Optionally, restore relevant data from the current state based on the thread identifier, including:

[0022] By performing M / P consecutive cycles, the relevant data at the scene is restored based on the thread identifier;

[0023] Where M is the total amount of on-site related data for the hardware thread, and P is the amount of data per row in the private storage.

[0024] Optionally, relevant field data is restored based on the thread identifier through M / P consecutive cycles, including:

[0025] Within each cycle, perform the following steps:

[0026] Based on the thread identifier, determine the private storage address for that cycle; the private storage address is located within private storage, and the private storage address is different for each hardware thread;

[0027] Data is read from a private storage address; the data read from the private storage address is a part of the field-related data, and the data read from the private storage address is different in each cycle. The sum of the data read from the private storage address in M / P cycles is the field-related data.

[0028] The data read from the private storage address is written into the register file, the logical register-physical register mapping table, the condition register, and the status register.

[0029] Optionally, the private storage address for this cycle is determined based on the thread identifier, including:

[0030] The private storage address for this period is set to i*M / P+j;

[0031] Where i is the thread identifier, i = 0, ..., n-1, n is the total number of hardware threads supported by the processor, and j is the cycle identifier, j = 0, ..., M / P-1.

[0032] Optionally, before the program execution direction control unit sends the PackSave command, it also includes:

[0033] The program execution direction control unit sends a first Fence command; the first Fence command is used to ensure that the command is executed completely.

[0034] The processor, based on the PackSave instruction, blocks the pipeline and stops dispatching new instructions into the pipeline. This includes:

[0035] After the processor receives the first Fence instruction, it confirms that there are no instructions that have not been completed.

[0036] Optionally, before the program executes the direction control unit to send the PackRestore command, it also includes:

[0037] The program execution direction control unit sends a second Fence command; the second Fence command is used to ensure that the command is executed.

[0038] Before the processor blocks the pipeline based on the PackRestore instruction and stops dispatching new instructions into the pipeline, it also includes:

[0039] After the processor receives the second fence instruction, it confirms that there are no instructions that have not been completed.

[0040] A second aspect of this application provides an electronic device, comprising: a program execution direction control unit, a processor, and private storage;

[0041] The program execution direction control unit is used to execute the steps of the program execution direction control unit as described in the first aspect above.

[0042] A processor for performing the steps of the processor as described in the first aspect above;

[0043] Private storage is used to store all relevant data of the hardware thread's context; the context-related data of each hardware thread has a different private storage address in the private storage.

[0044] This application provides a hardware thread switching method and device. The method includes: sending a PackSave instruction to a control unit; wherein the PackSave instruction is used to trigger saving the context, and the PackSave instruction carries a thread identifier; the processor, based on the PackSave instruction, blocks the pipeline and stops dispatching new instructions into the pipeline; saving relevant context data according to the thread identifier; and restoring the pipeline; wherein the relevant context data includes, but is not limited to: register file information, logical register-physical register mapping table, condition register information, and status register information. The method provided by this application can achieve hardware thread switching with a single PackSave instruction, reducing hardware thread switching time and improving hardware thread switching speed. Attached Figure Description

[0045] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0046] Figure 1 A flowchart illustrating a hardware thread switching method provided in an embodiment of this application;

[0047] Figure 2 A schematic diagram illustrating the storage of hardware thread context-related data provided in this application embodiment;

[0048] Figure 3 This is a schematic diagram illustrating the process of saving the hardware thread context using a hardware thread switching method provided in this application embodiment;

[0049] Figure 4 This application provides a schematic diagram illustrating the restoration of hardware thread context-related data in an embodiment of the present application.

[0050] Figure 5 This is a schematic diagram illustrating the process of hardware thread context recovery using a hardware thread switching method provided in this application embodiment. Detailed Implementation

[0051] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0052] In developing this application, the inventors discovered that during hardware thread switching, it is necessary to save and restore the thread's execution context, such as saving information like the thread's relevant registers and counters. Traditional hardware thread switching requires multiple instructions, resulting in long switching times and slow speed.

[0053] To address the aforementioned issues, this application provides a hardware thread switching method and device. The method includes: sending a PackSave instruction to a control unit; wherein the PackSave instruction triggers the saving of the current state and carries a thread identifier; the processor, based on the PackSave instruction, blocks the pipeline, stopping the dispatch of new instructions into the pipeline; saving relevant data based on the thread identifier; and restoring the pipeline; wherein the relevant data includes, but is not limited to, register file information, a logical register-physical register mapping table, condition register information, and status register information. The method provided in this application can achieve hardware thread switching with a single PackSave instruction, reducing hardware thread switching time and improving hardware thread switching speed.

[0054] See Figure 1 This embodiment provides a hardware thread switching method, the implementation process of which is as follows:

[0055] 101, The program execution direction control unit sends a PackSave command.

[0056] The PackSave instruction is used to trigger saving the current state, and it carries a thread identifier (such as the thread number).

[0057] In other words, when the program execution direction control unit confirms that it needs to save the current state, the program execution direction control unit will send a PackSave command.

[0058] 102. The processor, based on the PackSave instruction, blocks the pipeline, stopping the dispatch of new instructions into the pipeline. It then restores the pipeline by saving relevant context data based on the thread identifier.

[0059] The relevant data at the site includes, but is not limited to: register file information, logical register-physical register mapping table, condition register information, and status register information.

[0060] In other words, the relevant data on-site includes: register file information, logical register-physical register mapping table, condition register information, status register information, and other information that the threads need to save.

[0061] In practice, the process of saving relevant data based on the thread identifier can be achieved through M / P cycles, that is, by continuously performing M / P cycles, the relevant data based on the thread identifier is saved.

[0062] Where M is the total amount of on-site related data for the hardware thread, and P is the amount of data per row in the private storage.

[0063] When saving relevant data based on the thread identifier through M / P consecutive cycles, the following steps 201-203 are executed in each cycle:

[0064] 201. Determine the private storage address for this cycle based on the thread identifier.

[0065] The private storage address is used to access private storage, and the private storage address is different for each hardware thread.

[0066] This private storage can be SRAM (Static Random-Access Memory), used to store all relevant data of the hardware thread in the field.

[0067] The on-site data of each hardware thread has a different private storage address in the private storage.

[0068] For example, the private storage address of any period j is determined to be i*M / P+j.

[0069] Where i is the thread identifier, i = 0, ..., n-1, n is the total number of hardware threads supported by the processor, and j is the cycle identifier, j = 0, ..., M / P-1.

[0070] In practice, step 201 can be implemented through an address generation unit.

[0071] 202, retrieve the data saved within this period.

[0072] The data saved within each period is a portion of the field-related data, and the data saved in each period is different. The sum of the data saved in M / P periods is the field-related data.

[0073] 203, the data saved during this period will be stored in the private storage address of this period.

[0074] In other words, the relevant data on site will be stored in private storage through M / P consecutive cycles, and the storage location is from i*M / P to i*M / P+(M / P-1).

[0075] In addition, after the pipeline is restored, you can switch to a new thread to continue executing the program.

[0076] By using steps 101 and 102, hardware thread-related data can be stored based on a single PackSave instruction, reducing hardware thread switching time and improving hardware thread switching speed.

[0077] Figure 2 This diagram illustrates a method for saving hardware thread-related context data. Upon receiving a PackSave instruction (which carries a thread identifier), the processor blocks the pipeline, stopping the dispatch of new instructions into the pipeline. Within a continuous M / P cycle starting from the current cycle, each cycle determines its private memory address through the address generation unit, retrieves the register file information, logical register-physical register mapping table, condition register information, status register information, and other data saved within that cycle, and stores this data at the private memory address for that cycle.

[0078] In addition, to ensure the completion of the synchronization instruction, after the program execution direction control unit confirms the need for context saving, before executing step 101, the program execution direction control unit will send a Fence instruction (i.e., the program execution direction control unit sends the first Fence instruction). This Fence instruction is used to ensure the completion of the instruction execution.

[0079] To distinguish it from the Fence command sent during scene restoration, this embodiment and subsequent embodiments name the Fence command sent during scene saving as the first Fence command. That is, the "first" here is only used to identify the Fence command in different processes and has no other meaning; the first Fence command is actually a single Fence command. Therefore, the first Fence command is used to ensure that the command execution is complete.

[0080] After receiving the first Fence instruction, the processor checks if there are any unfinished instructions. If so, it waits until all unfinished instructions have been executed. If there are no unfinished instructions, the processor proceeds to step 102 (i.e., the processor blocks the pipeline based on the PackSave instruction, stops dispatching new instructions into the pipeline, saves relevant context data according to the thread identifier, and restores the pipeline).

[0081] Figure 3This embodiment illustrates the implementation process of saving the execution context using the hardware thread switching method. After receiving the Fence instruction, the processor checks for any unfinished instructions. If unfinished instructions exist, it waits until all unfinished instructions are completed. If no unfinished instructions exist, the processor blocks the pipeline based on the PackSave instruction, stopping the dispatch of new instructions into the pipeline. The relevant context data is saved to private storage according to the thread identifier. The pipeline is then restored, and the program is switched to a new thread to continue execution.

[0082] After saving the relevant data of the hardware thread, it is also possible to restore the state.

[0083] If the program execution direction control unit confirms that on-site restoration is required, it is achieved through steps 301 and 302.

[0084] 301, The program execution direction control unit sends the PackRestore command.

[0085] The PackRestore instruction is used to trigger the restoration of the current state. The PackRestore instruction also carries a thread identifier.

[0086] 302. The processor, based on the PackRestore instruction, blocks the pipeline, stopping the dispatch of new instructions into the pipeline. It restores the relevant context data based on the thread identifier. The pipeline is then restored.

[0087] The relevant data at the site includes, but is not limited to: register file information, logical register-physical register mapping table, condition register information, and status register information.

[0088] In practice, the process of restoring relevant data based on thread identifiers can be achieved through M / P cycles. That is, all relevant data in the field can be restored based on thread identifiers through M / P consecutive cycles.

[0089] Where M is the total amount of on-site related data for the hardware thread, and P is the amount of data per row in the private storage.

[0090] When restoring relevant data based on thread identifiers through M / P consecutive cycles, the following steps 401-403 are executed in each cycle:

[0091] 401. Determine the private storage address for this cycle based on the thread identifier.

[0092] The private storage address is used to access private storage, and the private storage address is different for each hardware thread.

[0093] For example, the private storage address of any period j is determined to be i*M / P+j.

[0094] Where i is the thread identifier, i = 0, ..., n-1, n is the total number of hardware threads supported by the processor, and j is the cycle identifier, j = 0, ..., M / P-1.

[0095] 402, Read data from private storage address.

[0096] The data read from the private storage address is a part of the field-related data, and the data read from the private storage address is different in each cycle. The sum of the data read from the private storage address in M / P cycles is the field-related data.

[0097] 403. Write the data read from the private storage address into the register file, the logical register-physical register mapping table, the condition register, and the status register.

[0098] In other words, the relevant data on site will be read from the storage location and restored through M / P consecutive cycles, and the reading location is from i*M / P to i*M / P+(M / P-1).

[0099] In addition, after the pipeline is restored, you can switch to a new thread to continue executing the program.

[0100] By using steps 301 and 302, hardware thread context-related data can be restored based on a single PackRestore instruction, reducing hardware thread switching time and improving hardware thread switching speed.

[0101] Figure 4 This diagram illustrates a method for restoring hardware thread-related context data. Upon receiving a PackRestore instruction (which carries a thread identifier), the processor blocks the pipeline, preventing the dispatch of new instructions. Within a continuous M / P cycle starting from the current cycle, each cycle determines its private memory address using the address generation unit, reads data from that private memory address, and writes the data to the register file, the logical register-physical register mapping table, the condition register, and the status register.

[0102] In addition, to ensure the completion of the synchronization command, after the program execution direction control unit confirms the need for field restoration, before executing step 301, the program execution direction control unit will send a Fence command (i.e., the program execution direction control unit sends a second Fence command). This Fence command is used to ensure the completion of the command execution.

[0103] To distinguish it from the Fence command sent during site saving, this embodiment and subsequent embodiments name the Fence command sent during site restoration as the second Fence command. That is, the "second" here is only used to identify the Fence command in a different process and has no other meaning; the second Fence command is actually a single Fence command. Therefore, the second Fence command is used to ensure that the command execution is complete.

[0104] After the processor receives the second Fence instruction, it checks if there are any unfinished instructions. If so, it waits until all unfinished instructions have been executed. Only after confirming that there are no unfinished instructions will the processor execute step 302 (i.e., the processor blocks the pipeline based on the PackRestore instruction, stops dispatching new instructions into the pipeline, restores the relevant context data according to the thread identifier, and restores the pipeline).

[0105] Figure 5 This embodiment illustrates the implementation process of context restoration using the hardware thread switching method provided. After receiving the Fence instruction, the processor checks for any unfinished instructions. If unfinished instructions exist, it waits until all unfinished instructions are completed. If no unfinished instructions exist, the processor blocks the pipeline based on the PackRestore instruction, stopping the dispatch of new instructions into the pipeline. Data is read from private storage according to the thread identifier, and context-related data is restored. The pipeline is then restored, and the program is switched to a new thread to continue execution.

[0106] The hardware thread switching method provided in this embodiment achieves fast switching of hardware threads through three instructions (PackSave, PackRestore, Fence).

[0107] PackSave is used to quickly save the current state, PackRestore is used to quickly restore the current state, and Fence is used to synchronize the execution of commands.

[0108] Meanwhile, an SRAM (Static Random-Access Memory) is used as private storage to store the context information of the hardware thread.

[0109] During context saving, 1) the program execution direction control unit first sends a Fence instruction to ensure that previously sent instructions have been executed, and then sends a PackSave instruction. The PackSave instruction carries a thread ID, indicating the thread identifier for which hardware thread context saving is to be performed. 2) Upon receiving the PackSave instruction, the processor blocks the pipeline and no longer dispatches new instructions into the pipeline. 3) In the first cycle, the processor calculates the private memory address for the first cycle based on the thread identifier of the PackSave instruction, retrieves the data to be saved in the first cycle, and writes the data to be saved in the private memory according to the private memory address. In the second cycle, the processor calculates the private memory address for the second cycle based on the thread identifier of the PackSave instruction, retrieves the data to be saved in the second cycle, and writes the data to be saved in the private memory according to the private memory address. … In the M / P cycle, the processor calculates the private memory address of the M / P cycle based on the thread identifier of the PackSave instruction, obtains the data to be saved in the M / P cycle, and writes the data to be saved in the second cycle into the private memory according to the private memory address of the M / P cycle.

[0110] In this way, all data of the hardware thread (including register file information, logical register-physical register mapping table, condition register information, and status register information) is saved in M / P cycles, the pipeline is restored, and the program is switched to a new thread to continue execution.

[0111] When data is saved to private storage, there is a one-to-one correspondence between the hardware thread and its address in the private storage.

[0112] The address of the private memory is calculated as follows:

[0113] If the processor supports N hardware threads, and each hardware thread needs to store M bits of data, including: register file information, logical register-physical register mapping table, condition register information, and status register information, and these data are stored in private storage in a fixed order and in cycles, with each line of data in private storage containing P bits, then storing one hardware thread requires M / P lines of data, and the write cycle also requires M / P. The address of each hardware thread is: [i*M / P, i*M / P+(M / P-1)].

[0114] During context restoration: 1) The program execution direction control unit first sends a Fence instruction to ensure that previously sent instructions have been executed, and then sends a PackRestore instruction. The PackSave instruction carries a thread ID, indicating the thread identifier for which hardware thread context restoration is being performed. 2) Upon receiving the PackRestore instruction, the processor blocks the pipeline and no longer dispatches new instructions into the pipeline. 3) In the first cycle, the processor calculates the private memory address for the first cycle based on the thread identifier of the PackRestore instruction, reads the data to be restored from that address in the private memory, and writes the data to be restored in the first cycle into the register file, the logical register-physical register mapping table, the condition register, and the status register. In the second cycle, the processor calculates the private memory address for the second cycle based on the thread identifier of the PackRestore instruction, reads the data to be restored from that address in the private memory, and writes the data to be restored in the second cycle into the register file, the logical register-physical register mapping table, the condition register, and the status register. … During the M / P cycle, the processor calculates the private memory address of the M / P cycle based on the thread identifier of the PackRestore instruction, reads the data to be restored in the M / P cycle from the private memory address of the M / P cycle, and writes the data to be restored in the M / P cycle into the register file, the logical register-physical register mapping table, the condition register, and the status register.

[0115] In this way, all thread data is restored in M / P cycles, the pipeline is restored, and the program is switched to a new thread to continue execution. The data in PackRestore is in the same order as the data saved in PackSave.

[0116] This embodiment provides a hardware thread switching method. The program execution direction sends a PackSave instruction to the control unit. The PackSave instruction triggers the saving of the current state and carries a thread identifier. Based on the PackSave instruction, the processor blocks the pipeline, stopping the dispatch of new instructions into the pipeline. It saves relevant data based on the thread identifier and then restores the pipeline. The relevant data includes, but is not limited to, register file information, logical register-physical register mapping tables, condition register information, and status register information. The method provided in this embodiment can achieve hardware thread switching with a single PackSave instruction, reducing hardware thread switching time and improving hardware thread switching speed.

[0117] Based on the same inventive concept of hardware thread switching method, this embodiment provides an electronic device, including: a program execution direction control unit, a processor and private storage.

[0118] The program execution direction control unit is used in the program execution direction control unit step of the hardware thread switching method.

[0119] The processor is used to execute the processor steps in the hardware thread switching method.

[0120] Private storage is used to store all relevant data for the hardware thread's execution state. The specific private storage addresses for the execution state-related data differ for each hardware thread.

[0121] Specifically,

[0122] The program execution direction control unit sends a PackSave command; the PackSave command is used to trigger saving the context, and the PackSave command carries a thread identifier;

[0123] The processor uses the PackSave instruction to block the pipeline, stopping the dispatch of new instructions into the pipeline; saves relevant context data based on thread identifiers; and restores the pipeline.

[0124] The relevant data at the site includes, but is not limited to: register file information, logical register-physical register mapping table, condition register information, and status register information.

[0125] Optionally, relevant on-site data can be saved based on the thread identifier, including:

[0126] By continuously performing M / P cycles, relevant on-site data is saved according to the thread identifier;

[0127] Where M is the total amount of on-site related data for the hardware thread, and P is the amount of data per row in the private storage.

[0128] Optionally, relevant field data is saved based on the thread identifier over M / P consecutive cycles, including:

[0129] Within each cycle, perform the following steps:

[0130] Based on the thread identifier, determine the private storage address for that cycle; the private storage address is used to access private storage, and the private storage address is different for each hardware thread;

[0131] Retrieve the data saved within this period; wherein, the data saved within this period is a part of the relevant field data, and the data saved in each period is different, and the sum of the data saved in M / P periods is all the relevant field data;

[0132] The data saved during this period will be stored in the private storage address of this period.

[0133] Optionally, after saving the relevant data based on the thread identifier, the method further includes:

[0134] The program execution direction control unit sends a PackRestore command; the PackRestore command is used to trigger the restoration of the context; and the PackRestore command carries a thread identifier;

[0135] The processor uses the PackRestore instruction to block the pipeline, stop dispatching new instructions into the pipeline, restore the relevant context data based on the thread identifier, and restore the pipeline.

[0136] Optionally, restore relevant data from the current state based on the thread identifier, including:

[0137] By performing M / P consecutive cycles, the relevant data at the scene is restored based on the thread identifier;

[0138] Where M is the total amount of on-site related data for the hardware thread, and P is the amount of data per row in the private storage.

[0139] Optionally, relevant field data is restored based on the thread identifier through M / P consecutive cycles, including:

[0140] Within each cycle, perform the following steps:

[0141] Based on the thread identifier, determine the private storage address for that cycle; the private storage address is located within private storage, and the private storage address is different for each hardware thread;

[0142] Data is read from a private storage address; the data read from the private storage address is a part of the field-related data, and the data read from the private storage address is different in each cycle. The sum of the data read from the private storage address in M / P cycles is the field-related data.

[0143] The data read from the private storage address is written into the register file, the logical register-physical register mapping table, the condition register, and the status register.

[0144] Optionally, the private storage address for this cycle is determined based on the thread identifier, including:

[0145] The private storage address for this period is set to i*M / P+j;

[0146] Where i is the thread identifier, i = 0, ..., n-1, n is the total number of hardware threads supported by the processor, and j is the cycle identifier, j = 0, ..., M / P-1.

[0147] Optionally, before the program execution direction control unit sends the PackSave command, it also includes:

[0148] The program execution direction control unit sends a first Fence command; the first Fence command is used to ensure that the command is executed completely.

[0149] The processor, based on the PackSave instruction, blocks the pipeline and stops dispatching new instructions into the pipeline. This includes:

[0150] After the processor receives the first Fence instruction, it confirms that there are no instructions that have not been completed.

[0151] Optionally, before the program executes the direction control unit to send the PackRestore command, it also includes:

[0152] The program execution direction control unit sends a second Fence command; the second Fence command is used to ensure that the command is executed.

[0153] Before the processor blocks the pipeline based on the PackRestore instruction and stops dispatching new instructions into the pipeline, it also includes:

[0154] After the processor receives the second fence instruction, it confirms that there are no instructions that have not been completed.

[0155] In the electronic device provided in this embodiment, the program execution direction sends a PackSave instruction to the control unit. The PackSave instruction triggers the saving of the current state and carries a thread identifier. Based on the PackSave instruction, the processor blocks the pipeline, stopping the dispatch of new instructions into the pipeline. It saves the relevant data based on the thread identifier and then resumes the pipeline. The relevant data includes, but is not limited to, register file information, logical register-physical register mapping tables, condition register information, and status register information. The electronic device provided in this embodiment can achieve hardware thread switching with a single PackSave instruction, reducing hardware thread switching time and improving hardware thread switching speed.

[0156] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of this application can be implemented in various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0157] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0158] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0159] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0160] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0161] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0162] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A hardware thread switching method, characterized in that, The method includes: The program execution direction control unit sends a first Fence command; wherein, the first Fence command is used to ensure that the command is executed completely; The program execution direction control unit sends a PackSave command; wherein, the PackSave command is used to trigger saving the context, and the PackSave command carries a thread identifier; After the processor receives the first Fence instruction, if there are any unexecuted instructions, it waits until all unexecuted instructions have been executed; then it confirms that there are no unexecuted instructions. Based on the PackSave instruction, the processor blocks the pipeline, stops dispatching new instructions into the pipeline, and saves relevant context data according to the thread identifier. The program execution direction control unit sends a second Fence command; wherein, the second Fence command is used to ensure that the command is executed; the second Fence command refers to the Fence command sent during the field restoration; The program execution direction control unit sends a PackRestore instruction; wherein, the PackRestore instruction is used to trigger the restoration of the context; and the PackRestore instruction carries a thread identifier; After the processor receives the second Fence instruction, it checks whether there are any unexecuted instructions. If there are unexecuted instructions, it waits until all unexecuted instructions have been executed; otherwise, it checks whether there are any unexecuted instructions. The processor, based on the PackRestore instruction, blocks the pipeline, stops dispatching new instructions into the pipeline, restores relevant context data according to the thread identifier, and restores the pipeline. The field-related data includes, but is not limited to: register file information, logical register-physical register mapping table, condition register information, and status register information.

2. The method according to claim 1, characterized in that, The step of saving relevant data based on the thread identifier includes: By continuously performing M / P cycles, relevant on-site data is saved according to the thread identifier; Where M is the total amount of on-site related data for the hardware thread, and P is the amount of data per row in the private storage.

3. The method according to claim 1, characterized in that, Through consecutive M / P cycles, relevant on-site data is saved according to the thread identifier, including: Within each cycle, perform the following steps: Based on the thread identifier, the private storage address for that cycle is determined; wherein, the private storage address is used to access private storage, and the private storage address is different for each hardware thread; Retrieve the data saved within this period; wherein, the data saved within this period is a part of the relevant field data, and the data saved in each period is different, and the sum of the data saved in M / P periods is all the relevant field data; The data saved during this period will be stored in the private storage address of this period.

4. The method according to claim 3, characterized in that, The step of restoring relevant on-site data based on the thread identifier includes: The relevant data at the scene is restored based on the thread identifier through M / P consecutive cycles; Where M is the total amount of on-site related data for the hardware thread, and P is the amount of data per row in the private storage.

5. The method according to claim 4, characterized in that, The process of restoring relevant on-site data based on the thread identifier through M / P consecutive cycles includes: Within each cycle, perform the following steps: Based on the thread identifier, the private storage address for this cycle is determined; wherein, the private storage address is located in private storage, and the private storage address is different for each hardware thread; Data is read from the private storage address; wherein the data read from the private storage address is a part of the field-related data, and the data read from the private storage address in each period is different, and the sum of the data read from the private storage address in M / P periods is the field-related data; The data read from the private storage address is written into the register file, the logical register-physical register mapping table, the condition register, and the status register.

6. The method according to claim 5, characterized in that, The step of determining the private storage address for this period based on the thread identifier includes: The private storage address for this period is set to i. M / P+j; Where i is the thread identifier, i=0,…,n-1, n is the total number of hardware threads supported by the processor, and j is the cycle identifier, j=0,…,M / P-1.

7. An electronic device, characterized in that, include: The program execution direction control unit, processor, and private storage; The program execution direction control unit is used to perform the steps of the program execution direction control unit in the method as described in any one of claims 1-6; The processor is configured to perform the steps of the processor in the method as described in any one of claims 1-6; The private storage is used to store all relevant data of the hardware thread in the field; wherein, the private storage address of the relevant data of each hardware thread is different in the private storage.

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