Display panel and display device

Abstract

The invention provides a display panel and a display device, a pixel circuit in the display panel comprises a driving transistor and a first switch transistor, a control part of the driving transistor is electrically connected with a first pole of the first switch transistor, and a control part of the first switch transistor comprises a first control part and a second control part. The first conductive layer is arranged on one side of the substrate and comprises a first conductive part, the active layer is arranged on the side, away from the substrate, of the first conductive layer and comprises a first channel part, and the orthographic projection of the first channel part on the substrate and the orthographic projection of the first control part on the substrate are arranged in an overlapped mode. The first channel portion is electrically connected to a first pole of the first switching transistor. The second conductive layer is arranged on the side, away from the substrate, of the active layer. The second conductive layer comprises a first control part and a second control part. Wherein the orthographic projection of the first conductive part on the substrate and the orthographic projection of the first channel part on the substrate are overlapped, and the first conductive part receives a transformation signal.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and in particular to a display panel and a display device. Background Art

[0002] With the continuous development of display technologies such as liquid crystal display (LCD) and organic light-emitting diode (OLED) displays, display panels are widely used in various industries. However, current display panels may still experience screen flickering during use, affecting the user's viewing experience. Summary of the Invention

[0003] Embodiments of the present application provide a display panel and a display device, which can improve the flicker problem.

[0004] In a first aspect, embodiments of the present application provide a display panel comprising a pixel circuit and a subpixel. The pixel circuit drives and controls the subpixel. The pixel circuit comprises a driving transistor and a first switching transistor. The control portion of the driving transistor is electrically connected to the first electrode of the first switching transistor. The control portion of the first switching transistor comprises a first control portion and a second control portion. The display panel further comprises a substrate. A first conductive layer, an active layer, and a second conductive layer. The first conductive layer is disposed on one side of the substrate and comprises a first conductive portion. The active layer is disposed on a side of the first conductive layer facing away from the substrate. The active layer comprises a first channel portion. The orthographic projection of the first channel portion on the substrate overlaps the orthographic projection of the first control portion on the substrate. The first channel portion is electrically connected to the first electrode of the first switching transistor. The second conductive layer is disposed on a side of the active layer facing away from the substrate and comprises a first control portion and a second control portion. The orthographic projection of the first conductive portion on the substrate overlaps the orthographic projection of the first channel portion on the substrate, and the first conductive portion receives a voltage-modified signal.

[0005] In a second aspect, an embodiment of the present application provides a display device, which includes the display panel in any of the aforementioned embodiments.

[0006] Embodiments of the present application provide a display panel and display device. A first conductive layer is added to the display panel. The first conductive layer is located on the side of the active layer facing away from the second conductive layer. The first conductive layer includes a first conductor portion, the orthographic projection of the first conductor portion on the substrate overlapping the orthographic projection of the first channel portion on the substrate. Based on this, when a first switching transistor transitions from an on state to an off state, a specific signal voltage is transmitted into the first conductor portion, thereby changing the electrical conductivity of the first channel portion. This adjusts the leakage between the intermediate node and the first node of the first switching transistor, thereby improving the problem of display flicker.

[0007] Furthermore, the first conductor portion receives a variable voltage signal rather than a constant voltage signal, meaning that the signal voltage of the first conductor portion varies at different times. By limiting and adjusting the timing of the variable voltage signal, the first conductor portion can mitigate leakage in the first channel portion during the transition from the on state to the off state of the first switching transistor. However, the first conductor portion has less impact on the first channel portion when the first switching transistor is either on or off. This mitigates display flicker without affecting the normal operation of the first switching transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0009] Figure 1 This is a schematic diagram of the layout structure of a pixel circuit in a display panel provided by an embodiment of the present application;

[0010] Figures 2a to 2d 1 is a schematic diagram of a partial structure of a first switch transistor in a display panel and the structures of each film layer in the first switch transistor provided by an embodiment of the present application;

[0011] Figure 3 This embodiment of the present application provides Figure 2a Schematic diagram of the cross-sectional structure at AA in the middle;

[0012] Figure 4 This is a simplified circuit diagram of a pixel circuit in a display panel provided by an embodiment of the present application;

[0013] Figure 5 This is a timing diagram corresponding to a pixel circuit in a display panel provided by an embodiment of the present application;

[0014] Figure 6 This is a schematic diagram of the layout structure of a pixel circuit in another display panel provided in an embodiment of the present application;

[0015] Figure 7 This is a partial structural diagram of a first switch transistor in another display panel provided by an embodiment of the present application;

[0016] Figure 8 This is a schematic diagram of the layout structure of a pixel circuit in a display panel provided in an embodiment of the present application;

[0017] Figure 9 This is a schematic structural diagram of a first conductive layer in another display panel provided in an embodiment of the present application;

[0018] Figure 10 This is a schematic diagram of a partial layout structure of another display panel provided in an embodiment of the present application;

[0019] Figure 11 This is a schematic structural diagram of an active layer in another display panel provided in an embodiment of the present application;

[0020] Figure 12 This is a schematic diagram of the layout structure of a pixel circuit in a display panel provided in an embodiment of the present application;

[0021] Figure 13 This is a schematic diagram of the layout structure of a pixel circuit in a display panel provided in an embodiment of the present application;

[0022] Figure 14 This is a schematic diagram of the layout structure of a pixel circuit in a display panel provided in an embodiment of the present application;

[0023] Figure 15 This is a schematic structural diagram of a first conductive layer in another display panel provided in an embodiment of the present application;

[0024] Figure 16 This is a schematic diagram of the layout structure of a pixel circuit in a display panel provided in an embodiment of the present application;

[0025] Figure 17 This is a schematic structural diagram of a first conductive layer in another display panel provided in an embodiment of the present application;

[0026] Figure 18 This is a schematic diagram of the layout structure of a pixel circuit in a display panel provided in an embodiment of the present application;

[0027] Figure 19 This is a schematic structural diagram of a first conductive layer in another display panel provided in an embodiment of the present application;

[0028] Figure 20 It is a structural schematic diagram of a display device provided in an embodiment of the present application.

[0029] Marking Description:

[0030] 10. Pixel circuit; 11. Driving transistor; 12. First switching transistor; 121. First control unit; 122. Second control unit; 13. Second switching transistor; 14. First transistor;

[0031] 20. Sub-pixel;

[0032] 30. substrate;

[0033] 40. First conductive layer; 41. First conductor portion; 411. First subsegment; 412. Second subsegment; 413. Connecting segment; 414. Third subsegment; 415. Fourth subsegment; 42. Second conductor portion; 43. Third conductor portion; 44. Connecting portion;

[0034] 50. Active layer; 51. First channel portion; 52. Second channel portion; 53. Third channel portion; 54. Fourth channel portion; 55. Fifth channel portion;

[0035] 60. Second conductive layer; 61. First scanning line;

[0036] 70. third conductive layer;

[0037] H, first via;

[0038] X, first direction; Y, second direction; DETAILED DESCRIPTION

[0039] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0040] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

[0041] First, see Figures 1 to 7An embodiment of the present application provides a display panel, comprising a pixel circuit 10 and a sub-pixel 20. The pixel circuit 10 drives and controls the sub-pixel 20. The pixel circuit 10 includes a driving transistor 11 and a first switching transistor 12. The control portion of the driving transistor 11 is electrically connected to the first electrode of the first switching transistor 12. The control portion of the first switching transistor 12 includes a first control portion 121 and a second control portion 122. The display panel also includes a substrate 30, a first conductive layer 40, an active layer 50, and a second conductive layer 60. The first conductive layer 40 is disposed on one side of the substrate 30 and includes a first conductive portion. The active layer 50 is disposed on a side of the first conductive layer 40 facing away from the substrate 30. The active layer 50 includes a first channel portion 51. The orthographic projection of the first channel portion 51 on the substrate 30 overlaps with the orthographic projection of the first control portion 121 on the substrate 30. The first channel portion 51 is electrically connected to the first electrode of the first switching transistor 12. The second conductive layer 60 is disposed on a side of the active layer 50 facing away from the substrate 30. The second conductive layer 60 includes a first control portion 121 and a second control portion 122. The orthographic projection of the first conductive portion on the substrate 30 overlaps the orthographic projection of the first channel portion 51 on the substrate 30, and the first conductive portion receives a voltage-modified signal.

[0042] The display panel provided in the embodiments of the present application can be of various types. For example, the display panel can be an organic light-emitting display panel or a liquid crystal display panel. The sub-pixel 20 is the main structure in the display panel for achieving the light-emitting function. When the display panel is an organic light-emitting display panel, the sub-pixel 20 may include an organic light-emitting material, an anode and a cathode located on either side of the organic light-emitting material. When the display panel is a liquid crystal display panel, the sub-pixel 20 may include a liquid crystal structure, pixel electrodes located on either side of the liquid crystal structure, and a common electrode.

[0043] The pixel circuit 10 is a circuit structure in the display panel that controls whether the sub-pixel 20 emits light. The pixel circuit 10 can have various forms. For example, the pixel circuit 10 can have a 7T1C structure, that is, the pixel circuit 10 includes seven thin-film transistors and a storage capacitor, or the pixel circuit 10 can have an 8T1C structure, etc., which is not limited in the embodiments of the present application. Each thin-film transistor includes a control unit, a first electrode, and a second electrode. The control unit is used to control whether the first electrode and the second electrode are conductive.

[0044] For ease of understanding, the embodiments of the present application are described below using the pixel circuit 10 being 7T1C and the display panel being an organic light emitting display panel as an example. Figure 4 FIG. 1 shows a schematic circuit diagram corresponding to the pixel circuit 10 when the pixel circuit 10 is 7T1C. Figure 1 and Figure 6 shows the corresponding layout structure when the pixel circuit 10 is 7T1C, Figure 5FIG. 2 shows a circuit timing diagram corresponding to when the pixel circuit 10 is in 7T1C state.

[0045] The pixel circuit 10 includes a driving transistor 11, a first switching transistor 12 and five other switching transistors. The driving transistor 11 is a transistor T3. The control part of the driving transistor 11 is electrically connected to the first node N1, and the control part of the driving transistor 11 can be reused as a plate structure of the storage capacitor C. The first electrode of the driving transistor 11 receives the first power supply signal VDD.

[0046] The control unit of the first switch transistor 12 receives a scan signal, and the first electrode of the first switch transistor 12 is electrically connected to the control unit of the control transistor, that is, the first electrode of the first switch transistor 12 is electrically connected to the first node N1. The first switch transistor 12 mentioned in the embodiment of the present application can be a transistor T4, or it can also be a transistor T5, and the embodiment of the present application is not limited to this. The scan signal includes a first scan signal scan1 and a second scan signal scan2. When the first switch transistor 12 is a transistor T4, the control unit of the first switch transistor 12 receives the second scan signal scan2, and the second electrode of the first switch transistor 12 is electrically connected to the second electrode of the transistor T3. When the first switch transistor 12 is a transistor T5, the control unit of the first switch transistor 12 receives the first scan signal scan1, and the second electrode of the first switch transistor 12 receives the first reset signal Vref1.

[0047] Figure 1 FIG shows a case where the first switching transistor 12 is a transistor m4, and Figures 2a to 2d for Figure 1 Schematic diagram of the local structure of the first switch transistor 12 and the film layer structure of the first switch transistor 12. Figure 6 FIG shows a case where the first switching transistor 12 is a transistor m5, and Figure 7 for Figure 6 FIG. 1 is a schematic diagram of a partial structure of the first switch transistor 12 in FIG.

[0048] Next, the embodiment of the present application will briefly introduce the operation process of the pixel circuit 10. Figure 4 and Figure 5 As shown, within a frame time I, the pixel circuit 10 may include a reset stage, a charging stage, and a light-emitting stage. The reset stage corresponds to the t1 period. In the reset stage, the control parts of the switching transistor T5 and the transistor T7 are turned on by the low level of the first scanning signal Scan1, the first reset signal Vref1 is applied to the first node N1, and the control part of the driving transistor 11 and a plate structure of the storage capacitor C are reset, and the second reset signal Vref2 is applied to the anode of the sub-pixel 20, and the anode of the sub-pixel 20 is reset.

[0049] The charging phase corresponds to the t2 period, during which transistors T4 and T2 are turned on by the low level of the second scan signal scan2. The data signal passes through transistors T2, T3, and T4 to charge the first node N1 (i.e., to charge a plate structure of the storage capacitor C), and the potential at the first node N1 increases. According to the characteristics of transistor T3, the potentials of the first node N1 and the third node N3 can increase to Vdata+Vth during the charging process. Vdata represents the voltage value of the data signal Data, and Vth represents the threshold voltage of transistor T3. Since transistor T3 is described as a PMOS transistor, the threshold voltage Vth is a negative value.

[0050] The light-emitting stage is the t3 period. At this time, the transistors T1 and T6 are turned on by the low level of the light-emitting signal Emit, and the potential maintained at the first node N1 causes the transistor T3 to be turned on as well. The first power supply signal VDD is applied to the anode of the sub-pixel 20 after passing through the transistors T1, T3 and T6, and the second power supply signal VEE is applied to the cathode of the sub-pixel 20. Under the joint drive of the anode and cathode of the sub-pixel 20, the organic light-emitting material in the sub-pixel 20 realizes the light-emitting function.

[0051] It should be noted that the structures shown in the drawings are all described as PMOS transistors (low level is on, high level is off). In the actual pixel circuit 10, some or all of the transistors can be adjusted to NMOS transistors (high level is on, low level is off).

[0052] The control unit of the first switching transistor 12 includes a first control unit 121 and a second control unit 122, meaning that the first switching transistor 12 has a dual-gate structure. Both the first control unit 121 and the second control unit 122 are located in the second conductive layer 60, meaning that the first control unit 121 and the second control unit 122 are made of the same material and are fabricated together in the same process. The first control unit 121 and the second control unit 122 receive the same signal. Specifically, when the first switching transistor 12 is transistor T4, both the first control unit 121 and the second control unit 122 receive the second scan signal scan2. When the first switching transistor 12 is transistor T5, both the first control unit 121 and the second control unit 122 receive the first scan signal scan1.

[0053] The active layer 50 is a film structure comprising semiconductor materials in the display panel. The active layer 50 includes a first channel portion 51, which overlaps with the first control portion 121 in an orthographic projection on the substrate 30. In addition to the first channel portion 51, the active layer 50 also includes a second channel portion 52, which overlaps with the second control portion 122 in an orthographic projection on the substrate 30. The first communication portion and the second channel portion 52 both form the channel structure of the first switching transistor 12. The first control portion 121 and the first channel portion 51 together form a first sub-transistor, and the second control portion 122 and the second channel portion 52 together form a second sub-transistor. The first sub-transistor and the second sub-transistor are arranged in series to form the first switching transistor 12.

[0054] It should be noted that the active layer 50 can be composed of a variety of materials, which are not limited in the present embodiment. For example, the first switching transistor 12 can be an IGZO (Indium Gallium Zinc Oxide)-TFT, in which case the material of the active layer 50 includes a metal oxide, or the first switching transistor 12 can be an LTPS (Low Temperature Poly-Silicon)-TFT, in which case the material of the active layer 50 includes low temperature polysilicon.

[0055] Compared to a single-gate transistor, configuring the first switch transistor 12 as a dual-gate transistor helps improve the stability of the first switch transistor 12 under high-frequency operation. However, there is an intermediate node between the first sub-transistor and the second sub-transistor. When the first switch transistor 12 is the transistor T4, the intermediate node of the first switch transistor 12 is the fifth node N5. When the first switch transistor 12 is the transistor T2, the intermediate node of the first switch transistor 12 is the sixth node N6.

[0056] When the first switching transistor 12 is in the on state, the voltage of the intermediate node is usually the same as or close to the first node N1. However, when the first switching transistor 12 switches from the on state to the off state, the voltage at the control unit of the first switching transistor 12 suddenly rises from a low level to a high level, which causes the voltage at the intermediate node to be easily coupled to a larger potential, resulting in a large voltage difference between the intermediate node and the first node, which in turn causes leakage between the two, that is, leakage is likely to occur in the first channel portion 51. Typically, the leakage problem in the first channel portion 51 is usually continuous. During the light-emitting stage, the first channel portion 51 will continue to leak, causing the display screen to flicker, affecting the actual viewing experience.

[0057] To address this issue, the embodiment of the present application adds a first conductive layer 40 to the display panel. The first conductive layer 40 is located on the side of the active layer 50 facing away from the second conductive layer 60. The first conductive layer 40 includes a first conductor portion 41. The orthographic projection of the first conductor portion 41 on the substrate 30 overlaps with the orthographic projection of the first channel portion 51 on the substrate 30. Based on this, when the first switching transistor 12 transitions from an on state to an off state, the electrical conductivity of the first channel portion 51 can be changed by transmitting a specific signal voltage into the first conductor portion 41. This adjusts the leakage level between the intermediate node of the first switching transistor 12 and the first node N1, thereby improving the display flicker problem.

[0058] Furthermore, the first conductor portion 41 receives a variable voltage signal rather than a constant voltage signal, meaning that the signal voltage of the first conductor portion varies at different times. By limiting and adjusting the timing of the variable voltage signal, the first conductor portion 41 can mitigate leakage in the first channel portion 51 during the transition from the on state to the off state of the first switching transistor 12. However, the first conductor portion 41 has minimal impact on the first channel portion 51 when the first switching transistor 12 is either on or off. This mitigates display flicker without affecting the normal operation of the first switching transistor 12.

[0059] In addition, since the first conductor portion 41 is located on the side of the first channel portion 51 facing the substrate 30, the presence of the first conductor portion 41 also helps to reduce the amount of reflected light propagating to the first channel portion 51, reduce the impact of the reflected light inside the display panel on the performance of the first switching transistor 12, and improve the operating reliability of the display panel.

[0060] It should be noted that the specific timing and specific voltage values ​​of the voltage-changing signal are not limited in the embodiments of the present application. In some optional embodiments, during the process of the first switching transistor 12 transitioning from the on state to the off state, the signal voltage received by the first control unit 121 suddenly changes to a high-level voltage, while the voltage-changing signal received by the first conductor portion 41 is a low-level voltage. Thus, the electric field formed by the first control unit 121 is in the opposite direction to the electric field formed by the first conductor. Since the first control unit 121 and the first conductor portion 41 are located on either side of the first channel portion 51, the combined action of these two oppositely directed electric fields can more quickly form induced charges on the surface of the first channel portion 51, and even form an inversion layer. This causes the threshold voltage of the first switching transistor 12 to be positively biased, and accelerates the rate of leakage current movement within the first channel portion 51. This quickly maintains the potential of the first node N1 and the intermediate node within the first switching transistor 12 consistent, thereby reducing the leakage between the first node N1 and the intermediate node during the light-emitting phase. This makes the potential of the first node N1 more stable during the light-emitting phase, thereby improving the display flicker problem.

[0061] In other optional embodiments, during the process of the first switching transistor 12 transitioning from the on state to the off state, the signal voltage received by the first control unit 121 suddenly changes to a high-level voltage, while the transformed signal received by the first conductor portion 41 is a high-level voltage. Thus, the electric field formed by the first control unit 121 and the electric field formed by the first conductor are in the same direction. Since the first control unit 121 and the first conductor portion 41 are disposed on either side of the first channel portion 51, the combined action of these two electric fields in the same direction can slow down the rate at which induced charges are formed on the surface of the first channel portion 51, thereby causing the threshold voltage of the first switching transistor 12 to become negatively biased and reducing the generation of leakage current in the first channel portion 51. Consequently, during the light-emitting phase, only a small amount of leakage current exists in the first channel portion 51, or even no leakage current exists at all, thereby also helping to alleviate the problem of display flicker.

[0062] The embodiment of the present application does not impose any restrictions on the size relationship between the first conductor portion 41 and the first channel portion 51. The orthographic projection of the first conductor portion 41 on the substrate 30 may be completely located within the orthographic projection of the first channel portion 51 on the substrate 30, or may be partially located outside the orthographic projection of the first channel portion 51 on the substrate 30. Furthermore, one first conductor portion 41 may be arranged to overlap with only the first channel portion 51 in one pixel circuit 10, or one first conductor portion 41 may be arranged to overlap with the first channel portions 51 in multiple pixel circuits 10. In addition, the first conductor portion 41 may overlap only with the channel structure of the first switching transistor 12, or may overlap with the channel structures of other transistors. The embodiment of the present application also does not impose any restrictions on this.

[0063] In some embodiments, as Figure 1 Figure 2 Figure 6 as well as Figure 7 As shown, the active layer 50 includes a second channel portion 52, which is connected between the first channel portion 51 and the second electrode of the first switching transistor 12. The orthographic projection of the second channel portion 52 on the substrate 30 overlaps with the orthographic projection of the second control portion 122 on the substrate 30. The orthographic projection of the second channel portion 52 on the substrate 30 overlaps with the orthographic projection of the first conductor portion 41 on the substrate 30.

[0064] The first channel portion 51 and the second channel portion 52 are used to form the channel structure of the first switching transistor 12. The first channel portion 51 and the second channel portion 52 are spaced apart. Exemplarily, the active layer 50 further includes an intermediate section, which is a portion of the active layer 50 located between the first channel portion 51 and the second channel portion 52 and does not overlap with the first control portion 121 and the second control portion 122. The ends of the intermediate section are respectively connected to the first channel portion 51 and the second channel portion 52 and are integrally arranged. Further optionally, the first conductor portion 41 is arranged to overlap with both the first channel portion 51 and the second channel portion 52, and at least a portion of the intermediate section is located outside the orthographic projection of the first conductor portion 41 on the substrate 30.

[0065] In the embodiment of the present application, the orthographic projection of the first conductor portion 41 on the substrate 30 overlaps both the orthographic projection of the first channel portion 51 on the substrate 30 and the orthographic projection of the second channel portion 52 on the substrate 30. Thus, during the transition of the first switching transistor 12 from the on state to the off state, the first conductor portion 41 not only accelerates the leakage rate of the first channel portion 51 or improves leakage problems in the first channel portion 51, but also accelerates the leakage rate of the second channel portion 52 or improves leakage problems in the second channel portion 52. This helps further improve the potential stability of the first node N1 during the light-emitting phase, improves display flicker, and enhances the user experience. Furthermore, this design allows the orthographic projection of the first conductor portion 41 on the substrate 30 to form a large block structure, thereby reducing the resistance of the first conductor portion 41 and the difficulty of manufacturing. It also reduces the difficulty of aligning the first conductor portion 41 with the first switching transistor 12.

[0066] In some embodiments, as Figure 1 Figure 2 Figure 6 as well as Figure 7 As shown, the first conductor portion 41 is electrically connected to the first control portion 121 .

[0067] like Figure 1 and Figure 2aAs shown, when the first switch transistor 12 is transistor T4, the first control unit 121, the second control unit 122 and the first conductor unit 41 all receive the second scan signal scan2; when the first switch transistor 12 is transistor T5, the first control unit 121, the second control unit 122 and the first conductor unit 41 all receive the first scan signal scan1.

[0068] The embodiment of the present application does not limit the electrical connection between the first conductor part 41 and the first control part 121. For example, Figure 2a As shown, the first conductor portion 41 and the first control portion 121 can be connected through a first via H, and the orthographic projection of the first via H on the substrate 30 is located within the orthographic projection of the pixel circuit 10 on the substrate 30 .

[0069] In the embodiment of the present application, by electrically connecting the first conductor portion 41 to the first control portion 121, the first conductor portion 41 and the first control portion 121 have the same signal timing. As a result, when the first switching transistor 12 changes from an on state to an off state, the first conductor portion 41 and the first control portion 121 both become high-level voltages. In this way, under the joint action of the first conductor portion 41 and the first control portion 121, the generation of leakage current in the first channel portion 51 can be reduced. As a result, in the light-emitting stage, only a small amount of leakage current exists in the first channel portion 51, or even no leakage current exists. This also helps to improve the problem of display screen flicker.

[0070] Furthermore, because the first conductor portion 41 and the first control portion 121 receive the same signal, when the first switching transistor 12 is in the on state, both the first conductor portion 41 and the first control portion 121 are at a low level. Therefore, the presence of the first control portion 121 does not hinder the conduction of the first switching transistor 12. Similarly, when the first switching transistor 12 is in the off state, both the first conductor portion 41 and the first control portion 121 are at a high level. Therefore, the presence of the first control portion 121 does not cause the first switching transistor 12 to abnormally conduct, thereby improving the reliability of the first switching transistor 12.

[0071] In some embodiments, see Figure 8 and Figure 9 The second conductive layer 60 includes a first scan line 61 extending along a first direction X. The first scan line 61 is electrically connected to the first control unit 121 and the second control unit 122. The first direction X is parallel to the plane of the substrate 30. The first conductor portion 41 extends along the first direction X and is connected to the first scan line 61.

[0072] The first scan line 61 is a signal line for transmitting a specific scan signal to the first control unit 121 and the second control unit 122. When the first switch transistor 12 is the transistor T4, the first scan line 61 is used to transmit the second scan signal scan2. When the first switch transistor 12 is the transistor T5, the first scan line 61 is used to transmit the first scan signal scan1. The first scan line 61 is electrically connected to the first control unit 121 and the second control unit 122. For example, in combination Figure 2b and Figure 2d For example, a portion of the first scan line 61 that overlaps with the first channel portion 51 is multiplexed as the first control portion 121 , and a portion of the first scan line 61 that overlaps with the second channel portion 52 is multiplexed as the second control portion 122 .

[0073] It should be noted that the "first scan line 61 extending along the first direction X" mentioned in the embodiment of the present application means that the direction corresponding to the overall extension trend of the first scan line 61 is the first direction X, and does not limit the first scan line 61 to a straight structure extending along the first direction X. The "first conductor portion 41 extending along the first direction X" mentioned in the embodiment of the present application is similar to the above and will not be further described.

[0074] In some optional embodiments, taking the first switching transistor 12 as transistor T4 and the first scan line 61 for transmitting the second scan signal scan2 as an example, the first scan line 61 may include an integrally arranged main section and a protruding section. The main section is a linear structure extending along a first direction X, and the protruding section extends along a second direction Y and protrudes relative to the main section. The first direction X and the second direction Y are both parallel to the plane of the substrate 30 and intersect with each other. On this basis, the portion of the main section that overlaps with the first channel portion 51 is reused as the second control section 122, and the portion of the protruding section that overlaps with the second channel portion 52 is reused as the first control section 121.

[0075] There are various connection methods between the first conductor portion 41 and the first scan line 61. For example, when the orthographic projections of the first conductor portion 41 and the first scan line 61 on the substrate 30 overlap, the first conductor portion 41 and the first scan line 61 can be connected using a via structure. Alternatively, the first conductor portion 41 and the first scan line 61 can be connected using other switching traces, which is not limited in this embodiment of the present application.

[0076] In the embodiment of the present application, the first conductor portion 41 and the first scan line 61 are arranged to extend in the same direction so that the two can have the same extension trend. In this way, in the display panel in the first direction X corresponding to the areas where different pixel circuits 10 are located, the orthographic projections of the first scan line 61 and the first conductor portion 41 on the substrate 30 can have the same relative positional relationship, thereby reducing the difficulty of connecting the first scan line 61 and the first conductor portion 41 in different areas and helping to improve the reliability of the signal received by the first conductor portion 41.

[0077] In some embodiments, as Figure 8 and Figure 9 As shown, the orthographic projection of the first scanning line 61 on the substrate 30 overlaps with the orthographic projection of the first conductor portion 41 on the substrate 30 , and the first scanning line 61 and the first conductor portion 41 are connected through a first via H.

[0078] In combination with the foregoing, it can be seen that the first scan line 61 and the first conductor portion 41 can have the same extension direction. On this basis, the embodiment of the present application also arranges the first scan line 61 and the first conductor portion 41 to overlap in their orthographic projection on the substrate 30, so that the two can be connected by a first via H, thereby eliminating the need to add additional transfer lines in the display panel and simplifying the wiring layout inside the display panel.

[0079] Furthermore, this design helps reduce the effect of the presence of the first conductor portion 41 on the transmittance of a localized portion of the display panel, thereby improving the display uniformity of the display panel. The specific positional relationship between the first conductor portion 41 and the first scan line 61 is not limited in this embodiment of the present application. The orthographic projection of the first conductor portion 41 on the substrate 30 can be completely within the orthographic projection of the first scan line 61 on the substrate 30, or the orthographic projection of the first conductor portion 41 on the substrate 30 can be partially outside the orthographic projection of the first scan line 61 on the substrate 30.

[0080] It should be noted that the first via can have a variety of layout methods. For example, the orthographic projection of the first via on the substrate 30 can be located within the pixel circuit 10. In this case, the orthographic projection of the first via on the substrate 30 needs to avoid the active layer 50, that is, the orthographic projection of the first via on the substrate 30 needs to be located outside the orthographic projection of the active layer 50 on the substrate 30 to reduce the risk of interference between the conductor material and the semiconductor material.

[0081] In some embodiments, see Figure 10 , a plurality of pixel circuits 10 are arranged along the first direction X, and an orthographic projection of the first via hole on the substrate 30 is located between orthographic projections of two pixel circuits 10 adjacently arranged along the first direction X on the substrate 30 .

[0082] The “two adjacent pixel circuits 10 ” mentioned in the embodiment of the present application refer to: the two pixel circuits 10 that are closest to each other in the first direction X, that is, there is no other pixel circuit 10 between the two pixel circuits 10 .

[0083] If the first direction X is the row direction of the display panel, then the multiple pixel circuits 10 arranged in the first direction X together constitute a circuit row. Optionally, in addition to being arranged along the first direction X, the multiple pixel circuits 10 may also be arranged along the second direction Y. Furthermore, the first direction X is perpendicular to the second direction Y. In this case, the multiple pixel circuits 10 arranged in the second direction Y together constitute a circuit column.

[0084] Normally, the active layer 50 is often not located between two adjacent pixel circuits 10 in the first direction X. In view of this, the embodiment of the present application adjusts the position of the first via hole, and sets the orthographic projection of the first via hole on the substrate 30 to be located between the orthographic projections of two adjacent pixel circuits 10 on the substrate 30. In this way, the existence of the first via hole will not interfere with the active layer 50, so there is no need to adjust the active structure size. At the same time, it helps to reduce the impact of the first via hole on the performance of the active layer 50 and improve the reliability of the display panel.

[0085] In some embodiments, see Figure 8 、 Figure 9 as well as Figure 11 The pixel circuit 10 further includes a first transistor 14. The active layer 50 includes a third channel portion 53. The orthographic projection of the third channel portion 53 on the substrate 30 overlaps with the orthographic projection of the control portion of the first transistor 14 on the substrate 30. The orthographic projection of the third channel portion 53 on the substrate 30 overlaps with the orthographic projection of the first conductor portion 41 on the substrate 30.

[0086] The first transistor 14 is a transistor in the pixel circuit 10 that is different from the first switching transistor 12 and the driving transistor 11. The third channel portion 53 is a channel structure in the first transistor 14. The first channel portion 51, the second channel portion 52, and the third channel portion 53 are arranged in the same layer, that is, they are made of the same material and are manufactured together in the same process. Optionally, the material of the first channel portion 51, the second channel portion 52, and the third channel portion 53 all include low-temperature polysilicon, that is, the first switching transistor 12 and the first transistor 14 are both LTPS-TFTs.

[0087] The embodiment of the present application does not limit the relative positional relationship between the first transistor 14 and the first switch transistor 12. Optionally, the first transistor 14 can be arranged adjacent to the first switch transistor 12, that is, there is no other transistor between the two transistors. The first transistor 14 and the first switch transistor 12 can be arranged in a first direction X or in a second direction Y.

[0088] Optionally, the first transistor 14 and the first switching transistor 12 are two transistors arranged adjacent to each other in the first direction X. Since the first conductor portion 41 can extend along the first direction X, by increasing the extension length of the first conductor portion 41, the first conductor portion 41 can be arranged to overlap with the first channel portion 51 and the third channel portion 53.

[0089] In the embodiment of the present application, by increasing the size of the first conductor portion 41, the first conductor portion 41 not only overlaps with the channel structure in the first switching transistor 12, but also overlaps with the third channel portion 53 in the first transistor 14. Under this design, the first conductor portion 41 can also have a light-shielding effect on the first transistor 14, reducing the amount of reflected light propagating to the third channel portion 53, reducing the impact of the reflected light on the first transistor 14, and improving the operational reliability of the first transistor 14.

[0090] In some embodiments, as Figure 8 、 Figure 9 as well as Figure 11 As shown, the second conductive layer 60 includes a first scan line 61 extending along a first direction X. The first scan line 61 is electrically connected to the first control unit 121 and the second control unit 122. The first direction X is parallel to the plane of the substrate 30. The first conductor portion 41 includes a first sub-segment 411, a second sub-segment 412, and a connecting segment 413, which are integrally connected. The orthographic projection of the first sub-segment 411 on the substrate 30 overlaps with the orthographic projection of the first channel portion 51 on the substrate 30. The orthographic projection of the second sub-segment 412 on the substrate 30 overlaps with the orthographic projection of the third channel portion 53 on the substrate 30. The connecting segment 413 extends along the first direction X, with its ends connected to the first sub-segment 411 and the second sub-segment 412, respectively. The orthographic projection of the connecting segment 413 on the substrate 30 overlaps with the orthographic projection of the first scan line 61 on the substrate 30.

[0091] The first sub-segment 411 is the portion of the first conductor portion 41 that overlaps with the first channel portion 51. The second sub-segment 412 is the portion of the first conductor portion 41 that overlaps with the third channel portion 53. The connecting segment 413 is used to connect and integrate the first sub-segment 411 and the second sub-segment 412, respectively. The width of the first sub-segment 411 can be equal to that of the connecting segment 413, or it can be smaller or larger than that of the connecting segment 413. The width relationship between the second sub-segment 412 and the connecting segment 413 is similar.

[0092] As can be seen from the accompanying drawings, different transistors are typically spaced apart. To ensure that the first conductor portion 41 overlaps the channel structures of different transistors, the first conductor portion 41 is required to have at least three segmented structures: a first sub-segment 411, a second sub-segment 412, and a connecting segment 413. Furthermore, the embodiment of the present application further restricts the relative positional relationship between the connecting segment 413 and the first scan line 61, arranging the orthographic projection of the connecting segment 413 on the substrate 30 to overlap with the orthographic projection of the first scan line 61 on the substrate 30. This reduces the impact of the connecting segment 413 on the transmittance of a local area of ​​the display panel, thereby improving the display uniformity of the display panel.

[0093] Furthermore, because the orthographic projection of the connecting segment 413 on the substrate 30 is located outside the orthographic projection of the active layer 50 on the substrate 30 and overlaps with the orthographic projection of the first scan line 61 on the substrate 30, the first conductor portion 41 can be electrically connected to the first scan line 61 through a via at a position corresponding to the connecting segment 413. In this way, the first conductor portion 41 and the first scan line 61 can be connected within the region where a single pixel circuit 10 is located. Of course, in other cases, the first conductor portion 41 can also overlap with the first scan line 61 at other positions other than the connecting segment 413, and a via connection between the first conductor portion 41 and the first scan line 61 can be achieved at this position, and this embodiment of the present application is not limited to this.

[0094] In some optional embodiments, the first channel portion 51 and the third channel portion 53 are arranged in the first direction X, the connecting segment 413 and the first scan line 61 both extend along the first direction X, and the connecting segment 413 is integrally connected to the first sub-segment 411 and the second sub-segment 412 at both ends in the first direction X. In this case, the first conductor portion 41 and the first scan line 61 both extend in the first direction X, thereby reducing the difficulty of connecting the two.

[0095] In some embodiments, as Figure 4 and Figure 8As shown, the second electrode of the first switch transistor 12 is electrically connected to the second electrode of the driving transistor 11, and the first electrode of the first transistor 14 receives the data signal. In other words, the first switch transistor 12 is a transistor T4, the first transistor 14 is a transistor T2, and the first scan line 61 is used to transmit the second scan signal scan2.

[0096] In the embodiment of the present application, the first conductor portion 41 overlaps with the channel structures of the transistors T4 and T2. This design can, on the one hand, reduce the leakage between the fifth node N5 and the first node N1, thereby improving the display flicker problem. On the other hand, the first conductor portion 41 can also have a light-shielding effect on the channel structures of the transistors T4 and T2, reducing the impact of reflected light on the transistors T4 and T2, thereby improving the operational reliability of the transistors T4 and T2.

[0097] In addition, since the channel structure in the transistor T4 and the channel structure in the transistor T2 are spaced apart in the first direction X, the first conductor portion 41 needs to extend along the first direction X to overlap with the channel structures of the two transistors respectively. In this case, the first conductor portion 41 and the first scan line 61 have the same extension direction, which helps to reduce the difficulty of connecting the two.

[0098] Or in other embodiments, see Figure 4 and Figure 12 The sub-pixel 20 includes an anode, a second electrode of the first switching transistor 12 receives a first reset signal Vref1, a first electrode of the first transistor 14 receives a second reset signal Vref2, and a second electrode of the first transistor 14 is electrically connected to the anode. In other words, the first switching transistor 12 is a transistor T5, the first transistor 14 is a transistor T7, and the first scan line 61 is used to transmit the first scan signal scan1.

[0099] In the embodiment of the present application, the first conductor portion 41 overlaps with the channel structures of the transistors T5 and T7. This design can, on the one hand, adjust the leakage level between the sixth node N6 and the first node N1, thereby improving the display flicker problem. On the other hand, the first conductor portion 41 can also have a light-shielding effect on the channel structures of the transistors T5 and T7, reducing the impact of reflected light on the transistors T5 and T7, and improving the operational reliability of the transistors T5 and T7.

[0100] Furthermore, since the channel structure of the transistor T5 and the channel structure of the transistor T7 are spaced apart in the first direction X, the first conductor portion 41 needs to extend along the first direction X to overlap with the channel structures of the two transistors respectively. In this case, the first conductor portion 41 and the first scan line 61 have the same extension direction, thereby reducing the difficulty of connecting the two.

[0101] In some embodiments, as Figures 2a to 2d As shown, the first conductor portion 41 includes a first sub-segment 411 , and the orthographic projection of the first channel portion 51 on the substrate 30 is located within the orthographic projection of the first sub-segment 411 on the substrate 30 .

[0102] The orthographic projection of the first channel portion 51 on the substrate 30 is located within the orthographic projection of the first sub-segment 411 on the substrate 30, indicating that the orthographic projection of the first sub-segment 411 is not smaller than the orthographic projection of the first channel portion 51. Optionally, the orthographic projection of the first sub-segment 411 on the substrate 30 overlaps and exceeds the orthographic projection of the first channel portion 51 on the substrate 30. Furthermore, the first sub-segment 411 is disposed beyond the first channel portion 51 in its width direction.

[0103] The "width direction" mentioned here refers to the dimension of the first sub-segment 411 perpendicular to its own extension direction. In different cases, the extension direction of the first sub-segment 411 may be the same as or different from the overall extension direction of the first conductor portion 41. This results in differences in the width direction of the first sub-segment 411 in different cases. For example, Figures 2a to 2d As shown, if the first switching transistor 12 is a transistor T4, the first conductor portion 41 extends entirely along the first direction X, but the first subsegment 411 extends along the second direction Y, resulting in different extension directions. In this case, the width of the first subsegment 411 is the first direction X. In other words, when the first switching transistor 12 is a transistor T4, the dimension L1 of the first subsegment 411 in the first direction X can exceed the dimension L2 of the first channel portion 51 in the first direction X.

[0104] If the first switching transistor 12 is a transistor T5, the first conductor portion 41 extends entirely along the first direction X, and the first subsegment 411 extends in the same direction. In this case, the width of the first subsegment 411 is the second direction Y. In other words, when the first switching transistor 12 is a transistor T5, the first subsegment 411 is disposed beyond the first channel portion 51 in the second direction Y.

[0105] In the embodiment of the present application, by increasing the size of the first sub-segment 411, the orthographic projection of the first channel portion 51 on the substrate 30 is located within the orthographic projection of the first sub-segment 411 on the substrate 30. In this way, the first sub-segment 411 can form an electrostatic shield around the first channel portion 51, thereby reducing the interference of the external electrostatic field on the first switching crystal and improving the operating reliability of the first switching transistor 12.

[0106] In some optional embodiments, the first conductor portion 41 further includes a fourth subsegment 415, and the orthographic projection of the second channel portion 52 on the substrate 30 is located within the orthographic projection of the fourth subsegment on the substrate 30. Furthermore, the fourth subsegment 415 has a width dimension L3 that extends beyond the first channel portion 51. When the first switching transistor 12 is transistor T4, the width of the first subsegment 411 is in the first direction X, and the width of the fourth subsegment 415 is in the second direction Y. When the first switching transistor 12 is transistor T5, the widths of both the first subsegment 411 and the fourth subsegment 415 are in the second direction Y.

[0107] In some embodiments, see Figure 8 and Figure 9 The first conductor portion 41 includes a third sub-segment 414 , the orthographic projection of the third sub-segment 414 on the substrate 30 is located outside the orthographic projection of the active layer 50 on the substrate 30 . A width L1 of the first sub-segment 411 is greater than a width L4 of the third sub-segment 414 .

[0108] The third subsegment 414 is the portion of the first conductor portion 41 that does not overlap with the active layer 50. The connecting segment 413 is part of the third subsegment 414. As can be seen from the foregoing, the width L1 of the first subsegment 411 can be increased so that it extends beyond the first channel portion 51 in its width direction, thereby reducing interference from external electrostatic fields on the first switching transistor. However, if the width L4 of the third subsegment 414 is too large, it can easily cause signal interference with other wiring structures, affect the layout of other wiring within the display panel, and affect the transmittance of the display panel in certain areas.

[0109] In view of this, the embodiment of the present application designs the sizes of the first sub-segment 411 and the third sub-segment 414 differently, and sets the width L1 of the first sub-segment 411 to be larger than the width L4 of the third sub-segment 414. In this way, on the one hand, the anti-static capability of the first switching transistor 12 is improved with the help of the first sub-segment 411, and on the other hand, it helps to reduce the signal interference between the third sub-segment 414 and other signal lines, and at the same time reduces the impact of the third sub-segment 414 on other line layout methods and the transmittance of local areas of the display panel, which has strong practicality.

[0110] In some embodiments, as Figure 10 As shown, the orthographic projection of one first conductor portion 41 on the substrate 30 overlaps with the orthographic projections of the corresponding first channel portions 51 in a plurality of pixel circuits 10 on the substrate 30 .

[0111] In the embodiment of the present application, a first conductor portion 41 does not overlap with only the first channel portion 51 in one pixel circuit 10, but rather overlaps with multiple first channel portions 51 in multiple pixel circuits 10. The presence of such a first conductor portion 41 can alleviate leakage issues associated with multiple pixel circuits 10. This design helps reduce the number of first conductor portions 41 in the display panel and the number of vias required to connect the first conductor portions 41 to the first scan lines 61, thereby simplifying the fabrication of the first conductive layer 40. Optionally, the first conductor portion 41 extends along the first direction X, with one first conductor portion 41 overlapping with the first channel portions 51 in multiple pixel circuits 10 arranged in the first direction X.

[0112] In some embodiments, as Figure 4 and Figure 8 As shown, the pixel circuit 10 further includes a second switch transistor 13. A first electrode of the second switch transistor 13 is electrically connected to the control unit of the drive transistor 11. The control unit of the second switch transistor 13 includes a third control unit and a fourth control unit. A second electrode of the first switch transistor 12 is electrically connected to the second electrode of the drive transistor 11. A second electrode of the second switch transistor 13 receives a first reset signal Vref1.

[0113] The second switching transistor 13 has a dual-gate structure. The third and fourth control units in the second switching transistor 13 are both located in the second conductive layer 60. This means that the third and fourth control units are made of the same material and are fabricated in the same process. The third and fourth control units receive the same signal. Specifically, the first and second control units 121 and 122 both receive the second scan signal scan2, and the third and fourth control units both receive the first scan signal scan1.

[0114] In the embodiment of the present application, the first switch transistor 12 is a transistor T4, the second switch transistor 13 is T5, and the first conductor portion 41 can be arranged to overlap with the channel structure in the transistor T4, thereby reducing the leakage level between the fifth node N5 and the first node N1, thereby improving the display screen flicker problem.

[0115] In other embodiments, such as Figure 4 and Figure 12 As shown, the second electrode of the second switch transistor 13 is electrically connected to the second electrode of the driving transistor 11 , and the second electrode of the first switch transistor 12 receives the first reset signal Vref1 .

[0116] In the embodiment of the present application, the first switching transistor 12 is a transistor T5, the second switching transistor 13 is a transistor T4, the first control unit 121 and the second control unit 122 both receive a first scan signal scan1, and the third control unit and the fourth control unit both receive a second scan signal scan2. The first conductor 41 can be arranged to overlap with the channel structure of the transistor T5, thereby reducing leakage between the sixth node N6 and the first node N1, thereby improving the display flicker problem.

[0117] In some embodiments, see Figure 13 The active layer 50 includes a fourth channel portion 54, whose orthographic projection on the substrate 30 overlaps with the orthographic projection of the third control portion on the substrate 30. The fourth channel portion 54 is electrically connected to the first electrode of the second switching transistor 13. The first conductive layer 40 also includes a second conductor portion 42, whose orthographic projection on the substrate 30 overlaps with the orthographic projection of the fourth channel portion 54 on the substrate 30. The second conductor portion 42 is electrically connected to the third control portion and is insulated from the first conductor portion 41.

[0118] The fourth channel portion 54 and the third control portion are arranged to overlap in the orthographic projection of the substrate 30. In addition to the fourth channel portion 54, the active layer 50 also includes a fifth channel portion 55. The fifth channel portion 55 and the fourth control portion are arranged to overlap in the orthographic projection of the substrate 30. The fourth communication portion and the fifth channel portion 55 are both channel structures of the second switching transistor 13, and the third control portion and the fourth channel portion 54 together constitute a third sub-transistor, and the fourth control portion and the fifth channel portion 55 together constitute a fourth sub-transistor. The third sub-transistor and the fourth sub-transistor are arranged in series to form the second switching transistor 13.

[0119] For the first switching transistor 12 and the second switching transistor 13 electrically connected to the control part of the driving transistor 11, when the two transistors change from the on state to the off state, a voltage difference may easily occur between the intermediate node and the first node N1, thereby causing leakage problems.

[0120] In view of this, in the embodiment of the present application, a first conductor portion 41 and a second conductor portion 42 are provided in the first conductive layer 40 at the same time. The first conductor portion 41 and the second conductor portion 42 are insulated from each other. The first conductor portion 41 is electrically connected to the first control portion 121 and overlaps with the first channel portion 51. The second conductor portion 42 is electrically connected to the third control portion and overlaps with the fourth channel portion 54. In this way, with the help of the first conductor portion 41 and the second conductor portion 42, the leakage degree between the fifth node N5 and the first node N1 can be reduced, and the leakage degree between the sixth node N6 and the first node N1 can be reduced, thereby further improving the display screen flickering problem and improving the user experience of the display panel.

[0121] In some embodiments, see Figure 14 and Figure 15 The first conductive layer 40 includes a third conductor portion 43 , the orthographic projection of the third conductor portion 43 on the substrate 30 overlaps with the orthographic projection of the control portion of the driving transistor 11 on the substrate 30 , and the third conductor portion 43 is electrically connected to the control portion of the driving transistor 11 .

[0122] The third conductor portion 43 and the first conductor portion 41 are both located within the first conductive layer 40. That is, the first conductor portion 41 and the third conductor portion 43 are made of the same material and are fabricated together in the same process. The orthographic projection of the third conductor portion 43 on the substrate 30 overlaps the orthographic projection of the control portion of the drive transistor 11 on the substrate 30. Because the channel structure of the drive transistor 11 generally corresponds to the position of the control portion of the drive transistor 11, the third conductor portion 43 overlaps the channel structure of the drive transistor 11.

[0123] As can be seen from the accompanying drawings, since the first switching transistor 12 and the driving transistor 11 are spaced apart in the second direction Y, the first conductor portion 41 and the third conductor portion 43 corresponding to the two transistors are also spaced apart in the second direction Y, thereby achieving mutual insulation between the first conductor portion 41 and the third conductor portion 43. On this basis, in the embodiment of the present application, the third conductor portion 43 is electrically connected to the control portion of the driving transistor 11, so that the third conductor portion 43 can receive a specific signal voltage. In this way, the third conductor portion 43 not only provides a light shielding effect for the driving transistor 11, thereby improving the performance of the driving transistor 11, but also improves the anti-static capability of the driving transistor 11, thereby improving the operational reliability of the pixel circuit 10.

[0124] The embodiment of the present application does not limit the electrical connection method between the third conductor portion 43 and the driving transistor 11. Optionally, the display panel includes a storage capacitor, and one of the plates of the storage capacitor is reused as the control unit of the driving transistor 11. The orthographic projection of this plate on the substrate 30 can be partially located outside the orthographic projection of the active layer 50 on the substrate 30 and overlap with the orthographic projection of the third conductor portion 43 on the substrate 30. On this basis, the third conductor portion 43 can be directly connected to the plate of the storage capacitor through a via hole to achieve electrical connection between the third conductor portion 43 and the driving transistor 11.

[0125] In some embodiments, see Figure 4 、 Figure 16 and Figure 17 The first conductor portion 41 is electrically connected to the control portion of the driving transistor 11 .

[0126] In the embodiment of the present application, by electrically connecting the first conductor portion 41 to the control portion of the driving transistor 11, the first conductor portion 41 can receive the signal voltage at the first node N1. As a result, when the first switching transistor 12 changes from an on state to an off state, the first control portion 121 becomes a high-level voltage, while the signal received by the first conductor portion 41 is a low-level voltage. In this way, under the joint action of the first conductor portion 41 and the first control portion 121, the leakage rate of the first channel portion 51 can be accelerated, thereby completing the leakage process in a shorter time. Furthermore, when the display panel is in the light-emitting stage, the intermediate node of the first switching transistor 12 and the first node N1 can maintain voltage balance. This design can improve the potential stability of the first node in the light-emitting stage and improve the flicker problem of the display screen.

[0127] In some embodiments, the first conductive layer 40 includes a third conductor portion 43 , the orthographic projection of the third conductor portion 43 on the substrate 30 overlaps with the orthographic projection of the control portion of the driving transistor 11 on the substrate 30 , and the third conductor portion 43 is electrically connected to the control portion of the driving transistor 11 .

[0128] The first conductor portion 41 and the third conductor portion 43 are both located within the first conductive layer 40. That is, the first conductor portion 41 and the third conductor portion 43 comprise the same components and are fabricated together in the same process. Because both the first conductor portion 41 and the third conductor portion 43 are electrically connected to the control unit of the driver transistor 11, the first conductor portion 41 and the third conductor portion 43 can be connected to the same wiring structure to achieve electrical connection therebetween. Alternatively, the first conductor portion 41 and the third conductor portion 43 can be spaced apart from each other and each electrically connected to the control unit of the driver transistor 11 via a different wiring structure.

[0129] In the embodiment of the present application, since the third conductor portion 43 is electrically connected to the control portion of the driving transistor 11 and the third conductor portion 43 overlaps with the channel structure of the driving transistor 11, the third conductor portion 43 can not only provide a light shielding effect for the driving transistor 11 to improve the performance of the driving transistor 11, but also improve the anti-static capability of the driving transistor 11 and improve the operational reliability of the pixel circuit 10.

[0130] In some embodiments, as Figure 4 、 Figure 16 as well as Figure 17 As shown, the first conductive layer 40 further includes a connecting portion 44 , and the first conductor portion 41 , the third conductor portion 43 and the first electrode of the first switch transistor 12 are all electrically connected to the connecting portion 44 .

[0131] As can be seen from the accompanying drawings, the orthographic projection of the first conductor portion 41 on the substrate 30 is offset from the orthographic projection of the control portion of the driving transistor 11 on the substrate 30. Therefore, the first conductor portion 41 cannot be directly connected to the control portion of the driving transistor 11 through a via. However, the third conductor portion 43 is arranged to overlap with the control portion of the driving transistor 11. Therefore, the third conductor portion 43 can be directly connected to the control portion of the driving transistor 11 through a via.

[0132] In view of this, the embodiment of the present application adds a connecting portion 44 in the first conductive layer 40, and the connecting portion 44 is connected between the first conductor portion 41 and the third conductor portion 43. In this way, the first conductor portion 41 can be electrically connected to the control portion of the driving transistor 11 with the help of the connecting portion 44 and the third conductor portion 43. There is no need to set connecting lines in other conductive film layers outside the first conductive layer 40, thereby reducing the occupation of space in other film layers and reducing the difficulty of internal wiring layout of the display panel.

[0133] It should be noted that in the related art, in order to electrically connect the first electrode of transistor T4 and the first electrode of transistor T5 to the control unit of the driving transistor 11, the display panel is provided with a third conductive layer on the side of the second conductive layer 60 facing away from the substrate 30. The third conductive layer includes a transition portion, which extends along the second direction Y. The scanning line that transmits the second scanning signal scan2 extends along the first direction X, and the two are correspondingly overlapped. On this basis, the two ends of the transition portion are respectively located on both sides of the scanning line, and one end is connected to a plate structure of the storage capacitor by means of a via to achieve connection with the control unit of the driving transistor 11, and the other end is connected to the active layer 50 by means of a via to achieve connection with the first electrode of transistor T4 and the first electrode of transistor T5.

[0134] However, in the embodiment of the present application, the connection portion 44 provided in the first conductive layer 40 can be electrically connected to the control portion of the driving transistor 11. Furthermore, as can be seen from the accompanying drawings, the connection portion 44 can overlap with a portion of the structure of the active layer 50 located in the transistors T4 and T5. Furthermore, in some optional embodiments, the connection portion 44 can be connected to the active layer 50 via a via, so that the first electrode of the transistor T4 and the first electrode of the transistor T5 can be electrically connected to the control portion of the driving transistor 11. This eliminates the need for a transition portion in the third conductive layer, simplifying the internal wiring layout of the display panel.

[0135] In some embodiments, as Figure 16As shown, the pixel circuit 10 further includes a second switch transistor 13. A first electrode of the second switch transistor 13 is electrically connected to the control unit of the drive transistor 11. The control unit of the second switch transistor 13 includes a third control unit and a fourth control unit. A second electrode of the first switch transistor 12 is electrically connected to the first electrode of the drive transistor 11, and a second electrode of the second switch transistor 13 receives a first reset signal Vref1.

[0136] The second switching transistor 13 has a dual-gate structure. The third and fourth control units in the second switching transistor 13 are both located in the second conductive layer 60. This means that the third and fourth control units are made of the same material and are fabricated in the same process. The third and fourth control units receive the same signal. Specifically, the first and second control units 121 and 122 both receive the second scan signal scan2, and the third and fourth control units both receive the first scan signal scan1.

[0137] In the embodiment of the present application, the first switching transistor 12 is a transistor T4, the second switching transistor 13 is T5, and the first conductor portion 41 can be arranged to overlap with the channel structure in the transistor T4, thereby accelerating the leakage rate between the fifth node N5 and the first node N1, thereby completing the leakage process in a shorter time. When the display panel is in the light-emitting stage, the fifth node N5 and the first node N1 can maintain a voltage balance, thereby improving the display screen flicker problem.

[0138] Alternatively, in some other embodiments, the second electrode of the second switch transistor 13 is electrically connected to the second electrode of the driving transistor 11 , and the second electrode of the first switch transistor 12 receives the first reset signal Vref1 .

[0139] In the embodiment of the present application, the first switching transistor 12 is a transistor T5, the second switching transistor 13 is a transistor T4, the first control unit 121 and the second control unit 122 both receive a first scan signal scan1, and the third control unit and the fourth control unit both receive a second scan signal scan2. The first conductor 41 can be arranged to overlap with the channel structure of the transistor T5, thereby accelerating the leakage rate between the sixth node N6 and the first node N1, thereby completing the leakage process in a shorter time. Furthermore, when the display panel is in the light-emitting stage, the sixth node N6 and the first node N1 can maintain voltage balance, thereby improving the display flicker problem.

[0140] In some embodiments, see Figure 11 、 Figure 18 and Figure 19The active layer 50 includes a fourth channel portion 54, whose orthographic projection on the substrate 30 overlaps with the orthographic projection of the third control portion on the substrate 30. The fourth channel portion 54 is electrically connected to the first electrode of the second switch transistor 13. The first conductive layer 40 also includes a second conductor portion 42, whose orthographic projection on the substrate 30 overlaps with the orthographic projection of the fourth channel portion 54 on the substrate 30. The first conductor portion 41 and the second conductor portion 42 are integrally formed.

[0141] The fourth channel portion 54 and the third control portion are arranged to overlap in the orthographic projection of the substrate 30. In addition to the fourth channel portion 54, the active layer 50 also includes a fifth channel portion 55. The fifth channel portion 55 and the fourth control portion are arranged to overlap in the orthographic projection of the substrate 30. The fourth communication portion and the fifth channel portion 55 are both channel structures of the second switching transistor 13, and the third control portion and the fourth channel portion 54 together constitute a third sub-transistor, and the fourth control portion and the fifth channel portion 55 together constitute a fourth sub-transistor. The third sub-transistor and the fourth sub-transistor are arranged in series to form the second switching transistor 13.

[0142] For the first switching transistor 12 and the second switching transistor 13 electrically connected to the control part of the driving transistor 11, when the two transistors change from the on state to the off state, a voltage difference may easily occur between the intermediate node and the first node N1, thereby causing leakage problems.

[0143] In view of this, in the embodiment of the present application, a first conductor portion 41 and a second conductor portion 42 are provided in the first conductive layer 40. The first conductor portion 41 and the second conductor portion 42 are both electrically connected to the control portion of the driving transistor 11. In this way, with the help of the first conductor portion 41 and the second conductor portion 42, the leakage rate between the fifth node N5 and the first node N1 can be accelerated, and the leakage rate between the sixth node N6 and the first node N1 can also be accelerated. In this way, when the display panel is in the light-emitting stage, the first node N1 can maintain a voltage balance with the fifth node N5 and the sixth node N6, thereby improving the problem of display screen flicker.

[0144] Furthermore, since the first conductor portion 41 and the second conductor portion 42 are both electrically connected to the control portion of the driving transistor 11, and the distance between the first switching transistor 12 and the second switching transistor 13 is relatively close, the embodiment of the present application also connects the first conductor portion 41 and the second conductor portion 42 as an integrated whole. This not only meets the signal transmission requirements, but also helps to simplify the wiring layout difficulty of the display panel, and has strong practicality.

[0145] It should be noted that, for different pixel circuits 10, at the same moment, the signal voltages at the first node N1 of different pixel circuits 10 are not the same. In view of this, the different first conductor portions 41 corresponding to different pixel circuits 10 need to be spaced apart from each other to meet the normal operation requirements of the pixel circuits 10.

[0146] In some embodiments, the plurality of sub-pixels 20 include a first sub-pixel 20 for emitting green light, and the plurality of pixel circuits 10 include a first pixel circuit 10 for driving the first sub-pixel 20. An orthographic projection of the first conductor portion 41 on the substrate 30 overlaps with an orthographic projection of the first channel portion 51 in the first pixel circuit 10 on the substrate 30.

[0147] The first sub-pixel 20 is a sub-pixel 20 for emitting green light among the multiple sub-pixels 20, and the first pixel circuit 10 is a pixel circuit 10 for driving the first sub-pixel 20 among the multiple pixel circuits 10. Optionally, in addition to the first sub-pixel 20, the multiple sub-pixels 20 may further include a second sub-pixel 20 for emitting red light and a third sub-pixel 20 for emitting blue light.

[0148] The human eye is more sensitive to green. Therefore, compared with sub-pixels 20 of other colors, the first sub-pixel 20 for emitting green light has a greater impact on the display effect. In view of this, the embodiment of the present application adds a first conductor portion 41 at a position corresponding to the first channel portion 51 in the first pixel circuit 10. The first conductor portion 41 is used to adjust the leakage level in the first pixel circuit 10, thereby improving the flicker problem corresponding to the first sub-pixel 20.

[0149] It should be noted that the embodiment of the present application does not limit the relationship between the pixel circuits 10 corresponding to other sub-pixels and the first conductor portion 41. For example, the display panel may be provided with the first conductor portion 41 only at the position corresponding to the first channel portion 51 in the first pixel circuit 10, or may be provided with the first conductor portion 41 at the position corresponding to the first channel portion 51 in the pixel circuits 10 of other sub-pixels 20.

[0150] Second, see Figure 20 , an embodiment of the present application provides a display device, the display device including the display panel in any of the aforementioned embodiments.

[0151] It should be noted that the display device provided in the embodiments of the present application has the beneficial effects of the display panel described in any of the aforementioned embodiments. For details, please refer to the aforementioned description of the beneficial effects of the display panel, which are not limited in the embodiments of the present application. Furthermore, in addition to the display panel, the display device may further include a midframe, which at least partially surrounds the display panel to protect it.

[0152] Although the embodiments disclosed in this application are as described above, the contents described are merely embodiments adopted to facilitate understanding of this application and are not intended to limit the present invention. Any person skilled in the art to which this application belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application. However, the scope of protection of this application shall still be based on the scope defined by the appended claims.

[0153] The above description is only a specific embodiment of the present application. Those skilled in the art will clearly understand that for the convenience and brevity of description, the replacement of other connection methods described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. It should be understood that the scope of protection of the present application is not limited to this. Any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the scope of protection of this application.

Claims

1. A display panel, characterized in that: The display panel includes a pixel circuit and a sub-pixel, wherein the pixel circuit drives and controls the sub-pixel, the pixel circuit includes a driving transistor and a first switching transistor, the control unit of the driving transistor is electrically connected to the first electrode of the first switching transistor, and the control unit of the first switching transistor includes a first control unit and a second control unit; the display panel also includes: substrate; A first conductive layer is provided on one side of the substrate, wherein the first conductive layer includes a first conductor portion; an active layer disposed on a side of the first conductive layer facing away from the substrate, the active layer comprising a first channel portion, an orthographic projection of the first channel portion on the substrate overlapping with an orthographic projection of the first control portion on the substrate, and the first channel portion electrically connected to a first electrode of the first switching transistor; a second conductive layer, disposed on a side of the active layer facing away from the substrate, the second conductive layer comprising the first control portion and the second control portion; The orthographic projection of the first conductor portion on the substrate overlaps with the orthographic projection of the first channel portion on the substrate, and the first conductor portion receives a voltage-transformed signal.

2. The display panel according to claim 1, wherein: The active layer includes a second channel portion, the second channel portion is connected between the first channel portion and the second electrode of the first switch transistor, and an orthographic projection of the second channel portion on the substrate overlaps with an orthographic projection of the second control portion on the substrate; The orthographic projection of the second channel portion on the substrate overlaps with the orthographic projection of the first conductor portion on the substrate.

3. The display panel according to claim 1, wherein: The first conductor portion is electrically connected to the first control portion.

4. The display panel according to claim 3, wherein: The second conductive layer includes a first scanning line extending along a first direction, the first scanning line is electrically connected to the first control portion and the second control portion, and the first direction is parallel to the plane where the substrate is located; The first conductor portion extends along the first direction and is connected to the first scan line.

5. The display panel according to claim 4, wherein: The orthographic projection of the first scanning line on the substrate overlaps with the orthographic projection of the first conductor portion on the substrate, and the first scanning line and the first conductor portion are connected through a first via hole.

6. The display panel according to claim 5, wherein: The plurality of pixel circuits are arranged along the first direction, and an orthographic projection of the first via on the substrate is located between orthographic projections of two pixel circuits adjacently arranged along the first direction on the substrate.

7. The display panel according to claim 3, wherein: The pixel circuit further includes a first transistor, the active layer includes a third channel portion, and an orthographic projection of the third channel portion on the substrate overlaps with an orthographic projection of a control portion of the first transistor on the substrate; The orthographic projection of the third channel portion on the substrate overlaps with the orthographic projection of the first conductor portion on the substrate.

8. The display panel according to claim 7, wherein: The second conductive layer includes a first scanning line extending along a first direction, the first scanning line is electrically connected to the first control portion and the second control portion, and the first direction is parallel to the plane where the substrate is located; The first conductor portion includes a first sub-segment, a second sub-segment, and a connecting segment that are integrally connected. The orthographic projection of the first sub-segment on the substrate overlaps with the orthographic projection of the first channel portion on the substrate. The orthographic projection of the second sub-segment on the substrate overlaps with the orthographic projection of the third channel portion on the substrate. The connecting segment extends along the first direction, with two ends connected to the first sub-segment and the second sub-segment, respectively. The orthographic projection of the connecting segment on the substrate overlaps with the orthographic projection of the first scanning line on the substrate.

9. The display panel according to claim 7, wherein: The second electrode of the first switch transistor is electrically connected to the second electrode of the driving transistor, and the first electrode of the first transistor receives a data signal; or, The sub-pixel includes an anode, a second electrode of the first switch transistor receives a first reset signal, a first electrode of the first transistor receives a second reset signal, and a second electrode of the first transistor is electrically connected to the anode.

10. The display panel according to claim 3, wherein: The first conductor portion includes a first subsegment, and an orthographic projection of the first channel portion on the substrate is located within the orthographic projection of the first subsegment on the substrate.

11. The display panel according to claim 10, wherein: The first conductor portion includes a third subsegment, wherein an orthographic projection of the third subsegment on the substrate is located outside an orthographic projection of the active layer on the substrate; The width of the first sub-segment is greater than the width of the third sub-segment.

12. The display panel according to claim 3, wherein: An orthographic projection of one first conductor portion on the substrate is overlapped with an orthographic projection of corresponding first channel portions in a plurality of pixel circuits on the substrate.

13. The display panel according to claim 3, wherein: The pixel circuit further includes a second switch transistor, a first electrode of the second switch transistor is electrically connected to the control unit of the drive transistor, and the control unit of the second switch transistor includes a third control unit and a fourth control unit; The second electrode of the first switching transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the second switching transistor receives a first reset signal; or the second electrode of the second switching transistor is electrically connected to the first electrode of the driving transistor, and the second electrode of the first switching transistor receives a first reset signal.

14. The display panel according to claim 13, wherein: The active layer includes a fourth channel portion, an orthographic projection of the fourth channel portion on the substrate overlaps with an orthographic projection of the third control portion on the substrate, and the fourth channel portion is electrically connected to the first electrode of the second switch transistor; The first conductive layer further includes a second conductor portion, wherein an orthographic projection of the second conductor portion on the substrate overlaps with an orthographic projection of the fourth channel portion on the substrate; The second conductor part is electrically connected to the third control part and is insulated from the first conductor part.

15. The display panel according to claim 3, wherein: The first conductive layer includes a third conductor portion, the orthographic projection of the third conductor portion on the substrate overlaps with the orthographic projection of the control portion of the driving transistor on the substrate, and the third conductor portion is electrically connected to the control portion of the driving transistor.

16. The display panel according to claim 1, wherein The first conductor portion is electrically connected to a control portion of the driving transistor.

17. The display panel according to claim 16, wherein: The first conductive layer includes a third conductor portion, the orthographic projection of the third conductor portion on the substrate overlaps with the orthographic projection of the control portion of the driving transistor on the substrate, and the third conductor portion is electrically connected to the control portion of the driving transistor.

18. The display panel according to claim 17, wherein: The first conductive layer further includes a connecting portion; The first conductor portion, the third conductor portion, and the first electrode of the first switch transistor are all electrically connected to the connecting portion.

19. The display panel according to claim 16, wherein: The pixel circuit further includes a second switch transistor, a first electrode of the second switch transistor is electrically connected to the control unit of the drive transistor, and the control unit of the second switch transistor includes a third control unit and a fourth control unit; The second electrode of the first switching transistor is electrically connected to the first electrode of the driving transistor, and the second electrode of the second switching transistor receives a first reset signal; or the second electrode of the second switching transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the first switching transistor receives a first reset signal.

20. The display panel according to claim 19, wherein The active layer includes a fourth channel portion, an orthographic projection of the fourth channel portion on the substrate overlaps with an orthographic projection of the third control portion on the substrate, and the fourth channel portion is electrically connected to the first electrode of the second switch transistor; The first conductive layer further includes a second conductor portion, wherein an orthographic projection of the second conductor portion on the substrate overlaps with an orthographic projection of the fourth channel portion on the substrate; Wherein, the first conductor part and the second conductor part are an integrated structure.

21. The display panel according to claim 1, wherein The plurality of sub-pixels include a first sub-pixel for emitting green light, and the plurality of pixel circuits include a first pixel circuit for driving the first sub-pixel; The orthographic projection of the first conductor portion on the substrate is overlapped with the orthographic projection of the first channel portion in the first pixel circuit on the substrate.

22. A display device, characterized in that: Comprising the display panel according to any one of claims 1 to 21.

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