Driving substrate and display panel

Abstract

The embodiment of the invention provides a driving substrate and a display panel, relates to the technical field of display, and is used for improving the maximum luminance of blue sub-pixels. The driving substrate comprises a substrate, a plurality of pixel circuits, a plurality of data lines and a switching signal line. The plurality of pixel circuits are arranged on the substrate and are arranged in multiple rows and multiple columns. The plurality of pixel circuits includes a first pixel circuit including a first access point for accessing a first data signal. The plurality of data lines extend along a second direction, and the plurality of data lines include a first data line. A distance is formed between the first data line and the first access point along a first direction. One end of the switching signal line is electrically connected with the first access point, and the other end of the switching signal line is electrically connected with the first data line. The driving backboard is used for preparing a display panel.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a driving substrate and a display panel. Background Art

[0002] With the continuous development of display technology, organic light-emitting diode (OLED) display devices have gradually become one of the mainstream products in the display field due to their excellent performance such as self-luminescence, no need for backlight, high contrast, thin thickness, wide viewing angle, and fast response speed. Summary of the Invention

[0003] An object of the embodiments of the present disclosure is to provide a driving substrate and a display panel for increasing the maximum luminance of a blue sub-pixel.

[0004] To achieve the above objectives, the embodiments of the present disclosure provide the following technical solutions:

[0005] On the one hand, a driving substrate is provided. The driving substrate includes a substrate, a plurality of pixel circuits, a plurality of data lines and a transfer signal line. The plurality of pixel circuits are provided on the substrate and arranged in multiple rows and columns. The plurality of pixel circuits include a first pixel circuit, and the first pixel circuit includes a first access point for accessing a first data signal. The plurality of data lines extend along a second direction, and the plurality of data lines include a first data line. There is a spacing between the first data line and the first access point along the first direction. One end of the transfer signal line is electrically connected to the first access point, and the other end of the transfer signal line is electrically connected to the first data line. The first direction is the row direction in which the plurality of pixel circuits are arranged, and the second direction is the column direction in which the plurality of pixel circuits are arranged.

[0006] The driver substrate includes a first pixel circuit, which includes a first access point for receiving a first data signal. The plurality of data lines includes a first data line, and a spacing is provided between the first data line and the first access point along a first direction. A transfer signal line is electrically connected to the first access point at one end and to the first data line at the other end. The electrical connection between the first data line and the first access point via the transfer signal line facilitates increasing the transmission path for the data signal. Furthermore, the transfer signal line can form parasitic capacitance with other conductive structures on the driver substrate, thereby increasing the load on the data signal transmission path, thereby reducing the voltage value of the data signal written to the first access point, thereby reducing the minimum voltage value written to the first access point, increasing the maximum drive current that can be generated by the first pixel circuit, and increasing the brightness of the light-emitting device electrically connected to the first pixel circuit.

[0007] In some embodiments, the transfer signal line includes a first sub-portion extending along the first direction. The drive substrate further includes a first reference signal line. The first reference signal line extends along the first direction, and an orthographic projection of the first sub-portion on the substrate overlaps with an orthographic projection of the first reference signal line on the substrate.

[0008] In some embodiments, the pixel circuit includes a first transistor and a third transistor, the first transistor including a first active pattern for forming a first electrode, a channel, and a second electrode of the first transistor, the first electrode of the first active pattern being electrically connected to the first reference signal line, and the second electrode of the first active pattern being electrically connected to the gate of the third transistor. In a direction perpendicular to the substrate, the first active pattern, the first reference signal line, and a first subsection of the transfer signal line in the first pixel circuit overlap, with the first reference signal line being located between the first active pattern and the first subsection.

[0009] In some embodiments, the transfer signal line further includes a second sub-portion extending along the second direction. The drive substrate further includes a second reference signal line extending along the first direction and located between the first reference signal line and the first access point in the second direction; an orthographic projection of the second sub-portion on the substrate overlaps with an orthographic projection of the second reference signal line on the substrate.

[0010] In some embodiments, one end of the first sub-unit is electrically connected to the first data line, the other end of the first sub-unit is electrically connected to one end of the second sub-unit, and the other end of the second sub-unit is electrically connected to the first access point.

[0011] In some embodiments, the drive substrate further comprises a semiconductor layer, a first source-drain conductive layer, and a second source-drain conductive layer stacked on the substrate in a direction away from the substrate. The first access point is provided in the semiconductor layer, the transfer signal line is provided in the first source-drain conductive layer, and the plurality of data lines are provided in the second source-drain conductive layer. One end of the transfer signal line is electrically connected to the first access point via a first via, and the other end of the transfer signal line is electrically connected to the first data line via a second via.

[0012] In some embodiments, the driving substrate further includes a first voltage signal line extending along the second direction and electrically connected to the pixel circuit. Along the first direction, the first access point and the first data line are respectively located on both sides of the first voltage signal line.

[0013] In some embodiments, the plurality of pixel circuits further include a second pixel circuit, wherein the first pixel circuit and the second pixel circuit are alternately arranged along the second direction; the second pixel circuit includes a second access point for receiving a second data signal. The plurality of data lines further include a second data line, wherein along the first direction, the first data line and the second data line are respectively located on either side of a pixel circuit column formed by the alternating arrangement of the first pixel circuit and the second pixel circuit. The first access point and the second access point are both located near the second data line, and the second access point is electrically connected to the second data line.

[0014] In some embodiments, along the first direction, three pixel circuits are spaced between two adjacent transfer signal lines; along the second direction, one pixel circuit is spaced between two adjacent transfer signal lines.

[0015] In some embodiments, the pixel circuit includes a second transistor, a third transistor, and a storage capacitor. The second transistor includes a second active pattern for forming a first electrode, a channel, and a second electrode of the second transistor. The third transistor includes a third active pattern for forming a first electrode, a channel, and a second electrode of the third transistor. The first electrode of the second active pattern is connected to the second electrode of the third transistor, and the connection between the second active pattern and the third active pattern forms a third node. The storage capacitor includes a first plate and a second plate arranged overlappingly in a direction perpendicular to the substrate. The first plate also forms a gate of the third transistor. The second plate is located on a side of the first plate away from the substrate and is configured to receive a first voltage signal. The multiple pixel circuits include a first preset pixel circuit and a second preset pixel circuit arranged adjacent to each other along the first direction. The third nodes of the first preset pixel circuit and the second preset pixel circuit are arranged close to each other. The second plate of the first preset pixel circuit and the second plate of the second preset pixel circuit are spaced apart from each other along the first direction. The orthographic projection of the second plate of the first preset pixel circuit onto the substrate does not overlap with the orthographic projection of the third node of the first preset pixel circuit onto the substrate, and the orthographic projection of the second plate of the second preset pixel circuit onto the substrate does not overlap with the orthographic projection of the third node of the second preset pixel circuit onto the substrate.

[0016] In some embodiments, the drive substrate further comprises: a second gate conductive layer and a first source-drain conductive layer stacked on the substrate in a direction away from the substrate. The second plate of the storage capacitor is disposed on the second gate conductive layer. The drive substrate further comprises a first connecting line disposed on the first source-drain conductive layer and extending along the first direction; one end of the first connecting line is electrically connected to the second plate of the first preset pixel circuit through a via, and the other end of the first connecting line is electrically connected to the second plate of the second preset pixel circuit through a via.

[0017] In some embodiments, the plurality of pixel circuits include a third preset pixel circuit, the third preset pixel circuit is adjacent to the second preset pixel circuit, and the first preset pixel circuit and the third preset pixel circuit are respectively located on either side of the second preset pixel circuit along the first direction. The third node of the second preset pixel circuit and the third node of the third preset pixel circuit are arranged away from each other, and the second plate of the second preset pixel circuit is connected to the second plate of the third preset pixel circuit.

[0018] In some embodiments, the drive substrate further includes a second connecting line, the second connecting line being disposed in the first source-drain conductive layer and extending along the first direction. One end of the second connecting line is electrically connected to the second plate of the second preset pixel circuit through a via, and the other end of the second connecting line is electrically connected to the second plate of the third preset pixel circuit through a via. The first connecting lines and the second connecting lines are alternately disposed and sequentially connected along the first direction.

[0019] In some embodiments, the drive substrate further comprises: a second source-drain conductive layer disposed on a side of the first source-drain conductive layer away from the substrate. The drive substrate further comprises a plurality of first voltage signal lines disposed in the second source-drain conductive layer, and the first voltage signal lines extend along the second direction. The first connecting lines and the second connecting lines are alternately arranged along the first direction and sequentially connected to form first auxiliary voltage signal lines. The first voltage signal lines are electrically connected to the plurality of first auxiliary voltage signal lines through a plurality of vias, and the orthographic projections of the plurality of first voltage signal lines and the plurality of first auxiliary voltage signal lines on the substrate form a mesh structure.

[0020] In some embodiments, the drive substrate comprises an array region and a peripheral region surrounding the array region. The drive substrate further comprises a cathode power bus, a plurality of first auxiliary power lines, a plurality of second auxiliary power lines, a first planarization layer, and a passivation layer. The cathode power bus is disposed in the peripheral region and at least partially surrounds the array region. The plurality of first auxiliary power lines extend along the first direction and are spaced apart along the second direction; at least one end of the first auxiliary power line is electrically connected to the cathode power bus. The plurality of second auxiliary power lines extend along the second direction and are spaced apart along the first direction. The plurality of second auxiliary power lines are located on a side of the plurality of first auxiliary power lines away from the substrate, and at least one end of the second auxiliary power line is electrically connected to the cathode power bus. The passivation layer is disposed between the plurality of first auxiliary power lines and the plurality of second auxiliary power lines and includes a plurality of third vias. The first planarization layer is disposed between the passivation layer and the plurality of second auxiliary power lines and includes a plurality of fourth vias, some of which are located within the passivation layer, and some of which are connected to the third vias to form overlapping vias. Part of the overlapping parts of the orthographic projections of the second auxiliary power line and the first auxiliary power line on the substrate at least partially overlaps with the orthographic projection of the fourth via on the substrate; one of the second auxiliary power lines is electrically connected to at least one of the first auxiliary power lines through the overlapping via.

[0021] In some embodiments, the peripheral area includes a fan-out area located on one side of the array area along the second direction, and the plurality of data lines include a plurality of target data lines. The drive substrate also includes a plurality of first fan-out lines and a plurality of second fan-out lines. The plurality of first fan-out lines extend along the first direction and are arranged at intervals along the second direction. The first fan-out line is arranged on the same layer as the first auxiliary power line, and one end of the first fan-out line is electrically connected to the target data line. The plurality of second fan-out lines extend along the second direction and are arranged at intervals along the first direction, the second fan-out line is arranged on the same layer as the second auxiliary power line, one end of the second fan-out line is electrically connected to one end of the first fan-out line away from the target data line through one of the overlapping vias, and the other end extends to the fan-out area, and the second fan-out line is closer to the center of the array area along the first direction than the target data line. Among them, the orthographic projections of the first fan-out line and the second fan-out line on the substrate overlap with the orthographic projections of the first auxiliary power line and the second auxiliary power line on the substrate, at least partially overlap with the orthographic projection of the fourth via on the substrate, and do not overlap with the orthographic projection of the third via on the substrate.

[0022] In another aspect, a display panel is provided, comprising the driving substrate described in any one of the above embodiments, and a plurality of light-emitting devices disposed on the driving substrate, the light-emitting devices being electrically connected to the pixel circuit of the driving substrate.

[0023] In some embodiments, the plurality of light-emitting devices includes a first light-emitting device configured to emit blue light, and the first light-emitting device is electrically connected to the first pixel circuit.

[0024] In some embodiments, the driving substrate includes a second pixel circuit, and the plurality of light emitting devices include a second light emitting device configured to emit red light, and the second light emitting device is electrically connected to the second pixel circuit.

[0025] In some embodiments, the drive substrate includes a third via and a fourth via. The light-emitting device includes an anode pattern. The plurality of light-emitting devices includes a third light-emitting device configured to emit green light. The orthographic projections of the third and fourth vias on the substrate do not overlap with the orthographic projections of the anode pattern of the first and second light-emitting devices on the substrate, and are located within the orthographic projection of the anode pattern of the third light-emitting device on the substrate.

[0026] In some embodiments, the orthographic projections of the third via hole and the fourth via hole on the substrate are located at a geometric center of the orthographic projection of the anode pattern of the third light-emitting device on the substrate.

[0027] The display panel also includes a second planar layer. The second planar layer is disposed on a side of the light-emitting device near the drive substrate and includes a plurality of fifth vias. The light-emitting device includes an anode pattern, a light-emitting layer, and a cathode layer sequentially arranged in a direction away from the substrate. The anode pattern is electrically connected to the pixel circuit of the drive substrate via the fifth vias. The fifth vias do not overlap with the orthographic projection of the light-emitting area of ​​the light-emitting device on the substrate.

[0028] The above-mentioned display device has the same structure and beneficial technical effects as the driving substrate provided in some of the above-mentioned embodiments, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0030] Figure 1 is a structural diagram of a display device according to some embodiments;

[0031] Figure 2 is a structural diagram of a display device according to some embodiments;

[0032] Figure 3 is a diagram of a film layer structure of a display panel according to some embodiments;

[0033] Figure 4 is a circuit diagram of a pixel circuit according to some embodiments;

[0034] Figure 5A is a structural diagram of a semiconductor layer and a first gate conductive layer according to some embodiments;

[0035] Figure 5B is a structural diagram of a second gate conductive layer according to some embodiments;

[0036] Figure 5C is a structural diagram of a first source-drain conductive layer according to some embodiments;

[0037] Figure 5D is a structural diagram of a second source-drain conductive layer according to some embodiments;

[0038] Figure 5E is a structural diagram of a first source-drain conductive layer and a second source-drain conductive layer according to some embodiments;

[0039] Figure 6 is a structural diagram of a first pixel circuit according to some embodiments;

[0040] Figure 7 is a partially enlarged view of a first pixel circuit according to some embodiments;

[0041] Figure 8 For the Figure 6 Sectional view along the middle section line A-A1;

[0042] Figure 9 is a structural diagram of a second pixel circuit according to some embodiments;

[0043] Figure 10 is a structural diagram of a first connecting line according to some embodiments;

[0044] Figure 11 is a structural diagram of a first connecting line and a second connecting line according to some embodiments;

[0045] Figure 12 is a schematic diagram of connecting a SIP signal line and a FIP signal line according to some embodiments;

[0046] Figure 13 A structural diagram showing a passivation layer covering a third via hole according to some embodiments;

[0047] Figure 14 is a structural diagram when the fourth via hole is connected to the third via hole according to some embodiments;

[0048] Figure 15 FIG. 4 is a projection relationship diagram between the anode pattern and the third via hole according to some embodiments. DETAILED DESCRIPTION

[0049] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0050] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0051] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0052] When describing some embodiments, the terms "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can mean a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0053] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0054] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0055] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0056] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0057] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0058] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0059] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0060] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0061] See Figure 1 Embodiments of the present disclosure provide a display device 1000, which is a product having an image display function. For example, the display device 1000 may be any device that displays either moving (e.g., video) or fixed (e.g., still images), and whether text or images.

[0062] In some embodiments, the display device 1000 may be a monitor (MNT), a television, a laptop computer, a tablet computer, a personal digital assistant (PDA), a mobile phone (cell phone), a watch, a clock, a calculator, a GPS receiver / navigator, a camera, a camera view display (for example, a display of a rearview camera in a vehicle), a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, a mixed reality (MR) device, an in-vehicle display, a flight display, or any other product or component with a display function.

[0063] From the perspective of the light-emitting type of the display device 1000, the display device 1000 may be an organic light-emitting diode display device or a quantum dot electroluminescent display device (Quantum Dot Light Emitting Diodes; QLED for short), etc. From the perspective of the form of the display device 1000, the display device 1000 may be a flat display device, a curved display device, or a foldable display device, etc. From the perspective of the shape of the display device 1000, the display device 1000 may be rectangular or circular, etc. The following takes an organic light-emitting diode display device that is rectangular and flat as an example to schematically illustrate some embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto, and any other display devices may also be considered as long as the same technical ideas are applied.

[0064] See Figure 2 In some embodiments, the display device 1000 includes a display panel 1100 and a driver circuit board 1200. The driver circuit board 1200 may include, for example, a timing controller (TCON), a power management chip DC / DC, and an adjustable resistor divider circuit (generating Vcom) and other driving circuits. The driver circuit board 1200 may also include other circuit structures, which are not listed here one by one. The driver circuit board 1200 is connected to the display panel 1100 and is used to transmit a control signal to the display panel 1100, thereby driving the display panel 1100 to realize image display. In addition, the display device 1000 may also include but is not limited to a touch structure, an under-screen camera, and an under-screen fingerprint recognition sensor, so that the display device 1000 can realize a variety of different functions such as touch, photo taking, video recording or fingerprint recognition.

[0065] Continue reading Figure 2 The display panel 1100 has a display area AA and a peripheral area BB. The peripheral area BB is located at least on one side of the display area AA. Exemplarily, the peripheral area BB is arranged around the display area AA. The peripheral area BB includes a fan-out area (Fanout) BB1 located on one side of the display area AA and adjacent to the display area AA. That is, the fan-out area BB1 is an area in the peripheral area BB located on one side of the display area AA. The display area AA is an area on the display panel 1100 for displaying images. The display area AA is provided with a plurality of sub-pixels P. The display area AA can also be considered as the area where the plurality of sub-pixels P are located. Among them, the sub-pixel P is the smallest light-emitting unit on the display panel 1100. The peripheral area BB can be used to set signal routing (such as power signal lines, clock signal lines, etc.), drive circuits (such as gate drive circuits) and binding pins (for binding with a drive circuit board or a source driver chip), etc. Of course, the structure and function of the peripheral area BB are not limited to this and are not listed here one by one. The fan-out area BB1 can be used to lead out signal lines (such as data lines, clock signal lines, power signal lines, etc.) from the display area and the peripheral area and bind them to a driver circuit board or a source driver chip.

[0066] The plurality of sub-pixels P may include at least two sub-pixels emitting light of different colors, which facilitates the display substrate to achieve color display. In one embodiment, the plurality of sub-pixels P may include a red sub-pixel emitting red light, a green sub-pixel emitting green light, and a blue sub-pixel emitting blue light. In addition, the sub-pixel P may include a pixel circuit 10 and a light-emitting device 20, wherein the pixel circuit 10 is configured to drive the light-emitting device 20 to emit light.

[0067] The multiple pixel circuits 10 included in the multiple sub-pixels P are arranged in multiple rows and columns. The multiple pixel circuits 10 arranged along the first direction X are referred to as a row of pixel circuits 10, and the multiple pixel circuits 10 arranged along the second direction Y are referred to as a column of pixel circuits 10. That is, the first direction X is the row direction of the multiple pixel circuits 10, and the second direction Y is the column direction of the multiple pixel circuits 10. The first direction X and the second direction Y intersect. For example, the first direction X and the second direction Y are perpendicular.

[0068] The display panel 1100 also includes a plurality of data lines DL, a plurality of scan signal lines GL, a gate driver circuit (GateDriverOnArray; GOA for short) 30 and a source driver chip (Source Driver IC) 40. The plurality of scan signal lines GL are spaced apart along the second direction Y and extend along the first direction X. A row of pixel circuits 10 can be electrically connected to the plurality of scan signal lines GL. The gate driver circuit 30 can be electrically connected to the pixel circuits 10 through the scan signal lines GL and transmit control signals to the scan signal lines GL. The plurality of data lines DL are arranged along the first direction X and extend along the second direction Y. A data line DL can be electrically connected to at least part of the pixel circuits 10 in a column of pixel circuits 10. For example, in an embodiment of the present disclosure, a column of pixel circuits 10 is electrically connected to two data lines DL. The source driver chip 40 refers to a chip for transmitting data signals to the plurality of data lines DL. The source driver chip 40 can be electrically connected to the pixel circuits 10 through the data lines DL and transmit data signals to the data lines DL and the pixel circuits 10.

[0069] See Figure 3 In some embodiments, the display panel 1100 may include a driving substrate 100, a light-emitting device layer 200, and an encapsulation layer 300. Of course, the display panel 1100 may also include a functional stack disposed on a side of the encapsulation layer 300 away from the driving substrate 100. The functional stack may be, for example, one or more of a touch function layer, an anti-reflection layer, a hardening layer, and an anti-fingerprint layer, so that the display panel can achieve corresponding functions. The embodiments of the present disclosure do not specifically limit the type and quantity of the above-mentioned functional stacks.

[0070] The light emitting device layer 200 may include an anode layer 21, a pixel defining layer 22, a light emitting function layer 23, and a cathode layer 24 arranged in sequence in a direction away from the driving substrate 100. The anode layer 21 includes a plurality of anode patterns 25 arranged at intervals, and the pixel defining layer 22 includes a plurality of openings 221 ( Figure 3(Only one anode pattern 25 and one opening 211 are shown as examples, and an opening 221 exposes at least a portion of an anode pattern 25.) A light-emitting device 20 may include an anode pattern 25, a portion of the light-emitting functional layer 23 located within the opening 221, and a portion of the cathode layer 24 located within the opening 221. An opening 221 also defines a light-emitting area of ​​the light-emitting device 20, i.e., the light-emitting area of ​​the light-emitting device 20 is the same size as the opening 221 on the anode pattern 25 of the light-emitting device 20.

[0071] The encapsulation layer 300 is configured to reduce the risk of water vapor and oxygen in the external environment entering the light emitting device 20, thereby increasing the service life of the display panel 1100. The encapsulation layer 300 can be an encapsulation film or an encapsulation substrate. For example, Figure 3 As shown, in the case where the encapsulation layer 300 is an encapsulation film, the encapsulation layer 300 may include a first inorganic encapsulation layer 301 , an organic encapsulation layer 302 , and a second inorganic encapsulation layer 303 which are sequentially stacked.

[0072] The driving substrate 100 is used to prepare and form the above-mentioned pixel circuit 10, gate driving circuit 30, data line DL and scanning signal line GL. Figure 3 The driving substrate 100 may include a substrate 11 and a semiconductor layer 12, a first gate insulating layer 13, a first gate conductive layer 14, a second gate insulating layer 15, a second gate conductive layer 16, an interlayer dielectric layer 17, a first source-drain conductive layer 18, a passivation layer 31, a first planarizing layer 19, a second source-drain conductive layer 32, and a second planarizing layer 33, which are arranged in sequence along a direction away from the substrate 11.

[0073] The pixel circuit 10 includes a plurality of thin film transistors (TFTs) and at least one storage capacitor Cst. The thin film transistors may include an active pattern located in the semiconductor layer 12, a gate located in the first gate conductive layer 14, and a source and drain located in the first source-drain conductive layer 18. The storage capacitor Cst may include a first electrode 141 located in the first gate conductive layer 14 and a second electrode 142 located in the second gate conductive layer 16.

[0074] See Figure 4 and Figure 5A In some embodiments, the pixel circuit 10 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor Cst.

[0075] The third transistor T3 is a driving transistor. The gate of the third transistor T3 is electrically connected to the first node N1, the first electrode is electrically connected to the second node N2, and the second electrode is electrically connected to the third node N3. The third transistor T3 is configured to generate a driving current under the control of the voltage difference (Vgs) between the first node N1 and the second node N2. The driving current is used to drive the light-emitting device 20 to emit light.

[0076] The first transistor T1 has a gate electrically connected to the first scan signal line GL1, a first electrode electrically connected to the first reference signal line Vinit1, and a second electrode electrically connected to the first node N1. The first reference signal line Vinit1 can be used to provide a constant first reference voltage. For example, the first reference voltage can be a negative voltage. The first transistor T1 is configured to be turned on or off under the control of the first scan signal line GL1. When the first transistor T1 is turned on, the first transistor T1 can electrically connect the first reference signal line Vinit1 to the first node N1, thereby transmitting the first reference voltage of the first reference signal line Vinit1 to the first node N1, thereby initializing (resetting) the potential of the first node N1.

[0077] The gate of the second transistor T2 is electrically connected to the second scan signal line GL2, the first electrode is electrically connected to the first node N1, and the second electrode is electrically connected to the second node N2. The gate of the fourth transistor T4 is electrically connected to the second scan signal line GL2, the first electrode is electrically connected to the data line DL, and the second electrode is electrically connected to the second node N2. In addition, the first electrode of the fourth transistor T4 also serves as an access point for receiving a data signal. The second transistor T2 and the fourth transistor T4 are configured to be turned on or off under the control of the second scan signal line GL2. When the second transistor T2 and the fourth transistor T4 are turned on, the fourth transistor T4 transmits the data signal transmitted by the data line DL to the first node N1. After passing through the third transistor T3 and the second transistor T2 in sequence, the data signal compensates for the threshold voltage Vth of the third transistor T3 and is transmitted to the first node N1.

[0078] The fifth transistor T5 has a gate electrically connected to the light-emission control signal line EM, a first electrode electrically connected to the first voltage signal line VDD, and a second electrode electrically connected to the second node N2. The sixth transistor T6 has a gate electrically connected to the light-emission control signal line EM, a first electrode electrically connected to the third node N3, and a second electrode electrically connected to the fourth node N4. The fourth node N4 is also electrically connected to the light-emitting device 20 (e.g., the anode pattern 25 of the light-emitting device 20). The first voltage signal line VDD is configured to provide a constant positive power supply voltage. The fifth transistor T5 and the sixth transistor T6 are configured to be turned on or off under the control of the light-emission control signal line EM. When the fifth transistor T5 and the sixth transistor T6 are turned on, the fifth transistor T5 electrically connects the first voltage signal line VDD to the second node N2. At this time, the third transistor T3 generates a drive current under the control of the voltages of the first node N1 and the second node N2. The sixth transistor T6 transmits this drive current to the light-emitting device 20, driving the light-emitting device 20 to emit light.

[0079] The seventh transistor T7 has a gate electrically connected to the second scan signal line GL2, a first electrode electrically connected to the second reference signal line Vinit2, and a second electrode electrically connected to the fourth node N4. The second reference signal line Vinit2 is configured to provide a constant second reference voltage. For example, the second reference voltage can be a negative voltage. For example, the first reference voltage can be the same as the second reference voltage. The seventh transistor T7 is configured to be turned on or off under the control of the second scan signal line GL2. When the seventh transistor T7 is turned on, it electrically connects the second reference signal line Vinit2 to the fourth node N4, thereby transmitting the second reference voltage of the second reference signal line Vinit2 to the fourth node N4, thereby initializing the potential of the fourth node N4.

[0080] The first plate 141 of the storage capacitor Cst is electrically connected to the first node N1, and the second plate 142 is electrically connected to the first voltage signal line VDD. The storage capacitor Cst can store and maintain the voltage of the first node N1 to ensure a stable driving current generated by the third transistor T3 within one frame period.

[0081] like Figure 4 In the pixel circuit 10 shown, as the voltage value of the data signal written into the first node N1 increases, the voltage value of the first node N1 also increases, the driving current generated by the third transistor T3 decreases, and the brightness of the light-emitting device 20 also decreases. In other words, when the light-emitting device 20 needs to display a high grayscale (such as L255), the voltage value of the data signal is lower than the voltage value of the data signal when the light-emitting device 20 needs to display a low grayscale (such as L0).

[0082] The inventors have discovered that for sub-pixels that emit light of different colors, at least part of the material of the light-emitting functional layer 23 in the light-emitting device 20 is different. And for the blue sub-pixel, due to the material characteristics of its light-emitting functional layer 23, the blue sub-pixel has the characteristic of being easy to black and difficult to bright. Compared with other sub-pixels (such as red sub-pixels and green sub-pixels), the blue sub-pixel can display the black state L0 grayscale under the control of a data signal with a smaller voltage value, and can only display the bright state L255 grayscale under the control of a data signal with an even smaller voltage value. However, due to the limitation of the adjustable voltage range that the source driver chip can provide, the brightness limit of the blue sub-pixel is limited by the data signal with the minimum voltage value that the source driver chip can provide within its adjustable voltage range.

[0083] See Figure 5A and Figure 6 In the driving substrate 100 in the embodiment of the present disclosure, the plurality of pixel circuits 10 may include a first pixel circuit 101, and the first pixel circuit 101 includes a first access point 41 for receiving a first data signal. The first access point 41 may be a first electrode of a fourth transistor T4 in the first pixel circuit 101. The plurality of data lines DL include a first data line DL1, and a spacing L1 is provided between the first data line DL1 and the first access point 41 along the first direction X. The driving substrate 100 further includes a transfer signal line 42, one end of the transfer signal line 42 being electrically connected to the first access point 41, and the other end of the transfer signal line 42 being electrically connected to the first data line DL1. The first data line DL1 and the first access point 41 are electrically connected via the transfer signal line 42, which helps to increase the transmission path of the data signal. The transfer signal line 42 can form a parasitic capacitance with other conductive structures on the drive substrate 100, thereby increasing the load on the data signal transmission path, thereby reducing the voltage value of the data signal written to the first access point 41, thereby reducing the minimum voltage value written to the first access point 41, increasing the maximum drive current that can be generated by the first pixel circuit 101, and improving the luminous brightness of the light-emitting device 20 electrically connected to the first pixel circuit 101.

[0084] In some embodiments, the display panel 1100 includes a first light-emitting device 201 configured to emit blue light. The first light-emitting device 201 is electrically connected to a first pixel circuit 101 via a transfer signal line 42. Thus, the first pixel circuit 101 and the first light-emitting device 201 together form a blue sub-pixel. The first pixel circuit 101 can reduce the minimum voltage value of the data signal transmitted to the first light-emitting device 201, thereby increasing the maximum brightness of the first light-emitting device 201 and the maximum brightness of the blue sub-pixel.

[0085] Because the blue sub-pixel also has the characteristic of being easily black, that is, the blue sub-pixel can display the black state L0 grayscale under the control of a data signal with a relatively small voltage value (a relatively small driving current), thus, even if the minimum driving current transmitted by the first pixel circuit 101 is correspondingly reduced, the blue sub-pixel can still display the black state L0 grayscale. In other words, the design of the first pixel circuit 101 of the present application can increase the brightness of the blue sub-pixel displaying the bright state L255 grayscale while ensuring that the blue sub-pixel normally displays the black state L0 grayscale, thereby alleviating the problem that the blue sub-pixel is easily black and difficult to brighten.

[0086] See also Figure 5C and Figure 6 In some embodiments, the transfer signal line 42 includes a first sub-portion 421 , which extends along the first direction X. The driving substrate 100 also includes a first reference signal line Vinit1 , which extends along the first direction X. The orthographic projection of the first sub-portion 421 on the substrate 11 overlaps with the orthographic projection of the first reference signal line Vinit1 on the substrate 11 . In this way, a parasitic capacitance can be formed between the first sub-portion 421 and the first reference signal line Vinit1 , further increasing the load of the first sub-portion 421 , thereby reducing the voltage value of the data signal written to the first access point 41 , further reducing the minimum voltage value written to the first access point 41 , increasing the maximum driving current that the first pixel circuit 101 can generate, and increasing the brightness of the light-emitting device 20 electrically connected to the first pixel circuit 101 .

[0087] See Figure 5A and Figure 6 The pixel circuit 10 includes a first transistor T1 and a third transistor T3. The connection relationship between the first transistor T1 and the third transistor T3 is described above and will not be further described here. The first transistor T1 includes a first active pattern 43 for forming a first electrode, a channel, and a second electrode of the first transistor T1. The first electrode of the first active pattern 43 is electrically connected to the first reference signal line Vinit1, and the second electrode of the first active pattern 43 is electrically connected to the gate of the third transistor T3.

[0088] See Figure 6 、 Figure 7 and Figure 8Along a direction perpendicular to the substrate 11, the first active pattern 43, the first reference signal line Vinit1, and the first sub-portion 421 of the transfer signal line 42 in the first pixel circuit 101 overlap, and the first reference signal line Vinit1 is located between the first active pattern 43 and the first sub-portion 421. The first reference signal line Vinit1 can provide a constant first reference voltage and is located between the first active pattern 43 and the first sub-portion 421. The first reference signal line Vinit1 can shield the voltage interference between the first sub-portion 421 and the first active pattern 43, reducing the impact of voltage fluctuations on the first sub-portion 421 (voltage fluctuations before and after data signal transmission and during data signal transmission) on the first active pattern 43.

[0089] For example, Figure 5B As shown, the first reference signal line Vinit1 is located in the second gate conductive layer 16. In other words, the second gate conductive layer 16 includes the first reference signal line Vinit1. One row of pixel circuits 10 may be provided with one first reference signal line Vinit1.

[0090] Continue reading Figure 5C 、 Figure 6 and Figure 8 The transfer signal line 42 further includes a second sub-portion 422, which extends along the second direction Y. The drive substrate 100 further includes a second reference signal line Vinit2. The second reference signal line Vinit2 extends along the first direction X and is located between the first reference signal line Vinit1 and the first access point 41 in the second direction Y. The orthographic projection of the second sub-portion 422 on the substrate 11 overlaps with the orthographic projection of the second reference signal line Vinit2 on the substrate 11. In this way, a parasitic capacitance can be formed between the second sub-portion 422 and the second reference signal line Vinit2, further increasing the load of the transfer signal line 42, thereby reducing the voltage value of the data signal written to the first access point 41 through the transfer signal line 42, further reducing the minimum voltage value written to the first access point 41, increasing the maximum drive current that the first pixel circuit 101 can generate, and increasing the luminous brightness of the first light-emitting device 201 electrically connected to the first pixel circuit 101.

[0091] Exemplarily, the second reference signal line Vinit2 is located in the second gate conductive layer 16. In other words, the second gate conductive layer 16 includes the second reference signal line Vinit2. One second reference signal line Vinit2 may be provided for each row of pixel circuits 10. The first reference signal line Vinit1 and the second reference signal line Vinit2 are both located in the second gate conductive layer 16. Multiple first reference signal lines Vinit1 and multiple second reference signal lines Vinit2 may be alternately arranged in the second direction Y.

[0092] like Figure 6 and Figure 7 As shown, one end of the first sub-section 421 is electrically connected to the first data line DL1, the other end of the first sub-section 421 is electrically connected to one end of the second sub-section 422, and the other end of the second sub-section 422 is electrically connected to the first access point 41. The transfer signal line 42 is formed into an "L"-shaped structure, which can greatly increase the load on the transfer signal line 42, reduce the voltage value of the data signal written to the first access point 41 through the transfer signal line 42, increase the maximum drive current that can be generated by the first pixel circuit 101, and improve the brightness of the first light-emitting device 201 electrically connected to the first pixel circuit 101.

[0093] See also Figure 5A 、 Figure 5C 、 Figure 5D 、 Figure 6 and Figure 8 In some embodiments, the first access point 41 is provided in the semiconductor layer 12, the transfer signal line 42 is provided in the first source-drain conductive layer 18, and the plurality of data lines DL are provided in the second source-drain conductive layer 32. One end of the transfer signal line 42 is electrically connected to the first access point 41 through a first via V1, and the other end of the transfer signal line 42 is electrically connected to the first data line DL1 through a second via V2.

[0094] See Figure 5A 、 Figure 5C 、 Figure 5D and Figure 5E , the driving substrate 100 also includes a first voltage signal line VDD. The first voltage signal line VDD extends along the second direction Y and is electrically connected to the pixel circuit 10. Exemplarily, the first voltage signal line VDD can be located in the second source-drain conductive layer 32. Along the first direction X, the first access point 41 and the first data line DL1 are respectively located on both sides of the first voltage signal line VDD. In this way, the positive projection of the transfer signal line 42 on the substrate 11 can also at least partially overlap with the positive projection of the first voltage signal line VDD on the substrate 11, thereby forming a parasitic capacitance between the transfer signal line 42 and the first voltage signal line VDD, thereby increasing the load on the transfer signal line 42, reducing the voltage value of the data signal written to the first access point 41, reducing the minimum voltage value written to the first access point 41, increasing the maximum driving current that the first pixel circuit 101 can generate, and increasing the luminous brightness of the first light-emitting device 201 electrically connected to the first pixel circuit 101.

[0095] See Figure 5A 、 Figure 5E and Figure 9The multiple pixel circuits 10 further include a second pixel circuit 102. The first pixel circuits 101 and the second pixel circuits 102 are alternately arranged along the second direction Y. In other words, two adjacent pixel circuits 102 along the second direction Y are respectively the first pixel circuit 101 and the second pixel circuit 102. The second pixel circuit 102 includes a second access point 44 for receiving a second data signal. The second access point 44 can be the first electrode of the fourth transistor T4 in the second pixel circuit 102. The multiple data lines DL further include a second data line DL2. Along the first direction X, the first data line DL1 and the second data line DL2 are respectively located on either side of a pixel circuit column formed by the alternating arrangement of the first pixel circuits 101 and the second pixel circuits 102. In other words, a first data line DL1 and a second data line DL2 are respectively provided on either side of a column of pixel circuits 10 along the first direction X. The driving substrate 100 adopts a dual data line (DDL) structure, which is beneficial to improving the writing time of a row of pixel circuits 10, that is, improving the time for the data line DL to transmit the data signal to the pixel circuit 10, which is beneficial to fully writing the data signal into the pixel circuit, improving the compensation effect of the threshold voltage Vth of the third transistor T3, and thus improving the display uniformity of the display panel.

[0096] For example, Figure 5A 、 Figure 5E and Figure 9 As shown, the first access point 41 of the first pixel circuit 101 and the second access point 44 of the second pixel circuit 102 are arranged at intervals along the second direction Y, and the first access point 41 and the second access point 44 are both located on the side close to the second data line DL2, that is, the interval between the first access point 41 and the second access point 44 and the second data line DL2 in the first direction X is smaller than the interval between the first access point 41 and the second access point 44 and the first data line DL1 in the first direction X.

[0097] The spacing between the second access point 44 and the second data line DL2 along the first direction X is smaller than the spacing between the first access point 41 and the first data line DL1 along the first direction X. The load on the connection line between the second data line DL2 and the second access point 44 is smaller than the load on the connection line (transfer signal line 42) between the first data line DL1 and the first access point 41. The plurality of light-emitting devices 20 may include a second light-emitting device 202. The second light-emitting device 202 may be configured to emit red light. The second light-emitting device 202 may be electrically connected to the second pixel circuit 102. The second light-emitting device 202 and the second pixel circuit 102 together form a red sub-pixel. This helps increase the voltage of the data signal written to the second access point 44, thereby reducing the load on the red data signal during transmission to the red sub-pixel. This helps reduce the risk of the red sub-pixel emitting light when displaying the black state (grayscale L0) and the risk of the red sub-pixel being overly bright when displaying the bright state (grayscale L255).

[0098] In some embodiments, the display panel may employ an RGBG pixel arrangement, i.e., one pixel unit includes one red sub-pixel, one blue sub-pixel, and two green sub-pixels, and multiple red sub-pixels and multiple blue sub-pixels are alternately arranged into pixel rows in a first direction X, and multiple green sub-pixels are alternately arranged into rows in the first direction X; multiple red sub-pixels and multiple blue sub-pixels are alternately arranged into pixel rows in a second direction Y, and multiple green sub-pixels are alternately arranged into columns in the second direction Y. Based on the above arrangement of sub-pixels P, three pixel circuits 10 are spaced between two adjacent transfer signal lines 42 along the first direction X, and one pixel circuit 10 is spaced between two adjacent transfer signal lines 42 along the second direction Y. In other words, three pixel circuits for sub-pixels of another color (two green sub-pixels and one red sub-pixel) are included between the first pixel circuits 101 of two adjacent blue sub-pixels along the first direction X, and one pixel circuit for a sub-pixel of another color (red) is included between the first pixel circuits 101 of two adjacent blue sub-pixels along the second direction Y.

[0099] In an embodiment of the present disclosure, the plurality of pixel circuits 10 may further include a third pixel circuit, the light-emitting device may include a third light-emitting device, the third light-emitting device is configured to emit green light, and the third light-emitting device is electrically connected to the third pixel circuit to form a green sub-pixel. In other words, the green sub-pixel includes the third pixel circuit and the third light-emitting device. The structure of part of the third pixel circuit may be the same as that of the first pixel circuit, and the structure of part of the third pixel circuit may be the same as that of the second pixel circuit. The embodiments of the present disclosure will not be further described in detail.

[0100] See Figure 4 、 Figure 5A and Figure 6The pixel circuit 10 includes a second transistor T2, a third transistor T3, and a storage capacitor Cst. The connection method of the second transistor T2, the third transistor T3, and the storage capacitor Cst is described above and will not be repeated here. The storage capacitor Cst includes a first electrode 141 and a second electrode 142 that are arranged in an overlapping manner perpendicular to the substrate 11. The first electrode 141 is located on the first gate conductive layer 14, and the second electrode 142 is located on the second gate conductive layer 16.

[0101] The second transistor T2 includes a second active pattern 45 for forming a first electrode, a channel, and a second electrode of the second transistor T2. The third transistor T3 includes a third active pattern 46 for forming a first electrode, a channel, and a second electrode of the third transistor T3. The first electrode of the second active pattern 45 is connected to the second electrode of the third transistor T3, and the connection between the second active pattern 45 and the third active pattern 46 forms a third node N3. The first electrode plate 141 also forms the gate of the third transistor T3. The second electrode plate 142 is located on a side of the first electrode plate 141 away from the substrate 11 and is configured to receive a first voltage signal (electrically connected to the first voltage signal line VDD).

[0102] See Figure 5A 、 Figure 5B 、 Figure 10 The plurality of pixel circuits 10 include a first preset pixel circuit 103 and a second preset pixel circuit 104 adjacently arranged along a first direction X. The third nodes N3 of the first preset pixel circuit 103 and the second preset pixel circuit 104 are arranged close to each other. The second plate 142 of the first preset pixel circuit 103 and the second plate 142 of the second preset pixel circuit 104 are spaced apart from each other along the first direction X. The orthographic projection of the second plate 142 of the first preset pixel circuit 103 onto the substrate 11 does not overlap with the orthographic projection of the third node N3 of the first preset pixel circuit 103 onto the substrate 11, and the orthographic projection of the second plate 142 of the second preset pixel circuit 104 onto the substrate 11 does not overlap with the orthographic projection of the third node N3 of the second preset pixel circuit 104 onto the substrate 11. In this way, the area of ​​overlap between the orthographic projections of the second electrode 142 and the third node N3 on the substrate 11 can be reduced, thereby reducing the parasitic capacitance formed between the second electrode 142 and the third node N3, which is conducive to fully writing the data signal to the gate of the third transistor T3 and reducing the risk of the sub-pixel being lit when displaying 0 grayscale.

[0103] The drive substrate 100 further includes a second gate conductive layer 16 and a first source-drain conductive layer 18 stacked on the substrate 11 in a direction away from the substrate 11. The second plate 142 of the storage capacitor Cst is disposed on the second gate conductive layer 16. The drive substrate 100 further includes a first connecting line 47 disposed on the first source-drain conductive layer 18. The first connecting line 47 extends along the first direction X. One end of the first connecting line 47 is electrically connected to the second plate 142 of the first preset pixel circuit 103 through a via, and the other end of the first connecting line 47 is electrically connected to the second plate 142 of the second preset pixel circuit 104 through a via. In this way, the second plate 142 of the first preset pixel circuit 103 can be electrically connected to the second plate 142 of the second preset pixel circuit 104 through multiple first connecting lines 47, which facilitates the transmission of the first voltage signal line VDD to (all) the second plates. Moreover, the first connecting line 47 is arranged in the first source-drain conductive layer 18, and the interval between the first connecting line 47 and the third node N3 is relatively large, which is beneficial to reducing the parasitic capacitance between the first connecting line 47 and the third node N3, and is beneficial to fully writing the data signal to the gate of the third transistor T3, thereby reducing the risk of the sub-pixel being lit when displaying 0 grayscale.

[0104] The plurality of pixel circuits 10 include a third preset pixel circuit 105, which is adjacent to the second preset pixel circuit 104. The first preset pixel circuit 103 and the third preset pixel circuit 105 are respectively located on either side of the second preset pixel circuit 104 along the first direction X. The third node N3 of the second preset pixel circuit 104 and the third node N3 of the third preset pixel circuit 105 are located apart from each other, and the second electrode plate 142 of the second preset pixel circuit 104 is connected to the second electrode plate 142 of the third preset pixel circuit 105. This helps increase the area of ​​the second electrode plate 142, increases the capacitance of the storage capacitor Cst, and facilitates storing and maintaining the gate voltage of the third transistor T3. In the embodiments of the present disclosure, when describing three non-identical and adjacent pixel circuits 10, the same pixel circuit can form the first preset pixel circuit 103, the second preset pixel circuit 104, and the third preset pixel circuit 105, that is, the same pixel circuit 10 can have different names when facing different division methods.

[0105] like Figure 5C 、 Figure 5E and Figure 11As shown, in some embodiments, the drive substrate 100 further includes a second connecting line 48. The second connecting line 48 is disposed on the first source-drain conductive layer 18 and extends along the first direction X. One end of the second connecting line 48 is connected to the second electrode plate 142 of the second preset pixel circuit 104 through a via, and the other end of the second connecting line 48 is connected to the second electrode plate 142 of the third preset pixel circuit 105 through a via. The first connecting lines 47 and the second connecting lines 48 are alternately disposed and sequentially connected along the first direction X. In other words, the first connecting lines 47 and the second connecting lines 48 are connected to form an integrated structure, and the first connecting lines 47 and the second connecting lines 48 are connected to form a first auxiliary voltage signal line 49.

[0106] In some embodiments, see Figure 5C 、 Figure 5D and Figure 5E The driver substrate 100 further includes a plurality of first voltage signal lines VDD. The first voltage signal lines VDD are disposed on the second source-drain conductive layer 32 and extend along the second direction Y. The first voltage signal lines VDD are electrically connected to the plurality of first auxiliary voltage signal lines 49 through a plurality of vias. The orthographic projections of the plurality of first voltage signal lines VDD and the plurality of first auxiliary voltage signal lines 49 on the substrate form a mesh structure. This helps reduce the resistance of the first voltage signal lines VDD, thereby reducing the voltage drop across the first voltage signal lines VDD, and thus improving brightness uniformity across different locations on the display panel.

[0107] See Figure 12 The driving substrate 100 has an array area A1 and a peripheral area BB surrounding the array area, wherein the array area A1 is a region on the driving substrate 100 for setting the pixel circuit 10 , or in other words, the array area A1 corresponds to the display area AA of the display panel 1100 .

[0108] The driving substrate 100 also includes a cathode power bus VSS, multiple first auxiliary power lines 53 and multiple second auxiliary power lines 54. The cathode power bus VSS is arranged in the peripheral area BB and at least partially surrounds the array area A1. For example, the cathode power bus VSS can be arranged around the array area A1.

[0109] Multiple first auxiliary power lines 53 extend along a first direction X and are spaced apart along a second direction Y. At least one end of the first auxiliary power lines 53 is electrically connected to the cathode power bus VSS. Multiple second auxiliary power lines 54 extend along the second direction Y and are spaced apart along the first direction X. The multiple second auxiliary power lines 54 are located on a side of the multiple first auxiliary power lines 53 away from the substrate 11, and at least one end of the second auxiliary power lines 54 is electrically connected to the cathode power bus VSS. In other words, multiple first auxiliary power lines 53 and multiple second auxiliary power lines 54 are provided in the array area A1 of the drive substrate 100, that is, the display panel adopts a SIP (VSS in Pixel) structure. The multiple first auxiliary power lines 53 and the multiple second auxiliary power lines 54 can reduce the voltage drop of the cathode power bus VSS, thereby improving the display uniformity of the display panel.

[0110] For example, the plurality of first auxiliary power lines 53 may be disposed in the first source-drain conductive layer 18 , and the plurality of second auxiliary power lines 54 may be disposed in the second source-drain conductive layer 32 .

[0111] See Figure 12 、 Figure 13 and Figure 14 The drive substrate 100 further includes a first planar layer 19 and a passivation layer 31. The passivation layer 31 is disposed between the plurality of first auxiliary power lines 53 and the plurality of second auxiliary power lines 54, and the passivation layer 31 includes a plurality of third via holes V3. The first planar layer 19 is disposed between the passivation layer 31 and the plurality of second auxiliary power lines 54. The first planar layer 19 includes a plurality of fourth via holes V4. Figure 13 As shown, the opening of part of the fourth via hole V4 is located in the passivation layer, that is, the opening of part of the fourth via hole V4 close to the passivation layer 31 is blocked by the passivation layer 31, and it is impossible to electrically connect the conductive layer of the passivation layer 31 close to the substrate side through this part of the fourth via hole V4. For example, the part of the second auxiliary power line 54 in the fourth via hole V4 is separated from the first auxiliary power line 53 by the passivation layer 31, and the two cannot be electrically connected in the above-mentioned fourth via hole V4. Figure 14 As shown, part of the fourth via V4 is connected to the third via V3 to form a overlapping via V6, that is, the positive projection of the part of the fourth via V4 and the third via V3 on the substrate at least partially overlaps, and the second auxiliary power line 54 can be electrically connected to the first auxiliary power line 53 on the lower side through the fourth via V4 and the third via V3 in sequence.

[0112] The overlapping portion of the orthographic projections of the second auxiliary power line 54 and the first auxiliary power line 53 on the substrate 11 at least partially overlaps the orthographic projection of the fourth via V4 on the substrate 11. That is, the first planar layer 19 is provided with fourth vias V4 at the locations where the second auxiliary power line 54 and the first auxiliary power line 53 overlap, and third vias V3 are only provided at locations where the fourth vias V4 overlap. A second auxiliary power line 54 is electrically connected to at least one first auxiliary power line 53 via a bridging via V6. The second auxiliary power line 54 and the first auxiliary power line 53 are electrically connected only at locations where both the third via V3 and the fourth via V4 are provided. They are separated by the passivation layer 31 at locations where only the fourth via V4 is provided, and no third via V3 is provided. In the embodiment of the present disclosure, by setting a fourth via V4 at a position where the second auxiliary power line 54 and the first auxiliary power line 53 do not need to be electrically connected, the structural uniformity (consistency of convexity and concavity) of the second auxiliary power line 54 at different positions can be improved, thereby reducing the reflection difference of the second auxiliary power line 54 at the overlapping position with the first auxiliary power line 53, and reducing the risk of screen-off Mura on the display panel.

[0113] like Figure 12 As shown, in some embodiments, the plurality of data lines DL include a plurality of target data lines DL3, and the drive substrate further includes a plurality of first fan-out lines 51 and a plurality of second fan-out lines 52. The plurality of first fan-out lines 51 extend along the first direction X and are arranged at intervals along the second direction Y. The first fan-out lines 51 and the first auxiliary power lines 53 are disposed in the same layer. For example, the first fan-out lines 51 and the first auxiliary power lines 53 are both located in the first source-drain conductive layer 18. The plurality of second fan-out lines 52 extend along the second direction Y and are arranged at intervals along the first direction X. The second fan-out lines 52 and the second auxiliary power lines 54 are disposed in the same layer. For example, the plurality of second fan-out lines 52 and the second auxiliary power lines 54 are both located in the second source-drain conductive layer 32.

[0114] One end of the first fan-out line 51 is electrically connected to the target data line DL3. One end of the second fan-out line 52 is electrically connected to the end of the first fan-out line 51 away from the target data line DL3 through a lap via V6. The other end extends to the fan-out area B1. Compared with the target data line DL, the second fan-out line 52 is closer to the center of the array area A1 along the first direction X. In other words, the data line DL adopts the display area fan-out (FIP) technology, which is beneficial to reducing the size of the fan-out area B1 along the second direction Y and facilitating the display panel to achieve a narrow frame.

[0115] The overlapping portions of the orthographic projections of the first fan-out line 51 and the second auxiliary power line 54 on the substrate 11, and the overlapping portions of the orthographic projections of the first auxiliary power line 53 and the second fan-out line 52 on the substrate 11, at least partially overlap with the orthographic projection of the fourth via V4 on the substrate 11, and do not overlap with the orthographic projection of the third via V3 on the substrate 11. In this way, without causing a short circuit between the first fan-out line 51 and the second auxiliary power line 54, and between the first auxiliary power line 53 and the second fan-out line 52, the structural uniformity (consistency of the concavities and convexities) of the second fan-out line 52 and the second auxiliary power line 54 at different locations can be improved, further reducing the difference in reflection between the second fan-out line 52 at the location where it overlaps with the first auxiliary power line 53 and at the location where it connects to the first fan-out line 51, thereby reducing the risk of screen-off mura on the display panel.

[0116] See Figure 15 In some embodiments, when a display panel includes blue, red, and green sub-pixels, the blue sub-pixel includes a first light-emitting device 201 configured to emit blue light; the red sub-pixel includes a second light-emitting device 202 configured to emit red light; and the green sub-pixel includes a third light-emitting device 203 configured to emit green light. The light-emitting device 20 includes an anode pattern 25. The light-emitting area of ​​the light-emitting device 20 is within the range of the anode pattern 25 and is generally slightly smaller than the range of the anode pattern 25.

[0117] The orthographic projections of the third via hole V3 and the fourth via hole V4 on the substrate 11 do not overlap with the orthographic projections of the anode pattern 25 of the first light-emitting device 201 and the anode pattern 25 of the second light-emitting device 202 on the substrate 11. In this way, the third via hole V3 and the fourth via hole V4 can avoid the anode pattern 25 of the first light-emitting device 201 and the second light-emitting device 202, which is beneficial to improving the flatness of the anode pattern 25 of the first light-emitting device 201 and the second light-emitting device 202, thereby reducing the degree and risk of color deviation at the position of the anode pattern 25 of the first light-emitting device 201 and the second light-emitting device 202.

[0118] Exemplarily, the orthographic projections of the third via hole V3 and the fourth via hole V4 on the substrate 11 do not overlap with the orthographic projections of the anode patterns 25 of the first light-emitting device 201 and the second light-emitting device 202 on the substrate 11 .

[0119] The orthographic projections of the third and fourth vias V3 and V4 on the substrate 11 are located within the orthographic projections of the anode pattern 25 of the third light-emitting device 203 on the substrate 11. Due to wiring space limitations, the third and fourth vias V3 and V4 cannot completely avoid the anode pattern 25 of the third light-emitting device 203. Compared to positioning the third and fourth vias V3 and V4 at the edges of the anode pattern 25 of the third light-emitting device 203, positioning the third and fourth vias V3 and V4 within the anode pattern 25 of the third light-emitting device 203 can reduce the problem of asymmetric color shift of the third light-emitting device 203 along different directions at the locations of the third and fourth vias V3 and V4.

[0120] Exemplarily, the orthographic projections of the third via hole V3 and the fourth via hole V4 on the substrate 11 are located within the range of the orthographic projection of the anode pattern 25 of the third light-emitting device 203 on the substrate 11 .

[0121] In some embodiments, the orthographic projections of the third via V3 and the fourth via V4 on the substrate 11 are located at the geometric center of the orthographic projection of the anode pattern 25 of the third light-emitting device 203 on the substrate 11. This can greatly reduce the asymmetric color shift of the third light-emitting device 203 along different directions at the locations of the third via V3 and the fourth via V4.

[0122] See Figure 3 and Figure 15 The display panel 1100 also includes a second planar layer 33, which is disposed on the side of the light-emitting device 20 closest to the drive substrate. The second planar layer 33 includes a plurality of fifth vias V5. The anode pattern 25 is electrically connected to the pixel circuit 10 of the drive substrate 100 through the fifth vias V5. The fifth vias V5 do not overlap with the orthographic projection of the light-emitting area of ​​the light-emitting device 20 on the substrate 11. This reduces color shift caused by the light-emitting device 20 at the location of the fifth vias V5.

[0123] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A driving substrate, characterized in that: include: substrate; A plurality of pixel circuits are provided on the substrate and arranged in a plurality of rows and columns; the plurality of pixel circuits include a first pixel circuit, the first pixel circuit including a first access point for accessing a first data signal; a plurality of data lines extending along a second direction; the plurality of data lines including a first data line, wherein a distance is provided between the first data line and the first access point along the first direction; the first direction being a row direction in which the plurality of pixel circuits are arranged, and the second direction being a column direction in which the plurality of pixel circuits are arranged; A transfer signal line, one end of which is electrically connected to the first access point, and the other end of which is electrically connected to the first data line.

2. The driving substrate according to claim 1, wherein: The transfer signal line includes a first sub-portion, and the first sub-portion extends along the first direction; The driving substrate further includes: A first reference signal line extends along the first direction, and an orthographic projection of the first sub-portion on the substrate overlaps with an orthographic projection of the first reference signal line on the substrate.

3. The driving substrate according to claim 2, wherein: The pixel circuit includes a first transistor and a third transistor, the first transistor includes a first active pattern for forming a first electrode, a channel, and a second electrode of the first transistor, the first electrode of the first active pattern is electrically connected to the first reference signal line, and the second electrode of the first active pattern is electrically connected to the gate of the third transistor; Along a direction perpendicular to the substrate, the first active pattern, the first reference signal line, and a first sub-portion of the transfer signal line in the first pixel circuit overlap, and the first reference signal line is located between the first active pattern and the first sub-portion.

4. The driving substrate according to claim 2, wherein: The transfer signal line further includes a second sub-portion, and the second sub-portion extends along the second direction; The driving substrate further includes: A second reference signal line extends along the first direction and is located between the first reference signal line and the first access point in the second direction; an orthographic projection of the second sub-portion on the substrate overlaps with an orthographic projection of the second reference signal line on the substrate.

5. The driving substrate according to claim 4, wherein: One end of the first sub-unit is electrically connected to the first data line, the other end of the first sub-unit is electrically connected to one end of the second sub-unit, and the other end of the second sub-unit is electrically connected to the first access point.

6. The driving substrate according to claim 1, wherein: The driving substrate further comprises: a semiconductor layer, a first source-drain conductive layer, and a second source-drain conductive layer stacked on the substrate in a direction away from the substrate; The first access point is provided in the semiconductor layer, the transfer signal line is provided in the first source-drain conductive layer, and the plurality of data lines are provided in the second source-drain conductive layer; One end of the transfer signal line is electrically connected to the first access point through a first via hole, and the other end of the transfer signal line is electrically connected to the first data line through a second via hole.

7. The driving substrate according to claim 1, wherein: The driving substrate further includes: a first voltage signal line extending along the second direction and electrically connected to the pixel circuit; Along the first direction, the first access point and the first data line are respectively located on two sides of the first voltage signal line.

8. The driving substrate according to claim 1, wherein: The plurality of pixel circuits further include a second pixel circuit, the first pixel circuit and the second pixel circuit are alternately arranged along the second direction; the second pixel circuit includes a second access point for accessing a second data signal; The plurality of data lines further include a second data line, and along the first direction, the first data line and the second data line are respectively located on both sides of a pixel circuit column formed by alternatingly arranging the first pixel circuits and the second pixel circuits; The first access point and the second access point are both arranged close to the second data line, and the second access point is electrically connected to the second data line.

9. The driving substrate according to claim 1, wherein: Along the first direction, three pixel circuits are spaced between two adjacent transfer signal lines; Along the second direction, there is one pixel circuit between two adjacent transfer signal lines.

10. The drive substrate according to any one of claims 1 to 9, wherein: The pixel circuit includes a second transistor, a third transistor, and a storage capacitor; the second transistor includes a second active pattern for forming a first electrode, a channel, and a second electrode of the second transistor; the third transistor includes a third active pattern for forming a first electrode, a channel, and a second electrode of the third transistor; the first electrode of the second active pattern is connected to the second electrode of the third transistor; and a connection position between the second active pattern and the third active pattern forms a third node; The storage capacitor includes a first plate and a second plate overlapped and arranged in a direction perpendicular to the substrate, the first plate is also used to form the gate of the third transistor, the second plate is located on a side of the first plate away from the substrate, and the second plate is configured to receive a first voltage signal; The plurality of pixel circuits include a first preset pixel circuit and a second preset pixel circuit adjacently arranged along the first direction, wherein the third nodes of the first preset pixel circuit and the second preset pixel circuit are arranged close to each other; and the second electrode plate of the first preset pixel circuit and the second electrode plate of the second preset pixel circuit are spaced apart from each other along the first direction; The orthographic projection of the second plate of the first preset pixel circuit onto the substrate does not overlap with the orthographic projection of the third node of the first preset pixel circuit onto the substrate, and the orthographic projection of the second plate of the second preset pixel circuit onto the substrate does not overlap with the orthographic projection of the third node of the second preset pixel circuit onto the substrate.

11. The driving substrate according to claim 10, wherein: The driving substrate further comprises: a second gate conductive layer and a first source-drain conductive layer stacked on the substrate in a direction away from the substrate; the second electrode of the storage capacitor is provided on the second gate conductive layer; The driving substrate further includes: A first connecting line is provided in the first source-drain conductive layer and extends along the first direction; one end of the first connecting line is electrically connected to the second electrode plate of the first preset pixel circuit through a via hole, and the other end of the first connecting line is electrically connected to the second electrode plate of the second preset pixel circuit through a via hole.

12. The driving substrate according to claim 11, wherein: The plurality of pixel circuits include a third preset pixel circuit, the third preset pixel circuit is adjacent to the second preset pixel circuit, and the first preset pixel circuit and the third preset pixel circuit are respectively located on both sides of the second preset pixel circuit along the first direction; The third node of the second preset pixel circuit and the third node of the third preset pixel circuit are arranged away from each other, and the second plate of the second preset pixel circuit is connected to the second plate of the third preset pixel circuit.

13. The driving substrate according to claim 12, wherein: The driving substrate further includes: a second connecting line, provided in the first source-drain conductive layer and extending along the first direction; one end of the second connecting line is electrically connected to the second electrode plate of the second preset pixel circuit through a via hole, and the other end of the second connecting line is electrically connected to the second electrode plate of the third preset pixel circuit through a via hole; The first connecting lines and the second connecting lines are alternately arranged along the first direction and connected in sequence.

14. The driving substrate according to claim 13, wherein: The driving substrate further comprises: a second source-drain conductive layer provided on a side of the first source-drain conductive layer away from the substrate; The driving substrate further includes: a plurality of first voltage signal lines, provided in the second source-drain conductive layer, and the first voltage signal lines extending along the second direction; The first connecting lines and the second connecting lines are alternately arranged along the first direction and connected in sequence to form first auxiliary voltage signal lines. The first voltage signal lines are electrically connected to multiple first auxiliary voltage signal lines through multiple vias, and the orthographic projections of the multiple first voltage signal lines and the multiple first auxiliary voltage signal lines on the substrate form a mesh structure.

15. The drive substrate according to any one of claims 1 to 9, wherein: The driving substrate comprises an array area and a peripheral area surrounding the array area; the driving substrate further comprises: a cathode power bus disposed in the peripheral area and at least partially surrounding the array area; a plurality of first auxiliary power lines extending along the first direction and arranged at intervals along the second direction; at least one end of the first auxiliary power line is electrically connected to the cathode power bus; a plurality of second auxiliary power lines extending along the second direction and arranged at intervals along the first direction, the plurality of second auxiliary power lines being located on a side of the plurality of first auxiliary power lines away from the substrate, and at least one end of the second auxiliary power line being electrically connected to the cathode power bus; a passivation layer, disposed between the plurality of first auxiliary power lines and the plurality of second auxiliary power lines, and comprising a plurality of third via holes; a first planar layer, disposed between the passivation layer and the plurality of second auxiliary power lines, comprising a plurality of fourth via holes, wherein openings of some of the fourth via holes are located in the passivation layer, and some of the fourth via holes are connected to the third via holes to form overlapping via holes; Part of the overlapping parts of the orthographic projections of the second auxiliary power line and the first auxiliary power line on the substrate at least partially overlaps with the orthographic projection of the fourth via on the substrate; one of the second auxiliary power lines is electrically connected to at least one of the first auxiliary power lines through the overlapping via.

16. The driving substrate according to claim 15, wherein: The peripheral area includes a fan-out area located on one side of the array area along the second direction, the plurality of data lines include a plurality of target data lines, and the driving substrate further includes: a plurality of first fan-out lines extending along the first direction and arranged at intervals along the second direction, the first fan-out lines being provided on the same layer as the first auxiliary power line, and one end of the first fan-out line being electrically connected to the target data line; a plurality of second fan-out lines extending along the second direction and arranged at intervals along the first direction, the second fan-out lines being provided on the same layer as the second auxiliary power lines, one end of the second fan-out line being electrically connected to an end of the first fan-out line away from the target data line through one of the overlapping vias, and the other end extending to the fan-out area, the second fan-out line being closer to the center of the array area along the first direction than the target data line; Among them, the orthographic projections of the first fan-out line and the second fan-out line on the substrate overlap with the orthographic projections of the first auxiliary power line and the second auxiliary power line on the substrate, at least partially overlap with the orthographic projection of the fourth via on the substrate, and do not overlap with the orthographic projection of the third via on the substrate.

17. A display panel, characterized in that: include: The driving substrate according to any one of claims 1 to 16; A plurality of light emitting devices are arranged on the driving substrate, and the light emitting devices are electrically connected to the pixel circuit of the driving substrate.

18. The display panel according to claim 17, wherein: The plurality of light emitting devices include a first light emitting device configured to emit blue light, and the first light emitting device is electrically connected to a first pixel circuit.

19. The display panel according to claim 18, wherein: The driving substrate includes a second pixel circuit; The plurality of light emitting devices include a second light emitting device configured to emit red light, and the second light emitting device is electrically connected to a second pixel circuit.

20. The display panel according to claim 19, wherein The driving substrate includes a third via hole and a fourth via hole; The light emitting device includes an anode pattern; The plurality of light emitting devices includes a third light emitting device configured to emit green light; The orthographic projections of the third via hole and the fourth via hole on the substrate do not overlap with the orthographic projections of the anode pattern of the first light-emitting device and the anode pattern of the second light-emitting device on the substrate, and are located within the orthographic projection of the anode pattern of the third light-emitting device on the substrate.

21. The display panel according to claim 20, wherein: The orthographic projections of the third via hole and the fourth via hole on the substrate are located at a geometric center of the orthographic projection of the anode pattern of the third light-emitting device on the substrate.

22. The display panel according to any one of claims 17 to 21, wherein: The display panel further includes: A second planar layer is provided on a side of the light emitting device close to the driving substrate and includes a plurality of fifth via holes; In which, the light-emitting device includes an anode pattern, a light-emitting layer and a cathode layer arranged in sequence in a direction away from the substrate, the anode pattern is electrically connected to the pixel circuit of the driving substrate through the fifth via hole, and the fifth via hole does not overlap with the orthographic projection of the light-emitting area of ​​the light-emitting device on the substrate.

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