Pixel, display device, and electronic device

Abstract

The invention relates to a pixel, a display device and an electronic device. The pixel includes: a first switching element including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second switching element including a control electrode connected to the second node, a first electrode connected to a fifth node, and a second electrode connected to the second node; a third switching element including a control electrode receiving a write gate signal, a first electrode receiving a data voltage, and a second electrode connected to the first node; a first capacitor including a first electrode connected to the first node and a second electrode connected to a fourth node; a second capacitor connected to the fourth node; a fourth switching element receiving an initialization gate signal and connected to the fourth node; and a light emitting element that emits light based on a driving current flowing to the light emitting element through the first switching element.

Description

Technical Field

[0001] Embodiments of the present invention relate to pixels, display devices including the pixels, and electronic devices including the display devices. More specifically, embodiments of the present invention relate to pixels including a second switching element, a first capacitor, and a second capacitor having a diode connection, thereby increasing a data swing range and enhancing uniformity, and a display device including the pixels. Background Art

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel may include multiple gate lines, multiple data lines, multiple emission lines, and multiple pixels. The display panel driver may include a gate driver, a data driver, an emission driver, and a drive controller. The gate driver may output gate signals to the gate lines. The data driver may output data voltages to the data lines. The emission driver may output emission signals to the emission lines. The drive controller may control the gate driver, the data driver, and the emission driver. Summary of the Invention

[0003] In a display device, the display quality of the display panel may deteriorate due to variations in the threshold voltage of the driving switching element and the threshold voltage of the light-emitting element. In addition, when the data swing range is small, the grayscale value may not be accurately represented, which may deteriorate the display quality of the display panel.

[0004] An embodiment of the present invention provides a pixel including a second switching element, a first capacitor, and a second capacitor having a diode connection and thereby increasing a data swing range and enhancing uniformity.

[0005] An embodiment of the present invention provides a display device including the pixel.

[0006] An embodiment of the present invention provides an electronic device including the display device.

[0007] In an embodiment of a pixel according to the present invention, the pixel includes: a first switching element, a second switching element, a third switching element, a first capacitor, a second capacitor, a fourth switching element, and a light-emitting element. In such an embodiment, the first switching element includes a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node. In such an embodiment, the second switching element includes a control electrode connected to the second node, a first electrode connected to a fifth node, and a second electrode connected to the second node. In such an embodiment, the third switching element includes a control electrode that receives a write gate signal, a first electrode that receives a data voltage, and a second electrode connected to the first node. In such an embodiment, the first capacitor includes a first electrode connected to the first node and a second electrode connected to a fourth node. In such an embodiment, the second capacitor is connected to the fourth node. In such an embodiment, the fourth switching element receives an initialization gate signal. In such an embodiment, the fourth switching element is connected to the fourth node. In such an embodiment, the light-emitting element emits light based on a drive current flowing to the light-emitting element through the first switching element.

[0008] In an embodiment, the fourth switching element may include: a control electrode receiving the initialization gate signal; a first electrode receiving a first power voltage; and a second electrode connected to the fourth node.

[0009] In an embodiment, the second capacitor may include: a first electrode connected to the fourth node; and a second electrode connected to the fifth node.

[0010] In an embodiment, the second capacitor may include: a first electrode connected to the fourth node; and a second electrode connected to the second node.

[0011] In an embodiment, the fourth switching element may include: a control electrode receiving the initialization gate signal; a first electrode connected to the fifth node; and a second electrode connected to the fourth node.

[0012] In an embodiment, the second capacitor may include: a first electrode connected to the fourth node; and a second electrode connected to the fifth node.

[0013] In an embodiment, the second capacitor may include: a first electrode connected to the fourth node; and a second electrode connected to the second node.

[0014] In an embodiment, the fourth switching element may include: a control electrode receiving the initialization gate signal; a first electrode connected to the second node; and a second electrode connected to the fourth node.

[0015] In an embodiment, the pixel may further include a fifth switching element including a control electrode receiving the emission signal, a first electrode receiving the first power voltage, and a second electrode connected to the fifth node.

[0016] In an embodiment, the pixel may further include a sixth switching element, the sixth switching element including a control electrode receiving an initialization gate signal of the light emitting element, a first electrode receiving an initialization voltage, and a second electrode connected to the third node.

[0017] In an embodiment, the pixel may further include a fifth switching element, the fifth switching element including a control electrode receiving an emission signal, a first electrode receiving a first power voltage, and a second electrode connected to the fifth node. In such an embodiment, the first switching element, the second switching element, the third switching element, the fourth switching element, the fifth switching element, and the sixth switching element are P-type transistors.

[0018] In an embodiment, breakdown voltages of the first switching element and the sixth switching element may be greater than breakdown voltages of the second switching element, the third switching element, the fourth switching element, and the fifth switching element.

[0019] In an embodiment, the pixel may further include a fifth switching element, the fifth switching element including a control electrode receiving an emission signal, a first electrode receiving a first power voltage, and a second electrode connected to the fifth node. In such an embodiment, the first switching element, the second switching element, the third switching element, the fourth switching element, and the fifth switching element may be P-type transistors, and the sixth switching element may be an N-type transistor.

[0020] In an embodiment, the pixel may further include a fifth switching element, the fifth switching element including a control electrode receiving an emission signal, a first electrode receiving a first power voltage, and a second electrode connected to the fifth node. In such an embodiment, the initialization gate signal may have an active level in a first period, the write gate signal may have an active level in the first period, the emission signal may have an active level in the first period, the light-emitting element initialization gate signal may have an active level in the first period, and the data voltage may have a reference voltage in the first period. In such an embodiment, the initialization gate signal may have an inactive level in a second period after the first period, the write gate signal may have the active level in the second period, the emission signal may have an inactive level in the second period, the light-emitting element initialization gate signal may have the active level in the second period, and the data voltage may have a current grayscale data voltage in the second period. In such an embodiment, the initialization gate signal may have the non-valid level in a third period after the second period, the write gate signal may have the non-valid level in the third period, the emission signal may have the valid level in the third period, and the light-emitting element initialization gate signal may have the non-valid level in the third period.

[0021] In an embodiment, the pixel may further include a fifth switching element, the fifth switching element including a control electrode receiving an emission signal, a first electrode receiving a first power voltage, and a second electrode connected to a fifth node. In such an embodiment, the initialization gate signal may have an active level in a first period, the write gate signal may have an active level in the first period, the emission signal may have an active level in the first period, and the light-emitting element initialization gate signal may have an active level in the first period. In such an embodiment, the initialization gate signal may have an inactive level in a second period after the first period, the write gate signal may have the active level in the second period, the emission signal may have an inactive level in the second period, and the light-emitting element initialization gate signal may have the active level in the second period. In such an embodiment, the initialization gate signal may have the non-active level in a third time period after the second time period, the write gate signal may have the non-active level in the third time period, the emission signal changes from the non-active level to the active level at a first time point after the starting point of the third time period, and the light-emitting element initialization gate signal changes from the active level to the non-active level at a second time point after the starting point of the third time period.

[0022] In an embodiment, the pixel may further include a fifth switching element, the fifth switching element including a control electrode receiving an emission signal, a first electrode receiving a first power voltage, and a second electrode connected to the fifth node. In such an embodiment, the initialization gate signal may have an active level in a first period, the write gate signal may have an active level in the first period, the emission signal may have an active level in the first period, the light-emitting element initialization gate signal may have an active level in the first period, and the data voltage may have a current grayscale data voltage in the first period. In such an embodiment, the initialization gate signal may have an inactive level in a second period after the first period, the write gate signal may have the active level in the second period, the emission signal may have an inactive level in the second period, the light-emitting element initialization gate signal may have the active level in the second period, and the data voltage may have the current grayscale data voltage in the second period. In such an embodiment, the initialization gate signal may have the non-valid level in a third period after the second period, the write gate signal may have the non-valid level in the third period, the emission signal may have the valid level in the third period, and the light-emitting element initialization gate signal may have the non-valid level in the third period.

[0023] In an embodiment, when I d represents the current flowing through the light emitting element, μ p represents the mobility of the first switching element, C ox represents the capacitance of the first switching element, W / L represents the ratio of the width to the length of the channel of the first switching element, VDD represents the first power voltage, V dsat2 represents the saturation voltage of the second switching element, V th2 represents the threshold voltage of the second switching element, C1 represents the capacitance of the first capacitor, C2 represents the capacitance of the second capacitor, V DATA Indicates the data voltage, V REF Indicates the reference voltage, V th1 represents the threshold voltage of the first switching element, g m represents the transconductance of the first switching element, and R dio When denoting the resistance of the second switching element, it can be satisfied:

[0024]

[0025] In an embodiment, the pixel may further include a seventh switching element including a control electrode receiving a second initialization gate signal, a first electrode receiving a reference voltage, and a second electrode connected to the first node.

[0026] In an embodiment, the pixel may further include: a fifth switching element including a control electrode receiving an emission signal, a first electrode receiving a first power voltage, and a second electrode connected to the fifth node; and a sixth switching element including a control electrode receiving a light-emitting element initialization gate signal, a first electrode receiving an initialization voltage, and a second electrode connected to the third node. In such an embodiment, the initialization gate signal may have an active level in a first period, the second initialization gate signal may have an active level in the first period, the write gate signal may have an active level in the first period, the emission signal may have an active level in the first period, the light-emitting element initialization gate signal may have an active level in the first period, and the data voltage may have the reference voltage in the first period. In such an embodiment, the initialization gate signal may have an inactive level in a second period after the first period, the second initialization gate signal may have an inactive level in the second period, the write gate signal may have the active level in the second period, the emission signal may have an inactive level in the second period, the light-emitting element initialization gate signal may have the active level in the second period, and the data voltage may have the current grayscale data voltage in the second period. In such an embodiment, the initialization gate signal may have the non-valid level in a third period after the second period, the second initialization gate signal may have the non-valid level in the third period, the write gate signal may have a non-valid level in the third period, the emission signal may have the valid level in the third period, and the light-emitting element initialization gate signal may have a non-valid level in the third period.

[0027] In an embodiment of a display device according to the present invention, the display device includes a display panel, a gate driver, and a data driver. In such an embodiment, the display panel includes pixels. In such an embodiment, the gate driver outputs gate signals to the pixels. In such an embodiment, the data driver outputs data voltages to the pixels. In such an embodiment, the pixels include a first switching element, a second switching element, a third switching element, a first capacitor, a second capacitor, a fourth switching element, and a light-emitting element. In such an embodiment, the first switching element includes a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node. In such an embodiment, the second switching element includes a control electrode connected to the second node, a first electrode connected to a fifth node, and a second electrode connected to the second node. In such an embodiment, the third switching element includes a control electrode that receives a write gate signal, a first electrode that receives the data voltage, and a second electrode connected to the first node. In such an embodiment, the first capacitor includes a first electrode connected to the first node and a second electrode connected to a fourth node. In such an embodiment, the second capacitor is connected to the fourth node. In such an embodiment, the fourth switching element receives an initialization gate signal. In such an embodiment, the fourth switching element is connected to the fourth node. In such an embodiment, the light emitting element is configured to emit light based on a driving current flowing to the light emitting element through the first switching element.

[0028] In an embodiment of an electronic device according to the present invention, the electronic device includes: a display panel, a gate driver, a data driver, a drive controller, and a processor. In such an embodiment, the display panel includes pixels. In such an embodiment, the gate driver outputs gate signals to the pixels. In such an embodiment, the data driver outputs data voltages to the pixels. In such an embodiment, the drive controller controls the gate driver and the data driver. In such an embodiment, the processor outputs input image data and input control signals. In such an embodiment, the pixels include a first switching element, a second switching element, a third switching element, a first capacitor, a second capacitor, a fourth switching element, and a light-emitting element. In such an embodiment, the first switching element includes a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node. In such an embodiment, the second switching element includes a control electrode connected to the second node, a first electrode connected to a fifth node, and a second electrode connected to the second node. In such an embodiment, the third switching element includes a control electrode for receiving a write gate signal, a first electrode for receiving the data voltage, and a second electrode connected to the first node. In such an embodiment, the first capacitor includes a first electrode connected to the first node and a second electrode connected to a fourth node. In such an embodiment, the second capacitor is connected to the fourth node. In such an embodiment, the fourth switching element receives an initialization gate signal. In such an embodiment, the fourth switching element is connected to the fourth node. In such an embodiment, the light emitting element is configured to emit light based on a drive current flowing to the light emitting element through the first switching element.

[0029] According to an embodiment of the pixel, the display device including the pixel, and the electronic device including the display device, the pixel may include the second switching element, the first capacitor, and the second capacitor having a diode connection.

[0030] In these embodiments, the pixel may include a second switching element having a diode connection so that variations in the threshold voltage of the driving switching element and variations in the threshold current of the light emitting element can be compensated.

[0031] Furthermore, due to the linearization effect of the second switching element, a data swing range wider than the data range of the driving switching element can be obtained. In addition, the data voltage is distributed by the charge distribution of the first capacitor and the second capacitor, so that the data swing range can be further expanded.

[0032] In these embodiments, the first switching element and the sixth switching element are implemented as high-voltage MOSFETs, and the second switching element, the third switching element, the fourth switching element and the fifth switching element are implemented as medium-voltage MOSFETs, so that the area of ​​the pixel can be reduced and the resolution of the display panel can be improved.

[0033] Furthermore, the second switching element is implemented as a medium voltage MOSFET, so that a voltage margin can be further obtained by the threshold voltage of the second switching element. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and other features of the embodiments of the present invention will become more apparent by describing in detail the embodiments of the present invention with reference to the accompanying drawings, in which:

[0035] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present invention;

[0036] Figure 2 It shows Figure 1 a circuit diagram of a pixel of a display panel;

[0037] Figure 3 is shown applied to Figure 2 A timing diagram of an example of an input signal for a pixel;

[0038] Figure 4 is shown applied to Figure 2 A timing diagram of an example of an input signal for a pixel;

[0039] Figure 5 is shown applied to Figure 2 A timing diagram of an example of an input signal for a pixel;

[0040] Figures 6 to 8 Is shown by Figure 2 a graph showing compensation of the threshold voltage of the first switching element and compensation of the threshold current of the light-emitting element by the second switching element;

[0041] Figure 9 It shows Figure 2 a graph showing an increase in the data swing range and an improvement in the consistency of the second switching element;

[0042] Figure 10 is a circuit diagram showing a pixel of a display panel of a display device according to an embodiment of the present invention;

[0043] Figure 11 is a circuit diagram showing a pixel of a display panel of a display device according to an embodiment of the present invention;

[0044] Figure 12is a circuit diagram showing a pixel of a display panel of a display device according to an embodiment of the present invention;

[0045] Figure 13 is a circuit diagram showing a pixel of a display panel of a display device according to an embodiment of the present invention;

[0046] Figure 14 is a circuit diagram showing a pixel of a display panel of a display device according to an embodiment of the present invention;

[0047] Figure 15 is shown applied to Figure 14 A timing diagram of an example of an input signal for a pixel;

[0048] Figure 16 is a circuit diagram showing a pixel of a display panel of a display device according to an embodiment of the present invention;

[0049] Figure 17 is a circuit diagram showing a pixel of a display panel of a display device according to an embodiment of the present invention;

[0050] Figure 18 is a circuit diagram showing a pixel of a display panel of a display device according to an embodiment of the present invention;

[0051] Figure 19 is a circuit diagram showing a pixel of a display panel of a display device according to an embodiment of the present invention;

[0052] Figure 20 is a circuit diagram showing a pixel of a display panel of a display device according to an embodiment of the present invention;

[0053] Figure 21 is shown applied to Figure 20 A timing diagram of an example of an input signal for a pixel;

[0054] Figure 22 is a circuit diagram showing a pixel of a display panel of a display device according to an embodiment of the present invention;

[0055] Figure 23 is a circuit diagram showing a pixel of a display panel of a display device according to an embodiment of the present invention;

[0056] Figure 24 is a circuit diagram showing a pixel of a display panel of a display device according to an embodiment of the present invention;

[0057] Figure 25 is a circuit diagram showing a pixel of a display panel of a display device according to an embodiment of the present invention;

[0058] Figure 26is a circuit diagram showing a pixel of a display panel of a display device according to an embodiment of the present invention;

[0059] Figure 27 is shown applied to Figure 26 A timing diagram of an example of an input signal for a pixel;

[0060] Figure 28 is a circuit diagram showing a pixel of a display panel of a display device according to an embodiment of the present invention;

[0061] Figure 29 is a circuit diagram showing a pixel of a display panel of a display device according to an embodiment of the present invention;

[0062] Figure 30 is a circuit diagram showing a pixel of a display panel of a display device according to an embodiment of the present invention;

[0063] Figure 31 is a circuit diagram showing a pixel of a display panel of a display device according to an embodiment of the present invention;

[0064] Figure 32 is a block diagram illustrating an electronic device according to an embodiment of the present invention;

[0065] Figure 33 It shows Figure 32 A schematic diagram of an example of an electronic device being implemented as a virtual reality display system; and

[0066] Figure 34 It shows Figure 32 Schematic diagram of an example in which the electronic device is implemented as a smart phone. DETAILED DESCRIPTION

[0067] The present invention will be described more fully below with reference to the accompanying drawings, in which various embodiments are shown. However, the present invention may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout.

[0068] It will be understood that when an element is referred to as being “on” another element, the element can be directly on the other element or intervening elements may be present between the element and the other element. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0069] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, the "first element," "first component," "first region," "first layer," or "first part" discussed below may be named "second element," "second component," "second region," "second layer," or "second part" without departing from the teachings herein.

[0070] The terms used herein are for the purpose of describing a particular embodiment and are not intended to be restrictive. As used herein, unless the context clearly indicates otherwise, "one (person)", "a kind of", "described (the)" and "at least one (person / kind)" do not represent the limitation to quantity, but are intended to include both singular and plural forms. Therefore, in the claims, "one" element is quoted, and then "the" element is quoted, including one element and multiple elements. For example, unless the context clearly indicates otherwise, "an element" has the same meaning as "at least one element". "At least one (person / kind)" is not interpreted as being limited to "one (person)" or "a kind of". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. It will also be understood that when used in this specification, the term "including" or "comprising" illustrates the presence of stated features, regions, entireties, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, regions, entireties, steps, operations, elements, components and / or their groups.

[0071] In addition, as shown in the accompanying drawings, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another. It will be understood that relative terms are intended to cover different orientations of the device in addition to the orientation depicted in the accompanying drawings. For example, if the device is turned over in a drawing, an element described as being on the "lower" side of other elements will subsequently be oriented to be on the "upper" side of the other elements. Thus, depending on the specific orientation of the drawing, the term "lower" can cover both "lower" and "upper" orientations. Similarly, if the device is turned over in a drawing, an element described as being "below" or "beneath" other elements will subsequently be oriented to be "above" the other elements. Thus, the terms "below" or "below" can cover both "upper" and "lower" orientations.

[0072] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0073] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that, unless expressly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense.

[0074] Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

[0075] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present invention.

[0076] Reference Figure 1 The embodiment of the display device includes a display panel 100 and a display panel driver. The display panel driver includes a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600.

[0077] In an embodiment, the display panel 100 includes a display area in which an image is displayed and a peripheral area (or non-display area) adjacent to the display area.

[0078] The display panel 100 includes a plurality of gate lines GIL, GWL, and EBL, a plurality of data lines DL, a plurality of emission lines EL, and a plurality of pixels electrically connected to the gate lines GIL, GWL, and EBL, the data lines DL, and the emission lines EL. The gate lines GIL, GWL, and EBL may extend in a first direction D1, the data lines DL may extend in a second direction D2 intersecting the first direction D1, and the emission lines EL may extend in the first direction D1.

[0079] The drive controller 200 receives input image data IMG and input control signals CONT from an external device (e.g., a processor). In an embodiment, for example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, cyan image data, and yellow image data. The input control signals CONT may include a master clock signal and a data enable signal. The input control signals CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0080] The driving controller 200 generates a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , a fourth control signal CONT4 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0081] The driving controller 200 generates a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0082] The driving controller 200 generates a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0083] The driving controller 200 generates a data signal DATA based on the input image data IMG and outputs the data signal DATA to the data driver 500 .

[0084] The driving controller 200 generates a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and outputs the third control signal CONT3 to the gamma reference voltage generator 400 .

[0085] The driving controller 200 generates a fourth control signal CONT4 for controlling the operation of the emission driver 600 based on the input control signal CONT, and outputs the fourth control signal CONT4 to the emission driver 600 .

[0086] The gate driver 300 generates a gate signal driving the gate lines GIL, GWL, and EBL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 may output the gate signal to the gate lines GIL, GWL, and EBL.

[0087] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to a third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to a level of the data signal DATA.

[0088] In an embodiment, the gamma reference voltage generator 400 may be provided in the driving controller 200 , or may be provided in the data driver 500 .

[0089] The data driver 500 receives the second control signal CONT2 and the data signal DATA from the driving controller 200, and receives the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 converts the data signal DATA into an analog data voltage using the gamma reference voltage VGREF. The data driver 500 outputs the data voltage to the data line DL.

[0090] The emission driver 600 generates an emission signal to drive the emission line EL in response to the fourth control signal CONT4 received from the driving controller 200. The emission driver 600 may output the emission signal to the emission line EL.

[0091] Although for ease of illustration and description, Figure 1 , the gate driver 300 is disposed on a first side of the display panel 100 and the emission driver 600 is disposed on a second side of the display panel 100 opposite the first side, but the present invention is not limited thereto. In another embodiment, for example, both the gate driver 300 and the emission driver 600 may be disposed on the first side of the display panel 100. In another embodiment, for example, both the gate driver 300 and the emission driver 600 may be disposed on both sides (for example, the first side and the second side) of the display panel 100. In another embodiment, for example, the gate driver 300 and the emission driver 600 may be integrally formed as a single chip.

[0092] Figure 2 It shows Figure 1 1 is a circuit diagram of a pixel of the display panel 100. Figure 3 is shown applied to Figure 2 FIG1 is a timing diagram of an example of an input signal for a pixel.

[0093] Reference Figures 1 to 3 In one embodiment, the display panel 100 includes a plurality of pixels. Each pixel includes a light emitting element EE. In one embodiment, the light emitting element EE may be a micro organic light emitting diode (Micro-OLED).

[0094] In an embodiment, for example, the display device may be a micro display device including a micro organic light emitting diode (Micro-OLED). In an embodiment, for example, the pixels may be formed on a silicon substrate. In an embodiment, for example, the display device may be a micro display device including pixels formed on a silicon substrate.

[0095] The pixel receives the write gate signal GW, the initialization gate signal GI, the light emitting element initialization gate signal EB, the data voltage VDATA and the emission signal EM, and the light emitting element EE of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0096] The pixel includes a first switching element M1, a second switching element M2, a third switching element M3, a first capacitor C1, a second capacitor C2, a fourth switching element M4 and a light emitting element EE.

[0097] The first switching element M1 includes a control electrode connected to the first node N1, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. The first switching element M1 may be referred to as a driving switching element.

[0098] The second switching element M2 includes a control electrode connected to the second node N2, a first electrode connected to the fifth node N5, and a second electrode connected to the second node N2. The second switching element M2 may have a diode connection (or be connected in a diode manner or in the form of a diode).

[0099] The third switching element M3 includes a control electrode receiving the write gate signal GW, a first electrode receiving the data voltage VDATA, and a second electrode connected to the first node N1.

[0100] The first capacitor C1 includes a first electrode connected to the first node N1 and a second electrode connected to the fourth node N4. The second capacitor C2 is connected to the fourth node N4. In an embodiment, the second capacitor C2 may include a first electrode connected to the fourth node N4 and a second electrode connected to the fifth node N5.

[0101] The fourth switching element M4 receives the initialization gate signal GI and is connected to the fourth node N4. In an embodiment, the fourth switching element M4 may include a control electrode receiving the initialization gate signal GI, a first electrode receiving the first power voltage ELVDD, and a second electrode connected to the fourth node N4.

[0102] The light-emitting element EE emits light based on the driving current flowing through the first switching element M1. For example, the light-emitting element EE emits light based on the driving current flowing to the light-emitting element EE through the first switching element M1. In an embodiment, for example, the light-emitting element EE may include a first electrode connected to the third node N3 and a second electrode receiving the second power voltage ELVSS. In an embodiment, for example, the first electrode of the light-emitting element EE may be an anode electrode, and the second electrode of the light-emitting element EE may be a cathode electrode.

[0103] In an embodiment, for example, the first power voltage ELVDD may be a high power voltage for causing the light emitting element EE to emit, and the second power voltage ELVSS may be a low power voltage for causing the light emitting element EE to emit. The first power voltage ELVDD may be greater than the second power voltage ELVSS, that is, the voltage level of the first power voltage ELVDD may be higher than the voltage level of the second power voltage ELVSS.

[0104] The pixel may further include a fifth switching element M5 including a control electrode receiving the emission signal EM, a first electrode receiving the first power voltage ELVDD, and a second electrode connected to a fifth node N5.

[0105] The pixel may further include a sixth switching element M6 including a control electrode receiving a light emitting element initialization gate signal EB, a first electrode receiving an initialization voltage VINT, and a second electrode connected to a third node N3.

[0106] In an embodiment, the first switching element M1, the second switching element M2, the third switching element M3, the fourth switching element M4, the fifth switching element M5, and the sixth switching element M6 may be P-type transistors. In an embodiment, for example, the first switching element M1, the second switching element M2, the third switching element M3, the fourth switching element M4, the fifth switching element M5, and the sixth switching element M6 may be low-temperature polysilicon (LTPS) thin-film transistors.

[0107] The breakdown voltage of the first switching element M1 and the sixth switching element M6 may be greater than the breakdown voltage of the second switching element M2, the third switching element M3, the fourth switching element M4, and the fifth switching element M5. The breakdown voltage may refer to a maximum voltage that the gate-source voltage, the gate-drain voltage, the gate-bulk voltage, the drain-source voltage, and the drain-bulk voltage of the switching element are not allowed to exceed for normal operation.

[0108] In an embodiment, for example, the first switching element M1 and the sixth switching element M6 may be high-voltage metal oxide semiconductor field effect transistors (MOSFETs). For example, the breakdown voltage of the first switching element M1 and the sixth switching element M6 may be approximately 6 volts (V), approximately 8 V, or approximately 10 V.

[0109] In an embodiment, for example, the second switching element M2, the third switching element M3, the fourth switching element M4, and the fifth switching element M5 may be medium voltage MOSFETs, and their breakdown voltages may be approximately 3.5V or approximately 5V.

[0110] In an embodiment, the first switching element M1 and the sixth switching element M6 are implemented as high-voltage MOSFETs, and the second switching element M2, the third switching element M3, the fourth switching element M4 and the fifth switching element M5 are implemented as medium-voltage MOSFETs, so that the area of ​​the pixel can be reduced compared to the case where the first switching element M1 to the sixth switching element M6 are all implemented as high-voltage MOSFETs, and therefore, in such an embodiment, the resolution of the display panel 100 can be improved.

[0111] The first switching element M1 and the sixth switching element M6 are switching elements that are directly connected to the anode electrode of the light-emitting element EE without any intermediate element (transistor or capacitor) connected between them, so that the first switching element M1 and the sixth switching element M6 can be implemented as high-voltage MOSFETs for reliability and stability of the pixel circuit.

[0112] like Figure 3 As shown in FIG, in the first period DU1, the initialization gate signal GI may have an active level, the write gate signal GW may have an active level, the emission signal EM may have an active level, the light emitting element initialization gate signal EB may have an active level, and the data voltage VDATA may have a reference voltage VREF. The first period DU1 may be an initialization period.

[0113] Figure 3 In the embodiment shown, the switch element receiving the signal is a P-type transistor, so that the active level can be a low level and the inactive level can be a high level. In another embodiment, the switch element receiving the signal is an N-type transistor, the active level can be a high level, and the inactive level can be a low level.

[0114] During the first period DU1, all of the first to sixth switching elements M1 to M6 may be turned on. During the first period DU1, the first power voltage ELVDD may be applied to the fourth node N4 via the turned-on fourth switching element M4, and the reference voltage VREF may be applied to the first node N1 via the turned-on third switching element M3. Furthermore, during the first period DU1, the first power voltage ELVDD may be applied to the fifth node N5 via the turned-on fifth switching element M5. Furthermore, during the first period DU1, the initialization voltage VINT may be applied to the third node N3 via the turned-on sixth switching element M6.

[0115] In the first period DU1 , even if the first switching element M1 is turned on, the light emitting element EE may not emit light due to the level of the initialization voltage VINT.

[0116] In the second period DU2 after the first period DU1, the initialization gate signal GI may have an inactive level, the write gate signal GW may have an active level, the emission signal EM may have an inactive level, the light emitting element initialization gate signal EB may have an active level, and the data voltage VDATA may have the current grayscale data voltage VDATA[n]. The second period DU2 may be a data write period.

[0117] In the second period DU2 , the third switching element M3 may be turned on by the write gate signal GW so that the current grayscale data voltage VDATA[n] may be applied to the first node N1 .

[0118] In the second period DU2 , the sixth switching element M6 may be turned on by the light emitting element initialization gate signal EB, so that the initialization voltage VINT may be applied to the third node N3 .

[0119] In a third period DU3 after the second period DU2, the initialization gate signal GI may have an inactive level, the write gate signal GW may have an inactive level, the emission signal EM may have an active level, and the light emitting element initialization gate signal EB may have an inactive level. The third period DU3 may be a light emitting period.

[0120] In the third period DU3 , the fifth switching element M5 , the second switching element M2 , and the first switching element M1 may be turned on, and a driving current may flow through the fifth switching element M5 , the second switching element M2 , the first switching element M1 , and the light emitting element EE, so that the light emitting element EE may emit light.

[0121] When I d represents the current flowing through the light emitting element EE, μ p represents the mobility of the first switching element M1, C oxrepresents the capacitance of the first switching element M1, W / L represents the ratio of the width to the length of the channel of the first switching element M1, VDD represents the first power voltage ELVDD, V dsat2 represents the saturation voltage of the second switching element M2, V th2 represents the threshold voltage of the second switching element M2, C1 represents the capacitance of the first capacitor C1, C2 represents the capacitance of the second capacitor C2, V DATA Indicates data voltage VDATA, V REF Indicates the reference voltage VREF, V th1 represents the threshold voltage of the first switching element M1, g m represents the transconductance of the first switching element M1, and R dio When denoting the resistance of the second switching element M2, the following equation can be satisfied:

[0122]

[0123] Figure 4 is shown applied to Figure 2 FIG1 is a timing diagram of an example of an input signal for a pixel.

[0124] Except for the third period DU3, Figure 4 The timing diagram and Figure 3 The timing diagrams are basically the same.

[0125] In an embodiment, Figure 4 As shown in FIG, in the third period DU3 after the second period DU2, the initialization gate signal GI may have a non-active level, and the write gate signal GW may have a non-active level. The emission signal EM may change from the non-active level to the active level at a first time point after the start point of the third period DU3, and the light emitting element initialization gate signal EB may change from the active level to the non-active level at a second time point after the start point of the third period DU3.

[0126] In the third period DU3 , the fifth switching element M5 , the second switching element M2 , and the first switching element M1 may be turned on, and a driving current may flow through the fifth switching element M5 , the second switching element M2 , the first switching element M1 , and the light emitting element EE, so that the light emitting element EE may emit light.

[0127] In such an embodiment, the write gate signal GW may change from an active level to an inactive level at the start point of the third period DU3, the emission signal EM may change from an inactive level to an active level at a first time point after the start point of the third period DU3, and the light-emitting element initialization gate signal EB may change from an active level to an inactive level at a second time point after the start point of the third period DU3. In such an embodiment, as described above, a time margin is set between the level change of the write gate signal GW, the level change of the emission signal EM, and the level change of the light-emitting element initialization gate signal EB, so that the reliability and stability of the light-emitting operation of the pixel can be improved.

[0128] Figure 5 is shown applied to Figure 2 FIG1 is a timing diagram of an example of an input signal for a pixel.

[0129] In addition to the data voltage VDATA in the first period DU1, Figure 5 The timing diagram and Figure 3 The timing diagrams are basically the same.

[0130] In an embodiment, Figure 5 As shown in, in the first period DU1, the initialization gate signal GI may have a valid level, the write gate signal GW may have a valid level, the emission signal EM may have a valid level, the light emitting element initialization gate signal EB may have a valid potential, and the data voltage VDATA may have a current grayscale data voltage VDATA[n].

[0131] In such an embodiment, in the first period DU1, the data voltage VDATA does not have the reference voltage VREF but has the current grayscale data voltage VDATA[n]. The level of the current grayscale data voltage VDATA[n] may have a similar level to the reference voltage VREF, so that the first node N1 may be initialized using the current grayscale data signal VDATA[n] instead of the reference voltage VREF.

[0132] Figures 6 to 8 Is shown by Figure 2 Graph showing compensation of the threshold voltage of the first switching element M1 and compensation of the threshold voltage of the light emitting element EE by the second switching element M2.

[0133] Reference Figures 1 to 8 The second switching element M2 connected in diode mode can operate source degeneration (or source degeneration). Source degeneration can mean linearizing the relationship between the output current or output voltage of the amplifier and the input voltage of the amplifier using a resistance component formed in the source electrode.

[0134] Micro organic light emitting diodes typically achieve white brightness at a current level of several nanoamperes (nA). Therefore, in an embodiment, source degeneration can be achieved by connecting a diode with a high resistance (eg, the second switching element M2) to the source electrode.

[0135] The threshold voltage of the first switching element M1 and the threshold voltage of the light emitting element EE may vary according to the area in the display panel 100. Therefore, the pixel may initially have a different threshold voltage of the first switching element M1 and a different threshold voltage of the light emitting element EE, and the natural frequency of the first switching element M1 may be very fast, so that the driving current Ids2 is Figures 6 to 8 The time required to converge to the compensation point in the manner shown in FIG can be very short. A second switching element M2 having a diode connection can be formed at the source electrode of the first switching element M1, so that a change in the threshold voltage of the first switching element M1 can be compensated due to a negative feedback effect on the change in the threshold voltage of the first switching element M1.

[0136] like Figure 6 As shown in , when the first switching element M1 in the pixel has a threshold voltage greater than the average threshold voltage and a voltage of the gate electrode (or control electrode) of the first switching element M is applied, the first switching element M1 supplies a current less than the average current to the light emitting element EE. Figure 6 As shown in , the operating point of the second switching element M2 moves from the first current point I1 to a second current point I2 less than the first current point I1, and therefore, the gate voltage Vg2 of the second switching element M2 can increase from the first voltage V1 to a second voltage V2 greater than the first voltage V1.

[0137] like Figure 7 As shown in Figure 6 As a result of the operation of the first switching element M1, the source-gate voltage (Vsg1) increases, and Figure 6 On the contrary, the driving current of the light emitting element EE increases. Figure 7 As shown in , the operating point of the second switching element M2 moves from the second current point I2 to the third current point I3 greater than the second current point I2, and therefore, the gate voltage Vg2 of the second switching element M2 can be reduced from the second voltage V2 to the third voltage V3 less than the second voltage V2. However, Figure 7 The change in the driving current Ids2 and the gate voltage Vg2 of the second switching element M2 is less than Figure 6 The change in the driving current Ids2 of the second switching element M2 and the change in the gate voltage Vg2 are shown in FIG.

[0138] like Figure 8 As shown in Figure 7 As a result of the operation of the first switching element M1, the source-gate voltage (Vsg1) decreases, and Figure 7 On the contrary, the driving current of the light emitting element EE increases. Figure 8 As shown in , the operating point of the second switching element M2 moves from the third current point I3 to the fourth current point I4 which is less than the third current point I3, and therefore, the gate voltage Vg2 of the second switching element M2 can increase from the third voltage V3 to the fourth voltage V4 which is greater than the third voltage V3. However, Figure 8 The change in the driving current Ids2 and the gate voltage Vg2 of the second switching element M2 is less than Figure 7 The change in the drive current Ids2 of the second switching element M2 and the change in the gate voltage Vg1 are shown in FIG.

[0139] In this way, the driving current Ids2 and the gate voltage Vg2 of the second switching element M2 may converge to specific values, and thus may compensate for the threshold voltage of the first switching element M1 and the threshold voltage of the light emitting element EE.

[0140] Figure 9 It shows Figure 2 FIG. 1 is a graph showing an increase in the data swing range and an improvement in the consistency of the second switching element M2.

[0141] Reference Figures 1 to 9 , the second switching element M2 can be modeled as a resistor, and the resistor of the second switching element M2 can be represented as RDIO. When the resistor RDIO of the second switching element M2 increases, the data swing range (DSR) is expanded, and the long-range uniformity (LRU) can be enhanced through the linearization effect, wherein a portion of the data voltage VDATA is applied to the diode-connected second switching element M2. In an embodiment, the data voltage VDATA can be distributed through the charge distribution of the first capacitor C1 and the second capacitor C2, so that the data swing range can be further expanded.

[0142] exist Figure 9 , a data swing range according to the resistor RDIO of the second switching element M2 is represented as CV1, and a long-range uniformity according to the resistor RDIO of the second switching element M2 is represented as CV2.

[0143] According to an embodiment, a pixel may include a second switching element M2 , a first capacitor C1 , and a second capacitor C2 having a diode connection.

[0144] In an embodiment, as described above, the pixel may include the second switching element M2 having a diode connection so that variations in the threshold voltage of the driving switching element M1 and variations in the threshold voltage of the light emitting element EE can be compensated.

[0145] In such an embodiment, due to the linearization effect of the second switching element M2, a data swing range wider than the data range of the driving switching element M1 can be obtained. In such an embodiment, the data voltage VDATA is distributed through the charge distribution of the first capacitor C1 and the second capacitor C2, so that the data swing range can be further expanded.

[0146] In an embodiment, the first switching element M1 and the sixth switching element M6 are implemented as high-voltage MOSFETs, and the second switching element M2, the third switching element M3, the fourth switching element M4 and the fifth switching element M5 are implemented as medium-voltage MOSFETs, so that the area of ​​the pixel can be reduced and the resolution of the display panel 100 can be improved.

[0147] In such an embodiment, the second switching element M2 is implemented as a medium voltage MOSFET, so that a voltage margin can be further obtained through the threshold voltage of the second switching element M2 .

[0148] Figure 10 is a circuit diagram illustrating a pixel of a display panel of a display device according to an embodiment of the present invention.

[0149] In addition to the fourth switching element M4 of the pixel, the Figure 10 The embodiment of the display device of the pixel shown in FIG. Figures 1 to 9 The embodiments of the display devices described are substantially the same. Therefore, the same reference numerals will be used to refer to the same embodiments as those described above. Figures 1 to 9 The components described are identical or similar components, and any repeated detailed description thereof will be omitted or simplified.

[0150] Reference Figure 1 as well as Figures 3 to 10 In one embodiment, the display panel 100 includes a plurality of pixels. Each pixel includes a light emitting element EE. In one embodiment, the light emitting element EE may be a micro organic light emitting diode (Micro-OLED).

[0151] The pixel receives the write gate signal GW, the initialization gate signal GI, the light emitting element initialization gate signal EB, the data voltage VDATA and the emission signal EM, and the light emitting element EE of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0152] In an embodiment, Figure 10As shown in , the pixel includes a first switching element M1, a second switching element M2, a third switching element M3, a first capacitor C1, a second capacitor C2, a fourth switching element M4 and a light emitting element EE.

[0153] The first capacitor C1 includes a first electrode connected to the first node N1 and a second electrode connected to the fourth node N4. The second capacitor C2 is connected to the fourth node N4. In such an embodiment, the second capacitor C2 may include a first electrode connected to the fourth node N4 and a second electrode connected to the fifth node N5.

[0154] The fourth switching element M4 receives the initialization gate signal GI and is connected to the fourth node N4. In such an embodiment, the fourth switching element M4 may include a control electrode receiving the initialization gate signal GI, a first electrode connected to the fifth node N5, and a second electrode connected to the fourth node N4.

[0155] According to an embodiment, a pixel may include a second switching element M2 , a first capacitor C1 , and a second capacitor C2 having a diode connection.

[0156] In such an embodiment, the pixel may include a second switching element M2 having a diode connection so that variations in the threshold voltage of the driving switching element M1 and the threshold voltage of the light emitting element EE can be compensated.

[0157] Furthermore, due to the linearization effect of the second switching element M2, a data swing range wider than that of the driving switching element M1 can be obtained. In addition, the data voltage VDATA is distributed by the charge distribution of the first and second capacitors C1 and C2, so that the data swing range can be further expanded.

[0158] In such an embodiment, the first switching element M1 and the sixth switching element M6 are implemented as high-voltage MOSFETs, and the second switching element M2, the third switching element M3, the fourth switching element M4 and the fifth switching element M5 are implemented as medium-voltage MOSFETs, so that the area of ​​the pixel can be reduced and the resolution of the display panel 100 can be improved.

[0159] Furthermore, the second switching element M2 is implemented as a medium voltage MOSFET, so that a voltage margin can be further obtained through the threshold voltage of the second switching element M2 .

[0160] Figure 11 is a circuit diagram illustrating a pixel of a display panel of a display device according to an embodiment of the present invention.

[0161] In addition to the fourth switching element M4 of the pixel, the Figure 11 The embodiment of the display device of the pixel shown in FIG. Figures 1 to 9The embodiments of the display devices described are substantially the same. Therefore, the same reference numerals will be used to refer to the same embodiments as those described above. Figures 1 to 9 The components described are identical or similar components, and any repeated detailed description thereof will be omitted or simplified.

[0162] Reference Figure 1 、 Figures 3 to 9 as well as Figure 11 In one embodiment, the display panel 100 includes a plurality of pixels. Each pixel includes a light emitting element EE. In one embodiment, the light emitting element EE may be a micro organic light emitting diode (Micro-OLED).

[0163] The pixel receives the write gate signal GW, the initialization gate signal GI, the light emitting element initialization gate signal EB, the data voltage VDATA and the emission signal EM, and the light emitting element EE of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0164] In an embodiment, Figure 11 As shown in , the pixel includes a first switching element M1, a second switching element M2, a third switching element M3, a first capacitor C1, a second capacitor C2, a fourth switching element M4 and a light emitting element EE.

[0165] The first capacitor C1 includes a first electrode connected to the first node N1 and a second electrode connected to the fourth node N4. The second capacitor C2 is connected to the fourth node N4. In such an embodiment, the second capacitor C2 may include a first electrode connected to the fourth node N4 and a second electrode connected to the fifth node N5.

[0166] The fourth switching element M4 receives the initialization gate signal GI and is connected to the fourth node N4. In such an embodiment, the fourth switching element M4 may include a control electrode receiving the initialization gate signal GI, a first electrode connected to the second node N2, and a second electrode connected to the fourth node N4.

[0167] According to an embodiment, a pixel may include a second switching element M2 , a first capacitor C1 , and a second capacitor C2 having a diode connection.

[0168] In such an embodiment, the pixel may include a second switching element M2 having a diode connection so that variations in the threshold voltage of the driving switching element M1 and the threshold voltage of the light emitting element EE can be compensated.

[0169] Furthermore, due to the linearization effect of the second switching element M2, a data swing range wider than that of the driving switching element M1 can be obtained. In addition, the data voltage VDATA is distributed by the charge distribution of the first and second capacitors C1 and C2, so that the data swing range can be further expanded.

[0170] In such an embodiment, the first switching element M1 and the sixth switching element M6 are implemented as high-voltage MOSFETs, and the second switching element M2, the third switching element M3, the fourth switching element M4 and the fifth switching element M5 are implemented as medium-voltage MOSFETs, so that the area of ​​the pixel can be reduced and the resolution of the display panel 100 can be improved.

[0171] Furthermore, the second switching element M2 is implemented as a medium voltage MOSFET, so that a voltage margin can be further obtained through the threshold voltage of the second switching element M2 .

[0172] Figure 12 is a circuit diagram illustrating a pixel of a display panel of a display device according to an embodiment of the present invention.

[0173] In addition to the second capacitor C2 of the pixel, it includes Figure 12 The embodiment of the display device of the pixel shown in FIG. Figures 1 to 9 The embodiments of the display devices described are substantially the same. Therefore, the same reference numerals will be used to refer to the same embodiments as those described above. Figures 1 to 9 The components described are identical or similar components, and any repeated detailed description thereof will be omitted or simplified.

[0174] Reference Figure 1 、 Figures 3 to 9 as well as Figure 12 In one embodiment, the display panel 100 includes a plurality of pixels. Each pixel includes a light emitting element EE. In one embodiment, the light emitting element EE may be a micro organic light emitting diode (Micro-OLED).

[0175] The pixel receives the write gate signal GW, the initialization gate signal GI, the light emitting element initialization gate signal EB, the data voltage VDATA and the emission signal EM, and the light emitting element EE of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0176] In an embodiment, Figure 12 As shown in , the pixel includes a first switching element M1, a second switching element M2, a third switching element M3, a first capacitor C1, a second capacitor C2, a fourth switching element M4 and a light emitting element EE.

[0177] The first capacitor C1 includes a first electrode connected to the first node N1 and a second electrode connected to the fourth node N4. The second capacitor C2 is connected to the fourth node N4. In such an embodiment, the second capacitor C2 may include a first electrode connected to the fourth node N4 and a second electrode connected to the second node N2.

[0178] The fourth switching element M4 receives the initialization gate signal GI and is connected to the fourth node N4. In such an embodiment, the fourth switching element M4 may include a control electrode receiving the initialization gate signal GI, a first electrode receiving the first power voltage ELVDD, and a second electrode connected to the fourth node N4.

[0179] According to an embodiment, a pixel may include a second switching element M2 , a first capacitor C1 , and a second capacitor C2 having a diode connection.

[0180] In such an embodiment, the pixel may include a second switching element M2 having a diode connection so that variations in the threshold voltage of the driving switching element M1 and variations in the threshold voltage of the light emitting element EE can be compensated.

[0181] Furthermore, due to the linearization effect of the second switching element M2, a data swing range wider than that of the driving switching element M1 can be obtained. In addition, the data voltage VDATA is distributed by the charge distribution of the first and second capacitors C1 and C2, so that the data swing range can be further expanded.

[0182] In such an embodiment, the first switching element M1 and the sixth switching element M6 are implemented as high-voltage MOSFETs, and the second switching element M2, the third switching element M3, the fourth switching element M4 and the fifth switching element M5 are implemented as medium-voltage MOSFETs, so that the area of ​​the pixel can be reduced and the resolution of the display panel 100 can be improved.

[0183] Furthermore, the second switching element M2 is implemented as a medium voltage MOSFET, so that a voltage margin can be further obtained through the threshold voltage of the second switching element M2 .

[0184] Figure 13 is a circuit diagram illustrating a pixel of a display panel of a display device according to an embodiment of the present invention.

[0185] In addition to the second capacitor C2 and the fourth switching element M4 of the pixel, the Figure 13 The embodiment of the display device of the pixel shown in FIG. Figures 1 to 9 The embodiments of the display devices described are substantially the same. Therefore, the same reference numerals will be used to refer to the same embodiments as those described above. Figures 1 to 9The components described are identical or similar components, and any repeated detailed description thereof will be omitted or simplified.

[0186] Reference Figure 1 、 Figures 3 to 9 as well as Figure 13 In one embodiment, the display panel 100 includes a plurality of pixels. Each pixel includes a light emitting element EE. In one embodiment, the light emitting element EE may be a micro organic light emitting diode (Micro-OLED).

[0187] The pixel receives the write gate signal GW, the initialization gate signal GI, the light emitting element initialization gate signal EB, the data voltage VDATA and the emission signal EM, and the light emitting element EE of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0188] In an embodiment, Figure 13 As shown in , the pixel includes a first switching element M1, a second switching element M2, a third switching element M3, a first capacitor C1, a second capacitor C2, a fourth switching element M4 and a light emitting element EE.

[0189] The first capacitor C1 includes a first electrode connected to the first node N1 and a second electrode connected to the fourth node N4. The second capacitor C2 is connected to the fourth node N4. In an embodiment, the second capacitor C2 may include a first electrode connected to the fourth node N4 and a second electrode connected to the second node N2.

[0190] The fourth switching element M4 receives the initialization gate signal GI and is connected to the fourth node N4. In an embodiment, the fourth switching element M4 may include a control electrode receiving the initialization gate signal GI, a first electrode connected to the fifth node N5, and a second electrode connected to the fourth node N4.

[0191] According to an embodiment, a pixel may include a second switching element M2 , a first capacitor C1 , and a second capacitor C2 having a diode connection.

[0192] In such an embodiment, the pixel may include a second switching element M2 having a diode connection so that variations in the threshold voltage of the driving switching element M1 and variations in the threshold voltage of the light emitting element EE can be compensated.

[0193] Furthermore, due to the linearization effect of the second switching element M2, a data swing range wider than that of the driving switching element M1 can be obtained. In addition, the data voltage VDATA is distributed by the charge distribution of the first and second capacitors C1 and C2, so that the data swing range can be further expanded.

[0194] In such an embodiment, the first switching element M1 and the sixth switching element M6 are implemented as high-voltage MOSFETs, and the second switching element M2, the third switching element M3, the fourth switching element M4 and the fifth switching element M5 are implemented as medium-voltage MOSFETs, so that the area of ​​the pixel can be reduced and the resolution of the display panel 100 can be improved.

[0195] Furthermore, the second switching element M2 is implemented as a medium voltage MOSFET, so that a voltage margin can be further obtained through the threshold voltage of the second switching element M2 .

[0196] Figure 14 is a circuit diagram illustrating a pixel of a display panel of a display device according to an embodiment of the present invention. Figure 15 is shown applied to Figure 14 FIG1 is a timing diagram of an example of an input signal for a pixel.

[0197] In addition to the pixel also including the seventh switching element M7, including Figure 14 The embodiment of the display device of the pixel shown in FIG. Figures 1 to 9 The embodiments of the display devices described are substantially the same. Therefore, the same reference numerals will be used to refer to the same embodiments as those described above. Figures 1 to 9 The components described are identical or similar components, and any repeated detailed description thereof will be omitted or simplified.

[0198] Reference Figure 1 、 Figures 4 to 9 、 Figure 14 as well as Figure 15 In one embodiment, the display panel 100 includes a plurality of pixels. Each pixel includes a light emitting element EE. In one embodiment, the light emitting element EE may be a micro organic light emitting diode (Micro-OLED).

[0199] The pixel receives the write gate signal GW, the initialization gate signal GI, the light emitting element initialization gate signal EB, the data voltage VDATA and the emission signal EM, and the light emitting element EE of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0200] In an embodiment, Figure 14 As shown in , the pixel includes a first switching element M1, a second switching element M2, a third switching element M3, a first capacitor C1, a second capacitor C2, a fourth switching element M4 and a light emitting element EE.

[0201] The first capacitor C1 includes a first electrode connected to the first node N1 and a second electrode connected to the fourth node N4. The second capacitor C2 is connected to the fourth node N4. In such an embodiment, the second capacitor C2 may include a first electrode connected to the fourth node N4 and a second electrode connected to the fifth node N5.

[0202] The fourth switching element M4 receives the initialization gate signal GI and is connected to the fourth node N4. In such an embodiment, the fourth switching element M4 may include a control electrode receiving the initialization gate signal GI, a first electrode receiving the first power voltage ELVDD, and a second electrode connected to the fourth node N4.

[0203] In such an embodiment, Figure 14 As shown in , the pixel may further include a seventh switching element M7, which includes a control electrode receiving the second initialization gate signal GI2, a first electrode receiving a reference voltage VREF, and a second electrode connected to the first node N1.

[0204] like Figure 15 As shown in, in the first period DU1, the initialization gate signal GI may have a valid level, the second initialization gate signal GI2 may have a valid level, the write gate signal GW may have a valid level, the emission signal EM may have a valid level, the light emitting element initialization gate signal EB may have a valid level, and the data voltage VDATA may have a reference voltage VREF.

[0205] In the second period DU2 after the first period DU1, the initialization gate signal GI may have a non-active level, the second initialization gate signal GI2 may have a non-active level, the write gate signal GW may have a valid level, the emission signal EM may have a non-active level, the light emitting element initialization gate signal EB may have a valid level, and the data voltage VDATA may have a current grayscale data voltage VDATA[n].

[0206] In the third period DU3 after the second period DU2, the initialization gate signal GI may have a non-active level, the second initialization gate signal GI2 may have a non-active level, the write gate signal GW may have a non-active level, the emission signal EM may have a valid level, and the light emitting element initialization gate signal EB may have a non-active level.

[0207] In such an embodiment, the seventh switching element M7 may be used to initialize the first node N1 so that Figure 3Compared with the embodiment of the present invention, the duration of the first period DU1 can be shortened and the duration of the second period DU2 can be increased. In such an embodiment, the ratio of the duration of the data writing period DU2 can be relatively increased, so that the display panel 100 can support ultra-high resolution and ultra-high speed operation.

[0208] According to an embodiment, a pixel may include a second switching element M2 , a first capacitor C1 , and a second capacitor C2 having a diode connection.

[0209] In such an embodiment, the pixel may include a second switching element M2 having a diode connection so that variations in the threshold voltage of the driving switching element M1 and variations in the threshold voltage of the light emitting element EE can be compensated.

[0210] Furthermore, due to the linearization effect of the second switching element M2, a data swing range wider than that of the driving switching element M1 can be obtained. In addition, the data voltage VDATA is distributed by the charge distribution of the first and second capacitors C1 and C2, so that the data swing range can be further expanded.

[0211] In such an embodiment, the first switching element M1 and the sixth switching element M6 are implemented as high-voltage MOSFETs, and the second switching element M2, the third switching element M3, the fourth switching element M4 and the fifth switching element M5 are implemented as medium-voltage MOSFETs, so that the area of ​​the pixel can be reduced and the resolution of the display panel 100 can be improved.

[0212] Furthermore, the second switching element M2 is implemented as a medium voltage MOSFET, so that a voltage margin can be further obtained through the threshold voltage of the second switching element M2 .

[0213] Figure 16 is a circuit diagram illustrating a pixel of a display panel of a display device according to an embodiment of the present invention.

[0214] In addition to the pixel also including the seventh switching element M7, including Figure 16 The embodiment of the display device of the pixel shown in FIG. Figure 10 The embodiments of the display devices described are substantially the same. Therefore, the same reference numerals will be used to refer to the same embodiments as those described above. Figure 10 The components described are identical or similar components, and any repeated detailed description thereof will be omitted or simplified.

[0215] Reference Figure 1 、 Figures 4 to 9 、 Figure 15 as well as Figure 16In one embodiment, the display panel 100 includes a plurality of pixels. Each pixel includes a light emitting element EE. In one embodiment, the light emitting element EE may be a micro organic light emitting diode (Micro-OLED).

[0216] The pixel receives the write gate signal GW, the initialization gate signal GI, the light emitting element initialization gate signal EB, the data voltage VDATA and the emission signal EM, and the light emitting element EE of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0217] In an embodiment, Figure 16 As shown in , the pixel includes a first switching element M1, a second switching element M2, a third switching element M3, a first capacitor C1, a second capacitor C2, a fourth switching element M4 and a light emitting element EE.

[0218] The first capacitor C1 includes a first electrode connected to the first node N1 and a second electrode connected to the fourth node N4. The second capacitor C2 is connected to the fourth node N4. In such an embodiment, the second capacitor C2 may include a first electrode connected to the fourth node N4 and a second electrode connected to the fifth node N5.

[0219] The fourth switching element M4 receives the initialization gate signal GI and is connected to the fourth node N4. In such an embodiment, the fourth switching element M4 may include a control electrode receiving the initialization gate signal GI, a first electrode connected to the fifth node N5, and a second electrode connected to the fourth node N4.

[0220] In such an embodiment, Figure 16 As shown in , the pixel may further include a seventh switching element M7 including a control electrode receiving the second initialization gate signal GI2 , a first electrode receiving a reference voltage VREF, and a second electrode connected to the first node N1 .

[0221] According to an embodiment, a pixel may include a second switching element M2 , a first capacitor C1 , and a second capacitor C2 having a diode connection.

[0222] In such an embodiment, the pixel may include a second switching element M2 having a diode connection so that variations in the threshold voltage of the driving switching element M1 and variations in the threshold voltage of the light emitting element EE can be compensated.

[0223] Furthermore, due to the linearization effect of the second switching element M2, a data swing range wider than that of the driving switching element M1 can be obtained. In addition, the data voltage VDATA is distributed by the charge distribution of the first and second capacitors C1 and C2, so that the data swing range can be further expanded.

[0224] In such an embodiment, the first switching element M1 and the sixth switching element M6 are implemented as high-voltage MOSFETs, and the second switching element M2, the third switching element M3, the fourth switching element M4 and the fifth switching element M5 are implemented as medium-voltage MOSFETs, so that the area of ​​the pixel can be reduced and the resolution of the display panel 100 can be improved.

[0225] Furthermore, the second switching element M2 is implemented as a medium voltage MOSFET, so that a voltage margin can be further obtained through the threshold voltage of the second switching element M2 .

[0226] Figure 17 is a circuit diagram illustrating a pixel of a display panel of a display device according to an embodiment of the present invention.

[0227] In addition to the pixel also including the seventh switching element M7, including Figure 16 The embodiment of the display device of the pixel shown in FIG. Figure 11 The embodiments of the display devices described are substantially the same. Therefore, the same reference numerals will be used to refer to the same embodiments as those described above. Figure 11 The components described are identical or similar components, and any repeated detailed description thereof will be omitted or simplified.

[0228] Reference Figure 1 、 Figures 4 to 9 、 Figure 15 as well as Figure 17 In one embodiment, the display panel 100 includes a plurality of pixels. Each pixel includes a light emitting element EE. In one embodiment, the light emitting element EE may be a micro organic light emitting diode (Micro-OLED).

[0229] The pixel receives the write gate signal GW, the initialization gate signal GI, the light emitting element initialization gate signal EB, the data voltage VDATA and the emission signal EM, and the light emitting element EE of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0230] In an embodiment, Figure 17 As shown in , the pixel includes a first switching element M1, a second switching element M2, a third switching element M3, a first capacitor C1, a second capacitor C2, a fourth switching element M4 and a light emitting element EE.

[0231] The first capacitor C1 includes a first electrode connected to the first node N1 and a second electrode connected to the fourth node N4. The second capacitor C2 is connected to the fourth node N4. In such an embodiment, the second capacitor C2 may include a first electrode connected to the fourth node N4 and a second electrode connected to the fifth node N5.

[0232] The fourth switching element M4 receives the initialization gate signal GI and is connected to the fourth node N4. In such an embodiment, the fourth switching element M4 may include a control electrode receiving the initialization gate signal GI, a first electrode connected to the second node N2, and a second electrode connected to the fourth node N4.

[0233] In such an embodiment, Figure 17 As shown in , the pixel may further include a seventh switching element M7 including a control electrode receiving the second initialization gate signal GI2 , a first electrode receiving a reference voltage VREF, and a second electrode connected to the first node N1 .

[0234] According to an embodiment, a pixel may include a second switching element M2 , a first capacitor C1 , and a second capacitor C2 having a diode connection.

[0235] In such an embodiment, the pixel may include a second switching element M2 having a diode connection so that variations in the threshold voltage of the driving switching element M1 and variations in the threshold voltage of the light emitting element EE can be compensated.

[0236] Furthermore, due to the linearization effect of the second switching element M2, a data swing range wider than that of the driving switching element M1 can be obtained. In addition, the data voltage VDATA is distributed by the charge distribution of the first and second capacitors C1 and C2, so that the data swing range can be further expanded.

[0237] In such an embodiment, the first switching element M1 and the sixth switching element M6 are implemented as high-voltage MOSFETs, and the second switching element M2, the third switching element M3, the fourth switching element M4 and the fifth switching element M5 are implemented as medium-voltage MOSFETs, so that the area of ​​the pixel can be reduced and the resolution of the display panel 100 can be improved.

[0238] Furthermore, the second switching element M2 is implemented as a medium voltage MOSFET, so that a voltage margin can be further obtained through the threshold voltage of the second switching element M2 .

[0239] Figure 18 is a circuit diagram illustrating a pixel of a display panel of a display device according to an embodiment of the present invention.

[0240] In addition to the pixel also including the seventh switching element M7, including Figure 18 The embodiment of the display device of the pixel shown in FIG. Figure 12 The embodiments of the display devices described are substantially the same. Therefore, the same reference numerals will be used to refer to the same embodiments as those described above. Figure 12 The components described are identical or similar components, and any repeated detailed description thereof will be omitted or simplified.

[0241] Reference Figure 1 、 Figures 4 to 9 、 Figure 15 as well as Figure 18 In one embodiment, the display panel 100 includes a plurality of pixels. Each pixel includes a light emitting element EE. In one embodiment, the light emitting element EE may be a micro organic light emitting diode (Micro-OLED).

[0242] The pixel receives the write gate signal GW, the initialization gate signal GI, the light emitting element initialization gate signal EB, the data voltage VDATA and the emission signal EM, and the light emitting element EE of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0243] In an embodiment, Figure 18 As shown in , the pixel includes a first switching element M1, a second switching element M2, a third switching element M3, a first capacitor C1, a second capacitor C2, a fourth switching element M4 and a light emitting element EE.

[0244] The first capacitor C1 includes a first electrode connected to the first node N1 and a second electrode connected to the fourth node N4. The second capacitor C2 is connected to the fourth node N4. In an embodiment, the second capacitor C2 may include a first electrode connected to the fourth node N4 and a second electrode connected to the second node N2.

[0245] The fourth switching element M4 receives the initialization gate signal GI and is connected to the fourth node N4. In an embodiment, the fourth switching element M4 may include a control electrode receiving the initialization gate signal GI, a first electrode receiving the first power voltage ELVDD, and a second electrode connected to the fourth node N4.

[0246] In such an embodiment, Figure 18 As shown in , the pixel may further include a seventh switching element M7 including a control electrode receiving the second initialization gate signal GI2 , a first electrode receiving a reference voltage VREF, and a second electrode connected to the first node N1 .

[0247] According to an embodiment, a pixel may include a second switching element M2 , a first capacitor C1 , and a second capacitor C2 having a diode connection.

[0248] In such an embodiment, the pixel may include a second switching element M2 having a diode connection so that variations in the threshold voltage of the driving switching element M1 and variations in the threshold voltage of the light emitting element EE can be compensated.

[0249] Furthermore, due to the linearization effect of the second switching element M2, a data swing range wider than that of the driving switching element M1 can be obtained. In addition, the data voltage VDATA is distributed by the charge distribution of the first and second capacitors C1 and C2, so that the data swing range can be further expanded.

[0250] In such an embodiment, the first switching element M1 and the sixth switching element M6 are implemented as high-voltage MOSFETs, and the second switching element M2, the third switching element M3, the fourth switching element M4 and the fifth switching element M5 are implemented as medium-voltage MOSFETs, so that the area of ​​the pixel can be reduced and the resolution of the display panel 100 can be improved.

[0251] Furthermore, the second switching element M2 is implemented as a medium voltage MOSFET, so that a voltage margin can be further obtained through the threshold voltage of the second switching element M2 .

[0252] Figure 19 is a circuit diagram illustrating a pixel of a display panel of a display device according to an embodiment of the present invention.

[0253] In addition to the pixel also including the seventh switching element M7, including Figure 19 The embodiment of the display device of the pixel shown in FIG. Figure 13 The embodiments of the display devices described are substantially the same. Therefore, the same reference numerals will be used to refer to the same embodiments as those described above. Figure 13 The components described are identical or similar components, and any repeated detailed description thereof will be omitted or simplified.

[0254] Reference Figure 1 、 Figures 4 to 9 、 Figure 15 as well as Figure 19 In one embodiment, the display panel 100 includes a plurality of pixels. Each pixel includes a light emitting element EE. In one embodiment, the light emitting element EE may be a micro organic light emitting diode (Micro-OLED).

[0255] The pixel receives the write gate signal GW, the initialization gate signal GI, the light emitting element initialization gate signal EB, the data voltage VDATA and the emission signal EM, and the light emitting element EE of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0256] In an embodiment, Figure 19 As shown in , the pixel includes a first switching element M1, a second switching element M2, a third switching element M3, a first capacitor C1, a second capacitor C2, a fourth switching element M4 and a light emitting element EE.

[0257] The first capacitor C1 includes a first electrode connected to the first node N1 and a second electrode connected to the fourth node N4. The second capacitor C2 is connected to the fourth node N4. In an embodiment, the second capacitor C2 may include a first electrode connected to the fourth node N4 and a second electrode connected to the second node N2.

[0258] The fourth switching element M4 receives the initialization gate signal GI and is connected to the fourth node N4. In an embodiment, the fourth switching element M4 may include a control electrode receiving the initialization gate signal GI, a first electrode connected to the fifth node N5, and a second electrode connected to the fourth node N4.

[0259] In such an embodiment, Figure 19 As shown in , the pixel may further include a seventh switching element M7 including a control electrode receiving the second initialization gate signal GI2 , a first electrode receiving a reference voltage VREF, and a second electrode connected to the first node N1 .

[0260] According to an embodiment, a pixel may include a second switching element M2 , a first capacitor C1 , and a second capacitor C2 having a diode connection.

[0261] In such an embodiment, the pixel may include a second switching element M2 having a diode connection so that variations in the threshold voltage of the driving switching element M1 and variations in the threshold voltage of the light emitting element EE can be compensated.

[0262] Furthermore, due to the linearization effect of the second switching element M2, a data swing range wider than that of the driving switching element M1 can be obtained. In addition, the data voltage VDATA is distributed by the charge distribution of the first and second capacitors C1 and C2, so that the data swing range can be further expanded.

[0263] In such an embodiment, the first switching element M1 and the sixth switching element M6 are implemented as high-voltage MOSFETs, and the second switching element M2, the third switching element M3, the fourth switching element M4 and the fifth switching element M5 are implemented as medium-voltage MOSFETs, so that the area of ​​the pixel can be reduced and the resolution of the display panel 100 can be improved.

[0264] Furthermore, the second switching element M2 is implemented as a medium voltage MOSFET, so that a voltage margin can be further obtained through the threshold voltage of the second switching element M2 .

[0265] Figure 20 is a circuit diagram illustrating a pixel of a display panel of a display device according to an embodiment of the present invention. Figure 21 is shown applied to Figure 20 FIG1 is a timing diagram of an example of an input signal for a pixel.

[0266] Except that the sixth switching element M6 of the pixel is an N-type transistor, the Figure 20 The embodiment of the display device of the pixel shown in FIG. Figures 1 to 9 The embodiments of the display devices described are substantially the same. Therefore, the same reference numerals will be used to refer to the same embodiments as those described above. Figures 1 to 9 The components described are identical or similar components, and any repeated detailed description thereof will be omitted or simplified.

[0267] Reference Figure 1 、 Figures 4 to 9 、 Figure 20 as well as Figure 21 In one embodiment, the display panel 100 includes a plurality of pixels. Each pixel includes a light emitting element EE. In one embodiment, the light emitting element EE may be a micro organic light emitting diode (Micro-OLED).

[0268] The pixel receives the write gate signal GW, the initialization gate signal GI, the light emitting element initialization gate signal EB, the data voltage VDATA and the emission signal EM, and the light emitting element EE of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0269] In an embodiment, Figure 20 As shown in , the pixel includes a first switching element M1, a second switching element M2, a third switching element M3, a first capacitor C1, a second capacitor C2, a fourth switching element M4 and a light emitting element EE.

[0270] The first capacitor C1 includes a first electrode connected to the first node N1 and a second electrode connected to the fourth node N4. The second capacitor C2 is connected to the fourth node N4. In such an embodiment, the second capacitor C2 may include a first electrode connected to the fourth node N4 and a second electrode connected to the fifth node N5.

[0271] The fourth switching element M4 receives the initialization gate signal GI and is connected to the fourth node N4. In such an embodiment, the fourth switching element M4 may include a control electrode receiving the initialization gate signal GI, a first electrode receiving the first power voltage ELVDD, and a second electrode connected to the fourth node N4.

[0272] In such an embodiment, the first switching element M1, the second switching element M2, the third switching element M3, the fourth switching element M4, and the fifth switching element M5 may be P-type transistors. In an embodiment, for example, the first switching element M1, the second switching element M2, the third switching element M3, the fourth switching element M4, and the fifth switching element M5 may be low-temperature polysilicon (LTPS) thin-film transistors.

[0273] In such an embodiment, the sixth switching element M6 may be an N-type transistor. In an embodiment, for example, the sixth switching element M6 may be an oxide semiconductor thin film transistor.

[0274] In addition to the light emitting element initialization gate signal EB being inverted, Figure 21 The timing diagram and Figure 3 The timing diagrams are basically the same.

[0275] According to an embodiment, a pixel may include a second switching element M2 , a first capacitor C1 , and a second capacitor C2 having a diode connection.

[0276] In such an embodiment, the pixel may include a second switching element M2 having a diode connection so that variations in the threshold voltage of the driving switching element M1 and variations in the threshold voltage of the light emitting element EE can be compensated.

[0277] Furthermore, due to the linearization effect of the second switching element M2, a data swing range wider than that of the driving switching element M1 can be obtained. In addition, the data voltage VDATA is distributed by the charge distribution of the first and second capacitors C1 and C2, so that the data swing range can be further expanded.

[0278] Figure 22 is a circuit diagram illustrating a pixel of a display panel of a display device according to an embodiment of the present invention.

[0279] Except that the sixth switching element M6 of the pixel is an N-type transistor, the Figure 22 The embodiment of the display device of the pixel shown in FIG. Figure 10 The embodiments of the display devices described are substantially the same. Therefore, the same reference numerals will be used to refer to the same embodiments as those described above. Figure 10 The components described are identical or similar components, and any repeated detailed description thereof will be omitted or simplified.

[0280] Reference Figure 1 、 Figures 4 to 9 、 Figure 21 as well as Figure 22 In one embodiment, the display panel 100 includes a plurality of pixels. Each pixel includes a light emitting element EE. In one embodiment, the light emitting element EE may be a micro organic light emitting diode (Micro-OLED).

[0281] The pixel receives the write gate signal GW, the initialization gate signal GI, the light emitting element initialization gate signal EB, the data voltage VDATA and the emission signal EM, and the light emitting element EE of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0282] In such an embodiment, the first switching element M1, the second switching element M2, the third switching element M3, the fourth switching element M4, and the fifth switching element M5 may be P-type transistors. In an embodiment, for example, the first switching element M1, the second switching element M2, the third switching element M3, the fourth switching element M4, and the fifth switching element M5 may be low-temperature polysilicon (LTPS) thin-film transistors.

[0283] In such an embodiment, the sixth switching element M6 may be an N-type transistor. In an embodiment, for example, the sixth switching element M6 may be an oxide semiconductor thin film transistor.

[0284] According to an embodiment, a pixel may include a second switching element M2 , a first capacitor C1 , and a second capacitor C2 having a diode connection.

[0285] In such an embodiment, the pixel may include a second switching element M2 having a diode connection so that variations in the threshold voltage of the driving switching element M1 and variations in the threshold voltage of the light emitting element EE can be compensated.

[0286] Furthermore, due to the linearization effect of the second switching element M2, a data swing range wider than that of the driving switching element M1 can be obtained. In addition, the data voltage VDATA is distributed by the charge distribution of the first and second capacitors C1 and C2, so that the data swing range can be further expanded.

[0287] Figure 23 is a circuit diagram illustrating a pixel of a display panel of a display device according to an embodiment of the present invention.

[0288] Except that the sixth switching element M6 of the pixel is an N-type transistor, the Figure 23 The embodiment of the display device of the pixel shown in FIG. Figure 11 The embodiments of the display devices described are substantially the same. Therefore, the same reference numerals will be used to refer to the same embodiments as those described above. Figure 11 The components described are identical or similar components, and any repeated detailed description thereof will be omitted or simplified.

[0289] Reference Figure 1 、 Figures 4 to 9 、 Figure 21 as well as Figure 23 In one embodiment, the display panel 100 includes a plurality of pixels. Each pixel includes a light emitting element EE. In one embodiment, the light emitting element EE may be a micro organic light emitting diode (Micro-OLED).

[0290] The pixel receives the write gate signal GW, the initialization gate signal GI, the light emitting element initialization gate signal EB, the data voltage VDATA and the emission signal EM, and the light emitting element EE of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0291] In such an embodiment, the first switching element M1, the second switching element M2, the third switching element M3, the switching element M4, and the fifth switching element M5 may be P-type transistors. In an embodiment, for example, the first switching element M1, the second switching element M2, the third switching element M3, the fourth switching element M4, and the fifth switching element M5 may be low-temperature polysilicon (LTPS) thin-film transistors.

[0292] In such an embodiment, the sixth switching element M6 may be an N-type transistor. In an embodiment, for example, the sixth switching element M6 may be an oxide semiconductor thin film transistor.

[0293] According to an embodiment, a pixel may include a second switching element M2 , a first capacitor C1 , and a second capacitor C2 having a diode connection.

[0294] In such an embodiment, the pixel may include a second switching element M2 having a diode connection so that variations in the threshold voltage of the driving switching element M1 and variations in the threshold voltage of the light emitting element EE can be compensated.

[0295] Furthermore, due to the linearization effect of the second switching element M2, a data swing range wider than that of the driving switching element M1 can be obtained. In addition, the data voltage VDATA is distributed by the charge distribution of the first and second capacitors C1 and C2, so that the data swing range can be further expanded.

[0296] Figure 24 is a circuit diagram illustrating a pixel of a display panel of a display device according to an embodiment of the present invention.

[0297] Except that the sixth switching element M6 of the pixel is an N-type transistor, the Figure 24 The embodiment of the display device of the pixel shown in FIG. Figure 12 The embodiments of the display devices described are substantially the same. Therefore, the same reference numerals will be used to refer to the same embodiments as those described above. Figure 12 The components described are identical or similar components, and any repeated detailed description thereof will be omitted or simplified.

[0298] Reference Figure 1 、 Figures 4 to 9 、 Figure 21 as well as Figure 24In one embodiment, the display panel 100 includes a plurality of pixels. Each pixel includes a light emitting element EE. In one embodiment, the light emitting element EE may be a micro organic light emitting diode (Micro-OLED).

[0299] The pixel receives the write gate signal GW, the initialization gate signal GI, the light emitting element initialization gate signal EB, the data voltage VDATA and the emission signal EM, and the light emitting element EE of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0300] In such an embodiment, the first switching element M1, the second switching element M2, the third switching element M3, the fourth switching element M4, and the fifth switching element M5 may be P-type transistors. In an embodiment, for example, the first switching element M1, the second switching element M2, the third switching element M3, the fourth switching element M4, and the fifth switching element M5 may be low-temperature polysilicon (LTPS) thin-film transistors.

[0301] In such an embodiment, the sixth switching element M6 may be an N-type transistor. In an embodiment, for example, the sixth switching element M6 may be an oxide semiconductor thin film transistor.

[0302] According to an embodiment, a pixel may include a second switching element M2 , a first capacitor C1 , and a second capacitor C2 having a diode connection.

[0303] In such an embodiment, the pixel may include a second switching element M2 having a diode connection so that variations in the threshold voltage of the driving switching element M1 and variations in the threshold voltage of the light emitting element EE can be compensated.

[0304] Furthermore, due to the linearization effect of the second switching element M2, a data swing range wider than that of the driving switching element M1 can be obtained. In addition, the data voltage VDATA is distributed by the charge distribution of the first and second capacitors C1 and C2, so that the data swing range can be further expanded.

[0305] Figure 25 is a circuit diagram illustrating a pixel of a display panel of a display device according to an embodiment of the present invention.

[0306] Except that the sixth switching element M6 of the pixel is an N-type transistor, the Figure 25 The embodiment of the display device of the pixel shown in FIG. Figure 13 The embodiments of the display devices described are substantially the same. Therefore, the same reference numerals will be used to refer to the same embodiments as those described above. Figure 13 The components described are identical or similar components, and any repeated detailed description thereof will be omitted or simplified.

[0307] Reference Figure 1 、 Figures 4 to 9 、 Figure 21 as well as Figure 25 In one embodiment, the display panel 100 includes a plurality of pixels. Each pixel includes a light emitting element EE. In one embodiment, the light emitting element EE may be a micro organic light emitting diode (Micro-OLED).

[0308] The pixel receives the write gate signal GW, the initialization gate signal GI, the light emitting element initialization gate signal EB, the data voltage VDATA and the emission signal EM, and the light emitting element EE of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0309] In such an embodiment, the first switching element M1, the second switching element M2, the third switching element M3, the fourth switching element M4, and the fifth switching element M5 may be P-type transistors. In an embodiment, for example, the first switching element M1, the second switching element M2, the third switching element M3, the fourth switching element M4, and the fifth switching element M5 may be low-temperature polysilicon (LTPS) thin-film transistors.

[0310] In such an embodiment, the sixth switching element M6 may be an N-type transistor. In an embodiment, for example, the sixth switching element M6 may be an oxide semiconductor thin film transistor.

[0311] According to an embodiment, a pixel may include a second switching element M2 , a first capacitor C1 , and a second capacitor C2 having a diode connection.

[0312] In such an embodiment, the pixel may include a second switching element M2 having a diode connection so that variations in the threshold voltage of the driving switching element M1 and variations in the threshold voltage of the light emitting element EE can be compensated.

[0313] Furthermore, due to the linearization effect of the second switching element M2, a data swing range wider than that of the driving switching element M1 can be obtained. In addition, the data voltage VDATA is distributed by the charge distribution of the first and second capacitors C1 and C2, so that the data swing range can be further expanded.

[0314] Figure 26 is a circuit diagram illustrating a pixel of a display panel of a display device according to an embodiment of the present invention. Figure 27 is shown applied to Figure 26 FIG1 is a timing diagram of an example of an input signal for a pixel.

[0315] Except that the sixth switching element M6 of the pixel is an N-type transistor, the Figure 26The embodiment of the display device of the pixel shown in FIG. Figure 14 and 15 The embodiments of the display devices described are substantially the same. Therefore, the same reference numerals will be used to refer to the same embodiments as those described above. Figure 14 and 15 The components described are identical or similar components, and any repeated detailed description thereof will be omitted or simplified.

[0316] Reference Figure 1 、 Figures 4 to 9 、 Figure 26 as well as Figure 27 In one embodiment, the display panel 100 includes a plurality of pixels. Each pixel includes a light emitting element EE. In one embodiment, the light emitting element EE may be a micro organic light emitting diode (Micro-OLED).

[0317] The pixel receives the write gate signal GW, the initialization gate signal GI, the light emitting element initialization gate signal EB, the data voltage VDATA and the emission signal EM, and the light emitting element EE of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0318] In an embodiment, Figure 26 As shown in , the pixel includes a first switching element M1, a second switching element M2, a third switching element M3, a first capacitor C1, a second capacitor C2, a fourth switching element M4 and a light emitting element EE.

[0319] The first capacitor C1 includes a first electrode connected to the first node N1 and a second electrode connected to the fourth node N4. The second capacitor C2 is connected to the fourth node N4. In such an embodiment, the second capacitor C2 may include a first electrode connected to the fourth node N4 and a second electrode connected to the fifth node N5.

[0320] The fourth switching element M4 receives the initialization gate signal GI and is connected to the fourth node N4. In such an embodiment, the fourth switching element M4 may include a control electrode receiving the initialization gate signal GI, a first electrode receiving the first power voltage ELVDD, and a second electrode connected to the fourth node N4.

[0321] In such an embodiment, the first switching element M1, the second switching element M2, the third switching element M3, the fourth switching element M4, and the fifth switching element M5 may be P-type transistors. In an embodiment, for example, the first switching element M1, the second switching element M2, the third switching element M3, the fourth switching element M4, and the fifth switching element M5 may be low-temperature polysilicon (LTPS) thin-film transistors.

[0322] In such an embodiment, the sixth switching element M6 may be an N-type transistor. In an embodiment, for example, the sixth switching element M6 may be an oxide semiconductor thin film transistor.

[0323] In such an embodiment, the pixel may further include a seventh switching element M7, the seventh switching element M7 including a control electrode receiving the second initialization gate signal GI2, a first electrode receiving the reference voltage VREF, and a second electrode connected to the first node N1. In an embodiment, for example, the seventh switching element M7 may be a P-type transistor.

[0324] In addition to the light emitting element initialization gate signal EB being inverted, Figure 27 The timing diagram and Figure 15 The timing diagrams are basically the same.

[0325] According to an embodiment, a pixel may include a second switching element M2 , a first capacitor C1 , and a second capacitor C2 having a diode connection.

[0326] In such an embodiment, the pixel may include a second switching element M2 having a diode connection so that variations in the threshold voltage of the driving switching element M1 and variations in the threshold voltage of the light emitting element EE can be compensated.

[0327] Furthermore, due to the linearization effect of the second switching element M2, a data swing range wider than that of the driving switching element M1 can be obtained. In addition, the data voltage VDATA is distributed by the charge distribution of the first and second capacitors C1 and C2, so that the data swing range can be further expanded.

[0328] Figure 28 is a circuit diagram illustrating a pixel of a display panel of a display device according to an embodiment of the present invention.

[0329] Except that the sixth switching element M6 of the pixel is an N-type transistor, the Figure 28 The embodiment of the display device of the pixel shown in FIG. Figure 16 The embodiments of the display devices described are substantially the same. Therefore, the same reference numerals will be used to refer to the same embodiments as those described above. Figure 16 The components described are identical or similar components, and any repeated detailed description thereof will be omitted or simplified.

[0330] Reference Figure 1 、 Figures 4 to 9 、 Figure 27 as well as Figure 28 In one embodiment, the display panel 100 includes a plurality of pixels. Each pixel includes a light emitting element EE. In one embodiment, the light emitting element EE may be a micro organic light emitting diode (Micro-OLED).

[0331] The pixel receives the write gate signal GW, the initialization gate signal GI, the light emitting element initialization gate signal EB, the data voltage VDATA and the emission signal EM, and the light emitting element EE of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0332] In such an embodiment, the first switching element M1, the second switching element M2, the third switching element M3, the fourth switching element M4, and the fifth switching element M5 may be P-type transistors. In an embodiment, for example, the first switching element M1, the second switching element M2, the third switching element M3, the fourth switching element M4, and the fifth switching element M5 may be low-temperature polysilicon (LTPS) thin-film transistors.

[0333] In such an embodiment, the sixth switching element M6 may be an N-type transistor. In an embodiment, for example, the sixth switching element M6 may be an oxide semiconductor thin film transistor.

[0334] According to an embodiment, a pixel may include a second switching element M2 , a first capacitor C1 , and a second capacitor C2 having a diode connection.

[0335] In such an embodiment, the pixel may include a second switching element M2 having a diode connection so that variations in the threshold voltage of the driving switching element M1 and variations in the threshold voltage of the light emitting element EE can be compensated.

[0336] Furthermore, due to the linearization effect of the second switching element M2, a data swing range wider than that of the driving switching element M1 can be obtained. In addition, the data voltage VDATA is distributed by the charge distribution of the first and second capacitors C1 and C2, so that the data swing range can be further expanded.

[0337] Figure 29 is a circuit diagram illustrating a pixel of a display panel of a display device according to an embodiment of the present invention.

[0338] Except that the sixth switching element M6 of the pixel is an N-type transistor, the Figure 29 The embodiment of the display device of the pixel shown in FIG. Figure 17 The embodiments of the display devices described are substantially the same. Therefore, the same reference numerals will be used to refer to the same embodiments as those described above. Figure 17 The components described are identical or similar components, and any repeated detailed description thereof will be omitted or simplified.

[0339] Reference Figure 1 、 Figures 4 to 9 、 Figure 27 as well as Figure 29In one embodiment, the display panel 100 includes a plurality of pixels. Each pixel includes a light emitting element EE. In one embodiment, the light emitting element EE may be a micro organic light emitting diode (Micro-OLED).

[0340] The pixel receives the write gate signal GW, the initialization gate signal GI, the light emitting element initialization gate signal EB, the data voltage VDATA and the emission signal EM, and the light emitting element EE of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0341] In such an embodiment, the first switching element M1, the second switching element M2, the third switching element M3, the fourth switching element M4, and the fifth switching element M5 may be P-type transistors. In an embodiment, for example, the first switching element M1, the second switching element M2, the third switching element M3, the fourth switching element M4, and the fifth switching element M5 may be low-temperature polysilicon (LTPS) thin-film transistors.

[0342] In such an embodiment, the sixth switching element M6 may be an N-type transistor. In an embodiment, for example, the sixth switching element M6 may be an oxide semiconductor thin film transistor.

[0343] According to an embodiment, a pixel may include a second switching element M2 , a first capacitor C1 , and a second capacitor C2 having a diode connection.

[0344] In such an embodiment, the pixel may include a second switching element M2 having a diode connection so that variations in the threshold voltage of the driving switching element M1 and variations in the threshold voltage of the light emitting element EE can be compensated.

[0345] Furthermore, due to the linearization effect of the second switching element M2, a data swing range wider than that of the driving switching element M1 can be obtained. In addition, the data voltage VDATA is distributed by the charge distribution of the first and second capacitors C1 and C2, so that the data swing range can be further expanded.

[0346] Figure 30 is a circuit diagram illustrating a pixel of a display panel of a display device according to an embodiment of the present invention.

[0347] Except that the sixth switching element M6 of the pixel is an N-type transistor, the Figure 30 The embodiment of the display device of the pixel shown in FIG. Figure 18 The embodiments of the display devices described are substantially the same. Therefore, the same reference numerals will be used to refer to the same embodiments as those described above. Figure 18 The components described are identical or similar components, and any repeated detailed description thereof will be omitted or simplified.

[0348] Reference Figure 1 、 Figures 4 to 9 、 Figure 27 as well as Figure 30 In one embodiment, the display panel 100 includes a plurality of pixels. Each pixel includes a light emitting element EE. In one embodiment, the light emitting element EE may be a micro organic light emitting diode (Micro-OLED).

[0349] The pixel receives the write gate signal GW, the initialization gate signal GI, the light emitting element initialization gate signal EB, the data voltage VDATA and the emission signal EM, and the light emitting element EE of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0350] In such an embodiment, the first switching element M1, the second switching element M2, the third switching element M3, the fourth switching element M4, and the fifth switching element M5 may be P-type transistors. In an embodiment, for example, the first switching element M1, the second switching element M2, the third switching element M3, the fourth switching element M4, and the fifth switching element M5 may be low-temperature polysilicon (LTPS) thin-film transistors.

[0351] In such an embodiment, the sixth switching element M6 may be an N-type transistor. In an embodiment, for example, the sixth switching element M6 may be an oxide semiconductor thin film transistor.

[0352] According to an embodiment, a pixel may include a second switching element M2 , a first capacitor C1 , and a second capacitor C2 having a diode connection.

[0353] In such an embodiment, the pixel may include a second switching element M2 having a diode connection so that variations in the threshold voltage of the driving switching element M1 and variations in the threshold voltage of the light emitting element EE can be compensated.

[0354] Furthermore, due to the linearization effect of the second switching element M2, a data swing range wider than that of the driving switching element M1 can be obtained. In addition, the data voltage VDATA is distributed by the charge distribution of the first and second capacitors C1 and C2, so that the data swing range can be further expanded.

[0355] Figure 31 is a circuit diagram illustrating a pixel of a display panel of a display device according to an embodiment of the present invention.

[0356] Except that the sixth switching element M6 of the pixel is an N-type transistor, the Figure 31 The embodiment of the display device of the pixel shown in FIG. Figure 19The embodiments of the display devices described are substantially the same. Therefore, the same reference numerals will be used to refer to the same embodiments as those described above. Figure 19 The components described are identical or similar components, and any repeated detailed description thereof will be omitted or simplified.

[0357] Reference Figure 1 、 Figures 4 to 9 、 Figure 27 as well as Figure 31 In one embodiment, the display panel 100 includes a plurality of pixels. Each pixel includes a light emitting element EE. In one embodiment, the light emitting element EE may be a micro organic light emitting diode (Micro-OLED).

[0358] The pixel receives the write gate signal GW, the initialization gate signal GI, the light emitting element initialization gate signal EB, the data voltage VDATA and the emission signal EM, and the light emitting element EE of the pixel emits light corresponding to the level of the data voltage VDATA to display an image.

[0359] In such an embodiment, the first switching element M1, the second switching element M2, the third switching element M3, the fourth switching element M4, and the fifth switching element M5 may be P-type transistors. In an embodiment, for example, the first switching element M1, the second switching element M2, the third switching element M3, the fourth switching element M4, and the fifth switching element M5 may be low-temperature polysilicon (LTPS) thin-film transistors.

[0360] In such an embodiment, the sixth switching element M6 may be an N-type transistor. In an embodiment, for example, the sixth switching element M6 may be an oxide semiconductor thin film transistor.

[0361] According to an embodiment, a pixel may include a second switching element M2 , a first capacitor C1 , and a second capacitor C2 having a diode connection.

[0362] In such an embodiment, the pixel may include a second switching element M2 having a diode connection so that variations in the threshold voltage of the driving switching element M1 and variations in the threshold voltage of the light emitting element EE can be compensated.

[0363] Furthermore, due to the linearization effect of the second switching element M2, a data swing range wider than that of the driving switching element M1 can be obtained. In addition, the data voltage VDATA is distributed by the charge distribution of the first and second capacitors C1 and C2, so that the data swing range can be further expanded.

[0364] Figure 32 is a block diagram illustrating an electronic device according to an embodiment of the present invention. Figure 33 It shows Figure 32A schematic diagram of an example of an electronic device implemented as a virtual reality display system. Figure 34 It shows Figure 32 Schematic diagram of an example in which the electronic device is implemented as a smart phone.

[0365] Reference Figures 1 to 34 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. In such an embodiment, the display device 1060 may correspond to Figure 1 In addition, the electronic device 1000 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.

[0366] In an embodiment, Figure 34 As shown in FIG, the electronic device 1000 can be implemented as a smart phone. However, the electronic device 1000 is not limited thereto. In an embodiment, for example, the electronic device 1000 can be implemented as a cellular phone, a video phone, a smart board, a smart watch, a tablet computer, a car navigation system, a computer monitor, a notebook computer, or a head-mounted display (HMD) device.

[0367] The processor 1010 may perform various computing functions or various tasks. The processor 1010 may be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 1010 may be coupled to other components via an address bus, a control bus, a data bus, etc. In addition, the processor 1010 may be coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0368] The processor 1010 can output the input image data IMG and the input control signal CONT to Figure 1 drive controller 200.

[0369] The memory device 1020 may store data used for the operation of the electronic device 1000. In an embodiment, for example, the memory device 1020 may include at least one non-volatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, or a ferroelectric random access memory (FRAM) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, or a mobile DRAM device, etc.).

[0370] The storage device 1030 may include a solid-state drive (SSD), a hard disk drive (HDD), or a CD-ROM device. The I / O device 1040 may include an input device such as a keyboard, a keypad, a mouse device, a touchpad, or a touch screen, and an output device such as a printer or a speaker. In some embodiments, a display device 1060 may be included in the I / O device 1040. The power supply 1050 may provide power for the operation of the electronic device 1000. The display device 1060 may be coupled to other components via a bus or other communication link.

[0371] Reference Figure 33 , a virtual reality (VR) display system may include a lens 10, a display device 20, and a housing 30. The display device 20 may be disposed adjacent to the lens 10. The housing 30 may house the lens 10 and the display device 20. Although Figure 33 , the lens 10 and the display device 20 are housed on the first side of the housing 30, but the present invention is not limited thereto. In another embodiment, for example, the lens 10 may be housed on the first side of the housing 30, and the display device 20 may be housed on the other side of the housing 30 opposite to the first side of the housing 30. In the embodiment where the lens 10 and the display device are housed on opposite sides of the housing 30, the housing 30 may have a transmissive portion to transmit light.

[0372] In an embodiment, for example, the VR display system can be a head-mounted display system worn on the user's head. Although not shown in the drawings, the VR display system can also include a headband to fix the VR display system to the user's head.

[0373] Optionally, the VR display system may have smart glasses designed in the shape of glasses.

[0374] In addition, the electronic device can be implemented as an augmented reality (AR) display system for supporting augmented reality. The AR display system can have a smartphone shape, a smart glasses shape, a head-mounted display shape, etc., but is not limited to these shapes.

[0375] In addition, the electronic device may be implemented as a mixed reality (MR) display system for supporting mixed reality. The MR display system may have a smartphone shape, a smart glasses shape, a head-mounted display shape, etc., but is not limited to these shapes.

[0376] According to the embodiments of the display device of the present invention as described above, the data swing range can be increased and the uniformity can be enhanced.

[0377] The present invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0378] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit or scope of the invention as defined by the following claims.

Claims

1. A pixel, wherein The pixels include: a first switching element including a control electrode connected to the first node, a first electrode connected to the second node, and a second electrode connected to the third node; a second switching element including a control electrode connected to the second node, a first electrode connected to a fifth node, and a second electrode connected to the second node; a third switching element comprising a control electrode receiving a write gate signal, a first electrode receiving a data voltage, and a second electrode connected to the first node; a first capacitor including a first electrode connected to the first node and a second electrode connected to a fourth node; a second capacitor connected to the fourth node; a fourth switching element receiving an initialization gate signal and connected to the fourth node; and The light emitting element emits light based on the driving current flowing to the light emitting element via the first switching element.

2. The pixel according to claim 1, wherein The fourth switching element includes: A control electrode receiving the initialization gate signal; a first electrode receiving a first power voltage; and The second electrode is connected to the fourth node.

3. The pixel according to claim 2, wherein: The second capacitor includes: a first electrode connected to the fourth node; and The second electrode is connected to the fifth node.

4. The pixel according to claim 2, wherein: The second capacitor includes: a first electrode connected to the fourth node; and A second electrode is connected to the second node.

5. The pixel according to claim 1, wherein The fourth switching element includes: A control electrode receiving the initialization gate signal; a first electrode connected to the fifth node; and The second electrode is connected to the fourth node.

6. The pixel according to claim 5, wherein The second capacitor includes: a first electrode connected to the fourth node; and The second electrode is connected to the fifth node.

7. The pixel according to claim 5, wherein The second capacitor includes: a first electrode connected to the fourth node; and A second electrode is connected to the second node.

8. The pixel according to claim 1, wherein The fourth switching element includes: A control electrode receiving the initialization gate signal; a first electrode connected to the second node; and The second electrode is connected to the fourth node.

9. The pixel according to claim 1, wherein The pixel further includes a fifth switching element including a control electrode receiving an emission signal, a first electrode receiving a first power voltage, and a second electrode connected to the fifth node.

10. The pixel according to claim 1, wherein The pixel further includes a sixth switching element including a control electrode receiving an initialization gate signal of the light emitting element, a first electrode receiving an initialization voltage, and a second electrode connected to the third node.

11. The pixel according to claim 10, wherein: The pixel further includes a fifth switching element, the fifth switching element including a control electrode receiving an emission signal, a first electrode receiving a first power voltage, and a second electrode connected to the fifth node. The first switching element, the second switching element, the third switching element, the fourth switching element, the fifth switching element and the sixth switching element are P-type transistors.

12. The pixel according to claim 11, wherein Breakdown voltages of the first switching element and the sixth switching element are greater than breakdown voltages of the second switching element, the third switching element, the fourth switching element, and the fifth switching element.

13. The pixel according to claim 10, wherein: The pixel further includes a fifth switching element, the fifth switching element including a control electrode receiving an emission signal, a first electrode receiving a first power voltage, and a second electrode connected to the fifth node. The first switching element, the second switching element, the third switching element, the fourth switching element and the fifth switching element are P-type transistors, and Wherein, the sixth switch element is an N-type transistor.

14. The pixel according to claim 10, wherein: The pixel further includes a fifth switching element, the fifth switching element including a control electrode receiving an emission signal, a first electrode receiving a first power voltage, and a second electrode connected to the fifth node. The initialization gate signal has an effective level in the first period, the write gate signal has an effective level in the first period, the emission signal has an effective level in the first period, the light emitting element initialization gate signal has an effective level in the first period, and the data voltage has a reference voltage in the first period. wherein the initialization gate signal has an inactive level in a second period after the first period, the write gate signal has the active level in the second period, the emission signal has an inactive level in the second period, the light emitting element initialization gate signal has the active level in the second period, and the data voltage has a current grayscale data voltage in the second period, and In which, the initialization gate signal has the non-valid level in the third time period after the second time period, the write gate signal has the non-valid level in the third time period, the emission signal has the valid level in the third time period, and the light-emitting element initialization gate signal has the non-valid level in the third time period.

15. The pixel according to claim 10, wherein: The pixel further includes a fifth switching element, the fifth switching element including a control electrode receiving an emission signal, a first electrode receiving a first power voltage, and a second electrode connected to the fifth node. wherein the initialization gate signal has an effective level in a first period, the write gate signal has an effective level in the first period, the emission signal has an effective level in the first period, and the light emitting element initialization gate signal has an effective level in the first period, wherein the initialization gate signal has an inactive level in a second period after the first period, the write gate signal has the active level in the second period, the emission signal has an inactive level in the second period, and the light emitting element initialization gate signal has the active level in the second period, and In which, the initialization gate signal has the non-active level in a third time period after the second time period, the write gate signal has the non-active level in the third time period, the emission signal changes from the non-active level to the active level at a first time point after the starting point of the third time period, and the light-emitting element initialization gate signal changes from the active level to the non-active level at a second time point after the starting point of the third time period.

16. The pixel according to claim 10, wherein: The pixel further includes a fifth switching element, the fifth switching element including a control electrode receiving an emission signal, a first electrode receiving a first power voltage, and a second electrode connected to the fifth node. wherein the initialization gate signal has an effective level in a first period, the write gate signal has an effective level in the first period, the emission signal has an effective level in the first period, the light emitting element initialization gate signal has an effective level in the first period, and the data voltage has a current grayscale data voltage in the first period, wherein the initialization gate signal has an inactive level in a second period after the first period, the write gate signal has the active level in the second period, the emission signal has an inactive level in the second period, the light emitting element initialization gate signal has the active level in the second period, and the data voltage has the current grayscale data voltage in the second period, and In which, the initialization gate signal has the non-valid level in the third time period after the second time period, the write gate signal has the non-valid level in the third time period, the emission signal has the valid level in the third time period, and the light-emitting element initialization gate signal has the non-valid level in the third time period.

17. The pixel according to claim 1, wherein When I d represents the current flowing through the light emitting element, μ p represents the mobility of the first switching element, C ox represents the capacitance of the first switching element, W / L represents the ratio of the width to the length of the channel of the first switching element, VDD represents the first power voltage, V dsat2 represents the saturation voltage of the second switching element, V th2 represents the threshold voltage of the second switching element, C1 represents the capacitance of the first capacitor, C2 represents the capacitance of the second capacitor, V DATA Indicates the data voltage, V REF Indicates the reference voltage, V th1 represents the threshold voltage of the first switching element, g m represents the transconductance of the first switching element, and R dio When represents the resistance of the second switching element, it satisfies:

18. The pixel according to claim 1, wherein The pixel further includes a seventh switching element including a control electrode receiving a second initialization gate signal, a first electrode receiving a reference voltage, and a second electrode connected to the first node.

19. The pixel according to claim 18, wherein The pixel further comprises: a fifth switching element including a control electrode receiving a transmission signal, a first electrode receiving a first power voltage, and a second electrode connected to the fifth node; and a sixth switching element, comprising a control electrode receiving an initialization gate signal of the light emitting element, a first electrode receiving an initialization voltage, and a second electrode connected to the third node; The initialization gate signal has an effective level in the first period, the second initialization gate signal has an effective level in the first period, the write gate signal has an effective level in the first period, the emission signal has an effective level in the first period, the light emitting element initialization gate signal has an effective level in the first period, and the data voltage has the reference voltage in the first period. wherein the initialization gate signal has an inactive level in a second period after the first period, the second initialization gate signal has an inactive level in the second period, the write gate signal has the active level in the second period, the emission signal has an inactive level in the second period, the light emitting element initialization gate signal has the active level in the second period, and the data voltage has a current grayscale data voltage in the second period, and In which, the initialization gate signal has the non-valid level in the third time period after the second time period, the second initialization gate signal has the non-valid level in the third time period, the write gate signal has the non-valid level in the third time period, the emission signal has the valid level in the third time period, and the light-emitting element initialization gate signal has the non-valid level in the third time period.

20. A display device, wherein: The display device comprises: a display panel, including pixels; a gate driver, outputting a gate signal to the pixel; and a data driver, outputting a data voltage to the pixel, The pixels include: a first switching element including a control electrode connected to the first node, a first electrode connected to the second node, and a second electrode connected to the third node; a second switching element including a control electrode connected to the second node, a first electrode connected to a fifth node, and a second electrode connected to the second node; a third switching element comprising a control electrode receiving a write gate signal, a first electrode receiving the data voltage, and a second electrode connected to the first node; a first capacitor including a first electrode connected to the first node and a second electrode connected to a fourth node; a second capacitor connected to the fourth node; a fourth switching element receiving an initialization gate signal and connected to the fourth node; and The light emitting element emits light based on the driving current flowing to the light emitting element via the first switching element.

21. An electronic device, wherein: The electronic device comprises: a display panel, including pixels; A gate driver, configured to output a gate signal to the pixel; a data driver, outputting a data voltage to the pixel; a driving controller to control the gate driver and the data driver; and Processor, output input image data and input control signal, The pixels include: a first switching element including a control electrode connected to the first node, a first electrode connected to the second node, and a second electrode connected to the third node; a second switching element including a control electrode connected to the second node, a first electrode connected to a fifth node, and a second electrode connected to the second node; a third switching element comprising a control electrode receiving a write gate signal, a first electrode receiving the data voltage, and a second electrode connected to the first node; a first capacitor including a first electrode connected to the first node and a second electrode connected to a fourth node; a second capacitor connected to the fourth node; a fourth switching element receiving an initialization gate signal and connected to the fourth node; and The light emitting element emits light based on the driving current flowing to the light emitting element via the first switching element.

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