Pixel, display device and electronic device

Abstract

The invention relates to a pixel, a display device, and an electronic device. A pixel of a light emitting display device includes: a first transistor including a gate coupled to a gate node, a first terminal, and a second terminal; a second transistor including a gate electrode receiving a gate write signal, a first terminal coupled to the data line, and a second terminal coupled to the first terminal of the first transistor; a fourth transistor including a gate receiving a gate initialization signal, a first terminal coupled to a line of an initialization voltage, and a second terminal coupled to an anode of the light emitting diode; and a sixth transistor including a gate receiving a second transmit signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the anode of the light emitting diode. A frequency of the gate write signal is different from a frequency of at least one of the second transmit signal and the gate initialization signal.

Description

[0001] This application is a divisional application of the patent application with application number 202110284987.4 filed on March 17, 2021 and titled “Luminous display device and its pixels”. Technical Field

[0002] The present inventive concept relates to display devices, and more particularly, to a light-emitting display device and a pixel thereof. Background Art

[0003] A display device such as an organic light emitting diode (OLED) display device can display images at a constant frame rate (or constant frame frequency) of approximately 60 Hz or higher. However, the frame rate of the rendering process of providing frame data to the OLED display device by a host processor (e.g., a graphics processing unit (GPU) and / or a graphics card) may be different from the frame rate (or refresh rate) of the OLED display device. Specifically, when the host processor provides frame data for game images (game images) or the like that requires complex rendering to the OLED display device, the frame rate mismatch may be exacerbated, and in the case where a boundary line is caused by a frame rate mismatch in the image of the OLED display device, a tearing phenomenon may occur.

[0004] To prevent or reduce tearing, a variable frame mode (e.g., free sync, G-sync, etc.) can be used, wherein the host processor provides frame data to the OLED display device at a variable frame rate (or variable frame frequency) by varying the length (or duration) of the blank period in each frame period. OLED display devices supporting the variable frame mode can display images in synchronization with the variable frame rate, thereby reducing or preventing tearing.

[0005] However, in an OLED display device operating in a variable frame mode, even if input image data represents a constant grayscale, the brightness of the OLED display device may not remain constant as the time length of a blank period changes. Summary of the Invention

[0006] Example embodiments provide pixels of a light emitting display device having substantially constant brightness even if a driving frequency changes.

[0007] Exemplary embodiments provide an organic light emitting diode (OLED) display device capable of having substantially constant brightness even if a driving frequency is changed.

[0008] According to an exemplary embodiment, a pixel of a light-emitting display device is provided, the pixel including: a capacitor having a first electrode coupled to a line of a first power supply voltage and a second electrode coupled to a gate node; a first transistor having a first terminal, a second terminal, and a gate coupled to the gate node; a second transistor having a gate for receiving a gate write signal, a first terminal coupled to a data line, and a second terminal coupled to the first terminal of the first transistor; a third transistor having a gate for receiving a scan signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the gate node; a fourth transistor having a gate for receiving a gate initialization signal, a first terminal coupled to a line of an initialization voltage, and a second terminal coupled to an anode of a light-emitting diode; a fifth transistor having a gate for receiving a first emission signal, a first terminal coupled to a line of the first power supply voltage, and a second terminal coupled to the first terminal of the first transistor; a sixth transistor having a gate for receiving a second emission signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the anode of the light-emitting diode; and a light-emitting diode having an anode and a cathode coupled to a line of a second power supply voltage. The scan signal and the gate write signal are provided at a first frequency, and the first emission signal, the second emission signal, and the gate initialization signal are provided at a second frequency higher than the first frequency.

[0009] In exemplary embodiments, the first transistor, the second transistor, the fourth transistor, and the fifth transistor may be P-type metal oxide semiconductor (PMOS) transistors, and the third transistor and the sixth transistor may be N-type metal oxide semiconductor (NMOS) transistors.

[0010] In exemplary embodiments, the first transistor, the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor may be PMOS transistors, and the third transistor may be an NMOS transistor.

[0011] In an exemplary embodiment, the second frequency may be a fixed frequency, and the first frequency may be a variable frequency.

[0012] In an exemplary embodiment, the light emitting diode is an organic light emitting diode (OLED), the light emitting display device is an OLED display device, the second frequency may correspond to twice the maximum frequency of the variable input frame frequency of the OLED display device, and the first frequency may correspond to the second frequency divided by N, where N is an integer greater than 1 and less than or equal to the maximum frequency.

[0013] In an exemplary embodiment, the light emitting diode is an organic light emitting diode (OLED), the light emitting display device is an OLED display device, and the frame period of the OLED display device may include: a gate and anode initialization period in which the gate node and the anode are initialized; a data writing period in which the data voltage of the data line is written to the capacitor; a first bias period in which a bias is applied to the first transistor; a first emission period in which the organic light emitting diode emits light; an anode initialization period in which the anode is initialized; a second bias period in which a bias is applied to the first transistor; and a second emission period in which the organic light emitting diode emits light.

[0014] In an exemplary embodiment, during the gate and anode initialization period, the first emission signal may have a cut-off level, the second emission signal may have a cut-off level, the gate initialization signal may have a cut-off level, the scan signal may have a cut-off level, the gate write signal may have a cut-off level, the third transistor, the fourth transistor, and the sixth transistor may be turned on, the initialization voltage may be applied to the anode through the fourth transistor, and the initialization voltage may be applied to the gate node through the fourth transistor, the sixth transistor, and the third transistor.

[0015] In an exemplary embodiment, in a data write period, the first emission signal may have an off level, the second emission signal may have an off level, the gate initialization signal may have an off level, the scan signal may have an on level, the gate write signal may have an on level, the second transistor and the third transistor may be turned on, the third transistor may be diode-connected to the first transistor, and the data voltage may be applied to the second electrode of the capacitor through the second transistor and the diode-connected first transistor.

[0016] In an exemplary embodiment, in the first bias period, the first emission signal may have an on-level, the second emission signal may have an off-level, the gate initialization signal may have an off-level, the scan signal may have an off-level, the gate write signal may have an off-level, the fifth transistor may be turned on, and the first power supply voltage may be applied to the first terminal of the first transistor through the fifth transistor.

[0017] In an exemplary embodiment, in each of the first emission period and the second emission period, the first emission signal may have an on-level, the second emission signal may have an on-level, the gate initialization signal may have an off-level, the scan signal may have an off-level, the gate write signal may have an off-level, the fifth transistor and the sixth transistor may be turned on, and the driving current generated by the first transistor may be provided to the organic light emitting diode.

[0018] In an exemplary embodiment, in an anode initialization period, the first emission signal may have an off level, the second emission signal may have an on level, the gate initialization signal may have an on level, the scan signal may have an off level, the gate write signal may have an off level, the fourth transistor and the sixth transistor may be turned on, and the initialization voltage may be applied to the anode through the fourth transistor.

[0019] In an exemplary embodiment, in the second bias period, the first emission signal may have an on-level, the second emission signal may have an off-level, the gate initialization signal may have an off-level, the scan signal may have an off-level, the gate write signal may have an off-level, the fifth transistor may be turned on, and the first power supply voltage may be applied to the first terminal of the first transistor through the fifth transistor.

[0020] According to an exemplary embodiment, an OLED display device is provided, including: a display panel having a plurality of pixels; a scan driver configured to provide a scan signal, a gate write signal, and a gate initialization signal to the plurality of pixels; an emission driver configured to provide a first emission signal and a second emission signal to the plurality of pixels; and a controller configured to control the scan driver and the emission driver. Each of the plurality of pixels includes: a capacitor having a first electrode coupled to a line of a first power supply voltage and a second electrode coupled to a gate node; a first transistor having a first terminal, a second terminal, and a gate coupled to the gate node; a second transistor having a gate for receiving a gate write signal, a first terminal coupled to a data line, and a second terminal coupled to the first terminal of the first transistor; a third transistor having a gate for receiving a scan signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the gate node; a fourth transistor having a gate for receiving a gate initialization signal, a first terminal coupled to a line of an initialization voltage, and a second terminal coupled to an anode of an organic light emitting diode; a fifth transistor having a gate for receiving a first emission signal, a first terminal coupled to a line of the first power supply voltage, and a second terminal coupled to the first terminal of the first transistor; a sixth transistor having a gate for receiving a second emission signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the anode of the organic light emitting diode; and an organic light emitting diode having an anode and a cathode coupled to a line of a second power supply voltage. The scan driver provides a scan signal and a gate write signal to the plurality of pixels at a first frequency and provides a gate initialization signal to the plurality of pixels at a second frequency higher than the first frequency. The emission driver provides a first emission signal and a second emission signal to the plurality of pixels at a second frequency.

[0021] In an exemplary embodiment, the OLED display device further includes: a data driver configured to provide a data voltage to a plurality of pixels. The controller may control the data driver to provide a scan start pulse and a gate write start pulse to the scan driver at a first frequency so that the scan signal and the gate write signal are provided at the first frequency; to provide a gate initialization start pulse to the scan driver at a second frequency so that the gate initialization signal is provided at the second frequency; and to provide a first emission start pulse and a second emission start pulse to the emission driver at the second frequency so that the first emission signal and the second emission signal are provided at the second frequency.

[0022] In an exemplary embodiment, the controller may provide one scan start pulse, one gate write start pulse, and at least two gate initialization start pulses to the scan driver, and may provide at least two first emission start pulses and at least two second emission start pulses to the emission driver in each frame period.

[0023] In an exemplary embodiment, the second frequency may be a fixed frequency, and the first frequency may be a variable frequency.

[0024] In an exemplary embodiment, the controller may receive input image data from an external host processor at a variable input frame frequency, the second frequency may correspond to twice a maximum frequency of the variable input frame frequency, and the first frequency may correspond to the second frequency divided by N, where N is an integer greater than 1 and less than or equal to the maximum frequency.

[0025] In exemplary embodiments, the first transistor, the second transistor, the fourth transistor, and the fifth transistor may be PMOS transistors, and the third transistor and the sixth transistor may be NMOS transistors.

[0026] In exemplary embodiments, the first transistor, the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor may be PMOS transistors, and the third transistor may be an NMOS transistor.

[0027] In an exemplary embodiment, a frame period of the OLED display device may include: a gate and anode initialization period in which the gate node and the anode are initialized; a data writing period in which the data voltage of the data line is written to the capacitor; a first bias period in which a bias is applied to the first transistor; a first emission period in which the organic light emitting diode emits light; an anode initialization period in which the anode is initialized; a second bias period in which a bias is applied to the first transistor; and a second emission period in which the organic light emitting diode emits light.

[0028] According to an exemplary embodiment, a display device includes: a display panel having a plurality of pixels; a scan driver configured to provide a scan signal to the plurality of pixels; and an emission driver configured to provide an emission signal to the plurality of pixels; wherein each of the plurality of pixels includes: a first transistor including a first terminal, a second terminal, and a gate coupled to a capacitor; a second transistor including a gate coupled to the scan driver, a first terminal coupled to a data line, and a second terminal coupled to the first terminal of the first transistor; a third transistor including a gate coupled to the scan driver, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the gate of the first transistor; a fifth transistor including a gate coupled to the emission driver, a first terminal coupled to a line of a first power supply voltage, and a second terminal coupled to the first terminal of the first transistor; and a sixth transistor including a first terminal coupled to the gate of the emission driver, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the first terminal of the emission device, wherein the scan driver provides a signal to the plurality of pixels at a first frequency; and wherein the emission driver provides a signal to the plurality of pixels at a second frequency greater than the first frequency.

[0029] In an exemplary embodiment, the display device may include a fourth transistor including a gate receiving a signal at a second frequency, a first terminal coupled to a line of an initialization voltage, and a second terminal coupled to the first terminal of the emission device.

[0030] In an exemplary embodiment, the first transistor, the second transistor, the fourth transistor, and the fifth transistor are PMOS transistors, and at least one of the third transistor and the sixth transistor is an NMOS transistor.

[0031] In an exemplary embodiment, the second frequency is a fixed frequency and the first frequency is a variable frequency.

[0032] In an exemplary embodiment, the emitting device is an organic light emitting diode (OLED), and the second frequency corresponds to a non-zero multiple of the first frequency.

[0033] As described above, in a pixel of an OLED display device and an OLED display device according to an exemplary embodiment, the pixel may include: a capacitor; a first transistor; a second transistor having a gate receiving a gate write signal; a third transistor having a gate receiving a scan signal; a fourth transistor having a gate receiving a gate initialization signal; a fifth transistor having a gate receiving a first emission signal; a sixth transistor having a gate receiving a second emission signal; and an OLED. The scan signal and the gate write signal may be provided at a first frequency, and the first emission signal, the second emission signal, and the gate initialization signal may be provided at a second frequency higher than the first frequency. Therefore, in a pixel according to an exemplary embodiment, a bias may be applied to the first transistor at a (constant) second frequency, and thus, even if the first frequency (e.g., the drive frequency or the display scan frequency) changes, an image may be displayed at substantially constant brightness at the same grayscale level. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Illustrative, non-limiting exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0035] Figure 1 is a circuit diagram illustrating a pixel of an organic light emitting diode (OLED) display device according to an exemplary embodiment;

[0036] Figure 2 is a diagram illustrating an example of driving characteristics of a first transistor;

[0037] Figure 3 is a diagram illustrating an example of luminance of a display panel driven at different driving frequencies;

[0038] Figure 4 is a timing diagram for describing an example of an operation of a pixel according to an exemplary embodiment;

[0039] Figure 5 is a circuit diagram for describing an example of the operation of a pixel in a gate and anode initialization period;

[0040] Figure 6 is a circuit diagram for describing an example of the operation of a pixel in a data writing period;

[0041] Figure 7 is a circuit diagram for describing an example of an operation of a pixel in a first bias period or a second bias period;

[0042] Figure 8 is a circuit diagram for describing an example of an operation of a pixel in a first emission period or a second emission period;

[0043] Figure 9is a circuit diagram for describing an example of the operation of a pixel in an anode initialization period;

[0044] Figure 10 is a timing diagram for describing another example of the operation of a pixel according to an exemplary embodiment;

[0045] Figure 11 is a circuit diagram illustrating a pixel of an OLED display device according to an exemplary embodiment;

[0046] Figure 12 is a timing diagram for describing an example of an operation of a pixel according to an exemplary embodiment;

[0047] Figure 13 is a block diagram illustrating an OLED display device according to an exemplary embodiment;

[0048] Figure 14 is a timing diagram for describing an example of input image data provided to an OLED display device according to an exemplary embodiment;

[0049] Figure 15 is a diagram for describing an example of a display scanning operation performed at a variable frequency and a self-scanning operation performed at a fixed frequency;

[0050] Figure 16 is a timing diagram for describing an example of operation of an OLED display device in which a driving frequency is changed according to an exemplary embodiment; and

[0051] Figure 17 is a block diagram illustrating an electronic device including an OLED display device according to an exemplary embodiment. DETAILED DESCRIPTION

[0052] Hereinafter, embodiments of the inventive concept will be explained in detail with reference to the accompanying drawings.

[0053] Figure 1 illustrates a pixel of an organic light emitting diode (OLED) display device according to an exemplary embodiment, Figure 2 An example of driving characteristics of the first transistor is illustrated, and Figure 3 Examples of the brightness of display panels driven at different driving frequencies are shown.

[0054] Reference Figure 1 , a pixel PX according to an exemplary embodiment may include a capacitor CST, a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , and an organic light emitting diode EL.

[0055] Although an OLED emitting device is shown and described, it should be understood that alternative embodiments may employ alternative emitting devices in place of and / or in addition to the OLED emitting device, such as, for example, an inorganic light emitting diode emitting device. The exemplary embodiments provided herein are provided for ease of understanding and are not intended to be limiting.

[0056] The capacitor CST can store a data voltage transmitted through the second transistor T2 and the first transistor T1 diode-connected by the third transistor T3. For example, the capacitor CST can be referred to as a storage capacitor for storing the data voltage. In an exemplary embodiment, the capacitor CST may include a first electrode coupled to a line of the first power supply voltage ELVDD and a second electrode coupled to the gate node NG.

[0057] The first transistor T1 may generate a driving current based on a voltage of the gate node NG or a voltage of the second electrode of the capacitor CST. For example, the first transistor T1 may be referred to as a driving transistor for generating a driving current. In an exemplary embodiment, the first transistor T1 may include a gate coupled to the gate node NG, a first terminal coupled to the second transistor T2 and the fifth transistor T5, and a second terminal coupled to the third transistor T3 and the sixth transistor T6.

[0058] The second transistor T2 can transmit the data voltage of the data line DL to the first terminal of the first transistor T1 in response to the gate write signal GW. For example, the second transistor T2 can be referred to as a switching transistor for transmitting the data voltage of the data line DL. In an exemplary embodiment, the second transistor T2 may include a gate for receiving the gate write signal GW, a first terminal coupled to the data line DL, and a second terminal coupled to the first terminal of the first transistor T1.

[0059] The third transistor T3 can operate as a diode-connected transistor (such as a metal oxide semiconductor field effect transistor (MOSFET) in a saturation region) in response to the scan signal SCAN, and diode-connect the first transistor T1. For example, the third transistor T3 can be referred to as a compensation transistor for compensating for the threshold voltage of the first transistor T1. In an exemplary embodiment, the third transistor T3 may include a gate for receiving the scan signal SCAN, a first terminal coupled to the second terminal of the first transistor T1, and a second terminal coupled to the gate node NG.

[0060] The fourth transistor T4 may apply the initialization voltage VINT to the anode of the organic light emitting diode EL in response to the gate initialization signal GI. For example, the fourth transistor T4 may be referred to as an initialization transistor for initializing the anode and / or the gate node NG. In an exemplary embodiment, the fourth transistor T4 may include a gate for receiving the gate initialization signal GI, a first terminal coupled to a line of the initialization voltage VINT, and a second terminal coupled to the anode of the organic light emitting diode EL.

[0061] The fifth transistor T5 can connect the line of the first power supply voltage ELVDD to the first terminal of the first transistor T1 in response to the first emission signal EM1. For example, the fifth transistor T5 can be referred to as a first emission transistor, and is configured to generate a current path from the line of the first power supply voltage ELVDD to the line of the second power supply voltage ELVSS. In an exemplary embodiment, the fifth transistor T5 can include a gate that receives the first emission signal EM1, a first terminal coupled to the line of the first power supply voltage ELVDD, and a second terminal coupled to the first terminal of the first transistor T1.

[0062] The sixth transistor T6 can connect the second terminal of the first transistor T1 to the line of the second power supply voltage ELVSS in response to the second emission signal EM2. For example, the sixth transistor T6 can be referred to as a second emission transistor, and is configured to generate a current path from the line of the first power supply voltage ELVDD to the line of the second power supply voltage ELVSS. In an exemplary embodiment, the sixth transistor T6 may include a gate that receives the second emission signal EM2, a first terminal coupled to the second terminal of the first transistor T1, and a second terminal coupled to the anode of the organic light emitting diode EL.

[0063] When the fifth transistor T5 and the sixth transistor T6 are turned on, the organic light emitting diode EL may emit light based on the driving current generated by the first transistor T1. In an exemplary embodiment, the organic light emitting diode EL may include an anode coupled to the second terminal of the sixth transistor T6 and a cathode coupled to a line of the second power supply voltage ELVSS.

[0064] In an OLED display device that supports a variable frame mode (e.g., a free sync mode, a G sync mode, a Q sync mode, etc.) in which input image data is provided at a variable input frame frequency (or a variable frame rate), the driving frequency of a display panel including a plurality of pixels PX or the display scanning frequency (or display refresh rate) at which data voltages are written to the plurality of pixels PX can be changed according to the variable input frame frequency, and the time length of each frame period can be changed according to the driving frequency (or display scanning frequency). In the case where the driving frequency of the display panel is changed, even if the input image data represents the same grayscale level, as the time length of each frame period increases, the brightness of the pixel PX or the display panel (especially at a high grayscale level) may be reduced through the leakage current of the first transistor T1 to the sixth transistor T6 of the pixel PX, or specifically through the leakage current of the third transistor T3 and the sixth transistor T6 directly or indirectly connected to the capacitor CST. For example, as Figure 3 As shown in FIG, if the driving frequency of the display panel is changed from about 120 Hz to about 60 Hz, the time length of each frame period may be doubled. In this case, even if the input image data represents the same 255 grayscale levels 255G, the brightness 210 of the display panel driven at about 120 Hz and the brightness 220 of the display panel driven at about 60 Hz may have a brightness difference 230. That is, the brightness 220 of the display panel driven at about 60 Hz, in which the time length of each frame period is increased, may be reduced compared to the brightness 210 of the display panel driven at about 120 Hz.

[0065] However, in Figure 1 In the pixel PX of the OLED display device according to the exemplary embodiment illustrated in FIG, the first transistor T1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 can be implemented using P-type metal oxide semiconductor (PMOS) transistors, and the third transistor T3 and the sixth transistor T6 can be implemented using N-type metal oxide semiconductor (NMOS) transistors with relatively low leakage current. In this case, since the third transistor T3 and the sixth transistor T6 directly or indirectly connected to the capacitor CST are implemented using NMOS transistors, the leakage current from the capacitor CST through the third transistor T3 and the sixth transistor T6 can be reduced. Therefore, even if the driving frequency or display scanning frequency of the display panel changes, the pixel PX or the display panel can display an image with substantially constant brightness at the same grayscale. Therefore, the pixel PX according to the exemplary embodiment can be suitable for an OLED display device that supports a variable frame mode in which the driving frequency or display scanning frequency of the display panel changes.

[0066] However, even if the third transistor T3 and the sixth transistor T6 are implemented using NMOS transistors, in the case where the driving frequency of the display panel changes, it is possible to change the driving characteristics of the first transistor T1 (i.e., the driving transistor), and therefore, as the time length of each frame period increases, the brightness of the pixel PX or the display panel (especially at a low gray level) can be increased at the same gray level. For example, Figure 2 As illustrated in , when a display scanning operation of writing a data voltage to a pixel PX is performed in each frame period, a bias (e.g., a turn-on bias) may be applied to the first transistor T1, and the first transistor T1 may have a first driving characteristic 110 of a drain-source current IDS according to a gate-source voltage VGS initialized by the bias. Thereafter, until the bias is applied to the first transistor T1 again in the next frame period, the driving characteristic of the first transistor T1 may gradually change from the first driving characteristic 110 to the second driving characteristic 130. Due to the change in the driving characteristic of the first transistor T1, the brightness of the pixel PX or the display panel may change according to the driving frequency of the display panel. For example, as Figure 3 As illustrated in FIG, even if the input image data represents the same 11 grayscale levels 11G, the luminance 260 of the display panel driven at approximately 120 Hz and the luminance 270 of the display panel driven at approximately 60 Hz may have a luminance difference 280. That is, the luminance 270 of the display panel driven at approximately 60 Hz, in which the time length of each frame period is increased, may be increased compared to the luminance 260 of the display panel driven at approximately 120 Hz. It should be understood that this is the opposite of the effect previously described for the higher grayscale level 255G, where the luminance 220 of the display panel driven at approximately 60 Hz may be reduced rather than increased compared to the luminance 210 of the display panel driven at approximately 120 Hz.

[0067] However, in an OLED display device according to an exemplary embodiment, a display scan operation for writing a data voltage to a plurality of pixels PX may be performed once during each frame period, and a self-scan operation for applying a bias to the first transistor T1 of the plurality of pixels PX may be performed two or more times. In an exemplary embodiment, a display scan operation and a self-scan operation may be performed substantially simultaneously during each frame period, and then one or more self-scan operations may be additionally performed. For example, when the display scan operation and the self-scan operation are performed substantially simultaneously, the gate node NG and the anode of the organic light emitting diode EL may be initialized, the data voltage may be written to the capacitor CST, and a bias may be applied to the first transistor T1. Further, when the self-scan operation is additionally performed, the anode of the organic light emitting diode EL may be initialized, and a bias may be applied to the first transistor T1.

[0068] To perform one display scan operation and two or more self-scan operations, the scan signal SCAN and the gate write signal GW may be provided to each pixel PX at a first frequency FF1, and the first emission signal EM1, the second emission signal EM2, and the gate initialization signal GI may be provided to each pixel PX at a second frequency FF2 higher than the first frequency FF1. For example, the first emission signal EM1, the second emission signal EM2, the gate initialization signal GI, the scan signal SCAN, and the gate write signal GW may be provided to each pixel PX so that the display scan operation and the self-scan operation can be performed substantially simultaneously, and then the first emission signal EM1, the second emission signal EM2, and the gate initialization signal GI may be provided to each pixel PX so that the self-scan operation can be additionally performed. Thus, the self-scan operation may be performed at a second frequency FF2 higher than the first frequency FF1, which is the frequency of the display scan operation or the display scan frequency.

[0069] In an exemplary embodiment, the first frequency FF1 may be a variable frequency, and the second frequency FF2 may be a fixed frequency. Thus, the first frequency FF1 may be changed according to the variable input frame frequency, but even if the variable input frame frequency is changed, the second frequency FF2 may be substantially constant. Therefore, since the second frequency FF2, which is the frequency of the self-scanning operation or the self-scanning frequency, is substantially constant even if the first frequency FF1, which is the frequency of the display scanning operation or the display scanning frequency, is changed, the bias may be applied to the first transistor T1 of each pixel PX at the substantially constant second frequency FF2, and thus, the first transistor T1 of each pixel PX may have a substantially constant driving characteristic at any driving frequency.

[0070] In an exemplary embodiment, the second frequency FF2 may correspond to twice the maximum frequency of the variable input frame frequency, and the first frequency FF1 may be determined as the second frequency FF2 divided by N, where N is an integer greater than 1 and less than or equal to the maximum frequency. For example, in the case where the variable input frame frequency is in the range of about 1 Hz to about 120 Hz, the second frequency FF2 may be determined to be about 240 Hz, which is twice the maximum frequency of about 120 Hz. Further, the first frequency FF1 may be determined in the current frame period corresponding to the variable input frame frequency among values ​​calculated by dividing the second frequency FF2 by N (e.g., about 120 Hz (when N is 2), about 80 Hz (when N is 3), about 60 Hz (when N is 4), ..., about 1 Hz (when N is 240), etc.).

[0071] As described above, in the pixel PX according to the exemplary embodiment, since the third transistor T3 and the sixth transistor T6, which are directly or indirectly connected to the capacitor CST, are implemented using NMOS transistors, leakage current from the capacitor CST through the third transistor T3 and the sixth transistor T6 can be reduced. Furthermore, in the OLED display device including the pixel PX according to the exemplary embodiment, the frequency of the self-scan operation of the first transistor T1 that applies a bias to each pixel PX, or the second frequency FF2, can be a fixed frequency higher than the first frequency FF1. Therefore, even if the driving frequency or display scanning frequency of the display panel changes, the pixel PX and the OLED display device according to the exemplary embodiment can display an image with substantially constant brightness at the same grayscale.

[0072] In an alternative embodiment, the first to fifth transistors T1, T2, T3', T4, and T5 may be implemented using PMOS transistors, and the sixth transistor T6 may be implemented using an NMOS transistor having relatively low leakage current. In this case, since the sixth transistor T6 indirectly connected to the capacitor CST is implemented using an NMOS transistor, leakage current from the capacitor CST through the sixth transistor T6 can be reduced.

[0073] Figure 4 illustrating an example of the operation of a pixel according to an exemplary embodiment, Figure 5 illustrates an example of the operation of a pixel in a gate and anode initialization period, Figure 6 illustrates an example of the operation of a pixel in a data writing period, Figure 7 illustrating an example of the operation of the pixel in the first bias period or the second bias period, Figure 8 illustrating an example of the operation of the pixel in the first emission period or the second emission period, Figure 9 illustrates an example of the operation of a pixel in an anode initialization period, and Figure 10 Another example of the operation of a pixel according to an exemplary embodiment is illustrated.

[0074] Reference Figure 1 and Figure 4 , a frame period of an OLED display device including a pixel PX according to an exemplary embodiment may include a gate and anode initialization period GAIP, a data write period DWP, a first bias period BP1, a first emission period EP1, at least one anode initialization period AIP, at least one second bias period BP2, and at least one second emission period EP2. Figure 4As illustrated in FIG, in a case where the first frequency FF1 as a driving frequency or a display scanning frequency is approximately 120 Hz and the second frequency FF2 as a self-scanning frequency is approximately 240 Hz, the frame period FP may include one anode initialization period AIP, one second bias period BP2, and one second emission period EP2. Further, the operation of the pixel PX in the gate and anode initialization period GAIP, the data write period DWP, and the first bias period BP1 may correspond to the display scanning operation and the self-scanning operation that are substantially simultaneously performed, and the operation of the pixel PX in the anode initialization period AIP and the second bias period BP2 may correspond to the self-scanning operation that is additionally performed.

[0075] In the gate and anode initialization period GAIP, the gate node NG and the anode of the organic light emitting diode EL may be initialized. Figure 4 As shown in FIG, in the gate and anode initialization period GAIP, the first emission signal EM1 may have an off level, the second emission signal EM2 may have an on level, the gate initialization signal GI may have an on level, the scan signal SCAN may have an on level, and the gate write signal GW may have an off level. Figure 4 As shown in FIG, at the start time point of the gate and anode initialization period GAIP, the first emission signal EM1, the scan signal SCAN and the gate initialization signal GI can be substantially simultaneously changed to the off level, the on level and the on level, respectively, but the time points at which the first emission signal EM1, the scan signal SCAN and the gate initialization signal GI are changed may not be limited thereto. For example, Figure 4 Unlike the example shown in FIG. 1 , the first emission signal EM1 may be changed to an off-level, the scan signal SCAN may be changed to an on-level, and then the gate initialization signal GI may be changed to an on-level. In an exemplary embodiment, the time length of the gate and anode initialization period GAIP may correspond to, but is not limited to, one horizontal time (1H time). Further, in an exemplary embodiment, one horizontal time of the OLED display device may be determined based on the maximum frequency of the variable input frame frequency.

[0076] In an exemplary embodiment, as Figure 1 and Figure 4As shown in FIG, the first emission signal EM1, the gate initialization signal GI, and the gate write signal GW may be active-low signals having a low level as a conduction level, and the second emission signal EM2 and the scan signal SCAN may be active-high signals having a high level as a conduction level. For example, the high level of the first emission signal EM1, the second emission signal EM2, the gate initialization signal GI, the scan signal SCAN, and the gate write signal GW may be, but is not limited to, approximately 7V, and the low level of the first emission signal EM1, the second emission signal EM2, the gate initialization signal GI, the scan signal SCAN, and the gate write signal GW may be, but is not limited to, approximately -8V.

[0077] like Figure 5 As shown in FIG. , during the gate and anode initialization period GAIP, the fifth transistor T5 may be turned off in response to the first emission signal EM1 having an off level, the sixth transistor T6 may be turned on in response to the second emission signal EM2 having an on level, the fourth transistor T4 may be turned on in response to the gate initialization signal GI having an on level, the third transistor T3 may be turned on in response to the scan signal SCAN having an on level, and the second transistor T2 may be turned off in response to the gate write signal GW having an off level. Therefore, during the gate and anode initialization period GAIP, the initialization voltage VINT may be applied to the anode of the organic light emitting diode EL via the fourth transistor T4, and thus, the voltage of the anode of the organic light emitting diode EL or the parasitic capacitor of the organic light emitting diode EL may be initialized. Furthermore, the initialization voltage VINT may be applied to the gate node NG via the fourth transistor T4, the sixth transistor T6, and the third transistor T3, and thus, the voltage of the gate node NG or the capacitor CST may be initialized.

[0078] In the data writing period DWP, the data voltage of the data line DL may be written into the capacitor CST. Figure 4 As shown in FIG, in the data write period DWP, the first emission signal EM1 may have an off level, the second emission signal EM2 may have an off level, the gate initialization signal GI may have an off level, the scan signal SCAN may have an on level, and the gate write signal GW may have an on level. Figure 4 As shown in FIG, at the start time point of the data write period DWP, the gate initialization signal GI, the second emission signal EM2, and the gate write signal GW can be substantially simultaneously changed to the off level, the off level, and the on level, respectively, but the time points at which the gate initialization signal GI, the second emission signal EM2, and the gate write signal GW change may not be limited thereto. For example, Figure 4Unlike the diagram shown in FIG, the gate initialization signal GI may be changed to an off level, then the second emission signal EM2 may be changed to an off level, and then the gate write signal GW may be changed to an on level. In an exemplary embodiment, the time length of the data write period DWP may correspond to, but is not limited to, one horizontal time (1H time).

[0079] like Figure 6 As shown in FIG, during the data write period DWP, the fifth transistor T5 may be turned off in response to the first emission signal EM1 having an off level, the sixth transistor T6 may be turned off in response to the second emission signal EM2 having an off level, the fourth transistor T4 may be turned off in response to the gate initialization signal GI having an off level, the third transistor T3 may be turned on in response to the scan signal SCAN having an on level, and the second transistor T2 may be turned on in response to the gate write signal GW having an on level. Therefore, during the data write period DWP, the third transistor T3 may be diode-connected to the first transistor T1, and the data voltage VDAT may be applied to the gate node NG or the second electrode of the capacitor CST through the second transistor T2 and the diode-connected first transistor T1. Since the data voltage VDAT is transmitted through the diode-connected first transistor T1, the second electrode of the capacitor CST or the gate node NG may have a voltage VDAT-VTH obtained by subtracting the threshold voltage VTH of the first transistor T1 from the data voltage VDAT.

[0080] In the first bias period BP1, a bias (eg, an on bias) may be applied to the first transistor T1. Figure 4 As shown in FIG, in the first bias period BP1, the first emission signal EM1 may have an on level, the second emission signal EM2 may have an off level, the gate initialization signal GI may have an off level, the scan signal SCAN may have an off level, and the gate write signal GW may have an off level. Figure 4 As shown in FIG, at the start time point of the first bias period BP1, the gate write signal GW, the scan signal SCAN and the first emission signal EM1 can be substantially changed to the off level, the off level and the on level respectively at the same time, but the time points at which the gate write signal GW, the scan signal SCAN and the first emission signal EM1 change are not limited thereto. For example, Figure 4 Unlike the example shown in FIG, the gate write signal GW may be changed to an off level, then the scan signal SCAN may be changed to an off level, and then the first emission signal EM1 may be changed to an on level. In an exemplary embodiment, the time length of the first bias period BP1 may be, but is not limited to, in a range from two horizontal times (2H time) to eight horizontal times (8H time).

[0081] like Figure 7 As shown in FIG, in the first bias period BP1, the fifth transistor T5 may be turned on in response to the first emission signal EM1 having a turn-on level, the sixth transistor T6 may be turned off in response to the second emission signal EM2 having a turn-off level, the fourth transistor T4 may be turned off in response to the gate initialization signal GI having a turn-off level, the third transistor T3 may be turned off in response to the scan signal SCAN having a turn-off level, and the second transistor T2 may be turned off in response to the gate write signal GW having a turn-off level. Therefore, in the first bias period BP1, the first power supply voltage ELVDD may be applied to the first terminal (e.g., source) of the first transistor T1 through the fifth transistor T5. Therefore, since the voltage of the gate node NG or the voltage VDAT-VTH in which the threshold voltage VTH is subtracted from the data voltage VDAT is applied to the gate of the first transistor T1 and the first power supply voltage ELVDD is applied to the first terminal (e.g., source) of the first transistor T1, a bias corresponding to the turn-on state or a turn-on bias using the first power supply voltage ELVDD may be applied to the first transistor T1.

[0082] In the first emission period EP1, the organic light emitting diode EL may emit light. Figure 4 As illustrated in FIG, in the first emission period EP1, the first emission signal EM1 may have an on level, the second emission signal EM2 may have an on level, the gate initialization signal GI may have an off level, the scan signal SCAN may have an off level, and the gate write signal GW may have an off level.

[0083] like Figure 8 As shown in FIG, in the first emission period EP1, the fifth transistor T5 may be turned on in response to the first emission signal EM1 having a turn-on level, the sixth transistor T6 may be turned on in response to the second emission signal EM2 having a turn-on level, the fourth transistor T4 may be turned off in response to the gate initialization signal GI having a turn-off level, the third transistor T3 may be turned off in response to the scan signal SCAN having a turn-off level, and the second transistor T2 may be turned off in response to the gate write signal GW having a turn-off level. Therefore, in the first emission period EP1, the first transistor T1 may generate a drive current corresponding to the voltage of the gate node NG or the voltage VDAT-VTH obtained by subtracting the threshold voltage VTH from the data voltage VDAT. The fifth transistor T5 and the sixth transistor T6 may form a current path from the line of the first power supply voltage ELVDD to the line of the second power supply voltage ELVSS. The drive current generated by the first transistor T1 may be provided to the organic light emitting diode EL. Therefore, the organic light emitting diode EL may emit light based on the drive current corresponding to the data voltage VDAT.

[0084] In the anode initialization period AIP, the anode of the organic light emitting diode EL may be initialized. Figure 4 As shown in FIG, in the anode initialization period AIP, the first emission signal EM1 may have an off level, the second emission signal EM2 may have an on level, the gate initialization signal GI may have an on level, the scan signal SCAN may have an off level, and the gate write signal GW may have an off level. During the first bias period BP1, the first emission period EP1, the anode initialization period AIP, the second bias period BP2, and the one second emission period EP2, the scan signal SCAN and the gate write signal GW may be maintained at an off level. Figure 4 As shown in FIG, at the start time point of the anode initialization period AIP, the first emission signal EM1 and the gate initialization signal GI can be changed to the off level and the on level respectively at substantially the same time, but the time points at which the first emission signal EM1 and the gate initialization signal GI are changed may not be limited thereto. Figure 4 Unlike illustrated in FIG, the first emission signal EM1 may be changed to a turn-off level, and then the gate initialization signal GI may be changed to a turn-on level.

[0085] like Figure 9 As shown in FIG. 1 , in the anode initialization period AIP, the fifth transistor T5 may be turned off in response to the first emission signal EM1 having an off level, the sixth transistor T6 may be turned on in response to the second emission signal EM2 having an on level, the fourth transistor T4 may be turned on in response to the gate initialization signal GI having an on level, the third transistor T3 may be turned off in response to the scan signal SCAN having an off level, and the second transistor T2 may be turned off in response to the gate write signal GW having an off level. Therefore, in the anode initialization period AIP, the initialization voltage VINT may be applied to the anode of the organic light emitting diode EL through the fourth transistor T4, and thus, the voltage of the anode of the organic light emitting diode EL or the parasitic capacitor of the organic light emitting diode EL may be initialized.

[0086] In the second bias period BP2, a bias (e.g., a turn-on bias) may be applied to the first transistor T1. In an exemplary embodiment, the length of the second bias period BP2 may be, but is not limited to, a range from two horizontal times (2H time) to eight horizontal times (8H time). The first emission signal EM1, the second emission signal EM2, the gate initialization signal GI, the scan signal SCAN, and the gate write signal GW in the second bias period BP2 may be substantially the same as the first emission signal EM1, the second emission signal EM2, the gate initialization signal GI, the scan signal SCAN, and the gate write signal GW in the first bias period BP1, and the operation of the pixel PX in the second bias period BP2 may be substantially the same as the operation of the pixel PX in the first bias period BP1. That is, the voltage of the gate node NG or the voltage VDAT-VTH in which the threshold voltage VTH is subtracted from the data voltage VDAT may be applied to the gate of the first transistor T1, and the first power supply voltage ELVDD may be applied to the first terminal (e.g., source) of the first transistor T1, and thus, a bias corresponding to an on-state or a turn-on bias using the first power supply voltage ELVDD may be applied to the first transistor T1. Therefore, even if the first frequency FF1 as the driving frequency or the display scanning frequency changes, the bias may be applied to the first transistor T1 at the second frequency FF2 as the self-scanning frequency.

[0087] In the second emission period EP2, the organic light emitting diode EL may emit light. The operation of the pixel PX in the second emission period EP2 may be substantially the same as the operation of the pixel PX in the first emission period EP1. That is, in the second emission period EP2, the organic light emitting diode EL may emit light based on the driving current corresponding to the data voltage VDAT.

[0088] In an exemplary embodiment, the second frequency FF2 can be determined as a fixed frequency (e.g., approximately 240 Hz) corresponding to twice the maximum frequency of the variable input frame frequency (e.g., approximately 120 Hz), and the first frequency FF1 can be determined as the second frequency FF2 divided by N based on the variable input frame frequency in each frame period, where N is an integer greater than 1 and less than or equal to the maximum frequency. Figure 4 The example in which N is 2 is shown, or the example in which the first frequency FF1 is determined to be approximately 120 Hz by dividing the second frequency FF2 of approximately 240 Hz by 2. Further, Figure 10 The example in which N is 3 or the example in which the first frequency FF1 is determined to be about 80 Hz by dividing the second frequency FF2 of about 240 Hz by 3 is shown. Figure 10As shown in FIG, in the case where the first frequency FF1 as a driving frequency or a display scanning frequency is about 80 Hz and the second frequency FF2 as a self-scanning frequency is about 240 Hz, the frame period FP may include two anode initialization periods AIP, two second bias periods BP2, and two second emission periods EP2. Figure 4 and Figure 10 As illustrated in FIG, even if the first frequency FF1 as a driving frequency or a display scanning frequency changes, a bias can be applied to the first transistor T1 of each pixel PX at a fixed or constant second frequency FF2, which is a self-scanning frequency in the first bias period BP1 and the second bias period BP2, and the OLED display device can display an image with substantially constant brightness at the same grayscale.

[0089] Figure 11 illustrates a pixel of an OLED display device according to an exemplary embodiment, and Figure 12 An example of an operation of a pixel according to an exemplary embodiment is illustrated.

[0090] Reference Figure 11 and Figure 12 According to an exemplary embodiment, a pixel PX' may include a capacitor CST, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6', and an organic light emitting diode EL. In addition, the sixth transistor T6' is implemented using a PMOS transistor. Figure 11 The pixel PX' can have Figure 1 The pixel PX has substantially the same configuration. Further, except that the second emission signal EM2 is an active low signal having a low level as a turn-on level, Figure 12 The signals EM1, GI, SCAN and GW provided to the pixel PX' as shown in FIG. Figure 4 The signals EM1, GI, SCAN, and GW provided to the pixel PX illustrated in FIG. 5 are substantially the same.

[0091] like Figure 11As shown in FIG, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6' can be implemented using PMOS transistors, and the third transistor T3 can be implemented using an NMOS transistor with relatively low leakage current. In this case, since the third transistor T3 directly connected to the capacitor CST is implemented using an NMOS transistor, the leakage current from the capacitor CST through the third transistor T3 can be reduced. Furthermore, in an OLED display device including a pixel PX' according to an exemplary embodiment, the frequency of the self-scanning operation of the first transistor T1 that applies a bias to each pixel PX', or the second frequency FF2, can be a fixed frequency higher than the first frequency FF1. Therefore, even if the driving frequency or display scanning frequency of the display panel changes, the pixel PX' and the OLED display device according to the exemplary embodiment can display an image with substantially constant brightness at the same grayscale.

[0092] Figure 13 illustrates an OLED display device according to an exemplary embodiment, Figure 14 illustrating an example of input image data provided to an OLED display device according to an exemplary embodiment, Figure 15 An example of a display scanning operation performed at a variable frequency and a self-scanning operation performed at a fixed frequency is illustrated, and Figure 16 An example of an operation of an OLED display device in which a driving frequency is changed according to an exemplary embodiment is illustrated.

[0093] Reference Figure 13 , the OLED display device 300 according to an exemplary embodiment may include a display panel 310 , a data driver 320 , a scan driver 330 , an emission driver 340 , and a controller 350 .

[0094] The display panel 310 may include a plurality of pixels PX. Each pixel PX of the display panel 310 may be Figure 1 Pixel PX, Figure 11 The pixel PX' or any other suitable pixel.

[0095] The data driver 320 may provide data voltages VDAT to a plurality of pixels PX based on output image data ODAT and a data control signal DCTRL received from the controller 350. In an exemplary embodiment, the data control signal DCTRL may include, but is not limited to, an output data enable signal, a horizontal start signal, and a load signal. The data driver 320 may receive frame data as output image data ODAT at a first frequency FF1, which is a driving frequency of the display panel 310, or at a display scanning frequency from the controller 350. In an exemplary embodiment, the data driver 320 and the controller 350 may be implemented using a single integrated circuit, which may be referred to as a timing controller embedded data driver (TED). In other exemplary embodiments, the data driver 320 and the controller 350 may be implemented using separate integrated circuits.

[0096] The scan driver 330 may provide a scan signal SCAN, a gate write signal GW, and a gate initialization signal GI to the plurality of pixels PX based on a scan control signal received from the controller 350. In an exemplary embodiment, the scan control signal may include a scan start pulse SCAN_SP, a gate write start pulse GW_SP, and a gate initialization start pulse GI_SP. The scan driver 330 may sequentially provide the scan signal SCAN to the plurality of pixels PX row by row in response to the scan start pulse SCAN_SP, may sequentially provide the gate write signal GW to the plurality of pixels PX row by row in response to the gate write start pulse GW_SP, and may sequentially provide the gate initialization signal GI to the plurality of pixels PX row by row in response to the gate initialization start pulse GI_SP. In an exemplary embodiment, the scan driver 330 may receive the scan start pulse SCAN_SP and the gate write start pulse GW_SP at a first frequency FF1, and may receive the gate initialization start pulse GI_SP at a second frequency FF2, which is a self-scan frequency. Furthermore, in an exemplary embodiment, the scan control signal may further include, but is not limited to, a scan clock signal, a gate write clock signal, and a gate initialization clock signal. In an exemplary embodiment, the scan driver 330 may be integrated or formed in a peripheral portion of the display panel 310. In other exemplary embodiments, the scan driver 330 may be implemented using one or more integrated circuits.

[0097] The emission driver 340 may provide first and second emission signals EM1 and EM2 to the plurality of pixels PX based on an emission control signal received from the controller 350. The emission control signal may include a first emission start pulse EM1_SP and a second emission start pulse EM2_SP. The emission driver 340 may sequentially provide the first emission signal EM1 to the plurality of pixels PX row by row in response to the first emission start pulse EM1_SP, and may sequentially provide the second emission signal EM2 to the plurality of pixels PX row by row in response to the second emission start pulse EM2_SP. In an exemplary embodiment, the emission driver 340 may receive the first and second emission start pulses EM1_SP and EM2_SP at a second frequency FF2. Furthermore, in an exemplary embodiment, the emission control signal may further include, but is not limited to, a first and second emission clock signal. In an exemplary embodiment, the emission driver 340 may be integrated or formed in a peripheral portion of the display panel 310. In other exemplary embodiments, the emission driver 340 may be implemented using one or more integrated circuits.

[0098] The controller 350 (e.g., a timing controller) may receive input image data IDAT and a control signal CTRL from an external host processor (e.g., a graphics processing unit (GPU), an application processor (AP), or a graphics card). In an exemplary embodiment, the input image data IDAT may be RGB image data including red image data, green image data, and blue image data. In an exemplary embodiment, the control signal CTRL may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, and the like. Based on the input image data IDAT and the control signal CTRL, the controller 350 may generate output image data ODAT, a data control signal DCTRL, a scan control signal, and an emission control signal. The controller 350 may control the operation of the data driver 320 by providing the output image data ODAT and the data control signal DCTRL to the data driver 320, control the operation of the scan driver 330 by providing the scan control signal to the scan driver 330, and control the operation of the emission driver 340 by providing the emission control signal to the emission driver 340.

[0099] According to an exemplary embodiment, an OLED display device 300 includes: a display panel 310 having a plurality of pixels PX; a scan driver 330 configured to provide a scan signal to the plurality of pixels; and an emission driver 340 configured to provide an emission signal to the plurality of pixels; wherein each of the plurality of pixels includes: a capacitor CST including a first electrode and a second electrode coupled to a line of a first power voltage ELVDD; a first transistor T1 including a first terminal, a second terminal, and a gate coupled to the second electrode of the capacitor CST; a second transistor T2 including a gate coupled to the scan driver, a first terminal coupled to a data line DL, and a second terminal coupled to the first terminal of the first transistor; and a capacitor CST including a first electrode and a second electrode coupled to a line of a first power voltage ELVDD. a scan driver, a first terminal coupled to the second terminal of the first transistor, and a third transistor T3 coupled to the second terminal of the gate of the first transistor; a fifth transistor T5 coupled to the gate of the emission driver, a first terminal coupled to the line of the first power supply voltage ELVDD, and a second terminal coupled to the first terminal of the first transistor; and a sixth transistor T6 coupled to the gate of the emission driver, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the first terminal of the emission device, wherein the scan driver provides a signal to the plurality of pixels PX at a first frequency FF1; wherein the emission driver provides a signal to the plurality of pixels PX at a second frequency FF2 greater than the first frequency FF1.

[0100] In an exemplary embodiment, an OLED display device may include a fourth transistor T4 including a gate that receives a signal at a second frequency FF2, a first terminal coupled to a line of an initialization voltage Vint, and a second terminal coupled to a first terminal of an emission device. The first transistor T1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 may be PMOS transistors, and at least one of the third transistor T3 and the sixth transistor T6 may be an NMOS transistor. The second frequency may be a fixed frequency, and the first frequency may be a variable frequency. The emission device may be an OLED, and the second frequency may correspond to a non-zero multiple of the first frequency.

[0101] The controller 350 of the OLED display device 300 according to an exemplary embodiment may receive input image data IDAT at a variable input frame frequency VIFF from a host processor in a variable frame mode (eg, free sync mode, G sync mode, Q sync mode, etc.). Figure 14As shown in FIG, the period of each of the renderings 410, 420, and 430 of the host processor may not be constant (especially in the case of rendering game image data), and in variable frame mode, the host processor may provide input image data IDAT or frame data FD1, FD2, FD3, and FD4 to the OLED display device 300 in synchronization with these irregular periods of rendering 410, 420, and 430, respectively. For example, in variable frame mode, each frame period FP1, FP2, and FP3 may include constant active periods AP1, AP2, and AP3 having a constant time length, and the host processor may provide frame data FD1, FD2, and FD3 to the OLED display device 300 at a variable input frame frequency VIFF by changing the time length of the variable blank periods BP1, BP2, and BP3 of the frame periods FP1, FP2, and FP3. For example, the variable input frame frequency VIFF may be changed in a range from about 1 Hz to about 120 Hz in each frame period FP1, FP2, and FP3.

[0102] In an exemplary embodiment, the second frequency FF2 as the self-scan frequency can be a fixed frequency (e.g., approximately 240 Hz) corresponding to twice the maximum frequency (e.g., approximately 120 Hz) of the variable input frame frequency VIFF. Further, the first frequency FF1 as the driving frequency or display scan frequency of the display panel 310 can be determined as the second frequency FF2 divided by N based on the variable input frame frequency VIFF in each frame period, where N is an integer greater than 1 and less than or equal to the maximum frequency. Therefore, the OLED display device 300 according to the exemplary embodiment can perform a display scan operation that writes a data voltage VDAT corresponding to the output image data ODAT to a plurality of pixels PX at the first frequency FF1 as a variable frequency, and can perform a self-scan operation that applies a bias to the drive transistors of the plurality of pixels PX at the second frequency FF2 as a fixed frequency. In an exemplary embodiment, in each frame period, the OLED display device 300 can substantially simultaneously perform one display scan operation and one self-scan operation, and can then additionally perform one or more self-scan operations.

[0103] For example, Figure 15 As shown in FIG, in the case where the maximum frequency of the variable input frame frequency VIFF is about 120 Hz, even if the variable input frame frequency VIFF changes, the OLED display device 300 can perform the self-scan operation at the fixed second frequency FF2 of about 240 Hz. Further, in the case where the variable input frame frequency VIFF is about 120 Hz, as shown in FIG. Figure 15As shown in FIG510, the OLED display device 300 can perform a display scanning operation at a first frequency FF1 of about 120 Hz. Therefore, in each frame period FP, a display scanning operation can be performed once, and a self-scanning operation can be performed twice. Further, in the case where the variable input frame frequency VIFF is about 80 Hz, as shown in FIG510, Figure 15 As shown in FIG520, the OLED display device 300 can perform a display scanning operation at a first frequency FF1 of about 80 Hz. Therefore, in each frame period FP, a display scanning operation can be performed once, and a self-scanning operation can be performed three times. Further, in the case where the variable input frame frequency VIFF is about 60 Hz, as shown in FIG521, Figure 15 As shown in FIG530, the OLED display device 300 can perform a display scanning operation at a first frequency FF1 of about 60 Hz. Therefore, in each frame period FP, a display scanning operation can be performed once, and a self-scanning operation can be performed four times. Further, in the case where the variable input frame frequency VIFF is about 48 Hz, as shown in FIG530, Figure 15 As shown in FIG540, the OLED display device 300 can perform a display scanning operation at a first frequency FF1 of about 48 Hz. Therefore, in each frame period FP, a display scanning operation can be performed once, and five self-scanning operations can be performed. Further, in the case where the variable input frame frequency VIFF is about 30 Hz, as shown in FIG540, Figure 15 As shown in FIG550, the OLED display device 300 can perform a display scanning operation at a first frequency FF1 of about 30 Hz. Therefore, in each frame period FP, a display scanning operation can be performed once, and eight self-scanning operations can be performed. Further, in the case where the variable input frame frequency VIFF is about 24 Hz, as shown in FIG55. Figure 15 As shown in FIG560, the OLED display device 300 may perform a display scanning operation at a first frequency FF1 of approximately 24 Hz. Therefore, in each frame period FP, the display scanning operation may be performed once, and the self-scanning operation may be performed ten times.

[0104] In order to perform a display scan operation at a variable first frequency FF1 and a self-scan operation at a second frequency FF2, the controller 350 may provide a scan start pulse SCAN_SP and a gate write start pulse GW_SP to the scan driver 330 at the first frequency FF1, may provide a gate initialization start pulse GI_SP to the scan driver 330 at the second frequency FF2, and may provide a first emission start pulse EM1_SP and a second emission start pulse EM2_SP to the emission driver 340 at the second frequency FF2. Furthermore, the time length of each frame period FP may correspond to the first frequency FF1. Therefore, in each frame period FP, the controller 350 may provide one scan start pulse SCAN_SP, one gate write start pulse GW_SP, and at least two gate initialization start pulses GI_SP to the scan driver 330, and may provide at least two first emission start pulses EM1_SP and at least two second emission start pulses EM2_SP to the emission driver 340.

[0105] For example, Figure 16As illustrated in FIG, in a case where the first frequency FF1 is approximately 120 Hz and the second frequency FF2 is approximately 240 Hz, in each frame period FP, the controller 350 may provide one scan start pulse SCAN_SP, one gate write start pulse GW_SP, and two gate initialization start pulses GI_SP to the scan driver 330, and may provide two first emission start pulses EM1_SP and two second emission start pulses EM2_SP to the emission driver 340. Therefore, in each frame period FP, the scan driver 330 can provide the scan signal SCAN to the multiple pixels PX at a first frequency FF1 of approximately 120 Hz in response to one scan start pulse SCAN_SP, so that the scan signal SCAN is provided to each pixel PX once, can provide the gate write signal GW to the multiple pixels PX at the first frequency FF1 of approximately 120 Hz in response to one gate write start pulse GW_SP, so that the gate write signal GW is provided to each pixel PX once, and can provide the gate initialization signal GI to the multiple pixels PX at a second frequency FF2 of approximately 240 Hz in response to two gate initialization start pulses GI_SP, so that the gate initialization signal GI is provided to each pixel PX twice. For example, the scan driver 330 may sequentially provide the gate initialization signal GI from the first row to the last row of the display panel 310 in response to the current gate initialization start pulse GI_SP, and at a time point when the scan driver 330 provides the gate initialization signal GI to the middle row of the display panel 310 in response to the current gate initialization start pulse GI_SP, the controller 350 may provide the next gate initialization start pulse GI_SP to the scan driver 330. Further, in each frame period FP, the emission driver 340 may provide the first emission signal EM1 to the plurality of pixels PX at a second frequency FF2 of approximately 240 Hz in response to two first emission start pulses EM1_SP, such that the first emission signal EM1 is provided to each pixel PX twice, and may provide the second emission signal EM2 to the plurality of pixels PX at a second frequency FF2 of approximately 240 Hz in response to two second emission start pulses EM2_SP, such that the second emission signal EM2 is provided to each pixel PX twice.For example, the emission driver 340 may sequentially provide the first emission signal EM1 and the second emission signal EM2 from the first row to the last row of the display panel 310 in response to the current first emission start pulse EM1_SP and the current second emission start pulse EM2_SP. When the emission driver 340 provides the first emission signal EM1 and the second emission signal EM2 to an intermediate row of the display panel 310 in response to the current first emission start pulse EM1_SP and the current second emission start pulse EM2_SP, the controller 350 may provide the next first emission start pulse EM1_SP and the next second emission start pulse EM2_SP to the emission driver 340. Furthermore, the controller 350 may provide frame data FD as output image data ODAT to the data driver 320 at a first frequency FF1 of approximately 120 Hz, so that one frame data FD is provided in each frame period FP. Therefore, a display scan operation may be performed at the first frequency FF1 of approximately 120 Hz, and a self-scan operation may be performed at the second frequency FF2 of approximately 240 Hz.

[0106] Further, if Figure 16As illustrated in FIG, in a case where the first frequency FF1 is approximately 60 Hz and the second frequency FF2 is approximately 240 Hz, in each frame period FP, the controller 350 may provide one scan start pulse SCAN_SP, one gate write start pulse GW_SP, and four gate initialization start pulses GI_SP to the scan driver 330, and may provide four first emission start pulses EM1_SP and four second emission start pulses EM2_SP to the emission driver 340. Therefore, in each frame period FP, the scan driver 330 can provide the scan signal SCAN to the multiple pixels PX at a first frequency FF1 of approximately 60 Hz in response to one scan start pulse SCAN_SP, so that the scan signal SCAN is provided to each pixel PX once, can provide the gate write signal GW to the multiple pixels PX at the first frequency FF1 of approximately 60 Hz in response to one gate write start pulse GW_SP, so that the gate write signal GW is provided to each pixel PX once, and can provide the gate initialization signal GI to the multiple pixels PX at a second frequency FF2 of approximately 240 Hz in response to four gate initialization start pulses GI_SP, so that the gate initialization signal GI is provided to each pixel PX four times. Furthermore, in each frame period FP, the emission driver 340 may provide the first emission signal EM1 to the plurality of pixels PX at a second frequency FF2 of approximately 240 Hz in response to four first emission start pulses EM1_SP, such that the first emission signal EM1 is provided to each pixel PX four times. Furthermore, in response to four second emission start pulses EM2_SP, the emission driver 340 may provide the second emission signal EM2 to the plurality of pixels PX at a second frequency FF2 of approximately 240 Hz, such that the second emission signal EM2 is provided to each pixel PX four times. Furthermore, the controller 350 may provide the frame data FD as the output image data ODAT to the data driver 320 at a first frequency FF1 of approximately 60 Hz, such that one frame data FD is provided in each frame period FP. Therefore, a display scan operation may be performed at the first frequency FF1 of approximately 60 Hz, and a self-scan operation may be performed at the second frequency FF2 of approximately 240 Hz.

[0107] As described above, in the OLED display device 300 according to the exemplary embodiment, the self-scanning frequency or the second frequency FF2 may be a fixed frequency higher than the first frequency FF1. Therefore, even if the first frequency FF1, which is the driving frequency or the display scanning frequency of the display panel 310, changes, the OLED display device 300 according to the exemplary embodiment can display an image with substantially constant brightness at the same grayscale.

[0108] Although exemplary embodiments have been shown and described in which the higher self-scan frequency is fixed and the potential lower frequency frame rate is variable, the embodiments are not limited thereto. For example, the higher self-scan frequency may be a minimum multiple of the variable frame rate to reach or exceed a threshold frequency.

[0109] Figure 17 An electronic device including an OLED display device according to an exemplary embodiment is illustrated.

[0110] Reference Figure 17 , the electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output (I / O) device 1140, a power supply 1150, and an OLED display device 1160. The electronic device 1100 may further include a plurality of ports for communicating video cards, sound cards, memory cards, universal serial bus (USB) devices, other electronic devices, and the like.

[0111] The processor 1110 may perform various computing functions or tasks. The processor 1110 may be an application processor (AP), a microprocessor, a central processing unit (CPU), or the like. The processor 1110 may be coupled to other components via an address bus, a control bus, a data bus, or the like. Furthermore, in an exemplary embodiment, the processor 1110 may be further coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0112] The memory device 1120 may store data for operating the electronic device 1100. For example, the memory device 1120 may include at least one nonvolatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc.), and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, etc.).

[0113] The storage device 1130 may be a solid-state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc. The I / O device 1140 may be an input device such as a keyboard, a keypad, a mouse, a touch screen, etc., and an output device such as a printer, a speaker, etc. The power supply 1150 may supply power for operating the electronic device 1100. The OLED display device 1160 may be coupled to other components via a bus or other communication link.

[0114] The OLED display device 1160 may be substantially similar to Figure 13 OLED display device 300 without limitation. In the OLED display device 1160, each pixel may include: a capacitor; a first transistor; a second transistor including a gate receiving a gate write signal; a third transistor including a gate receiving a scan signal; a fourth transistor including a gate receiving a gate initialization signal; a fifth transistor including a gate receiving a first emission signal; a sixth transistor including a gate receiving a second emission signal; and an OLED. The scan signal and the gate write signal may be provided at a first frequency, and the first emission signal, the second emission signal, and the gate initialization signal may be provided at a second frequency higher than the first frequency. Therefore, a bias may be applied to the first transistor at a (fixed or constant) second frequency, and therefore, even if the first frequency (e.g., the driving frequency or the display scan frequency) changes, the OLED display device 1160 can display an image with substantially constant brightness at the same grayscale.

[0115] The present inventive concept can be applied to any OLED display device 1160 that supports a variable frame mode and any electronic device 1100 including the OLED display device 1160. For example, the present inventive concept can be applied to smartphones, wearable electronic devices, tablet computers, mobile phones, televisions (TVs), digital TVs, three-dimensional (3D) TVs, personal computers (PCs), home appliances, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, navigation devices, and the like.

[0116] Although exemplary embodiments have been described, those skilled in the relevant art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the teachings of the present inventive concept. Therefore, all such modifications are intended to be included within the scope of the present inventive concept as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of various exemplary embodiments and is not to be construed as limiting the specific exemplary embodiments disclosed, and that modifications to the disclosed exemplary embodiments as well as other embodiments are intended to be included within the scope of the appended claims.

Claims

1. A pixel of a light-emitting display device, the pixel comprising: a first transistor comprising a gate coupled to the gate node, a first terminal, and a second terminal; a second transistor including a gate receiving a gate write signal, a first terminal coupled to a data line, and a second terminal coupled to the first terminal of the first transistor; a fourth transistor including a gate receiving a gate initialization signal, a first terminal coupled to a line of an initialization voltage, and a second terminal coupled to an anode of the light emitting diode; a sixth transistor including a gate receiving a second emission signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the anode of the light emitting diode, The frequency of the gate write signal is different from the frequency of at least one of the second emission signal and the gate initialization signal.

2. The pixel according to claim 1, wherein The first transistor, the second transistor, and the fourth transistor are P-type transistors, and Wherein, the sixth transistor is an N-type transistor.

3. The pixel according to claim 1, wherein The first transistor, the second transistor, the fourth transistor, and the sixth transistor are P-type transistors.

4. The pixel according to claim 1, wherein The gate write signal is provided at a first frequency, and the second emission signal and the gate initialization signal are provided at a second frequency higher than the first frequency, and The second frequency is an integer multiple of the first frequency.

5. The pixel according to claim 4, wherein The second frequency is a fixed frequency, and the first frequency is a variable frequency.

6. The pixel according to claim 1, further comprising: a capacitor including a first electrode coupled to a line of a first power supply voltage and a second electrode coupled to the gate node; a third transistor including a gate receiving a scan signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the gate node; a fifth transistor including a gate receiving a first transmit signal, a first terminal coupled to the line of the first power supply voltage, and a second terminal coupled to the first terminal of the first transistor; as well as The light emitting diode includes the anode and a cathode coupled to a line of a second power supply voltage.

7. The pixel according to claim 6, wherein: The scan signal and the gate write signal are provided at a first frequency, and the first emission signal, the second emission signal, and the gate initialization signal are provided at a second frequency higher than the first frequency, and The second frequency is an integer multiple of the first frequency.

8. The pixel according to claim 7, in, The light emitting diode is an organic light emitting diode, and the light emitting display device is an organic light emitting diode display device, wherein the second frequency corresponds to twice the maximum frequency of the variable input frame frequency of the organic light emitting diode display device, and The first frequency corresponds to the second frequency divided by N, where N is an integer greater than 1 and less than or equal to the maximum frequency.

9. The pixel according to claim 6, wherein: The light emitting diode is an organic light emitting diode, the light emitting display device is an organic light emitting diode display device, and a frame period of the organic light emitting diode display device includes: a gate and anode initialization period during which the gate node and the anode are initialized; a data writing period during which the data voltage of the data line is written into the capacitor; A bias is applied to the first transistor for a first bias period; a first emission period during which the organic light emitting diode emits light; an anode initialization period during which the anode is initialized; The bias is applied to a second bias period of the first transistor; and The organic light emitting diode emits light in a second emission period.

10. A display device comprising: a display panel comprising a plurality of pixels; a scan driver coupled to the plurality of pixels; as well as an emission driver coupled to the plurality of pixels; Each of the plurality of pixels includes: a first transistor comprising a gate coupled to the capacitor, a first terminal, and a second terminal; a second transistor including a gate coupled to the scan driver, a first terminal coupled to a data line, and a second terminal coupled to the first terminal of the first transistor; and a sixth transistor comprising a gate coupled to the emission driver, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the first terminal of the emission device, wherein the scan driver provides the gate write signal to the plurality of pixels at a first frequency, and The emission driver provides emission signals to the plurality of pixels at a second frequency different from the first frequency.

11. A pixel of a light-emitting display device, the pixel comprising: a first transistor comprising a gate coupled to the gate node, a first terminal, and a second terminal; a second transistor including a gate receiving a first signal, a first terminal coupled to a data line, and a second terminal coupled to the first transistor; a third transistor including a gate receiving a second signal, a first terminal coupled to a line of an initialization voltage, and a second terminal coupled to an anode of the light emitting diode; as well as a fourth transistor including a gate receiving a third signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the anode of the light emitting diode, wherein the frequency of the first signal is different from the frequency of at least one of the second signal and the third signal, and Wherein, the fourth transistor is a P-type transistor.

12. The pixel according to claim 11, wherein The first transistor, the second transistor, and the third transistor are P-type transistors.

13. The pixel according to claim 11, wherein The first signal is provided at a first frequency, and the second signal and the third signal are provided at a second frequency higher than the first frequency, and The second frequency is an integer multiple of the first frequency.

14. The pixel according to claim 13, wherein: The second frequency is a fixed frequency, and the first frequency is a variable frequency.

15. The pixel of claim 11, further comprising: a capacitor coupled to the gate node; a fifth transistor comprising a gate receiving a fourth signal, a first terminal, and a second terminal coupled to the gate node; a sixth transistor including a gate receiving a fifth signal, a first terminal coupled to a line of a first power supply voltage, and a second terminal coupled to the first terminal of the first transistor; as well as The light emitting diode includes the anode and a cathode coupled to a line of a second power supply voltage.

16. The pixel according to claim 15, wherein: The first signal and the fourth signal are provided at a first frequency, and the second signal, the third signal, and the fifth signal are provided at a second frequency higher than the first frequency, and The second frequency is an integer multiple of the first frequency.

17. The pixel according to claim 16, in, The second frequency corresponds to twice the maximum frequency of the variable input frame frequency of the light emitting display device, and The first frequency corresponds to the second frequency divided by N, where N is an integer greater than 1 and less than or equal to the maximum frequency.

18. A pixel of a light-emitting display device, the pixel comprising: a first transistor comprising a gate coupled to the gate node, a first terminal, and a second terminal; a second transistor including a gate receiving a first signal, a first terminal coupled to a data line, and a second terminal coupled to the first transistor; a third transistor comprising a gate receiving a second signal, a first terminal, and a second terminal coupled to the gate node; as well as a fourth transistor including a gate receiving a third signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the anode of the light emitting diode, wherein a frequency of at least one of the first signal and the second signal is different from a frequency of the third signal, and At least one of the first transistor, the second transistor, and the third transistor is an N-type transistor, and the fourth transistor is a P-type transistor.

19. A pixel of a light-emitting display device, the pixel comprising: a first transistor comprising a gate coupled to the gate node, a first terminal, and a second terminal; a second transistor including a gate receiving a first signal, a first terminal coupled to a data line, and a second terminal coupled to the first transistor; a third transistor comprising a gate receiving a second signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the gate node; as well as a fourth transistor including a gate receiving a third signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the anode of the light emitting diode, The frame period of the light-emitting display device includes a first sub-frame period and a second sub-frame period. In the first subframe period, the second transistor, the third transistor and the fourth transistor are turned on. wherein, in the second subframe period, the fourth transistor is turned on, and the second transistor and the third transistor are not turned on, and At least one of the first transistor, the second transistor, and the third transistor is an N-type transistor, and the fourth transistor is a P-type transistor.

20. An electronic device comprising: a processor configured to provide input image data; a light-emitting display device configured to receive the input image data from the processor and display an image based on the input image data, the light-emitting display device including a plurality of pixels, Wherein, at least one pixel among the plurality of pixels comprises: a first transistor comprising a gate coupled to the gate node, a first terminal, and a second terminal; a second transistor including a gate receiving a first signal, a first terminal coupled to a data line, and a second terminal coupled to the first transistor; a third transistor including a gate receiving the second signal, a first terminal coupled to a line of an initialization voltage, and a second terminal coupled to an anode of the light emitting diode; and a fourth transistor including a gate receiving a third signal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the anode of the light emitting diode, wherein the frequency of the first signal is different from the frequency of at least one of the second signal and the third signal, and Wherein, the fourth transistor is a P-type transistor.

Images