Display device and data driver

Abstract

The invention relates to a display device and a data driver. The display device includes: a display panel on which a plurality of sub-pixels are disposed; a data driver configured to convert image data input from outside and supply a data voltage to the plurality of sub-pixels through the plurality of data lines; and a multiplexer connected between the data driver and the plurality of data lines and composed of a plurality of switching elements controlled by a plurality of multiplexer control signals, in which the data driver includes a plurality of output buffers configured to amplify and output a data voltage based on a bias current, and the plurality of output buffers are configured to output the data voltage based on the bias current. And control the bias current supplied to each of the output buffers based on a gradation difference of the image data supplied to the plurality of sub-pixels.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2024-0027086, filed on February 26, 2024, which is hereby incorporated by reference in its entirety for all purposes. Technical Field

[0003] The present disclosure relates to a data driver and a display device including the same. Background Art

[0004] As the information society develops, various types of display devices are being developed. Recently, various display devices such as liquid crystal display (LCD) devices, plasma display panel (PDP) display devices, and organic light emitting diode (OLED) display devices are used.

[0005] OLED displays use OLEDs to display images. OLEDs (hereinafter referred to as light-emitting elements) are self-luminous and do not require a separate light source, thus reducing the thickness and weight of the display. Furthermore, OLED displays exhibit high-quality characteristics such as low power consumption, high brightness, and fast response time.

[0006] The display device consumes a large amount of power because it is constantly on when providing information to the user. Therefore, research and development are continuously being conducted to reduce the power consumption of the display device. Summary of the Invention

[0007] Embodiments are directed to providing a data driver connecting two or more sub-pixels having the same color to one output buffer through a multiplexer, and a display device including the same.

[0008] Embodiments also provide a data driver for variably controlling consumption power according to grayscale changes between data voltages output from an external buffer in the data driver, and a display device including the same.

[0009] According to one embodiment, a display device may include: a display panel on which a plurality of sub-pixels are arranged; a data driver configured to convert image data input from the outside and provide data voltages to the plurality of sub-pixels through a plurality of data lines; and a multiplexer connected between the data driver and the plurality of data lines and composed of a plurality of switching elements, the plurality of switching elements being controlled by a plurality of multiplexer control signals.

[0010] The data driver may include a plurality of output buffers configured to amplify and output a data voltage based on a bias current, and control a bias current supplied to each of the plurality of output buffers based on a grayscale difference value of image data provided to the plurality of sub-pixels.

[0011] The data driver may further include: a register unit configured to generate a sampling signal using a data drive control signal applied from the outside; a latch unit configured to sequentially latch image data in response to the sampling signal and sequentially output the image data; a digital-to-analog converter configured to convert the image data output from the latch unit into a gamma compensation voltage and generate a data voltage; a calculation unit configured to determine a grayscale difference value of the image data sequentially output from the latch unit; and a power control circuit configured to generate a bias current having an amplitude corresponding to the grayscale difference value and apply the bias current to a plurality of output buffers.

[0012] The power control circuit may reduce the amplitude of the bias current when the grayscale difference is small, and the power control circuit may increase the amplitude of the bias current when the grayscale difference is large.

[0013] The power consumption of the output buffer may be changed in proportion to the magnitude of the bias current.

[0014] The calculation unit may determine a grayscale difference value of the sequentially output image data for each of the plurality of output buffers, and the power control circuit may independently adjust a magnitude of a bias current of each of the output buffers in response to the grayscale difference value.

[0015] The calculation unit may compare grayscale differences for a plurality of output buffers configured to output data voltages to sub-pixels having the same color, and the power control circuit may adjust the magnitude of bias currents of the plurality of output buffers according to a result of the comparison.

[0016] The calculation unit may determine a maximum value or an average value of grayscale difference values ​​for a plurality of output buffers, the plurality of output buffers being configured to output data voltages to sub-pixels having the same color, and the power control circuit may adjust the magnitude of the bias current for the plurality of output buffers in response to the maximum value or the average value of the grayscale difference values, the plurality of output buffers being configured to output data voltages to sub-pixels having the same color.

[0017] One output buffer may be connected to a plurality of sub-pixels having the same color through a plurality of switching elements of a multiplexer.

[0018] A switching element may be connected between an output buffer and a sub-pixel.

[0019] A plurality of switching elements connected to one output buffer may be controlled by a multiplexer control signal having different on-periods.

[0020] When one multiplexer control signal is turned on, data voltages may be output from the plurality of output buffers to sub-pixels having different colors constituting one unit pixel.

[0021] According to one embodiment, a display device may include: a display panel on which a plurality of sub-pixels are arranged; a data driver configured to convert image data input from the outside and provide data voltages to the plurality of sub-pixels through a plurality of data lines; and a multiplexer connected between the data driver and the plurality of data lines and composed of a plurality of switching elements, the plurality of switching elements being controlled by a plurality of multiplexer control signals.

[0022] One output buffer may be connected to a plurality of sub-pixels having the same color through a plurality of switching elements of a multiplexer.

[0023] A switching element may be connected between an output buffer and a sub-pixel.

[0024] A plurality of switching elements connected to one output buffer may be controlled by a multiplexer control signal having different on-periods.

[0025] When one multiplexer control signal is turned on, data voltages may be output from the plurality of output buffers to sub-pixels having different colors constituting one unit pixel.

[0026] The data driver may change the consumed power based on a grayscale difference of the image data provided to the plurality of sub-pixels.

[0027] The data driver may include: a register unit configured to generate a sampling signal using a data drive control signal applied from the outside; a latch unit configured to sequentially latch image data in response to the sampling signal and sequentially output the image data; a digital-to-analog converter configured to convert the image data output from the latch unit into a gamma compensation voltage and generate a data voltage; a plurality of output buffers configured to amplify and output the data voltage based on a bias current; a calculation unit configured to determine a grayscale difference value of the image data sequentially output from the latch unit; and a power control circuit configured to generate a bias current having an amplitude corresponding to the grayscale difference value and apply the bias current to the plurality of output buffers.

[0028] The power control circuit may reduce the amplitude of the bias current when the grayscale difference is small, and the power control circuit may increase the amplitude of the bias current when the grayscale difference is large.

[0029] The calculation unit may determine a grayscale difference value of the sequentially output image data for each of the output buffers, and the power control circuit may independently adjust a magnitude of a bias current of each of the output buffers in response to the grayscale difference value.

[0030] The calculation unit can determine a maximum value or an average value of grayscale difference values ​​for a plurality of output buffers configured to output data voltages to sub-pixels having the same color, and the power control circuit can adjust the amplitude of the bias current for the plurality of output buffers configured to output data voltages to sub-pixels having the same color in response to the maximum value or the average value of the grayscale difference values. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a block diagram showing a configuration of a display device according to one embodiment.

[0032] Figure 2 is a block diagram illustrating a connection relationship among an output buffer, a multiplexer, and a display panel according to one embodiment.

[0033] Figure 3 is a waveform diagram of control and driving signals applied to a display device according to one embodiment.

[0034] Figure 4 is a block diagram illustrating a configuration of a data driver according to one embodiment.

[0035] Figure 5 is a circuit diagram illustrating a connection relationship among a calculation unit, a power control circuit, and an output buffer according to one embodiment.

[0036] Figures 6A to 6C is a view for describing a method of controlling consumption power of an output buffer according to one embodiment.

[0037] Figure 7 is a view for describing a method of controlling power consumption of an output buffer according to another embodiment.

[0038] Figure 8 and Figure 9 is a waveform diagram illustrating a method of controlling the bias current. DETAILED DESCRIPTION

[0039] Details of other embodiments are included in the detailed description and accompanying drawings.

[0040] The advantages and features of the present disclosure and methods for achieving them will become clear with reference to the embodiments described in detail below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below, but can be implemented in any of a variety of different forms, and in the following description, when a certain part is connected to another part, it includes not only the case where the certain part is directly connected to the other part, but also the case where the certain part is electrically connected to the other part with other elements interposed therebetween. In addition, in the accompanying drawings, parts not related to the present disclosure are omitted to clarify the description of the present disclosure, and similar parts are represented by the same reference numerals throughout the specification.

[0041] Figure 1 is a block diagram showing a configuration of a display device according to one embodiment.

[0042] Reference Figure 1 , the display device 1 includes a timing controller 10 , a gate driver 20 , a data driver 30 , a power supply unit 40 and a display panel 50 .

[0043] The timing controller 10 may receive an image signal RGB and a control signal CS from the outside. The image signal RGB may include a plurality of grayscale data. The control signal CS may include, for example, a horizontal synchronization signal, a vertical synchronization signal, and a main clock signal.

[0044] The timing controller 10 may process the image signals RGB and the control signal CS according to the operating conditions of the display panel 50 to generate and output image data DATA, a gate drive control signal CONT1, a data drive control signal CONT2, and a power supply control signal CONT3. The data drive control signal CONT2 may include, for example, a source output enable SOE signal, a power control signal, and the like.

[0045] The gate driver 20 may be connected to the unit pixels PX of the display panel 50 through a plurality of gate lines GL. The gate driver 20 may generate gate signals based on the gate driving control signal CONT1 output from the timing controller 10. The gate driver 20 may provide the generated gate signals to the unit pixels PX through the plurality of gate lines GL.

[0046] The data driver 30 may be connected to the unit pixels PX of the display panel 50 via a plurality of data lines DL. The data driver 30 may generate data voltages based on the image data DATA and the data drive control signal CONT2 output from the timing controller 10. The data driver 30 may provide the generated data voltages to the unit pixels PX via the plurality of data lines DL. The data voltages may be applied to the unit pixels PX of the pixel columns selected by the gate signals. To this end, the data driver 30 may supply the data voltages to the plurality of data lines DL in synchronization with the gate signals.

[0047] The data driver 30 may be a data driver integrated circuit (IC). Alternatively, the data driver 30 may be referred to as a group of one or more data driver ICs. In the following embodiments, no particular distinction is made between the data driver 30 and the data driver IC. In other words, in the following embodiments, the data driver 30 may be referred to as one data driver IC, or may be referred to as one driver consisting of multiple data driver ICs. The data driver 30 may include a register unit, a latch unit, a digital-to-analog converter, and one or more output buffers, generate a data voltage, and output the generated data voltage to the data line DL connected to the output buffer.

[0048] The power supply unit 40 can be connected to the unit pixels PX of the display panel 50 via a plurality of power lines PL1 and PL2. The power supply unit 40 can generate driving voltages to be provided to the display panel 50 based on the power supply control signal CONT3. The driving voltages can include, for example, a high-potential driving voltage VDD and a low-potential driving voltage VSS. The power supply unit 40 can provide the generated driving voltages VDD and VSS to the unit pixels PX via the corresponding power supply lines PL1 and PL2.

[0049] The unit pixel PX is provided on the display panel 50. Each unit pixel PX may include one or more sub-pixels SP. For example, as shown, the unit pixel PX may include a plurality of sub-pixels SP. The sub-pixels SP may be arranged in a matrix on the display panel 50.

[0050] Each sub-pixel SP may be electrically connected to corresponding gate and data lines DL, and may emit light having brightness corresponding to a gate signal and a data voltage supplied through the gate and data lines DL.

[0051] Each sub-pixel SP can display one of the first to third colors. In one embodiment, each sub-pixel SP can display any one of red, green, and blue. In another embodiment, each sub-pixel SP can display any one of cyan, magenta, and yellow. In various embodiments, the sub-pixels SP can be configured to display any one of four or more colors. For example, each sub-pixel SP can display any one of red, green, blue, and white.

[0052] In one embodiment, the display device 1 may include a multiplexer 60 connected between the data driver 30 and the sub-pixels to drive the data lines DL in a time-division manner. The multiplexer 60 connects the output buffer in the data driver 30 to two or more data lines DL. In addition, the multiplexer 60 can reduce the number of data driver ICs and output buffers provided in the data driver 30 by dividing the data voltage output from the output buffer in the data driver 30 to the data lines DL in a time-division manner.

[0053] In one embodiment, the multiplexer 60 may include a plurality of switching elements connected between the data driver 30 and the data lines DL. For example, the multiplexer 60 may be configured to connect one output buffer to one or more data lines DL through the switching elements.

[0054] exist Figure 1 , the gate driver 20, the data driver 30, and the multiplexer 60 are illustrated as components separate from the display panel 50, but at least one of the gate driver 20, the data driver 30, and the multiplexer 60 may be configured as an in-panel type integrally formed with the display panel 50. For example, the gate driver 20 may be integrally formed with the display panel 50 according to a gate-in-panel (GIP) type.

[0055] The timing controller 10, the gate driver 20, the data driver 30, and the power supply unit 40 may each be configured as a separate IC or an at least partially integrated IC. For example, the timing controller 10, the data driver 30, and the power supply unit 40 may be configured as a driver chip in the form of an integrated IC. For example, such a driver chip may be implemented in the form of a flexible printed circuit board (FPCB).

[0056] Figure 2 is a block diagram illustrating a connection relationship among an output buffer, a multiplexer, and a display panel according to one embodiment.

[0057] Reference Figure 2 , data driver 30 (see Figure 1 ) includes a plurality of output buffers 341, 342 and 343. The output buffers 341, 342 and 343 can output data voltages through corresponding channels CH1, CH2 and CH3 respectively. Figure 2 , only three output buffers 341 , 342 , and 343 are shown as an example, but more output buffers may be provided on the right side.

[0058] Multiplexer 60 (see Figure 1 ) includes a plurality of switching elements M1 to M15. Figure 2, only fifteen switching elements M1 to M15 are shown as an example, but a larger number of switching elements may be provided on the right side.

[0059] Each of the switching elements M1 to M15 can be connected to any one of the output buffers 341, 342, and 343 of the data driver 30. In this case, two or more of the switching elements M1 to M15 can be connected to one of the output buffers 341, 342, and 343. For example, the first switching element M1, the fourth switching element M4, the seventh switching element M7, the tenth switching element M10, and the thirteenth switching element M13 can be connected to the first output buffer 341, the second switching element M2, the fifth switching element M5, the eighth switching element M8, the eleventh switching element M11, and the fourteenth switching element M14 can be connected to the second output buffer 342, and the third switching element M3, the sixth switching element M6, the ninth switching element M9, the twelfth switching element M12, and the fifteenth switching element M15 can be connected to the third output buffer 343. For example, five of the switching elements M1 to M15 are connected to one of the output buffers 341, 342, and 343, but the present disclosure is not limited thereto.

[0060] The switching elements M1 to M15 can be turned on and off by the timing controller 10 (see Figure 1 ) and the like. Specifically, the first to third switching elements M1 to M3 can be controlled according to the first multiplexer control signal MUX1, the fourth to sixth switching elements M4 to M6 can be controlled according to the second multiplexer control signal MUX2, and the seventh to ninth switching elements M7 to M9 can be controlled according to the third multiplexer control signal MUX3. In addition, the tenth to twelfth switching elements M10 to M12 can be controlled according to the fourth multiplexer control signal MUX4, and the thirteenth to fifteenth switching elements M13 to M15 can be controlled according to the fifth multiplexer control signal MUX5. Here, since the switching elements M1 to M15 are controlled by five multiplexer control signals MUX1 to MUX5, the multiplexer 60 can be referred to as a 5MUX structure.

[0061] In the present embodiment, the switching elements M1 to M15 controlled by the multiplexer control signals MUX1 to MUX5 having different conduction periods are connected to one of the output buffers 341, 342, and 343. In other words, the fifteen switching elements M1 to M15 controlled by the first to fifth multiplexer control signals MUX1 to MUX5, respectively, may be connected to each of the output buffers 341, 342, and 343. For example, the switching elements M1 to M3 controlled by the first multiplexer control signal MUX1 may be connected to each of the output buffers 341, 342, and 343, respectively.

[0062] Display panel 50 (see Figure 1 ) includes a plurality of unit pixels PX arranged in a matrix form. Figure 2 An example is shown in which one unit pixel PX is composed of three sub-pixels R, G and B, wherein Figure 2 The plurality of unit pixels are shown to include sub-pixels (R0, G0, B0), (R1, G1, B1), (R2, G2, B2), (R3, G3, B3), and (R4, G4, B4). For example, the sub-pixels R0 to R4, G0 to G4, and B0 to B4 may include red sub-pixels R0 to R4, green sub-pixels G0 to G4, and blue sub-pixels B0 to B4.

[0063] Each of the sub-pixels R0 to R4 , G0 to G4 , and B0 to B4 is connected to corresponding data lines DL1 to DL15 and gate lines GL1 and GL2 . Figure 2 Fifteen data lines DL1 to DL15 are shown as an example, but more data lines may be provided on the right side. Figure 2 Two gate lines GL1 and GL2 are shown as an example, but a greater number of gate lines may be provided downward.

[0064] The red sub-pixels R0 to R4, the green sub-pixels G0 to G4, and the blue sub-pixels B0 to B4 may be sequentially and repeatedly arranged in one sub-pixel row. One of the red sub-pixels R0 to R4, one of the green sub-pixels G0 to G4, and one of the blue sub-pixels B0 to B4 disposed adjacent to each other may form one unit pixel PX (see Figure 1 ).

[0065] In one embodiment, sub-pixels R0 to R4, G0 to G4, and B0 to B4 having the same color may be arranged in the same sub-pixel column. For example, a plurality of red sub-pixels R0 may be arranged in a first sub-pixel column, a plurality of red sub-pixels R1 may be arranged in a fourth sub-pixel column, a plurality of green sub-pixels G0 may be arranged in a second sub-pixel column, a plurality of green sub-pixels G1 may be arranged in a fifth sub-pixel column, a plurality of blue sub-pixels B0 may be arranged in a third sub-pixel column, and a plurality of blue sub-pixels B1 may be arranged in a sixth sub-pixel column. However, this embodiment is not limited thereto. In other words, in various other embodiments, sub-pixels R0 to R4, G0 to G4, and B0 to B4 having different colors may be arranged in a sub-pixel row according to a predetermined pattern.

[0066] The switching elements M1 to M15 of the multiplexer 60 are connected to the input terminals of the data lines DL1 to DL15, respectively. In one embodiment, sub-pixels R0 to R4, G0 to G4, and B0 to B4 of the same color can be connected to one of the output buffers 341, 342, and 343 through the switching elements M1 to M15. For example, the red sub-pixels R0 to R4 can be connected to the first output buffer 341 through the first switching element M1, the fourth switching element M4, the seventh switching element M7, the tenth switching element M10, and the thirteenth switching element M13; the green sub-pixels G0 to G4 can be connected to the second output buffer 342 through the second switching element M2, the fifth switching element M5, the eighth switching element M8, the eleventh switching element M11, and the fourteenth switching element M14; and the blue sub-pixels B0 to B4 can be connected to the third output buffer 343 through the third switching element M3, the sixth switching element M6, the ninth switching element M9, the twelfth switching element M12, and the fifteenth switching element M15. However, this embodiment is not limited thereto.

[0067] When the switching elements M1 to M15 are turned on according to the multiplexer control signals MUX1 to MUX5, the data voltage can be applied to the data lines DL1 to DL15 connected to the corresponding switching elements M1 to M15. In one embodiment, when one of the multiplexer control signals MUX1 to MUX5 is turned on, the data voltage can be applied to one of the sub-pixels R0 to R4, one of G0 to G4, and one of B0 to B4 constituting one unit pixel PX. In other words, the sub-pixels R0 to R4, G0 to G4, and B0 to B4 constituting one unit pixel PX can each be connected to three of the switching elements M1 to M15 controlled by one multiplexer control signal MUX, where MUX can be one of the multiplexer control signals MUX1 to MUX5.

[0068] Therefore, when the first to third switching elements M1 to M3 are turned on according to the first multiplexer control signal MUX1, data voltages can be applied to the sub-pixels R0, G0, and B0 that are connected one-to-one with the first to third data lines DL1 to DL3. Furthermore, when the fourth to sixth switching elements M4 to M6 are turned on according to the second multiplexer control signal MUX2, data voltages can be applied to the sub-pixels R1, G1, and B1 that are connected one-to-one with the fourth to sixth data lines DL4 to DL6. Furthermore, when the seventh to ninth switching elements M7 to M9 are turned on according to the third multiplexer control signal MUX3, data voltages can be applied to the sub-pixels R2, G2, and B2 that are connected one-to-one with the seventh to ninth data lines DL7 to DL9. In addition, when the tenth to twelfth switching elements M10 to M12 are turned on according to the fourth multiplexer control signal MUX4, the data voltages may be applied to the sub-pixels R3, G3, and B3 connected one-to-one with the tenth to twelfth data lines DL10 to DL12. In addition, when the thirteenth to fifteenth switching elements M13 to M15 are turned on according to the fifth multiplexer control signal MUX5, the data voltages may be applied to the sub-pixels R4, G4, and B4 connected one-to-one with the thirteenth to fifteenth data lines DL13 to DL15.

[0069] In one embodiment, the switching elements M1 to M15 may be formed as transistors. In the illustrated embodiment, the switching elements M1 to M15 are NMOS transistors. In this embodiment, the on-levels of the multiplexer control signals MUX1 to MUX3 are high. However, this embodiment is not limited thereto. In other words, in another embodiment, the switching elements M1 to M15 may be PMOS transistors. In this embodiment, the on-levels of the multiplexer control signals MUX1 to MUX3 are low.

[0070] Figure 3 is a waveform diagram of control and driving signals applied to a display device according to one embodiment.

[0071] Refer to it together Figure 2 and Figure 3 , in driving the display device 1 (see Figure 1 ), the gate signals at the on level are sequentially applied to the gate lines GL1 and GL2. In this case, each gate signal at the on level may be applied within one horizontal period (1H).

[0072] Each of the output buffers 341, 342, and 343 may divide one horizontal period (1H) in a time division manner and sequentially output the data voltage to the plurality of unit pixels PX (see FIG. Figure 1) of the subpixels R0 to R4, G0 to G4, and B0 to B4 of the horizontal period (1H). For example, each of the output buffers 341, 342, and 343 may output the data voltage of the first red subpixel R0, the first green subpixel G0, and the first blue subpixel B0 during the first period t1 of one horizontal period (1H), output the data voltage of the second red subpixel R1, the second green subpixel G1, and the second blue subpixel B1 during the second period t2, and output the data voltage of the third red subpixel R2, the third green subpixel G2, and the third blue subpixel B2 during the third period t3. For example, the output buffers 341, 342, and 343 may output the data voltage of the fourth red subpixel R3, the fourth green subpixel G3, and the fourth blue subpixel B3, respectively, during the fourth period t4 of the horizontal period (1H), and output the data voltage of the fifth red subpixel R4, the fifth green subpixel G4, and the fifth blue subpixel B4, respectively, during the fifth period t5.

[0073] Timing control unit 10 (see Figure 1 ) provides multiplexer control signals MUX1 to MUX5 to allow switching elements M1 to M15 of the multiplexer 60 to be sequentially turned on during one horizontal period (1H).

[0074] During a first period t1 of the first horizontal period, a first multiplexer control signal MUX1 at an on level is applied to the multiplexer 60. Then, the first to third switching elements M1 to M3 may be turned on to apply the data voltages output from the output buffers 341, 342, and 343 to the first sub-pixels R0, G0, and B0, respectively. During a second period t2, a second multiplexer control signal MUX2 at an on level is applied to the multiplexer 60. Then, the fourth to sixth switching elements M4 to M6 may be turned on to apply the data voltages output from the output buffers 341, 342, and 343 to the second sub-pixels R1, G1, and B1, respectively.

[0075] During the third period t3, the third multiplexer control signal MUX3 at an on level is applied to the multiplexer 60. Then, the seventh to ninth switching elements M7 to M9 may be turned on to apply the data voltages output from the output buffers 341, 342, and 343 to the third sub-pixels R2, G2, and B2, respectively. During the fourth period t4, the fourth multiplexer control signal MUX4 at an on level is applied to the multiplexer 60. Then, the tenth to twelfth switching elements M10 to M12 may be turned on to apply the data voltages output from the output buffers 341, 342, and 343 to the fourth sub-pixels R3, G3, and B3, respectively. During the fifth period t5, the fifth multiplexer control signal MUX5 at an on level is applied to the multiplexer 60. Then, the thirteenth to fifteenth switching elements M13 to M15 may be turned on to apply the data voltages output from the output buffers 341 , 342 , and 343 to the fifth subpixels R4 , G4 , and B4 , respectively.

[0076] Figure 4 is a block diagram illustrating a configuration of a data driver according to one embodiment.

[0077] Reference Figure 4 , the data driver 30 may include a register unit 31 , a latch unit 32 , a digital-to-analog converter 33 and a plurality of output buffers 34 .

[0078] The register unit 31 uses the slave timing controller 10 (see Figure 1 ) receives the data driving control signal CONT2 to generate a sampling signal, and provides the generated sampling signal to the latch unit 32.

[0079] The latch unit 32 sequentially latches the image data DATA received from the timing controller 10 in response to the sampling signal received from the register unit 31 , and then sequentially outputs the image data DATA to the digital-to-analog converter 33 .

[0080] The digital-to-analog converter 33 converts the image data received from the latch unit 32 into a gamma compensation voltage to generate a data voltage.

[0081] Each of the output buffers 34 outputs the data voltage output from the digital-to-analog converter 33 to the data line DL through the channel CH according to the source output enable SOE signal received from the timing controller 10. The output buffer 34 may amplify the data voltage based on the bias current Ibias and output the amplified data voltage to the data line DL.

[0082] The data driver 30 according to one embodiment may be configured to adjust the consumed power of the data driver 30 and / or the output buffer 34 based on the grayscale of the image data DATA to be output from the output buffer 34. To this end, the data driver 30 may further include a calculation unit 35 and a power control circuit 36.

[0083] The calculation unit 35 can compare the image data DATA sequentially received from the latch unit 32 and determine the grayscale difference value of the image data DATA. In other words, the calculation unit 35 can determine the grayscale difference value of the image data DATA to be output next based on the grayscale of the image data DATA to be output first relative to the image data DATA sent from the latch unit 32.

[0084] The calculation unit 35 may send the determined grayscale difference value to the power control circuit 36. For example, the grayscale difference value may be output in the form of a power control signal PWRC. In one embodiment, the power control signal PWRC may be a logic signal at a predetermined level corresponding to the grayscale difference value. In this embodiment, the calculation unit 35 may be configured to divide the grayscale difference value into a plurality of threshold ranges and output a logic signal indicating the threshold range including the determined grayscale difference value. However, this embodiment is not limited thereto.

[0085] The power control circuit 36 ​​can generate a bias current Ibias based on the power control signal PWRC provided by the calculation unit 35, and apply the generated bias current Ibias to the output buffer 34. The magnitude of the bias current Ibias can be changed according to the grayscale difference indicated by the power control signal PWRC or the like. For example, the power control circuit 36 ​​can reduce the magnitude of the bias current Ibias when the grayscale difference is small, and can increase the magnitude of the bias current Ibias when the grayscale difference is large. The magnitude of the bias current Ibias according to the grayscale difference can be defined as shown in Table 1 below.

[0086] [Table 1]

[0087] Grayscale difference Bias current amplitude 200 grayscale or greater Maximum current (fifth level) 150 grayscale or higher to less than 200 grayscale High current (fourth level) 100 gray or higher to less than 150 gray Commercial Current (Third Level) 50 gray or higher to less than 100 gray Low current (second level) 50 grayscale or less Minimum current (first level)

[0088] The output buffer 34 can be configured to amplify the data voltage based on the bias current Ibias and output the amplified data voltage to the data line DL. The bias current Ibias determines the slew rate of the data voltage output from the output buffer 34. As the grayscale difference between the data voltages sequentially output from the output buffer 34 increases, the transition amplitude of the data voltage increases, and the slew rate should be increased to quickly reach the desired data voltage. Therefore, the output buffer 34 can increase the slew rate of the output voltage by increasing the amplitude of the bias current Ibias according to the grayscale difference between the data voltages.

[0089] On the contrary, when the grayscale difference between the data voltages sequentially output from the output buffer 34 is small, the conversion rate can be reduced, and thus the output buffer 34 can reduce the magnitude of the bias current Ibias to reduce the power consumption of the output buffer. The power consumption of the output buffer 34 changes in proportion to the magnitude of the bias current Ibias.

[0090] Therefore, the data driver 30 according to one embodiment controls the consumption power of the output buffer 34 based on the grayscale difference value of the image data DATA.

[0091] Figure 5 is a circuit diagram illustrating a connection relationship among a calculation unit, a power control circuit, and an output buffer according to one embodiment.

[0092] Reference Figure 5 The calculation unit 35 may determine the grayscale difference value of the sequentially input image data DATA and output the power control signal PWRC corresponding to the determined grayscale difference value. The output power control signal PWRC may be provided to the power control circuit 36.

[0093] The power control circuit 36 ​​receives a bias current Ibias from an external current source or the like. The plurality of current control circuits CC1 to CC4 convert the amplitude of the bias current Ibias in response to the power control signal PWRC. The plurality of current control circuits CC1 to CC4 supply the bias current Ibias, whose amplitudes have been converted, to the output buffer 34. In this case, the bias current Ibias can be amplified to the same number as the number of current control circuits CC1 to CC4 to be turned on for output. Although Figure 5 Four current control circuits CC1 to CC4 are shown in FIG. 2 , but the number of current control circuits CC1 to CC4 is not limited thereto, and a smaller or larger number of current control circuits CC1 to CC4 may be used.

[0094] The output buffer 34 may output the data voltage based on the bias current Ibias transmitted from the power control circuit 36. In this case, the consumption power of the output buffer 34 and the data driver 30 may be adjusted according to the magnitude of the bias current Ibias changed in the output buffer 34.

[0095] Figures 6A to 6C is a view for describing a method of controlling consumption power of an output buffer according to one embodiment.

[0096] Refer to it together Figure 4 and Figures 6A to 6C, a plurality of output buffers 341, 342, and 343 may be provided, each output buffer outputting a data voltage to the sub-pixels R0 to R4, G0 to G4, and B0 to B4 of a corresponding color. Each of the output buffers 341, 342, and 343 is configured to sequentially output the data voltage to the sub-pixels R0 to R4, G0 to G4, and B0 to B4 of the corresponding color in response to sequentially applied multiplexer control signals MUX1 to MUX5.

[0097] For example, Figure 6A As shown, the first output buffer 341 can sequentially output the data voltages to the red sub-pixels R0 to R4. Figure 6B As shown, the second output buffer 342 can sequentially output the data voltages to the green sub-pixels G0 to G4, and at the same time, as shown in FIG. Figure 6C As shown, the third output buffer 343 can sequentially output the data voltage to the blue sub-pixels B0 to B4. To this end, during the on period of each of the multiplexer control signals MUX1 to MUX5, the image data DATA to be output from the output buffers 341, 342, and 343 is sequentially output from the latch unit 32 to the output buffers 341, 342, and 343.

[0098] In this embodiment, the data driver 30 can independently control the power consumption of the output buffers 341, 342, and 343 based on the grayscale difference value of the image data DATA sequentially provided to each of the output buffers 341, 342, and 343. Here, the grayscale difference value may indicate the grayscale difference value of the data voltage to be sequentially output from each of the output buffers 341, 342, and 343 in response to the multiplexer control signals MUX1 to MUX5.

[0099] First, the calculation unit 35 may determine a grayscale difference value of the image data sequentially provided to each of the output buffers 341, 342, and 343. Specifically, the calculation unit 35 may determine the grayscale difference value of the image data DATA by comparing the grayscale of the image data DATA output from the latch unit 32 with the grayscale of the previously output image data DATA for each of the output buffers 341, 342, and 343.

[0100] The calculation unit 35 may transmit a power control signal PWRC corresponding to the determined grayscale difference value to the power control circuit 36. The power control circuit 36 ​​may determine the magnitude of the bias current Ibias to be provided to the output buffers 341, 342, and 343 in response to the grayscale difference value indicated by the power control signal PWRC. In this case, the threshold range of the grayscale difference value and the power consumption mode corresponding to each threshold range may be the same as defined in Table 1.

[0101] Next, the power control circuit 36 ​​may provide the bias current Ibias having the determined magnitude to the output buffers 341, 342, and 343. The output buffers 341, 342, and 343 may output data voltages of the image data DATA having corresponding grayscale difference values ​​based on the bias current Ibias, the magnitude of which is controlled by the power control circuit 36.

[0102] The output buffers 341, 342, and 343 may output the amplified data voltage to the data line DL during the on-period of the multiplexer control signals MUX1 to MUX5 sequentially supplied. Therefore, the power consumption of the output buffers 341, 342, and 343 varies based on the grayscale difference value for each on-period of each of the multiplexer control signals MUX1 to MUX5.

[0103] As described above, the data driver 30 may independently control and change the consumption power of the output buffers 341 , 342 , and 343 for each on-period of each of the multiplexer control signals MUX1 to MUX5 based on the grayscale difference, thereby more effectively reducing the consumption power.

[0104] Figure 7 is a view for describing a method of controlling power consumption of an output buffer according to another embodiment.

[0105] Refer to it together Figure 4 and Figure 7 , a plurality of output buffers 3411, 3412, and 3413 for outputting data voltages to sub-pixels R0 to R14 having the same color may be provided. Each of the output buffers 3411, 3412, and 3413 may sequentially output data voltages to sub-pixels R0 to R4, R5 to R9, and R10 to R14 connected thereto in response to sequentially applied multiplexer control signals MUX1 to MUX5.

[0106] For example, the first output buffer 3411 can sequentially output the data voltage to the first red sub-pixel R0 to the fifth red sub-pixel R4, and at the same time, the second output buffer 3412 can sequentially output the data voltage to the sixth red sub-pixel R5 to the tenth red sub-pixel R9, and at the same time, the third output buffer 3413 can sequentially output the data voltage to the eleventh red sub-pixel R10 to the fifteenth red sub-pixel R14.

[0107] To this end, the image data DATA to be output during the on-period of each of the multiplexer control signals MUX1 to MUX5 may be sequentially output from the latch unit 32 to the output buffers 341 , 342 , and 343 .

[0108] In this embodiment, the data driver 30 can control the power consumption of the output buffers 3411, 3412, and 3413 based on the grayscale difference of the image data DATA sequentially provided to each of the output buffers 3411, 3412, and 3413. In other words, the data driver 30 can control the power consumption of the output buffers 3411, 3412, and 3413 based on the grayscale difference of the data voltage to be sequentially output from each of the output buffers 3411, 3412, and 3413 in response to the multiplexer control signals MUX1 to MUX5.

[0109] First, the calculation unit 35 may determine a grayscale difference value of the image data DATA sequentially provided to each of the output buffers 3411, 3412, and 3413. Specifically, the calculation unit 35 may determine the grayscale difference value of the image data DATA by comparing the grayscale of the image data DATA output from the latch unit 32 with the previously output image data DATA for each of the output buffers 3411, 3412, and 3413.

[0110] In one embodiment, as shown in Table 2 below, the grayscale of the image data DATA to be output from the output buffers 3411 , 3412 , and 3413 during the on period of each of the multiplexer control signals MUX1 to MUX5 may be assumed.

[0111] [Table 2]

[0112] MUX1 MUX2 MUX3 MUX4 MUX5 Output Buffer (3411) 122 190 243 154 49 Output Buffer (3412) 152 34 84 39 182 Output Buffer(3413) 81 177 248 178 41

[0113] In this embodiment, during the conduction period of each of the multiplexer control signals MUX1 to MUX5, the grayscale difference value Δ of the image data from the output buffers 3411, 3412 and 3413 (for example, the absolute value of the grayscale difference between the image data continuously output from the latch unit in response to one output buffer) is as shown in Table 3 below.

[0114] [Table 3]

[0115]

[0116]

[0117] Furthermore, the calculation unit 35 may change the consumed power by comparing the grayscale difference values ​​determined for the output buffers 3411 , 3412 , and 3413 .

[0118] In one embodiment, the calculation unit 35 may determine the maximum value of the grayscale difference values ​​of the output buffers 3411, 3412, and 3413. In the example of Table 3, the maximum value Δmax of the grayscale difference values ​​of the output buffers 3411, 3412, and 3413 is shown in Table 4 below.

[0119] [Table 4]

[0120] Δ(MUX1) Δ(MUX2) Δ(MUX3) Δ(MUX4) Δ(MUX5) Δmax 152 118 71 89 143

[0121] The calculation unit 35 may transmit a power control signal PWRC corresponding to the maximum value Δmax of the grayscale difference value to the power control circuit 36. The power control circuit 36 ​​may determine the magnitude of the bias current Ibias to be provided to the output buffers 3411, 3412, and 3413 in response to the grayscale difference value indicated by the power control signal PWRC.

[0122] When the threshold ranges of the grayscale difference values ​​and the magnitude of the bias current consumed corresponding to each threshold range are as shown in Table 1, the magnitude of the bias current Ibias during the on-period of each of the multiplexer control signals MUX1 to MUX5 is as shown in Table 5 below according to the maximum value Δmax of the grayscale difference values ​​in Table 4.

[0123] [Table 5]

[0124] Δ(MUX1) Δ(MUX2) Δ(MUX3) Δ(MUX4) Δ(MUX5) Δmax 152 118 71 89 143 Ibias Fourth level Third level Second level Third level Third level

[0125] In another embodiment, the calculation unit 35 may determine an average value of the grayscale difference values ​​of the output buffers 3411, 3412, and 3413. In the embodiment of Table 3, the average value Δmean of the grayscale difference values ​​of the output buffers 3411, 3412, and 3413 is shown in Table 6 below.

[0126] [Table 6]

[0127] Δ(MUX1) Δ(MUX2) Δ(MUX3) Δ(MUX4) Δ(MUX5) Δmean 118 94 58 68 128

[0128] The calculation unit 35 may transmit a power control signal PWRC corresponding to the average value Δmean of the grayscale difference values ​​to the power control circuit 36. The power control circuit 36 ​​may determine the magnitude of the bias current Ibias to be provided to the output buffers 3411, 3412, and 3413 in response to the grayscale difference values ​​indicated by the power control signal PWRC.

[0129] When the threshold ranges of the grayscale difference values ​​and the magnitude of the consumed bias current corresponding to each threshold range are as shown in Table 1, according to the average value Δmean of the grayscale difference values ​​in Table 6, the magnitude of the bias current Ibias during the on-period of each of the multiplexer control signals MUX1 to MUX5 is as shown in Table 7 below.

[0130] [Table 7]

[0131] Δ(MUX1) Δ(MUX2) Δ(MUX3) Δ(MUX4) Δ(MUX5) Δmean 118 94 58 68 128 Ibias Third level Second level Second level Second level Third level

[0132] Next, the power control circuit 36 ​​may provide the bias current Ibias having the determined magnitude to the output buffers 3411, 3412, and 3413. The output buffers 3411, 3412, and 3413 may amplify the data voltage of the image data DATA having the corresponding grayscale difference value based on the bias current Ibias, the magnitude of which is controlled by the power control circuit 36.

[0133] The output buffers 3411, 3412, and 3413 can output the amplified data voltage to the data line DL during the on-period of the multiplexer control signals MUX1 to MUX5 provided sequentially. Therefore, the power consumption of the output buffers 3411, 3412, and 3413 varies based on the grayscale difference value for each on-period of each of the multiplexer control signals MUX1 to MUX5.

[0134] Figure 8 and Figure 9 is a waveform diagram illustrating a method of controlling the bias current.

[0135] As reference Figures 4 to 7 As described above, the data driver 30 according to one embodiment adaptively controls the power consumption of the output buffer 34 based on the grayscale difference value of the image data DATA to be output from the output buffer 34. For example, the data driver 30 changes the power consumption of the output buffer 34 based on the grayscale difference value of the image data DATA (or data voltage) to be sequentially output from one output buffer 34 during the on-period of each of the multiplexer control signals MUX1 to MUX5. Alternatively, for example, the data driver 30 may compare the grayscale difference values ​​of a plurality of adjacent output buffers 34 connected to sub-pixels having the same color, and change the power consumption of the plurality of output buffers 34 based on the maximum value or average value of the grayscale difference values.

[0136] Therefore, if Figure 8 As shown, in response to the on-period of each of the multiplexer control signals MUX1 to MUX5, the magnitude of the bias current Ibias supplied to the output buffer 34 is changed. For example, during one horizontal period (1H), in each on-period of the multiplexer control signals MUX1 to MUX5, the magnitude of the bias current Ibias may be as follows: Figure 8 As shown in (a), it gradually increases, or as Figure 8Alternatively, during one horizontal period (1H), in each on period of the multiplexer control signals MUX1 to MUX5, the magnitude of the bias current Ibias may be as follows: Figure 8 As shown in (c), it gradually increases (or decreases) and then gradually decreases (or increases).

[0137] exist Figure 9 In the figure, it is shown that Figure 7 In one embodiment, when the data driver 30 controls the bias current Ibias based on the maximum grayscale difference between the output buffers 3411, 3412, and 3413, the bias current Ibias can be controlled according to Table 7. Figure 9 In another embodiment, when the data driver 30 controls the bias current Ibias based on the average value of the grayscale difference between the output buffers 3411, 3412 and 3413, the bias current Ibias can be controlled according to Table 9. Figure 9 The bias current Ibias is controlled as shown in (b).

[0138] According to the data driver and the display device including the same according to the embodiment, the consumption power of the display device can be reduced by changing the consumption power of the data driver during one horizontal period.

[0139] Furthermore, according to the data driver and the display device including the same according to the embodiment, efficient low-power driving can be achieved by changing the consumption power of the output buffer in the data driver according to the grayscale difference.

[0140] Those skilled in the art to which the present disclosure belongs will be able to understand that the present disclosure can be carried out in other specific forms without changing its technical spirit or basic characteristics. Therefore, it should be understood that the above-mentioned embodiments are illustrative in all aspects and not restrictive. The scope of the present disclosure is defined by the appended claims to be described below rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be interpreted as being included within the scope of the present disclosure.

Claims

1. A display device, comprising: A display panel having a plurality of sub-pixels arranged thereon; a data driver configured to convert image data input from the outside and provide data voltages to the plurality of sub-pixels through a plurality of data lines; as well as a multiplexer connected between the data driver and the plurality of data lines and comprising a plurality of switching elements controlled by a plurality of multiplexer control signals, wherein the data driver includes a plurality of output buffers, each of the plurality of output buffers being configured to amplify and output the data voltage based on a bias current supplied to the output buffer, and The data driver controls the bias current supplied to each of the plurality of output buffers based on a grayscale difference value of the image data supplied to the plurality of sub-pixels.

2. The display device according to claim 1, wherein The data driver further includes: a register unit configured to generate a sampling signal using a data driving control signal applied from the outside; a latch unit configured to sequentially latch the image data in response to the sampling signal and sequentially output the image data; a digital-to-analog converter configured to convert the image data output from the latch unit into a gamma compensation voltage and generate the data voltage; a calculation unit configured to determine the grayscale difference value of the image data sequentially output from the latch unit; and The power control circuit is configured to generate the bias current having an amplitude corresponding to the grayscale difference and apply the bias current to the plurality of output buffers.

3. The display device according to claim 2, wherein: The power control circuit reduces the amplitude of the bias current when the grayscale difference is small, and increases the amplitude of the bias current when the grayscale difference is large.

4. The display device according to claim 3, wherein The power consumption of the output buffer changes in proportion to the magnitude of the bias current.

5. The display device according to claim 2, wherein The calculation unit determines the grayscale difference value of the image data sequentially output for each of the plurality of output buffers, and The power control circuit independently adjusts the magnitude of the bias current of each of the plurality of output buffers in response to the grayscale difference value. The display device according to claim 2 , wherein: The calculation unit compares the grayscale difference values ​​with respect to a plurality of output buffers configured to output the data voltages to sub-pixels having the same color, and The power control circuit adjusts the magnitudes of the bias currents of the plurality of output buffers according to a result of the comparison.

7. The display device according to claim 6, wherein: The calculation unit determines a maximum value or an average value of the grayscale difference values ​​for the plurality of output buffers configured to output the data voltages to the sub-pixels having the same color, and The power control circuit adjusts the magnitude of the bias current of the plurality of output buffers configured to output the data voltage to the sub-pixels having the same color in response to the maximum value or the average value of the grayscale difference values.

8. The display device according to claim 2, wherein: One of the plurality of output buffers is connected to some sub-pixels having the same color through the plurality of switching elements of the multiplexer.

9. The display device according to claim 8, wherein One of the plurality of switching elements is connected between the one of the plurality of output buffers and one sub-pixel.

10. The display device according to claim 9, wherein The plurality of switch elements connected to the one of the plurality of output buffers are controlled by multiplexer control signals having different on-periods. The display device according to claim 10 , wherein: When one multiplexer control signal is turned on, the data voltages are output from the plurality of output buffers to sub-pixels having different colors constituting one unit pixel.

12. A display device comprising: A display panel, the display panel comprising a plurality of sub-pixels; a data driver configured to convert image data input from the outside and provide data voltages to the plurality of sub-pixels through a plurality of data lines; as well as a multiplexer connected between the data driver and the plurality of data lines and comprising a plurality of switching elements controlled by a plurality of multiplexer control signals, An output buffer is connected to some sub-pixels of the plurality of sub-pixels having the same color through the plurality of switching elements of the multiplexer.

13. The display device according to claim 12, wherein: One of the plurality of switching elements is connected between the output buffer and a sub-pixel.

14. The display device according to claim 13, wherein: The plurality of switch elements connected to the one output buffer are controlled by multiplexer control signals having different on-periods.

15. The display device according to claim 14, wherein When one multiplexer control signal is turned on, the data voltages are output from the plurality of output buffers to sub-pixels having different colors constituting one unit pixel.

16. The display device according to claim 15, wherein The data driver has a consumption power that changes based on a grayscale difference value of the image data provided to the plurality of sub-pixels.

17. The display device according to claim 16, wherein: The data driver further includes: a register unit configured to generate a sampling signal using a data driving control signal applied from the outside; a latch unit configured to sequentially latch the image data in response to the sampling signal and sequentially output the image data; a digital-to-analog converter configured to convert the image data output from the latch unit into a gamma compensation voltage and generate the data voltage; a plurality of output buffers configured to amplify and output the data voltage based on a bias current; a calculation unit configured to determine the grayscale difference value of the image data sequentially output from the latch unit; and The power control circuit is configured to generate the bias current having an amplitude corresponding to the grayscale difference and apply the bias current to the plurality of output buffers.

18. The display device according to claim 17, wherein: The power control circuit reduces the amplitude of the bias current when the grayscale difference is small, and increases the amplitude of the bias current when the grayscale difference is large.

19. The display device according to claim 17, wherein: The calculation unit determines the grayscale difference value of the image data sequentially output for each of the plurality of output buffers, and The power control circuit independently adjusts the magnitude of the bias current of each of the plurality of output buffers in response to the grayscale difference value.

20. The display device according to claim 17, in, The calculation unit determines a maximum value or an average value of the grayscale difference values ​​for a plurality of output buffers configured to output the data voltages to sub-pixels having the same color, and The power control circuit adjusts the magnitude of the bias current of the plurality of output buffers configured to output the data voltage to the sub-pixels having the same color in response to a maximum value or an average value of the grayscale difference values.

Images