Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a first gate drive circuit which comprises a plurality of first shift register units in cascade connection, and the first shift register units are used for generating first scanning signals; the second gate drive circuit comprises a plurality of second shift register units which are in cascade connection, and the second shift register units are used for generating second scanning signals; in the first driving mode, the first gate driving circuit is used for providing a first scanning signal for a pixel row corresponding to the first display area, and the second gate driving circuit is used for providing a second scanning signal for a pixel row corresponding to the second display area; the refresh rate of the first scanning signal is different from the refresh rate of the second scanning signal in the first driving mode. According to the embodiment of the invention, the partition refreshing of the display panel can be realized, and the partition position can be flexibly adjusted.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Currently, with the continuous development of display technology, display panels can now implement a zoned refresh function. After the display panel is divided into multiple display areas, different display areas can apply different refresh rates, thereby reducing the overall power consumption of the display panel.

[0003] When implementing the partitioned refresh function, the related art cannot flexibly adjust the range of two display areas with different refresh rates. Moreover, during the partitioned refresh process, the refresh rate of the display area with the lower refresh rate can only be set to a fixed refresh rate, which cannot meet the actual needs of the partitioned refresh function.

[0004] Therefore, how to achieve flexible adjustment of the display area for partition refresh and flexible adjustment of the refresh rates of different display areas has become a technical problem that those skilled in the art urgently need to solve. Summary of the Invention

[0005] The embodiments of the present application provide a display panel and a display device, which can improve the technical problems of the inability to flexibly adjust partitions and the inability to flexibly adjust the refresh rate within each partition in the partition refresh function.

[0006] In a first aspect, an embodiment of the present application provides a display panel, comprising:

[0007] A first gate driving circuit includes a plurality of first shift register units connected in cascade, the first shift register units being used to generate a first scanning signal;

[0008] A second gate driving circuit includes a plurality of second shift register units connected in cascade, and the second shift register units are used to generate a second scanning signal;

[0009] In the first driving mode, the first gate driving circuit is used to provide a first scanning signal to the pixel rows corresponding to the first display area, and the second gate driving circuit is used to provide a second scanning signal to the pixel rows corresponding to the second display area; in the first driving mode, the refresh rate of the first scanning signal is different from the refresh rate of the second scanning signal.

[0010] In a second aspect, an embodiment of the present application provides a display device, including the display panel according to the first aspect, and further comprising:

[0011] A driver chip, the driver chip is used to receive a first refresh rate parameter corresponding to the first display area, a second refresh rate parameter corresponding to the second display area, and a split-screen configuration parameter; wherein the split-screen configuration parameter is used to determine the first display area and the second display area;

[0012] When the first refresh rate parameter is different from the second refresh rate parameter, the driving chip is used to control the first gate driving circuit to provide a first scanning signal to the pixel row corresponding to the first display area, and control the second gate driving circuit to provide a second scanning signal to the pixel row corresponding to the second display area in a single data frame.

[0013] Compared with the related art, the display panel and display device provided in the embodiment of the present application can independently generate a first scan signal and a second scan signal with different refresh rates by setting a first gate drive circuit and a second gate drive circuit. In the first drive mode, the display panel can provide the first scan signal to the first display area and the second scan signal to the second display area, so that the first display area and the second display area can realize the partition refresh function. Moreover, when the scan signal is output row by row, if the output scan signal is the first scan signal, the corresponding pixel row belongs to the first display area, and if the output scan signal is the second scan signal, the corresponding pixel row belongs to the second display area. Therefore, after determining the pixel rows corresponding to the first display area and the second display area respectively, the scan signal output row by row is switched in the first pixel row of the latter display area to realize the partitioning of the display area. The display panel can flexibly select the switching time of the scan signal according to actual needs to realize flexible adjustment of the partition. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 is a structural diagram of a display panel provided in one embodiment of the present application;

[0016] Figure 2 is a structural diagram of a display panel provided by another embodiment of the present application;

[0017] Figure 3 is a schematic structural diagram of a single pixel row of a display panel provided in one embodiment of the present application;

[0018] Figure 4 is a schematic structural diagram of a single pixel row provided by another embodiment of the present application;

[0019] Figure 5 is a structural diagram of a single pixel row provided by another embodiment of the present application;

[0020] Figure 6 This is one of the structural diagrams of a single pixel row provided in yet another embodiment of the present application;

[0021] Figure 7 is a structural diagram of a display panel provided in another embodiment of the present application;

[0022] Figure 8 is a schematic structural diagram of a display device provided in one embodiment of the present application;

[0023] Figure 9 is a structural diagram of a display panel provided in yet another embodiment of the present application;

[0024] Figure 10 1 is a schematic diagram of signal transmission of a display device provided in one embodiment of the present application;

[0025] Figure 11 This is the second structural diagram of a single pixel row provided in yet another embodiment of the present application.

[0026] In the attached figure:

[0027] 11. First display area; 12. Second display area; 13. First non-display area; 14. Second non-display area; 20. Pixel circuit; 31. First gate drive circuit; 32. Second gate drive circuit; 41. First switch unit; 42. Second switch unit; 50. Reset unit; Switch, selection signal line; Switch1, first selection signal line; Switch2, second selection signal line; RST, reset signal line; M1, first reset transistor; M2, second reset transistor. DETAILED DESCRIPTION

[0028] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0029] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

[0030] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The embodiments will be described in detail below with reference to the accompanying drawings.

[0031] Currently, with the continuous development of display technology, display panels can now implement a zoned refresh function. After the display panel is divided into multiple display areas, different display areas can apply different refresh rates, thereby reducing the overall power consumption of the display panel.

[0032] When implementing the partitioned refresh function, the related art cannot flexibly adjust the range of two display areas with different refresh rates. Moreover, during the partitioned refresh process, the refresh rate of the display area with the lower refresh rate can only be set to a fixed refresh rate, which cannot meet the actual needs of the partitioned refresh function.

[0033] Therefore, how to achieve flexible adjustment of the display area for partition refresh and flexible adjustment of the refresh rates of different display areas has become a technical problem that those skilled in the art urgently need to solve.

[0034] In order to solve the above technical problems, the embodiments of the present application provide a display panel and a display device. The display panel provided by the embodiments of the present application is first introduced below.

[0035] Figure 1 A schematic diagram of the structure of a display panel provided by an embodiment of the present application is shown. The display panel includes a first gate driving circuit 31 and a second gate driving circuit 32.

[0036] The first gate driver circuit 31 may include a plurality of cascade-connected first shift register units VSR1, which may generate a first scan signal. Upon receiving a valid signal level of the first scan signal, the pixel circuit 20 in the display panel may implement a data write function, writing the data signal on the data signal line into the pixel circuit 20.

[0037] Similarly, the second gate driver circuit 32 may include a plurality of cascade-connected second shift register units VSR2, which may generate a second scanning signal. When the pixel circuits 20 in the same row of the display panel receive a valid signal level of the second scanning signal, they may also implement a data writing function, writing the data signal on the data signal line into the pixel circuits 20.

[0038] The display panel can switch between different drive modes when in normal display. For example, in the first drive mode, the first gate drive circuit 31 can provide a first scan signal to the pixel row corresponding to the first display area 11, and the second gate drive circuit 32 can provide a second scan signal to the pixel row corresponding to the second display area 12. The refresh rate of the first scan signal in the first drive mode is different from the refresh rate of the second scan signal. Therefore, in the first drive mode, the refresh rate of the first display area 11 is consistent with the refresh rate of the first scan signal, and the refresh rate of the second display area 12 is consistent with the refresh rate of the second scan signal.

[0039] In the first driving mode, the entire platform where the display panel is located can send a first refresh rate parameter and a second refresh rate parameter to the driver chip. The driver chip can generate corresponding first clock signals and second clock signals according to the first refresh rate parameter and the second refresh rate parameter, respectively. The first clock signal can be used as the clock signal of the first gate driver circuit 31, and the second clock signal can be used as the clock signal of the second gate driver circuit 32. Therefore, the first scanning signal output by the first gate driver circuit 31 is a scanning signal with a first refresh rate, and the second scanning signal output by the second gate driver circuit 32 is a scanning signal with a second refresh rate.

[0040] It should be noted that when the first gate circuit outputs the first scan signal row by row, the effective signal level of the first scan signal output by each first shift register unit VSR1 can be output to the scan signal line corresponding to the first shift register unit VSR1 and the next first shift register unit VSR1 in the cascade. When outputting to the corresponding scan signal line, the pixel row corresponding to the scan signal line is in the refresh frame in this data frame. Similarly, when the second gate circuit outputs the second scan signal row by row, the effective signal level of the second scan signal output by each second shift register unit VSR2 can be output to the scan signal line corresponding to the second shift register unit VSR2 and the next second shift register unit VSR2 in the cascade.

[0041] Take the maximum refresh rate supported by the display panel as 120Hz, and the refresh rate of the first display area 11 in the first driving mode as 120Hz, and the refresh rate of the second display area 12 as 60Hz as an example. In the 120 data frames within 1 second, the driving chip can generate corresponding first clock signals in all 120 data frames according to the first refresh rate parameter. At this time, in each data frame, the first gate driving circuit 31 can output the first scanning signal row by row, so that the pixel row that can receive the first scanning signal is refreshed at a refresh rate of 120Hz. Similarly, the driving chip can generate corresponding second clock signals in 60 data frames out of 120 data frames according to the second refresh rate parameter. Therefore, in every two data frames, the second gate driving circuit 32 can output the second scanning signal in one of the data frames, so that the pixel row that receives the second scanning signal is refreshed at a refresh rate of 60Hz.

[0042] In the first driving mode, pixel rows receiving the first scanning signal can be refreshed at the first refresh rate, while pixel rows receiving the second scanning signal can be refreshed at the second refresh rate. Therefore, based on the boundary pixel row between the first display area 11 and the second display area 12, the provided scanning signals can be switched to achieve partitioned refresh of the first display area 11 and the second display area 12.

[0043] Taking a display panel with 1080 pixel rows as an example, the entire platform can determine the first display area 11 and the second display area 12 based on the actual image content being played. For example, if the upper half of the image content is video content and the lower half is text content, the video content can be determined to correspond to rows 1-300 of the 1080 pixel rows, and the text content can be determined to correspond to rows 301-1080 of the 1080 pixel rows. When the first gate driver circuit 31 and the second gate driver circuit 32 generate the first scan signal and the second scan signal, respectively, the first shift register units VSR1 in the first gate driver circuit 31 and the second shift register units VSR2 in the second gate driver circuit 32 transmit the effective signal levels of the scan signals downward at the same speed. Therefore, during the row-by-row scanning process, when providing scan signals to the pixels in rows 1-300, the display panel can control the first gate driver circuit 31 to sequentially provide the first scan signals to the 300 scan signal lines corresponding to the pixel rows 1-300. At this time, each first shift register unit VSR1 in the first gate driver circuit 31 can also transmit the first scan signal to the downstream. At this time, each second shift register unit VSR2 in the second gate driver circuit 32 can only transmit the second scan signal to the downstream, and cannot provide the second scan signal to the 300 scan signal lines corresponding to the pixel rows 1-300. Therefore, the pixels in rows 1-300 can be displayed at the first refresh rate.

[0044] When providing scan signals to the pixels in row 301, the display panel can switch the gate driver circuit providing the scan signal lines from the first gate driver circuit 31 to the second gate driver circuit 32. Starting from row 301, the second gate driver circuit 32 can sequentially provide the second scan signals to the scan signal lines corresponding to the pixels in rows 301-1080. At this time, each first shift register unit VSR1 in the first gate driver circuit 31 can only transmit the first scan signal to the downstream level. Therefore, the pixels in rows 301-1080 can be displayed at the second refresh rate.

[0045] In the above embodiment, the pixels in the 1st to 300th rows are the first display area 11 , and the pixels in the 301st to 1080th rows are the second display area 12 .

[0046] In this embodiment, by setting the first gate drive circuit 31 and the second gate drive circuit 32, the first scan signal and the second scan signal with different refresh rates can be generated independently. In the first drive mode, the display panel can provide the first scan signal to the first display area 11 and the second scan signal to the second display area 12, so that the first display area 11 and the second display area 12 can realize the partition refresh function. Moreover, when the scan signal is output row by row, if the output scan signal is the first scan signal, the corresponding pixel row belongs to the first display area 11, and if the output scan signal is the second scan signal, the corresponding pixel row belongs to the second display area 12. Therefore, after determining the pixel rows corresponding to the first display area 11 and the second display area 12, respectively, the scan signal output row by row is switched in the first pixel row of the latter display area, thereby realizing the partitioning of the display area. The display panel can flexibly select the switching time of the scan signal according to actual needs to realize flexible adjustment of the display area for partition refresh.

[0047] Please refer to Figure 2 In some embodiments, the display panel may include a plurality of first switch units 41 and a plurality of second switch units 42 .

[0048] The first switch unit 41 may be connected between the output end of the corresponding first shift register unit VSR1 and the scan signal line, and the second switch unit 42 may be connected between the output end of the corresponding second shift register unit VSR2 and the scan signal line.

[0049] When both the first gate driving circuit 31 and the second gate driving circuit 32 generate scan signals row by row, if the first switching unit 41 is turned on, the scan signal received by the pixel row corresponding to the turned-on first switching unit 41 is the first scan signal. Similarly, if the second switching unit 42 is turned on, the scan signal received by the pixel row corresponding to the turned-on second switching unit 42 is the second scan signal.

[0050] It can be understood that, for the same scan signal line, if the first switch unit 41 is turned on, the scan signal line receives the first scan signal; if the second switch unit 42 is turned on, the scan signal line receives the second scan signal; if both the first switch unit 41 and the second switch unit 42 are turned on, the scan signal line receives bilateral drive of the first scan signal and the second scan signal.

[0051] In some embodiments, in the first driving mode, the first switch unit 41 can be turned on during the scanning signal writing phase corresponding to the first display area 11 , and the second switch unit 42 can be turned on during the scanning signal writing phase corresponding to the second display area 12 .

[0052] Taking the above-mentioned display panel as an example, where the display panel includes 1080 pixel rows, when the entire platform determines that the first display area 11 includes pixels in rows 1-300 and the second display area 12 includes pixels in rows 301-1080, it can send the split-screen configuration parameters of the two display areas to the driver chip. The driver chip can then determine the boundary pixel row between the two display areas based on the split-screen configuration parameters. For example, it can determine that the boundary pixel row corresponding to the switching of the scan signal is row 301. That is, when the multiple first shift registers VSR1 and the multiple second shift registers VSR2 synchronously generate the first scan signal and the second scan signal row by row, it can be determined that the scan signal writing phase corresponding to the row-by-row scanning from row 1 to row 300 is the scan signal writing phase corresponding to the first display area 11. During this phase, all first switch units 41 in the display panel receive the on signal, and starting from row 1, each pixel row receives the first scan signal sequentially through the first switch unit 41. When the scan reaches row 300, all first switch units 41 are still in the on state, and the pixels in row 300 also receive the first scan signal.

[0053] When scanning row 301, all first switch units 41 in the display panel are turned off, and all second switch units 42 are turned on. That is, starting from row 301, each pixel row receives the second scan signal through the second switch units 42 one by one. Therefore, in any image frame, the first display area 11 can be refreshed at the first refresh rate of the first scan signal, while the second display area 12 can be refreshed at the second refresh rate of the second scan signal, ultimately achieving a partitioned refresh function.

[0054] The display panel can achieve flexible adjustment of the partitioning by adjusting the pixel row that separates the two display areas. For example, if the display panel turns off all first switch units 41 and turns on all second switch units 42 when scanning row by row to row 541, the pixels in rows 1-540 are refreshed at the first refresh rate, and the pixels in rows 541-1080 are refreshed at the second refresh rate. At this time, the first display area 11 is the pixels in rows 1-540, and the second display area 12 is the pixels in rows 541-1080.

[0055] In a single data frame, the sum of the scan signal writing phases of the first display area 11 and the second display area 12 is the duration of scanning from the first row to the last row. For example, when the maximum refresh rate supported by the display panel is 120Hz, the duration of scanning from the first row to the last row in a single data frame is approximately 8.33ms. In each data frame, the scan signal writing phase can be divided into a scan signal writing phase corresponding to the first display area 11 and a scan signal writing phase corresponding to the second display area 12. In the scan signal writing phases corresponding to the two, the first switch unit 41 and the second switch unit 42 can be turned on respectively to provide the corresponding display areas with scan signals of the corresponding refresh rates.

[0056] As an optional embodiment, in a single data frame, multiple first display areas 11 or second display areas 12 can also be divided. For example, if the split-screen display parameters indicate that rows 1-100 are the second display area 12, rows 101-300 are the first display area 11, and rows 301-1080 are the second display area 12. Then in a single data frame, when scanning from row 1 to row 100, the second switch unit 42 is controlled to be turned on; when scanning from row 101 to row 300, the first switch unit 41 is controlled to be turned on; when scanning from row 301 to row 1080, the second switch unit 42 is controlled to be turned on. At this time, the two second display areas 12 are separated by the first display area 11, but both second display areas 12 can be displayed at the second refresh rate.

[0057] Please refer to Figure 3 In some embodiments, the display panel may further include a selection signal line Switch.

[0058] Taking the first switch unit 41 and the second switch unit 42 corresponding to a single row of pixels as an example, the selection signal line Switch can be connected to the control end of the first switch unit 41 and the control end of the second switch unit 42 respectively.

[0059] In the first driving mode, the selection signal line Switch can provide a first conduction signal during the scanning signal writing phase corresponding to the first display area 11, and provide a second conduction signal during the scanning signal writing phase corresponding to the second display area 12. The first conduction signal can drive the first switch unit 41 to conduct, and the second conduction signal can drive the second switch unit 42 to conduct.

[0060] Taking a single data frame as an example, the scan signal writing phase corresponding to the first display area 11 can be the phase corresponding to outputting scan signals row by row starting from row 1 to row 300, and the scan signal writing phase corresponding to the second display area 12 can be the phase corresponding to outputting scan signals row by row starting from row 301 to row 1080. Therefore, when the first gate driver circuit 31 and the second gate driver circuit 32 synchronously output scan signals, a first on-signal can be output by selecting the signal line Switch during the scan signal writing phase corresponding to the first display area 11. At this time, all first switch units 41 are turned on, all second switch units 42 are turned off, and the first gate driver circuit 31 outputs the first scan signal row by row starting from row 1 to the corresponding scan signal line, so that the pixel circuits 20 in the first display area 11 are refreshed at the first refresh rate. At this time, each second shift register unit VSR2 in the second gate driver circuit 32 can still transmit the second scan signal to the downstream layer row by row, but cannot provide the second scan signal to the corresponding scan signal line.

[0061] Similarly, when entering the scanning signal writing stage corresponding to the second display area 12, the second conduction signal is output by selecting the signal line Switch. At this time, all the second switch units 42 are turned on, and all the first switch units 41 are turned off. The second gate drive circuit 32 outputs the second scanning signal row by row starting from the 301st row, so that the pixel circuit 20 in the second display area 12 is refreshed at the second refresh rate.

[0062] Please refer to Figure 4 In some embodiments, the display panel may further include a reset unit 50 .

[0063] The reset unit 50 is connected between the reset signal line RST and the selection signal line Switch. The reset signal provided by the reset signal line RST can drive the first switch unit 41 and the second switch unit 42 to be disconnected.

[0064] In a single data frame, in addition to the first display area 11 and the second display area 12, the first gate drive circuit 31 and the second gate drive circuit 32 also need to provide corresponding scan signals to the blanking display area blank. However, the blanking display area does not actually correspond to a pixel row. Therefore, in the first driving mode, when the first gate drive circuit 31 and the second gate drive circuit 32 synchronously output scan signals to the blanking display area row by row, the reset unit 50 can be controlled to be turned on to transmit the reset signal output by the reset signal line RST to the selection signal line Switch. The first switch unit 41 and the second switch unit 42 connected to the selection signal line Switch are both kept in the off state under the reset signal, so that the first gate drive circuit 31 and the second gate drive circuit 32 will not output the scan signal to the scan signal line even if the scan signal is generated during the scan writing interval of the blanking display area.

[0065] In some embodiments, the first switch unit 41 may be an N-type transistor or a P-type transistor, and the second switch unit 42 may be the other of the N-type transistor and the P-type transistor.

[0066] Please refer to Figure 5 , taking the first switch unit 41 as an N-type transistor and the second switch unit 42 as a P-type transistor as an example. In a single data frame under the first driving mode, during the scanning signal writing phase corresponding to the first display area 11, the first switch unit 41 and the second switch unit 42 both receive a high-level signal. At this time, all the first switch units 41 are turned on, and all the second switch units 42 are turned off. The first scanning signal generated row by row by the first gate drive circuit 31 can be sequentially transmitted to the scanning signal line of each pixel row through the first switch unit 41 corresponding to each pixel row, thereby enabling the first display area 11 to display at the first refresh rate.

[0067] Similarly, in the scanning signal writing phase corresponding to the second display area 12, the first switch unit 41 and the second switch unit 42 both receive low-level signals. At this time, all the second switch units 42 are turned on, and all the first switch units 41 are turned off. The second scanning signals generated row by row by the second gate drive circuit 32 can be transmitted to the scanning signal lines of each pixel row in turn through the second switch units 42 corresponding to each pixel row, so that the second display area 12 can be displayed at the second refresh rate.

[0068] Please continue to refer to Figure 5 In some embodiments, the selection signal line Switch may include a first selection signal line Switch1 and a second selection signal line Switch2.

[0069] The first selection signal line Switch1 is connected to the control end of the first switch unit 41 , and the second selection signal line Switch2 is connected to the control end of the second switch unit 42 .

[0070] In the first driving mode, the first selection signal line Switch1 and the second selection signal line Switch2 can provide a high-level signal during the scanning signal writing phase corresponding to the first display area 11, and provide a low-level signal during the scanning signal writing phase corresponding to the second display area 12. That is, in the first driving mode, the first selection signal line Switch1 and the second selection signal line Switch2 provide the same level signal, and the conduction states of the first switch unit 41 and the second switch unit 42 are opposite.

[0071] The display panel can also switch to a second drive mode. The second drive mode can be a normal drive mode without split screens. In the second drive mode, the first scan signal generated by the first gate drive circuit 31 and the second scan signal generated by the second gate drive circuit 32 have the same refresh rate. In this case, both the first display area 11 and the second display area 12 in the display panel are driven by bilateral VSR.

[0072] Because the first switch unit 41 and the second switch unit 42 are different types of transistors, to keep both the first switch unit 41 and the second switch unit 42 in the on state, the first selection signal line Switch1 and the second selection signal line Switch2 need to provide signals of different levels. For example, during the scanning signal writing phase corresponding to the first display area 11 and the second display area 12, the first selection signal line Switch1 provides a high-level signal, and the second selection signal line Switch2 provides a low-level signal, so that both the first switch unit 41 and the second switch unit 42 are in the on state.

[0073] Please refer to Figure 6 In some embodiments, the reset unit 50 may include a first reset transistor M1 and a second reset transistor M2.

[0074] The first reset transistor M1 is connected between the first reset signal line RST1 and the first selection signal line Switch1 , and the second reset transistor M2 is connected between the second reset signal line RST2 and the second selection signal line Switch2 .

[0075] The first reset signal line RST1 provides a first reset signal that is one of the positive power signal VDD and the negative power signal VSS. The second reset signal line RST2 provides a second reset signal that is the other of the positive power signal VDD and the negative power signal VSS.

[0076] The first reset signal provided by the first reset signal line RST1 can be determined based on the transistor type of the first switch unit 41. For example, if the first switch unit 41 is an N-type transistor, Figure 6 As shown, since the first reset signal can drive the first switch unit 41 to maintain the off state, the first reset signal can be a cut-off signal for an N-type transistor, that is, a negative power supply signal VSS. In this case, the second reset signal provided by the second reset signal line RST2 can be a positive power supply signal VDD. Conversely, if the first switch unit 41 is a P-type transistor, the first reset signal can be the positive power supply signal VDD, and the second reset signal can be the negative power supply signal VSS.

[0077] In some embodiments, in the second driving mode, the first gate driving circuit 31 may provide a first scanning signal to the first display area 11 and the second display area 12. The second gate driving circuit 32 may provide a second scanning signal to the first display area 11 and the second display area 12. The refresh rates of the first scanning signal and the second scanning signal are the same.

[0078] The second driving mode may be a normal driving mode. In the second driving mode, the first scanning signal generated by the first gate driving circuit 31 and the second scanning signal generated by the second gate driving circuit 32 have the same refresh rate.

[0079] Please refer to Figure 7 In some embodiments, the non-display area of ​​the display panel includes a first non-display area 13 and a second non-display area 14. One side of the display area along the pixel row direction is the first non-display area 13, and the other side of the display area along the pixel row direction is the second non-display area 14.

[0080] The first gate drive circuit 31 can be disposed in the first non-display area 13, and the second gate drive circuit 32 can be disposed in the second non-display area 14. That is, the first gate drive circuit 31 and the second gate drive circuit 32 are disposed on either side of the display area. In the second drive mode, both the first display area 11 and the second display area 12 of the display panel are driven by bilateral VSR.

[0081] See Figure 8 The embodiment of the present application also provides a display device 1000, which can be a PC, a TV, a monitor, a mobile terminal, a tablet computer, a wearable device, etc. The display device 1000 can include the display panel 100 provided in the embodiment of the present application.

[0082] Please refer to Figure 9 The display device may further include a driving chip DDIC, and the driving chip DDIC may be disposed in a binding area in the non-display area.

[0083] The driver chip DDIC can receive a first refresh rate parameter and a second refresh rate parameter sent by the display device. The first refresh rate parameter corresponds to the first display area 11, and the second refresh rate parameter corresponds to the second display area 12. The driver chip DDIC can also receive split-screen configuration parameters sent by the display device. Based on the received split-screen configuration parameters, the driver chip DDIC can divide the first display area 11 into the second display area 12.

[0084] When the first refresh rate parameter and the second refresh rate parameter are different, it indicates that the display panel needs to operate in the first drive mode, that is, the first display area 11 and the second display area 12 display at different refresh rates. In this case, the driver chip DDIC can, in a single data frame, control the first switch unit 41 to conduct when it is necessary to provide a scan signal to the pixel row corresponding to the first display area 11, so that the first gate drive circuit 31 provides the first scan signal; and control the second switch unit 42 to conduct when it is necessary to provide a scan signal to the pixel row corresponding to the second display area 12, so that the second gate drive circuit 32 provides the second scan signal.

[0085] As an optional embodiment, take the maximum refresh rate supported by the display panel as 144 Hz, the first refresh rate as 144 Hz, and the second refresh rate as 60 Hz as an example. Since the first refresh rate is consistent with the maximum refresh rate, the first display area 11 is a refresh frame in each data frame. The ratio of the second refresh rate to the maximum refresh rate is 5:12, so the second display area 12 can have 5 refresh frames and 7 hold frames in 12 consecutive data frames.

[0086] As an example, taking the first five of every twelve data frames of the second display area 12 as refresh frames, the driver chip DDIC can provide a first clock signal to the first gate driver circuit 31 in each of the twelve data frames according to the first refresh rate parameter. The driver chip DDIC can also provide a second clock signal to the second gate driver circuit 32 in the first five of the twelve data frames according to the second refresh rate parameter. It is understood that in order to enable the first gate driver circuit 31 and the second gate driver circuit 32 to synchronously output scan signals row by row in a single data frame, the first clock signal and the second clock signal can be synchronization signals.

[0087] Taking the first of the 12 data frames as an example, since both the first gate drive circuit 31 and the second gate drive circuit 32 receive valid clock signals, they can synchronously generate scan signals row by row. Starting from row 1, all first switch units 41 are in the on state, and the first gate drive circuit 31 can provide the first scan signal row by row, so that each pixel row in the first display area 11 is sequentially written with data signals, achieving refresh. Starting from row 301, all second switch units 42 are in the on state, and the second gate drive circuit 32 can provide the second scan signal row by row, so that each pixel row in the second display area 12 is sequentially written with data signals, achieving refresh. That is, in the first data frame, both the first display area 11 and the second display area 12 are refresh frames.

[0088] Taking the sixth frame as an example, only the first gate drive circuit 31 can receive a valid clock signal, and the second gate drive circuit 32 cannot generate scan signals row by row. Therefore, starting from row 1, all first switch units 41 are in the on state, and the first gate drive circuit 31 can still provide the first scan signal row by row, so that each pixel row in the first display area 11 is written with data signals in sequence to achieve refresh. However, starting from row 301, when all second switch units 42 are in the on state, the second gate drive circuit 32 cannot generate the second scan signal row by row, and therefore each pixel row in the second display area 12 does not receive a valid scan signal. That is, in the sixth data frame, the first display area 11 is a refresh frame, and the second display area 12 is a hold frame.

[0089] It can be understood that, in every 12 data frames, the first display area 11 includes 12 refresh frames, and the second display area 12 includes 5 refresh frames and 7 hold frames. If the maximum refresh rate of the display panel is 144 Hz, then in 144 data frames within 1 second, the first display area 11 has 144 refresh frames, and the second display area 12 has 60 refresh frames. Therefore, the first display area 11 displays at the first refresh rate of 144 Hz, and the second display area 12 displays at the second refresh rate of 60 Hz.

[0090] In some embodiments, the driving chip DDIC may be connected to the first selection signal line Switch1 , the second selection signal line Switch2 , the gate of the first reset transistor M1 , and the gate of the second reset transistor M2 .

[0091] When the first refresh rate parameter and the second refresh rate parameter are different, in a single data frame, the driver chip DDIC can provide a first turn-on signal to the first selection signal line Switch1 and the second selection signal line Switch2 during the scan signal writing phase corresponding to the first display area 11, so as to turn on all first switch units 41 and turn off all second switch units 42. The driver chip DDIC can also provide a second turn-on signal to the first selection signal line Switch1 and the second selection signal line Switch2 during the scan signal writing phase corresponding to the second display area 12, so as to turn on all second switch units 42 and turn off all first switch units 41.

[0092] During the scanning signal writing phase corresponding to the blanked display area in a single data frame, the driving chip DDIC can also provide a reset turn-on signal to the gate of the first reset transistor M1 and the gate of the second reset transistor M2, so that the first switch unit 41 and the second switch unit 42 remain in the off state under the drive of the reset signal.

[0093] It can be understood that when the scanning signal writing phase corresponding to the blanked display area ends and the scanning signal writing phase corresponding to the first display area 11 in the next data frame begins, the driving chip DDIC can reset the reset conduction signal. At this time, the first reset transistor M1 and the second reset transistor M2 are disconnected, and the on-off state of the first switch unit 41 and the second switch unit 42 is not controlled by the reset signal, but is controlled by the first conduction signal or the second conduction signal.

[0094] In some embodiments, when the first refresh rate parameter and the second refresh rate parameter are the same, it indicates that the display panel needs to operate in the second driving mode. At this time, the driver chip DDIC can provide a first conduction signal to the first selection signal line Switch1 and a second conduction signal to the second selection signal line Switch2 in a single data frame. That is, in a single data frame under the second mode, all first switch units 41 are in the on state based on the first conduction signal. All second switch units 42 are also in the on state based on the second conduction signal. The first gate drive circuit 31 and the second gate drive circuit 32 can provide the first scan signal and the second scan signal with the same refresh rate. At this time, each pixel row is equivalent to receiving bilateral drive of the first scan signal and the second scan signal.

[0095] As an optional implementation, Figure 10As shown, the mainboard of the display device can send three parameters to the driver chip DDIC, namely the first refresh rate parameter TE1, the second refresh rate parameter TE2 and the split-screen configuration parameter Config. The driver chip DDIC can generate various parameters sent to the panel Panel based on the received parameters. For example, the driver chip DDIC determines the register value of the PARTIAL_B_ON parameter based on whether the first refresh rate parameter TE1 and the second refresh rate parameter TE2 are consistent, and stores it in the first register. When the PARTIAL_B_ON parameter value is 0, it indicates that it is in the second drive mode, and when the PARTIAL_B_ON parameter value is 1, it indicates that it is in the first drive mode. The driver chip DDIC can determine the starting row of the second display area 12 based on the split-screen configuration parameter Config, and store the number of the starting row as the PSL_Y_B parameter in the second register.

[0096] In the first driving mode, since the first refresh rate parameter TE1 and the second refresh rate parameter TE2 are inconsistent, the PARTIAL_B_ON parameter is set to 1 at this time. In each data frame, the driver chip DDIC can use the Switch signal as the first conduction signal or the second conduction signal. For example, when the Switch signal is high, it can be used as the first conduction signal; when the Switch signal is low, it can be used as the second conduction signal. Therefore, when the first row scan signal of each data frame is written, the Switch signal can be set to a high level to provide the first scan signal to the first display area 11 row by row through the first gate drive circuit 31; when the starting row of the second display area 12 corresponding to the PSL_Y_B parameter is scanned row by row, the Switch signal can jump to a low level to provide the second scan signal to the second display area 12 row by row through the second gate drive circuit 32;

[0097] After completing the row-by-row scanning of the first display area 11 and the second display area 12, the driver chip DDIC can set the reset signal SWITCH_RST to an active level to reset the SWITCH signal. Before performing the row-by-row scanning of the next data frame, the reset signal SWITCH_RST can be reset.

[0098] The driver chip DDIC may further provide a first clock signal CK_L and a second clock signal CK_R according to the first refresh rate parameter TE1 and the second refresh rate parameter TE2, respectively.

[0099] like Figure 11 As shown, the first clock signal generated by the driving chip DDIC includes CK_L and XCK_L, and the second clock signal may include CK_R and XCK_R.

[0100] In the first driving mode, the effective frequencies of the first clock signals CK_L and XCK_L are the same as the first refresh rate, and the effective frequencies of the second clock signals CK_R and XCK_R are the same as the second refresh rate.

[0101] In the second driving mode, since the first refresh rate parameter TE1 and the second refresh rate parameter TE2 are consistent, the PARTIAL_B_ON parameter is set to 0 at this time, and the driving chip DDIC can provide the first conduction signal and the second conduction signal to the first gate driving circuit 31 and the second gate driving circuit 32 through the Switch signal, so that both gate driving circuits can provide scanning signals row by row. At this time, the first display area 11 and the second display area 12 are both bilaterally driven.

[0102] The functional blocks shown in the above-described block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of the present application are programs or code segments that are used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier wave. "Machine-readable medium" can include any medium that can store or transmit information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROMs, flash memories, erasable ROMs (EROMs), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.

[0103] It should be noted that, in this article, the terms "comprises", "includes" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or apparatus that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements that are inherent to such process, method, article or apparatus.

[0104] This article uses specific examples to illustrate the principles and implementation methods of this application. The above examples are only used to help understand the method and core ideas of this application. The above are only preferred implementation methods of this application. It should be pointed out that due to the limitations of textual expression, there are objectively infinite specific structures. For ordinary technicians in this technical field, without departing from the principles of this application, they can make several improvements, modifications or changes, and can also combine the above technical features in an appropriate manner; these improvements, modifications, changes or combinations, or the direct application of the concept and technical solution of this application to other occasions without improvement, should be regarded as the scope of protection of this application.

Claims

1. A display panel, characterized in that: include: A first gate driving circuit includes a plurality of first shift register units connected in cascade, wherein the first shift register units are used to generate a first scanning signal; A second gate driving circuit includes a plurality of second shift register units connected in cascade, wherein the second shift register units are used to generate a second scanning signal; In the first driving mode, the first gate driving circuit is used to provide the first scanning signal to the pixel row corresponding to the first display area, and the second gate driving circuit is used to provide the second scanning signal to the pixel row corresponding to the second display area; in the first driving mode, the refresh rate of the first scanning signal is different from the refresh rate of the second scanning signal.

2. The display panel according to claim 1, wherein: The display panel includes: a plurality of first switch units, wherein the first switch units are connected between the output end of the corresponding first shift register unit and the scan signal line; A plurality of second switch units are provided, wherein the second switch units are connected between the output end of the corresponding second shift register unit and the scan signal line.

3. The display panel according to claim 2, wherein: In the first driving mode, the first switch unit is configured to be turned on during a scan signal writing phase corresponding to the first display area, and the second switch unit is configured to be turned on during a scan signal writing phase corresponding to the second display area.

4. The display panel according to claim 3, wherein: The display panel further includes: a selection signal line, the selection signal line being connected to the control end of the first switch unit and the control end of the second switch unit respectively; In the first driving mode, the selection signal line is used to provide a first conduction signal in the scanning signal writing phase corresponding to the first display area, and to provide a second conduction signal in the scanning signal writing phase corresponding to the second display area; wherein, the first conduction signal is used to drive the first switch unit to turn on, and the second conduction signal is used to drive the second switch unit to turn on.

5. The display panel according to claim 4, wherein: The display panel further includes: a reset unit connected between a reset signal line and the selection signal line; wherein the reset signal provided by the reset signal line is used to drive the first switch unit and the second switch unit to be disconnected; In the first driving mode, the reset unit is configured to be turned on during a scanning signal writing phase corresponding to the blanking display area.

6. The display panel according to claim 5, wherein: The first switch unit is one of an N-type transistor and a P-type transistor, and the second switch unit is the other of the N-type transistor and the P-type transistor.

7. The display panel according to claim 6, wherein: The selection signal line includes: a first selection signal line connected to a control terminal of the first switch unit; A second selection signal line is connected to the control end of the second switch unit.

8. The display panel according to claim 7, wherein: The reset unit includes: a first reset transistor connected between the first reset signal line and the first selection signal line; A second reset transistor is connected between a second reset signal line and a second selection signal line; wherein the first reset signal provided by the first reset signal line is one of a positive power supply signal and a negative power supply signal, and the second reset signal provided by the second reset signal line is the other of the positive power supply signal and the negative power supply signal.

9. The display panel according to claim 4, wherein: In the second driving mode, the first gate driving circuit is used to provide the first scanning signal to the first display area and the second display area, and the second gate driving circuit is used to provide the second scanning signal to the first display area and the second display area; in the second driving mode, the refresh rate of the first scanning signal is the same as the refresh rate of the second scanning signal.

10. The display panel according to any one of claims 1 to 9, characterized in that: The display panel further includes a first non-display area and a second non-display area, one side of the display area along the pixel row direction is the first non-display area, and the other side of the display area along the pixel row direction is the second non-display area; The first gate driving circuit is disposed in the first non-display area, and the second gate driving circuit is disposed in the second non-display area.

11. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1 to 10, further comprising: A driver chip, the driver chip being configured to receive a first refresh rate parameter corresponding to the first display area, a second refresh rate parameter corresponding to the second display area, and a split-screen configuration parameter; wherein the split-screen configuration parameter is used to determine the first display area and the second display area; When the first refresh rate parameter is different from the second refresh rate parameter, the driving chip is used to control the first gate driving circuit to provide the first scanning signal to the pixel row corresponding to the first display area, and control the second gate driving circuit to provide the second scanning signal to the pixel row corresponding to the second display area in a single data frame.

12. The display device according to claim 11, wherein The driving chip is connected to the first selection signal line, the second selection signal line, the gate of the first reset transistor and the gate of the second reset transistor; When the first refresh rate parameter is different from the second refresh rate parameter, the driver chip is configured to provide a first conduction signal to the first selection signal line and the second selection signal line during a scan signal writing phase corresponding to the first display area, and provide a second conduction signal to the first selection signal line and the second selection signal line during a scan signal writing phase corresponding to the second display area in a single data frame; The driving chip is further configured to provide a reset turn-on signal to the gate of the first reset transistor and the gate of the second reset transistor during a scanning signal writing phase corresponding to a blanked display area in a single data frame.

13. The display device according to claim 12, wherein: When the first refresh rate parameter is the same as the second refresh rate parameter, the driver chip is configured to provide a first conduction signal to the first selection signal line and a second conduction signal to the second selection signal line in a single data frame.

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