Semiconductor module device

Abstract

The semiconductor module device includes a substrate and at least one semiconductor component disposed on the substrate. Each of the at least one semiconductor component includes a semiconductor chip having first and second electrodes, a first metal layer attached to the first electrode of the semiconductor chip through a conductive connection layer, a second metal layer attached to the second electrode of the semiconductor chip through a conductive connection layer, and a dielectric insulating layer covering a surface of the semiconductor chip, wherein surfaces of the first and second metal layers facing away from the semiconductor chip are not covered by the dielectric insulating layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor module arrangement, in particular a semiconductor module arrangement including one or more semiconductor chips. Background Art

[0002] A power semiconductor module arrangement typically includes at least one semiconductor substrate disposed within a housing. A semiconductor arrangement comprising a plurality of controllable semiconductor elements (e.g., two IGBTs in a half-bridge configuration) or uncontrollable semiconductor elements (e.g., an arrangement of diodes) is disposed on each of the at least one substrate. Each substrate typically includes a substrate layer (e.g., a ceramic layer), a first metallization layer deposited on a first side of the substrate layer, and a second metallization layer deposited on a second side of the substrate layer. The controllable semiconductor elements are, for example, mounted on the first metallization layer. The second metallization layer may optionally be attached to the substrate.

[0003] For example, due to thermal requirements, the distance between adjacent controllable or uncontrollable semiconductor components is often quite large. Furthermore, the overall cost of a semiconductor module can be high in order to meet all thermal, electrical, and environmental requirements. Testing individual semiconductor components can be difficult or even impossible.

[0004] There is a need for a semiconductor module arrangement which is small in size and has improved thermal characteristics and improved environmental stability and in which individual semiconductor elements can be easily tested. Summary of the Invention

[0005] A semiconductor module device includes: a substrate; and at least one semiconductor component arranged on the substrate. Each of the at least one semiconductor component includes: a semiconductor chip having a first electrode and a second electrode; a first metal layer attached to the first electrode of the semiconductor chip via a conductive connection layer; a second metal layer attached to the second electrode of the semiconductor chip via a conductive connection layer; and a dielectric insulating layer covering a surface of the semiconductor chip, wherein surfaces of the first and second metal layers facing away from the semiconductor chip are not covered by the dielectric insulating layer.

[0006] The present invention may be better understood with reference to the following drawings and descriptions. The components in the drawings are not necessarily drawn to scale, but rather emphasize the principles of the present invention. In addition, in the drawings, like reference numerals indicate corresponding components throughout the different views. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a cross-sectional view of a power semiconductor module device.

[0008] Figure 2 is a cross-sectional view of a semiconductor element of a semiconductor module device according to an embodiment of the present disclosure.

[0009] Figure 3 is a cross-sectional view of a semiconductor module device according to an embodiment of the present disclosure.

[0010] Figure 4A A conventional semiconductor module arrangement is schematically shown, and Figure 4B A semiconductor module arrangement according to an embodiment of the present disclosure is schematically shown.

[0011] Figure 5 Schematically shows a cross-sectional view of a semiconductor component of a semiconductor module arrangement according to a further embodiment of the present disclosure.

[0012] Figure 6 is a cross-sectional view of a semiconductor module arrangement according to a further embodiment of the present disclosure.

[0013] Figure 7 is a cross-sectional view of a semiconductor module device according to a further embodiment of the present disclosure.

[0014] Figure 8 is a cross-sectional view of a semiconductor module device according to a further embodiment of the present disclosure.

[0015] Figure 9 is a cross-sectional view of a semiconductor module device according to a further embodiment of the present disclosure.

[0016] Figure 10 is a cross-sectional view of a semiconductor module device according to a further embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] In the following detailed description, reference is made to the accompanying drawings. The accompanying drawings show specific examples in which the invention may be practiced. It will be understood that the features and principles described with respect to the various examples may be combined with each other unless otherwise specifically noted. In the specification and in the claims, designation of certain elements as "first element," "second element," "third element," etc. should not be understood as enumeration. On the contrary, such designations are only used to address different "elements." That is, for example, the presence of a "third element" does not require the presence of a "first element" and a "second element." The wires or electrical connections described herein may be a single conductive element, or may include at least two individual conductive elements connected in series and / or in parallel. The wires and electrical connections may include metal and / or semiconductor materials and may be permanently conductive (i.e., non-switchable).

[0018] refer to Figure 1, shows a cross-sectional view of a power semiconductor module arrangement 100. The power semiconductor module arrangement 100 includes a housing 7 and a substrate 10. The substrate 10 includes a dielectric insulating layer 11, a (structured) first metallization layer 111 attached to the dielectric insulating layer 11, and a (structured) second metallization layer 112 attached to the dielectric insulating layer 11. The dielectric insulating layer 11 is arranged between the first metallization layer 111 and the second metallization layer 112.

[0019] Each of the first metallization layer 111 and the second metallization layer 112 can be composed of or include one of the following materials: copper; a copper alloy; aluminum; an aluminum alloy; or any other metal or alloy that remains solid during operation of the power semiconductor module device. The substrate 10 can be a ceramic substrate, i.e., a substrate in which the dielectric insulating layer 11 is a ceramic (e.g., a thin ceramic layer). The ceramic can be composed of or include one of the following materials: aluminum oxide; aluminum nitride; zirconium oxide; silicon nitride; boron nitride; or any other dielectric ceramic. For example, the dielectric insulating layer 11 can be composed of or include one of the following materials: Al2O3, AlN, SiC, BeO, or Si3N4. For example, the substrate 10 can be, for example, a direct copper bonding (DCB) substrate, a direct aluminum bonding (DAB) substrate, or an active metal brazing (AMB) substrate. Furthermore, the substrate 10 can be an insulated metal substrate (IMS). For example, the insulated metal substrate typically includes a dielectric insulating layer 11 comprising a (filling) material such as epoxy or polyimide. For example, the material of the dielectric insulating layer 11 may be filled with ceramic particles. Such particles may include, for example, SiO2, Al2O3, AlN, or BN, and may have a diameter between about 1 μm and about 50 μm.

[0020] The substrate 10 is arranged in the housing 7. Figure 1 In the example shown, the substrate 10 forms the ground surface of the housing 7, while the housing 7 itself only includes side walls and a cover. However, this is only an example. It is also possible that the housing 7 also includes a ground surface and that the substrate 10 is arranged inside the housing 7. According to another example, the substrate 10 can be mounted on a base plate (not shown). In some power semiconductor module devices 100, more than one substrate 10 is arranged on a single base plate. For example, the base plate can form the ground surface of the housing 7. The top of the housing 7 can be a separate cover or lid that can be removed from the side walls, or it can be formed integrally with at least the side walls of the housing 7. In the latter case, the top and at least the side walls of the housing 7 can be formed as a single piece, so that the top cannot be removed from the side walls without destroying the housing.

[0021] One or more semiconductor bodies 20 may be arranged on the substrate 10. Each semiconductor body 20 arranged on the substrate 10 may include a diode, an IGBT (insulated gate bipolar transistor), a MOSFET (metal oxide semiconductor field effect transistor), a JFET (junction field effect transistor), a HEMT (high electron mobility transistor), or any other suitable controllable or uncontrollable semiconductor element.

[0022] One or more semiconductor bodies 20 may form a semiconductor device on the substrate 10. Figure 1 In FIG. 2 , only two semiconductor bodies 20 are shown by way of example. Figure 1 The second metallization layer 112 of the substrate 10 is a continuous layer. Figure 1 In the example shown, the first metallization layer 111 is a structured layer. By "structured layer" is meant that the first metallization layer 111 is not a continuous layer but comprises recesses between different parts of the layer. Figure 1 . Such a recess is schematically shown in . In this example, the first metallization layer 111 includes four different parts. Different semiconductor bodies 20 can be mounted to the same or different parts of the first metallization layer 111. The different parts of the first metallization layer may not have an electrical connection, or may be electrically connected to one or more other parts using, for example, bonding wires 3. The electrical connection 3 may also include, for example, a connecting plate or a conductor track, to name just a few examples. One or more semiconductor bodies 20 can be electrically and mechanically connected to the semiconductor substrate 10 via a conductive connection layer 30. Such a conductive connection layer may be, for example, a solder layer, a diffusion solder layer, a conductive adhesive layer, or a sintered metal powder (e.g., sintered silver powder) layer.

[0023] Figure 1 The power semiconductor module arrangement 100 shown further comprises a terminal element 4. The terminal element 4 is electrically connected to the first metallization layer 111 and provides an electrical connection between the interior and the exterior of the housing 7. The terminal element 4 can be electrically connected to the first metallization layer 111 via a first end 41, while a second end 42 of the terminal element 4 protrudes outside the housing 7. The terminal element 4 can be electrically contacted from the outside at its second end 42. However, Figure 1 The terminal elements 4 shown are merely examples. The terminal elements 4 can be implemented in any other manner and can be arranged in any other position. For example, one or more terminal elements 4 can be arranged close to or adjacent to the side wall of the housing 7. Any other suitable embodiment is possible. For example, the terminal elements 4 can be composed of or include metals such as copper, aluminum, gold, silver or any alloy thereof. The terminal elements 4 can be electrically and mechanically connected to the substrate 10 via a conductive connecting layer (the terminal elements 4 are not specifically shown). For example, such a conductive connecting layer can typically be a solder layer, a diffusion solder layer, a conductive adhesive layer or a sintered metal powder layer, such as sintered silver powder.

[0024] Conventional power semiconductor module devices 100 typically also include a casting compound 5. For example, the casting compound 5 can consist of or include silicone gel, or can be a rigid molding compound. The casting compound 5 can at least partially fill the interior of the housing 7, thereby covering the components and electrical connections arranged on the substrate 10. The terminal elements 4 can be partially embedded in the casting compound 5. However, at least their second ends 42 are not covered by the casting compound 5 and protrude from the casting compound 5 through the housing 7 to the outside of the housing 7. The casting compound 5 is configured to protect the interior of the power semiconductor module 100, in particular the components and electrical connections inside the housing 7, from certain environmental conditions and mechanical damage.

[0025] The semiconductor bodies 20 arranged on the substrate 10 are typically semiconductor chips that are not individually packaged in any way. That is, they are so-called bare dies. Once the semiconductor device is formed on the substrate 10, the final semiconductor module device can be tested. However, it is usually impossible to test each semiconductor chip individually before arranging it on the substrate 10. Bare die semiconductor chips must usually be handled carefully to avoid any damage to the bare die semiconductor chips that may reduce the overall life of the semiconductor module. When arranging semiconductor chips on the substrate 10, thermal and electrical requirements must be met. This usually results in a considerable distance between adjacent semiconductor chips and, therefore, a considerable size of the entire semiconductor module. In order to overcome these shortcomings, the semiconductor module device according to an embodiment of the present disclosure includes at least one pre-packaged semiconductor chip, which will be described in further detail below.

[0026] In particular, a semiconductor module device according to an embodiment of the present disclosure includes a substrate 10 and at least one semiconductor component 200 arranged on substrate 10. Each of the at least one semiconductor component 200 includes a semiconductor chip 20 having first and second electrodes. The semiconductor chip 20 corresponds to a semiconductor chip / body used in conventional semiconductor module devices. However, the semiconductor component 200 according to an embodiment of the present disclosure further includes a first metal layer 202 attached to the first electrode of the semiconductor chip 20 via a conductive connection layer 208, a second metal layer 204 attached to the second electrode of the semiconductor chip 20 via the conductive connection layer 208, and a dielectric insulation layer 210 covering a surface of the semiconductor chip 20, wherein the surfaces of the first metal layer 202 and the second metal layer 204 facing away from the semiconductor chip 20 are not covered by the dielectric insulation layer 210. For example, the conductive connection layer 208 may be a solder layer, a diffusion solder layer, a conductive adhesive layer, or a sintered metal powder layer.

[0027] That is, first metal layer 202 and second metal layer 204 allow for electrical contact, respectively, between a first electrode and a second electrode disposed within a package formed by dielectric insulating layer 210. Dielectric insulating layer 210 can be formed from a rigid material, such as, for example, a rigid plastic or ceramic material. Dielectric insulating layer 210 can be formed in any suitable manner, for example, using a molding technique. According to some examples, the material forming dielectric insulating layer 210 can be configured to withstand high temperatures, for example, temperatures greater than 100°C or greater than 200°C. This can improve the local temperature stability of the semiconductor module device.

[0028] refer to Figure 2 , schematically shows a semiconductor component 200 according to a further embodiment of the present disclosure. In this example, the semiconductor chip 20 further comprises a third electrode, and the semiconductor component 200 further comprises a third metal layer 206 attached to the third electrode of the semiconductor chip 20 via a conductive connection layer 208. The surface of the third metal layer 206 facing away from the semiconductor chip 20 is not covered by the dielectric insulation layer 210. In this way, the third electrode can be electrically contacted via the third metal layer 206. The number of electrodes generally depends on the kind of component formed in the semiconductor chip 20. For example, a diode generally has only two electrodes (a first electrode and a second electrode), while an IGBT (insulated gate bipolar transistor), a MOSFET (metal oxide semiconductor field effect transistor), a JFET (junction field effect transistor), a HEMT (high electron mobility transistor) or any other type of transistor generally has at least three electrodes. The general principle applies analogously to semiconductor bodies 20 having two, three or even more electrodes. One or more semiconductor components 200 can be arranged in a semiconductor module, as described above with respect to Figure 1 For example, the semiconductor component 200 may replace a conventional semiconductor body (chip) 20 .

[0029] The first electrode of the semiconductor chip 20 may be arranged on a first side of the semiconductor chip 20 facing away from the substrate 10, and the second electrode of the semiconductor chip 20 may be arranged on a second side of the semiconductor chip 20 opposite the first side and facing the substrate 10. For example, if the semiconductor chip 20 includes a diode, the first electrode may be an anode electrode, and the second electrode may be a cathode electrode. If the semiconductor chip includes a transistor, the third electrode may be arranged on the same side as the first electrode, that is, on the first side of the semiconductor chip 20 facing away from the substrate 10. In this case, for example, the first electrode may be a source electrode or an emitter electrode, the second electrode may be a drain electrode or a collector electrode, and the third electrode may be a gate electrode or a base electrode.

[0030] Electrodes are typically formed on the semiconductor material of the semiconductor chip by a fairly thin metal layer. Such a thin metal layer can have a thickness of, for example, up to 20 μm. It is generally believed that a thickness of 20 μm is quite thick. However, for example, when the electrodes are contacted by fairly thick bonding wires, electrodes of greater thickness may be required. However, forming a semiconductor chip 20 with fairly thick electrodes (e.g., 20 μm or even larger) is typically expensive. Alternatively, attaching thick metal layers 202, 204, 206 to the electrodes can significantly reduce the overall cost of the semiconductor component 200.

[0031] For example, the first metal layer 202, the second metal layer 204, and the optional third metal layer 206 can each include or consist of copper, tungsten, AlSiC, MgSiC, or a conductive material having a CTE (coefficient of thermal expansion) of 2 to 17 ppm. The first metal layer 202 and the optional third metal layer 206 can each have a thickness d202, d206 of, for example, between 50 μm and 300 μm in the vertical direction y perpendicular to the first side of the semiconductor chip 20. The second metal layer 204 can even have a thickness d204 of between 2.0 mm and 3.0 mm in the vertical direction y. Still referring to Figure 2 The semiconductor chip 20 has a first length l20 in a first horizontal direction x perpendicular to the vertical direction y, and a first width in a second horizontal direction z perpendicular to the first horizontal direction x and the vertical direction y. The second metal layer 204 has a second length l204 in the first horizontal direction x and a second width in the second horizontal direction z. According to an embodiment of the present disclosure, the surface area of ​​the second metal layer 204 defined by the second length l204 and the second width (second surface area = second length × second width) is 1 and 2 times the surface area of ​​the semiconductor chip 20 defined by the first length l20 and the first width (first surface area = first length × first width).

[0032] In this manner, second metal layer 204 can act as a heat sink. That is, heat generated by semiconductor chip 20 during operation of the semiconductor module device can be diffused throughout the thickness d204 and large cross-sectional area of ​​second metal layer 204 before being further transferred to substrate 10. Due to the considerable thickness d204 and large cross-sectional area of ​​second metal layer 204, the overall thermal resistance Rth of the semiconductor module device can be significantly reduced (e.g., by up to 30% or even more compared to a semiconductor module device including a bare die semiconductor chip 20). Figure 4A and Figure 4B Schematically shows a direct attachment to the substrate 10 ( Figure 4A) and the semiconductor component 200 according to an embodiment of the present disclosure, the semiconductor component 200 includes a second metal layer 204 and an additional conductive connection layer 208 arranged between the semiconductor chip 20 and the substrate 10 ( Figure 4B ).

[0033] Compared to a bare die, the semiconductor component 200 including the semiconductor chip 20 in a very simple package (formed by the dielectric insulating layer 210) can be handled more easily. Furthermore, the semiconductor component 200 can be individually tested before being arranged on the substrate 10. In other words, any faulty or damaged semiconductor components 200 can be sorted out even before the semiconductor module device is assembled. This significantly improves the overall yield.

[0034] The semiconductor components 200, i.e., the metal layers 202, 204, 206, can be electrically contacted in any suitable manner similar to conventional bare die components. Due to the fact that packaged semiconductor components 200 are more robust than bare die, they can even be electrically contacted in additional ways that are not possible with more fragile bare die. Figure 3 As schematically shown in FIG, the semiconductor component 200 may be attached and electrically coupled to the substrate 10 via the conductive connection layer 30, similar to the above description of Figure 1 The conductive connection layer 30 may be, for example, a solder layer, a diffusion solder layer, a conductive adhesive layer, or a sintered metal powder layer. The semiconductor component 200 may also be electrically connected to other parts of the first metallization layer 111 of the substrate 10 via electrical connections 3, such as, for example, bonding wires, bonding ribbons, connection pads, or conductor tracks.

[0035] Similar to what was described above with respect to second metal layer 204, the surface area of ​​first metal layer 202 may be greater than the surface area of ​​the first electrode of semiconductor chip 20, and the surface area of ​​optional third metal layer 206 may be greater than the surface area of ​​the third electrode of semiconductor chip 20. In this way, for example, a larger surface area is available for attaching electrical connections 3 or terminal elements 4 thereto compared to a bare die semiconductor chip 20.

[0036] like Figure 6 As schematically shown in FIG, it is also possible to form connections between different substrates 10. That is, the semiconductor component 200 can be electrically coupled to the first metallization layer 111 of another substrate 10 via the electrical connection 3. Figure 7 It is also possible that the first semiconductor component 200 arranged on the first substrate 10 is electrically coupled to the second semiconductor component 200 arranged on the second substrate 10 via the electrical connection 3. Alternatively, the second semiconductor component 200 can also be arranged on the same substrate 10 as the first semiconductor component 200.

[0037] Since the first metal layer 202 and the optional third metal layer 206 are relatively thick and therefore robust, it is even possible to place the terminal element 4 as described above with respect to Figure 1 The ground is arranged directly on the first or third metal layer 202, 206. For example, Figure 8 The terminal element 4 can be connected by a conductive connecting layer ( Figure 8 The conductive connection layer is not specifically shown in FIG. 2 ) and is attached to the corresponding metal layers 202 and 206. Figure 9 , it is even possible to arrange a sleeve or bushing 48 on the corresponding metal layer (eg, the first metal layer 202 or the third metal layer 206). The terminal element 4 can then be inserted into the sleeve or bushing.

[0038] It is even possible that Figure 10 As schematically shown in FIG, the first metal layer 202 and the optional third metal layer 206 are directly attached to the other substrate 10. That is, one or more semiconductor components 200 can be sandwiched between two substrates 10. The first and optional third metal layers 202, 206 can be connected by conductive connection layers (in FIG) as already described with respect to the second metal layer 204. Figure 10 The corresponding parts of the first metallization layer 111 for attaching the first and third metal layers 202, 206 to the second substrate 10 are not specifically shown. Figure 10 As shown, more than one semiconductor component 200 can be sandwiched between two separate substrates 10. It is also possible that one or more semiconductor components 200 are arranged "upside down" between two substrates 10, such as Figure 10 That is, one or more semiconductor components 200 may be attached to the second substrate 10 using their respective second metal layers 204 , and attached to the first substrate 10 using their first metal layers 202 and optional third metal layers 206 .

[0039] The semiconductor module arrangement can generally also be implemented in any other suitable manner. The substrate 10 with one or more semiconductor components 200 arranged thereon can ultimately be arranged in a housing 7 or form the base surface of the housing 7, similar to the above description of the embodiment of the present invention. Figure 1 The semiconductor housing 7 can be at least partially filled with a casting compound 5, similar to the above description of Figure 1 described.

[0040] Now refer to Figure 5 , a single semiconductor component 200 may even include more than one semiconductor chip 20. Figure 5In the example shown, the semiconductor component 200 includes two semiconductor chips 20. For example, each of the plurality of semiconductor chips 20 may include a diode, or each of the plurality of semiconductor chips 20 may include a transistor. Thus, the semiconductor component 200 may include, for example, two or more diodes or two or more transistors coupled in parallel with each other. To achieve this, the first metal layer 202 may be attached to and electrically coupled not only to the first electrode of the first semiconductor chip 20, but also to the first electrode of the second semiconductor chip 20 (and any additional semiconductor chips included in the semiconductor component 200). Similarly, the second metal layer 204 may be attached to and electrically coupled to the second electrode of the first semiconductor chip 20, and also to the second electrode of the second semiconductor chip 20 (and any additional semiconductor chips included in the semiconductor component 200).

[0041] In the first horizontal direction x, the first semiconductor chip 20 and the second semiconductor chip 20 (and any additional semiconductor chips 20) may be spaced apart from each other. A gap formed between the first semiconductor chip 20 and the second semiconductor chip 20 (and any additional semiconductor chips 20) in the first horizontal direction x may be filled with a dielectric insulating layer 210, as shown in FIG. Figure 5 Schematically shown in .

Claims

1. A semiconductor module device, comprising: substrate (10); as well as At least one semiconductor component (200) arranged on the substrate (10), wherein each of the at least one semiconductor component (200) comprises: a semiconductor chip (20) having a first electrode and a second electrode, a first metal layer (202) attached to the first electrode of the semiconductor chip (20) via a conductive connection layer (208), a second metal layer (204) attached to the second electrode of the semiconductor chip (20) via a conductive connection layer (208), and A dielectric insulating layer (210) covers the surface of the semiconductor chip (20), wherein surfaces of the first metal layer (202) and the second metal layer (204) facing away from the semiconductor chip (20) are not covered by the dielectric insulating layer (210).

2. The semiconductor module device according to claim 1, wherein The substrate (10) comprises a dielectric insulating layer (11) and a first metallization layer (111) attached to the dielectric insulating layer (11), and wherein the at least one semiconductor component (200) is arranged on a surface of the first metallization layer (111) facing away from the dielectric insulating layer (11).

3. The semiconductor module device according to claim 2, wherein: The dielectric insulating layer (11) is a ceramic layer.

4. The semiconductor module arrangement according to claim 1 , wherein: The first electrode of the semiconductor chip (20) is arranged on a first side of the semiconductor chip (20) facing away from the substrate (10), and The second electrode of the semiconductor chip (20) is arranged on a second side of the semiconductor chip (20) opposite to the first side and facing the substrate (10).

5. The semiconductor module arrangement according to claim 1, wherein: The first metal layer (202) has a thickness (d202) between 50 μm and 300 μm in a vertical direction (y) perpendicular to the first side of the semiconductor chip (20), and The second metal layer (204) has a thickness (d204) in the vertical direction (y) between 2.0 mm and 3.0 mm.

6. The semiconductor module arrangement according to claim 1, wherein: The semiconductor chip (20) of at least one of the at least one semiconductor component (200) further comprises a third electrode, and the respective semiconductor component (200) further comprises a third metal layer (206) attached to the third electrode of the semiconductor chip (20) via a conductive connection layer (208), wherein a surface of the third metal layer (206) facing away from the semiconductor chip (20) is not covered by the dielectric insulation layer (210).

7. The semiconductor module arrangement according to claim 6, wherein: The third electrode is arranged on a side of the semiconductor chip (20) facing away from the substrate (10).

8. The semiconductor module arrangement according to claim 6 or 7, wherein: The third metal layer (206) has a thickness (d206) between 50 μm and 300 μm in a vertical direction (y) perpendicular to the first side of the semiconductor chip (20).

9. The semiconductor module arrangement according to claim 1, wherein: The first metal layer (202), the second metal layer (204) and the third metal layer (206) each include or consist of copper, tungsten, AlSiC, MgSiC or a conductive material with a CTE of 2 to 17 ppm.

10. The semiconductor module arrangement according to claim 1, wherein: The conductive connection layer (208) is a solder layer, a diffusion solder layer, a conductive adhesive layer or a sintered metal powder layer.

11. The semiconductor module arrangement according to claim 1, wherein: The semiconductor chip (20) has a first length (l20) in a first horizontal direction (x) perpendicular to the vertical direction (y), and has a first width in a second horizontal direction (z) perpendicular to the first horizontal direction (x) and the vertical direction (y), The second metal layer (204) has a second length (1204) in the first horizontal direction (x) and a second width in the second horizontal direction (z), and The surface area of ​​the second metal layer (204) defined by the second length (1204) and the second width is between 1 and 2 times the surface area of ​​the semiconductor chip (20) defined by the first length (120) and the first width.

12. The semiconductor module arrangement according to claim 1, wherein: Each of the at least one semiconductor component (200) is attached to the substrate (10) by a conductive connection layer (30).

13. The semiconductor module arrangement according to claim 12, wherein: Each of the at least one conductive connection layer (30) is a solder layer, a diffusion solder layer, a conductive adhesive layer or a sintered metal powder layer.

14. The power semiconductor module arrangement according to claim 1, wherein: At least one of the at least one semiconductor component (200) further comprises a second semiconductor chip (20) having a first electrode and a second electrode, The first metal layer (202) extends from the first electrode of the first semiconductor chip (20) to the first electrode of the second semiconductor chip (20) and is attached to the first electrode of the second semiconductor chip (20) via a conductive connection layer (208), and The second metal layer (204) extends from the second electrode of the first semiconductor chip (20) to the second electrode of the second semiconductor chip (20) and is attached to the second electrode of the second semiconductor chip (20) through a conductive connection layer (208).

15. The power semiconductor module device according to claim 14, wherein: In the first horizontal direction (x), the first semiconductor chip (20) and the second semiconductor chip (20) are spaced apart from each other, and wherein a gap formed between the first semiconductor chip (20) and the second semiconductor chip (20) in the first horizontal direction (x) is filled by the dielectric insulating layer (210).

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