Chopped wave self-stabilization zero fully differential operational amplifier circuit with digital calibration

Abstract

The invention belongs to the technical field of integrated circuits, and relates to a chopping self-stabilization zero fully differential operational amplifier circuit with digital calibration, which comprises a switch module, a transconductance module, a transimpedance amplification module, a capacitor module, a digital calibration module, a common mode feedback module and an output module, wherein the switch module is used for realizing chopping and zero self-stabilization, the digital calibration module is used for preliminarily calibrating the offset voltage of the main amplifier, the common-mode feedback module is used for stabilizing the output common-mode voltage of the transimpedance amplification module, meanwhile, the common-mode feedback module can also reduce burrs of output signals, and the output module is used for outputting differential signals. After the digital calibration module preliminarily calibrates the offset voltage of the main amplifier, chopping and self-zero-stabilizing are realized by switching a switch in the switch module, so that the offset voltage of the operational amplifier is greatly reduced, and meanwhile, the noise of the operational amplifier is also reduced to a relatively low value; therefore, the operational amplifier has the characteristics of low offset voltage, low noise, low ripple and high precision.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits and relates to a chopper-zero fully differential operational amplifier circuit with digital calibration. The operational amplifier is suitable for application scenarios with ultra-low offset, low noise and high precision. Background Art

[0002] As a key module in integrated circuits, operational amplifiers (OPA) are widely used in digital signal processing, wireless communications, medical, and automotive electronics. Depending on the application scenario, OPA can be broadly categorized as audio, power, general-purpose, high-speed, and precision. Precision OPA are defined as amplifiers with an input offset voltage below 1mV, offering significantly higher accuracy than other amplifiers. Op AMPs with low offset, low noise, and high precision have long been a hot topic of research.

[0003] In analog circuits, indicators such as power consumption, area, noise, offset, speed, and accuracy constrain each other. To achieve low offset, low noise, and high precision, operational amplifiers require structural optimization. Existing methods for reducing offset voltage mainly include chopping technology and auto-zeroing technology. These two technologies are relatively mature, but the offset voltage accuracy they can achieve is often at the μV level. This paper combines chopping technology with auto-zero technology and introduces digital calibration technology on this basis to further reduce the offset voltage and noise of the operational amplifier. At the same time, the two fully differential operational amplifiers use the same common-mode feedback circuit, which greatly optimizes the output signal glitches. The fully differential operational amplifier circuit proposed in this invention can achieve an offset voltage of nV and a gain of up to 100,000,000 times, achieving lower offset voltage and higher precision. Summary of the Invention

[0004] Based on this, the present invention proposes a chopper-zero fully differential operational amplifier circuit with digital calibration.

[0005] The present application provides a chopper-zero fully differential operational amplifier circuit with digital calibration, comprising a switch module, a transconductance module, a transresistance amplifier module, a capacitor module, a digital calibration module, a common-mode feedback module, and an output module;

[0006] The first transconductance module and the first transimpedance amplifier module serve as a first main amplifier; the third transconductance module and the second transimpedance amplifier module serve as a second main amplifier; the second transconductance module and the first transimpedance amplifier module serve as a first zeroing amplifier; and the fourth transconductance module and the second transimpedance amplifier module serve as a second zeroing amplifier.

[0007] The first digital calibration module is used to preliminarily calibrate the offset voltage of the first main amplifier, and the second digital calibration module is used to preliminarily calibrate the offset voltage of the second main amplifier; the common-mode feedback module is used to stabilize the output common-mode voltage of the first transimpedance amplifier module and the second transimpedance amplifier module, and reduce the burrs of the output signal; the output module is used to output a differential signal;

[0008] After the digital calibration module preliminarily calibrates the offset voltage of the main amplifier, chopping and auto-zeroing are achieved by switching switches in the first switch module, the second switch module, the third switch module, and the fourth switch module.

[0009] Preferably, the first input terminal of the first switch module is connected to the first input signal, the input signal number is VINP, and the second input terminal is connected to the second input signal, the input signal number is VINN;

[0010] The first output terminal and the second output terminal of the first switch module are connected to the first input terminal and the second input terminal of the first transconductance module respectively, and the connection nodes are numbered N1 and N2 respectively;

[0011] The first input terminal and the second input terminal of the third switch module are connected to the second input signal and the first input signal respectively;

[0012] The first output terminal and the second output terminal of the third switch module are connected to the first input terminal and the second input terminal of the third transconductance module respectively, and the connection nodes are numbered N9 and N10 respectively;

[0013] The first input terminal of the first transimpedance amplification module is connected to the first output terminal of the first transconductance module, the first output terminal of the first digital calibration module, the first output terminal of the second transconductance module, and the first output terminal of the common-mode feedback module, and the connection node is numbered N3;

[0014] The second input terminal of the first transimpedance amplification module is connected to the second output terminal of the first transconductance module, the second output terminal of the first digital calibration module, the second output terminal of the second transconductance module, and the second output terminal of the common-mode feedback module, and the connection node is numbered N4;

[0015] The first input terminal of the second transimpedance amplification module is connected to the first output terminal of the third transconductance module, the first output terminal of the second digital calibration module, the first output terminal of the fourth transconductance module, and the third output terminal of the common-mode feedback module, and the connection node is numbered N11;

[0016] The second input terminal of the second transimpedance amplification module is connected to the second output terminal of the third transconductance module, the second output terminal of the second digital calibration module, the second output terminal of the fourth transconductance module, and the fourth output terminal of the common-mode feedback module, and the connection node is numbered N12;

[0017] A first input terminal of the second switch module is connected to the first output terminal of the first transresistance amplifier module, the first input terminal of the first digital calibration module, and the first input terminal of the common-mode feedback, and the connection node is numbered N5;

[0018] The second input terminal of the second switch module is connected to the second output terminal of the first transimpedance amplifier module, the second input terminal of the first digital calibration module, and the second input terminal of the common-mode feedback, and the connection node is numbered N6;

[0019] The first output terminal and the second output terminal of the second switch module are connected to the first input terminal and the second input terminal of the first capacitor module respectively, and the connection nodes are numbered N19 and N20 respectively;

[0020] The third output terminal of the second switch module is connected to the third output terminal of the fourth switch module and the first input terminal of the output module, and the connection node is numbered N17;

[0021] The fourth output terminal of the second switch module is connected to the fourth output terminal of the fourth switch module and the second input terminal of the output module, and the connection node is numbered N18;

[0022] The first input terminal of the fourth switch module is connected to the first output terminal of the second transimpedance amplifier module, the first input terminal of the second digital calibration module, and the third input terminal of the common-mode feedback, and the connection node is numbered N13;

[0023] The second input terminal of the fourth switch module is connected to the second output terminal of the second transimpedance amplifier module, the second input terminal of the second digital calibration module, and the fourth input terminal of the common-mode feedback, and the connection node is numbered N14;

[0024] The first output terminal and the second output terminal of the fourth switch module are connected to the first input terminal and the second input terminal of the second capacitor module respectively, and the connection nodes are numbered N21 and N22 respectively;

[0025] The first output terminal and the second output terminal of the first capacitor module are connected to the first input terminal and the second input terminal of the second transconductance module respectively, and the connection nodes are numbered N7 and N8 respectively;

[0026] The first output terminal and the second output terminal of the second capacitor module are connected to the first input terminal and the second input terminal of the fourth transconductance module respectively, and the connection nodes are numbered N15 and N16 respectively;

[0027] The first output terminal and the second output terminal of the output module are connected to the first output signal and the second output signal respectively. The first output signal is numbered VOUTP and the second output signal is numbered VOUTN.

[0028] Preferably, the first switch module includes: a first switch, a second switch, a third switch, a fourth switch, a fifth switch and a sixth switch;

[0029] The first end of the first switch, the first end of the second switch, the first end of the third switch, and the first end of the fourth switch are all connected to the first input signal VINP; the first end of the fifth switch and the first end of the sixth switch are all connected to the second input signal VINN; the second end of the first switch, the second end of the fourth switch, and the second end of the sixth switch are all connected to the node N2; the second end of the second switch, the second end of the third switch, and the second end of the fifth switch are all connected to the node N1;

[0030] The third switch module includes: a sixteenth switch, a seventeenth switch, an eighteenth switch, a nineteenth switch, a twentieth switch, and a twenty-first switch;

[0031] The first terminal of the sixteenth switch, the first terminal of the seventeenth switch, the first terminal of the eighteenth switch, and the first terminal of the nineteenth switch are all connected to the second input signal VINN; the first terminal of the twentieth switch and the first terminal of the twenty-first switch are all connected to the first input signal VINP; the second terminal of the sixteenth switch, the second terminal of the nineteenth switch, and the second terminal of the twenty-first switch are all connected to the node N10; the second terminal of the seventeenth switch, the second terminal of the eighteenth switch, and the second terminal of the twentieth switch are all connected to the node N9;

[0032] The second switch module includes: a seventh switch, an eighth switch, a ninth switch, a tenth switch, an eleventh switch and a twelfth switch;

[0033] The first end of the seventh switch, the first end of the eighth switch, and the first end of the ninth switch are all connected to the node N5; the first end of the tenth switch, the first end of the eleventh switch, and the first end of the twelfth switch are all connected to the node N6; the second end of the ninth switch is connected to the node N19; the second end of the tenth switch is connected to the node N20; the second end of the seventh switch and the second end of the eleventh switch are both connected to the node N18; the second end of the eighth switch and the second end of the twelfth switch are both connected to the node N17;

[0034] The fourth switch module includes: a twenty-second switch, a twenty-third switch, a twenty-fourth switch, a twenty-fifth switch, a twenty-sixth switch, and a twenty-seventh switch;

[0035] The first end of the twenty-second switch, the first end of the twenty-third switch, and the first end of the twenty-fourth switch are all connected to the node N13; the first end of the twenty-fifth switch, the first end of the twenty-sixth switch, and the first end of the twenty-seventh switch are all connected to the node N14; the second end of the twenty-fourth switch is connected to the node N21; the second end of the twenty-fifth switch is connected to the node N22; the second end of the twenty-second switch and the second end of the twenty-sixth switch are both connected to the node N18; the second end of the twenty-third switch and the second end of the twenty-seventh switch are both connected to the node N17.

[0036] Preferably, in the first transconductance module, the second transconductance module, the third transconductance module and the fourth transconductance module:

[0037] The voltage positive input terminal is the first input terminal;

[0038] The voltage negative input terminal is the second input terminal;

[0039] The current positive output terminal is the first output terminal;

[0040] The current negative output terminal is the second output terminal.

[0041] Preferably, in the first transresistance amplification module and the second transgroup amplification module:

[0042] The current positive input terminal is the first input terminal;

[0043] The current negative input terminal is the second input terminal;

[0044] The voltage positive output terminal is the first output terminal;

[0045] The negative voltage output terminal is the second output terminal.

[0046] Preferably, the first digital calibration module includes a COMP1 module, a SAR LOGIC1 module and an IDAC1 module;

[0047] The COMP1 module is a comparator module, the SAR LOGIC1 module is a successive approximation logic module, and the IDAC1 module is a current-mode digital-to-analog converter module;

[0048] The two input terminals of the COMP1 module are respectively the first input terminal and the second input terminal of the first digital calibration module;

[0049] The output of the COMP1 module is connected to the input of the SAR LOGIC1 module;

[0050] The input of the IDAC1 module is connected to the output of the SAR LOGIC1 module;

[0051] The two output terminals of the IDAC1 module are respectively a first output terminal and a second output terminal of the first digital calibration module;

[0052] Preferably, the second digital calibration module includes a COMP2 module, a SAR LOGIC2 module and an IDAC2 module;

[0053] The COMP2 module is a comparator module, the SAR LOGIC2 module is a successive approximation logic module, and the IDAC2 module is a current-mode digital-to-analog converter module;

[0054] The two input terminals of the COMP2 module are respectively the first input terminal and the second input terminal of the second digital calibration module;

[0055] The output of the COMP2 module is connected to the input of the SAR LOGIC2 module;

[0056] The input end of the IDAC2 module is connected to the output end of the SAR LOGIC2 module;

[0057] The two output terminals of the IDAC2 module are respectively the first output terminal and the second output terminal of the second digital calibration module.

[0058] Preferably, the first capacitor module includes a first capacitor and a second capacitor;

[0059] The first end of the first capacitor is connected to the ground, which is a ground port;

[0060] The second end of the first capacitor is simultaneously the first input end and the first output end of the first capacitor module;

[0061] A first terminal of the second capacitor is connected to the ground terminal;

[0062] The second end of the second capacitor is also the second input end and the second output end of the first capacitor module;

[0063] The second capacitor module includes a third capacitor and a fourth capacitor;

[0064] A first terminal of the third capacitor is connected to the ground terminal;

[0065] The second end of the third capacitor is simultaneously the first input end and the first output end of the second capacitor module;

[0066] A first terminal of the fourth capacitor is connected to the ground terminal;

[0067] The second end of the fourth capacitor is simultaneously the second input end and the second output end of the second capacitor module.

[0068] Preferably, the common-mode feedback module includes a thirteenth switch, a fourteenth switch, a fifteenth switch, a twenty-eighth switch, a twenty-ninth switch, a thirtieth switch, a fifth capacitor, a sixth capacitor, an OPA1 module, a GM3 module, and a GM6 module;

[0069] The OPA1 module is a dual-ended input, single-ended output operational amplifier;

[0070] The GM3 and GM6 modules are single-ended input and double-ended output transconductance amplifiers;

[0071] The first end of the thirteenth switch is the first input end of the common-mode feedback module;

[0072] The first end of the fourteenth switch is the second input end of the common-mode feedback module;

[0073] The first end of the twenty-eighth switch is the fourth input end of the common-mode feedback module;

[0074] The first end of the twenty-ninth switch is the third input end of the common-mode feedback module;

[0075] The second end of the thirteenth switch, the second end of the fourteenth switch, the second end of the twenty-eighth switch, and the second end of the twenty-ninth switch are connected to the inverting input terminal of OPA1;

[0076] The positive input terminal of OPA1 is connected to the reference voltage VREF;

[0077] The output terminal of OPA1 is connected to the first terminal of the fifteenth switch and the first terminal of the thirtieth switch;

[0078] The second end of the fifteenth switch is connected to the first end of the fifth capacitor and the input end of GM3;

[0079] The second terminal of the 30th switch is connected to the first terminal of the sixth capacitor and the input terminal of GM6;

[0080] The second terminal of the fifth capacitor is grounded;

[0081] The second terminal of the sixth capacitor is grounded;

[0082] The two output terminals of GM3 are the first output terminal and the second output terminal of the common mode feedback module respectively;

[0083] The two output terminals of GM6 are respectively the third output terminal and the fourth output terminal of the common-mode feedback module.

[0084] Preferably, the output module includes a seventh capacitor, an eighth capacitor and a DFFOPA module;

[0085] The DFFOPA module is a fully differential voltage operational amplifier;

[0086] The positive input terminal of the DFFOPA module is the first input terminal of the output module;

[0087] The inverting input terminal of the DFFOPA module is the second input terminal of the output module;

[0088] The reverse output terminal of the DFFOPA module is the first output terminal of the output module;

[0089] The positive output terminal of the DFFOPA module is the second output terminal of the output module;

[0090] A first end of the seventh capacitor is connected to the positive input end of the DFFOPA;

[0091] The second end of the seventh capacitor is connected to the reverse output end of the DFFOPA;

[0092] A first end of the eighth capacitor is connected to the inverting input end of the DFFOPA;

[0093] The second end of the eighth capacitor is connected to the positive output end of the DFFOPA.

[0094] Technical Effects

[0095] The present invention uses a first switch module, a second switch module, a third switch module, and a fourth switch module to achieve chopping and auto-zeroing. A first digital calibration module is used to preliminarily calibrate the offset voltage of the first main amplifier, a second digital calibration module is used to preliminarily calibrate the offset voltage of the second main amplifier, a common-mode feedback module is used to stabilize the output common-mode voltage of the first transimpedance amplifier module and the second transimpedance amplifier module, and the common-mode feedback module can also reduce the burrs of the output signal. The output module is used to output a differential signal. After the digital calibration module preliminarily calibrates the offset voltage of the main amplifier, chopping and auto-zeroing are achieved by switching the switches in the first switch module, the second switch module, the third switch module, and the fourth switch module, thereby greatly reducing the offset voltage of the operational amplifier. At the same time, the noise of the operational amplifier is also reduced to a lower value. Therefore, the operational amplifier has the characteristics of low offset voltage, low noise, low ripple, and high precision. BRIEF DESCRIPTION OF THE DRAWINGS

[0096] In order to more clearly illustrate the technical solutions in this application and one embodiment, the drawings required for use will be briefly introduced below. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0097] Figure 1 This is a circuit architecture diagram of a chopper-zero fully differential operational amplifier with digital calibration according to the present application;

[0098] Figure 2 A chopping schematic diagram of a chopper-zero fully differential operational amplifier with digital calibration according to the present application;

[0099] Figure 3 This is a self-zeroing principle diagram of a chopper-zeroed fully differential operational amplifier with digital calibration in the present application;

[0100] Figure 4 This is a working principle diagram of a chopper-zero fully differential operational amplifier with digital calibration in the present application;

[0101] Figure 5 This is a schematic diagram of a digital calibration module in a chopper-zero fully differential operational amplifier with digital calibration according to the present application;

[0102] Figure 6 A switching phase diagram of a chopper-zero fully differential operational amplifier with digital calibration according to the present application;

[0103] Figure 7This is a graph showing the gain and phase simulation results of a chopper-zero fully differential operational amplifier with digital calibration according to the present application;

[0104] Figure 8 This is a diagram showing the offset voltage simulation results of a chopper-zero fully differential operational amplifier with digital calibration in this application. DETAILED DESCRIPTION

[0105] In order to enable those skilled in the art to have a more comprehensive understanding of the present invention, the present invention will be further described below with reference to the accompanying drawings.

[0106] like Figure 1 As shown, this embodiment provides a chopper-stabilized-zero fully differential operational amplifier circuit with digital calibration, including a switch module, a transconductance module, a transresistance amplifier module, a capacitor module, a digital calibration module, a common-mode feedback module and an output module;

[0107] The first transconductance module and the first transimpedance amplifier module serve as a first main amplifier; the third transconductance module and the second transimpedance amplifier module serve as a second main amplifier; the second transconductance module and the first transimpedance amplifier module serve as a first zeroing amplifier; and the fourth transconductance module and the second transimpedance amplifier module serve as a second zeroing amplifier.

[0108] The first digital calibration module is used to preliminarily calibrate the offset voltage of the first main amplifier, and the second digital calibration module is used to preliminarily calibrate the offset voltage of the second main amplifier; the common-mode feedback module is used to stabilize the output common-mode voltage of the first transimpedance amplifier module and the second transimpedance amplifier module, and reduce the burrs of the output signal; the output module is used to output a differential signal;

[0109] After the digital calibration module preliminarily calibrates the offset voltage of the main amplifier, chopping and auto-zeroing are achieved by switching switches in the first switch module, the second switch module, the third switch module, and the fourth switch module.

[0110] In this embodiment, the first switch module includes: a first switch, a second switch, a third switch, a fourth switch, a fifth switch and a sixth switch;

[0111] The first end of the first switch, the first end of the second switch, the first end of the third switch, and the first end of the fourth switch are all connected to the first input signal VINP; the first end of the fifth switch and the first end of the sixth switch are all connected to the second input signal VINN; the second end of the first switch, the second end of the fourth switch, and the second end of the sixth switch are all connected to the node N2; the second end of the second switch, the second end of the third switch, and the second end of the fifth switch are all connected to the node N1;

[0112] The third switch module includes: a sixteenth switch, a seventeenth switch, an eighteenth switch, a nineteenth switch, a twentieth switch, and a twenty-first switch;

[0113] The first terminal of the sixteenth switch, the first terminal of the seventeenth switch, the first terminal of the eighteenth switch, and the first terminal of the nineteenth switch are all connected to the second input signal VINN; the first terminal of the twentieth switch and the first terminal of the twenty-first switch are all connected to the first input signal VINP; the second terminal of the sixteenth switch, the second terminal of the nineteenth switch, and the second terminal of the twenty-first switch are all connected to the node N10; the second terminal of the seventeenth switch, the second terminal of the eighteenth switch, and the second terminal of the twentieth switch are all connected to the node N9;

[0114] The second switch module includes: a seventh switch, an eighth switch, a ninth switch, a tenth switch, an eleventh switch and a twelfth switch;

[0115] The first end of the seventh switch, the first end of the eighth switch, and the first end of the ninth switch are all connected to the node N5; the first end of the tenth switch, the first end of the eleventh switch, and the first end of the twelfth switch are all connected to the node N6; the second end of the ninth switch is connected to the node N19; the second end of the tenth switch is connected to the node N20; the second end of the seventh switch and the second end of the eleventh switch are both connected to the node N18; the second end of the eighth switch and the second end of the twelfth switch are both connected to the node N17;

[0116] The fourth switch module includes: a twenty-second switch, a twenty-third switch, a twenty-fourth switch, a twenty-fifth switch, a twenty-sixth switch, and a twenty-seventh switch;

[0117] The first end of the twenty-second switch, the first end of the twenty-third switch, and the first end of the twenty-fourth switch are all connected to the node N13; the first end of the twenty-fifth switch, the first end of the twenty-sixth switch, and the first end of the twenty-seventh switch are all connected to the node N14; the second end of the twenty-fourth switch is connected to the node N21; the second end of the twenty-fifth switch is connected to the node N22; the second end of the twenty-second switch and the second end of the twenty-sixth switch are both connected to the node N18; the second end of the twenty-third switch and the second end of the twenty-seventh switch are both connected to the node N17.

[0118] In this embodiment, in the first transconductance module, the second transconductance module, the third transconductance module, and the fourth transconductance module:

[0119] The voltage positive input terminal is the first input terminal;

[0120] The voltage negative input terminal is the second input terminal;

[0121] The current positive output terminal is the first output terminal;

[0122] The current negative output terminal is the second output terminal.

[0123] In this embodiment, in the first transresistance amplification module and the second trans-group amplification module:

[0124] The current positive input terminal is the first input terminal;

[0125] The current negative input terminal is the second input terminal;

[0126] The voltage positive output terminal is the first output terminal;

[0127] The negative voltage output terminal is the second output terminal.

[0128] In this embodiment, the first digital calibration module includes a COMP1 module, a SAR LOGIC1 module, and an IDAC1 module;

[0129] The COMP1 module is a comparator module, the SAR LOGIC1 module is a successive approximation logic module, and the IDAC1 module is a current-mode digital-to-analog converter module;

[0130] The two input terminals of the COMP1 module are respectively the first input terminal and the second input terminal of the first digital calibration module;

[0131] The output of the COMP1 module is connected to the input of the SAR LOGIC1 module;

[0132] The input of the IDAC1 module is connected to the output of the SAR LOGIC1 module;

[0133] The two output terminals of the IDAC1 module are respectively a first output terminal and a second output terminal of the first digital calibration module;

[0134] The second digital calibration module includes a COMP2 module, a SAR LOGIC2 module, and an IDAC2 module;

[0135] The COMP2 module is a comparator module, the SAR LOGIC2 module is a successive approximation logic module, and the IDAC2 module is a current-mode digital-to-analog converter module;

[0136] The two input terminals of the COMP2 module are respectively the first input terminal and the second input terminal of the second digital calibration module;

[0137] The output of the COMP2 module is connected to the input of the SAR LOGIC2 module;

[0138] The input end of the IDAC2 module is connected to the output end of the SAR LOGIC2 module;

[0139] The two output terminals of the IDAC2 module are respectively the first output terminal and the second output terminal of the second digital calibration module.

[0140] In this embodiment, the first capacitor module includes a first capacitor and a second capacitor;

[0141] The first end of the first capacitor is connected to the ground, which is a ground port;

[0142] The second end of the first capacitor is simultaneously the first input end and the first output end of the first capacitor module;

[0143] A first terminal of the second capacitor is connected to the ground terminal;

[0144] The second end of the second capacitor is also the second input end and the second output end of the first capacitor module;

[0145] The second capacitor module includes a third capacitor and a fourth capacitor;

[0146] A first terminal of the third capacitor is connected to the ground terminal;

[0147] The second end of the third capacitor is simultaneously the first input end and the first output end of the second capacitor module;

[0148] A first terminal of the fourth capacitor is connected to the ground terminal;

[0149] The second end of the fourth capacitor is simultaneously the second input end and the second output end of the second capacitor module.

[0150] In this embodiment, the common-mode feedback module includes a thirteenth switch, a fourteenth switch, a fifteenth switch, a twenty-eighth switch, a twenty-ninth switch, a thirtieth switch, a fifth capacitor, a sixth capacitor, an OPA1 module, a GM3 module, and a GM6 module;

[0151] The OPA1 module is a dual-ended input, single-ended output operational amplifier;

[0152] The GM3 and GM6 modules are single-ended input and double-ended output transconductance amplifiers;

[0153] The first end of the thirteenth switch is the first input end of the common-mode feedback module;

[0154] The first end of the fourteenth switch is the second input end of the common-mode feedback module;

[0155] The first end of the twenty-eighth switch is the fourth input end of the common-mode feedback module;

[0156] The first end of the twenty-ninth switch is the third input end of the common-mode feedback module;

[0157] The second end of the thirteenth switch, the second end of the fourteenth switch, the second end of the twenty-eighth switch, and the second end of the twenty-ninth switch are connected to the inverting input terminal of OPA1;

[0158] The positive input terminal of OPA1 is connected to the reference voltage VREF;

[0159] The output terminal of OPA1 is connected to the first terminal of the fifteenth switch and the first terminal of the thirtieth switch;

[0160] The second end of the fifteenth switch is connected to the first end of the fifth capacitor and the input end of GM3;

[0161] The second terminal of the 30th switch is connected to the first terminal of the sixth capacitor and the input terminal of GM6;

[0162] The second terminal of the fifth capacitor is grounded;

[0163] The second terminal of the sixth capacitor is grounded;

[0164] The two output terminals of GM3 are the first output terminal and the second output terminal of the common mode feedback module respectively;

[0165] The two output terminals of GM6 are respectively the third output terminal and the fourth output terminal of the common-mode feedback module.

[0166] In this embodiment, the output module includes a seventh capacitor, an eighth capacitor and a DFFOPA module;

[0167] The DFFOPA module is a fully differential voltage operational amplifier;

[0168] The positive input terminal of the DFFOPA module is the first input terminal of the output module;

[0169] The inverting input terminal of the DFFOPA module is the second input terminal of the output module;

[0170] The reverse output terminal of the DFFOPA module is the first output terminal of the output module;

[0171] The positive output terminal of the DFFOPA module is the second output terminal of the output module;

[0172] A first end of the seventh capacitor is connected to the positive input end of the DFFOPA;

[0173] The second end of the seventh capacitor is connected to the reverse output end of the DFFOPA;

[0174] A first end of the eighth capacitor is connected to the inverting input end of the DFFOPA;

[0175] The second end of the eighth capacitor is connected to the positive output end of the DFFOPA.

[0176] like Figure 2 Figure 2 shows a chopping principle diagram of a chopper-zero fully differential operational amplifier circuit with digital calibration. Chopping technology is essentially a modulation technology that can suppress input offset voltage and low-frequency noise.

[0177] The input signal is modulated to a high frequency by the chopper, accompanied by odd harmonics with reduced amplitude. It is then superimposed with the noise signal and offset voltage and amplified by the amplifier. It then passes through the second chopper. At this time, the useful signal will be demodulated back to a DC signal by the chopper, while the offset voltage and noise will be modulated to a high frequency by the second chopper, also accompanied by higher frequency odd harmonics. Finally, the low-pass filter filters out the high-frequency noise and offset, leaving the useful signal, low-frequency noise and partial offset.

[0178] like Figure 3 As shown in the figure, the self-zeroing working principle diagram of a chopper-zeroed fully differential operational amplifier circuit with digital calibration is shown. In the self-zeroing mode, the input signal is not connected to the transconductance module. At the same time, the output switch is disconnected and no signal is output. At this time, the voltage difference between the zeroing capacitors C1 and C2 is V C for:

[0179] V C =V OS1 GM1R O -(V C +V OS2 )GM2R O

[0180] Right now

[0181]

[0182] In the amplification mode, the input signal is amplified and output normally, and the output signal VOA is:

[0183] V OA =(V IN +V OS1 )GM1R O -(V C +V OS2 )GM2R O

[0184] Simplified

[0185]

[0186] Then the input residual offset is

[0187]

[0188] It can be seen that the equivalent input offset voltage is reduced by a factor of the amplifier's gain.

[0189] like Figure 4 、 Figure 5 and Figure 6 FIG. 4 is a working principle diagram of a chopper-zero fully differential operational amplifier circuit with digital calibration;

[0190] The digital calibration module detects the output voltage of the transimpedance amplifier module and sends the output voltage to the comparator for comparison. The comparison result of the comparator is sent to the SAR LOGIC module to obtain a digital control signal. The digital control signal output by the SAR LOGIC controls the IDAC module to inject current into the input end of the transimpedance amplifier module, thereby adjusting the output voltage of the transimpedance amplifier module, that is, performing preliminary calibration of the offset voltage. Figure 5 As shown;

[0191] The clock phase of the chopper-zero fully differential operational amplifier is as follows: Figure 6 As shown, in phase 1, switches SN3 and SN5 are closed, and the remaining switches are open. The upper half of the circuit is in the auto-zero mode, and the lower half of the module is in the normal amplification mode.

[0192] In phase 2, switches SN2 and SN4 are closed, and the remaining switches are open. The upper half of the circuit is in common-mode level calibration mode, and the lower half of the module is in normal amplification mode.

[0193] In phase 3, switches SN2 and SN6 are closed, and the remaining switches are open. The upper half of the circuit is in normal amplification mode, and the lower half of the module is in auto-zero mode.

[0194] In phase 4, switches SN1 and SN5 are closed, and the remaining switches are open. The upper half of the circuit is in normal amplification mode, and the lower half of the module is in normal common-mode level calibration mode.

[0195] If the upper and lower modules each use a common-mode feedback module, when the common-mode feedback modules are mismatched, the output common-mode levels of the upper and lower modules will deviate, which will cause large glitches in the output signal. When the upper and lower modules use the same common-mode feedback module, it can effectively prevent the output common-mode levels of the upper and lower modules from being different due to the common-mode feedback module mismatch, thereby reducing the output signal glitches.

[0196] like Figure 7 FIG4 shows a gain-phase simulation result of a chopper-zero fully differential operational amplifier with digital calibration;

[0197] As can be seen from the figure, the gain of the fully differential operational amplifier of the present invention is as high as 172.47 dB, which is about 416,869,383 times, with very high precision, a bandwidth of 1.71 MHz, and a phase margin of 82.08°. The phase margin is sufficient and the circuit is stable.

[0198] like Figure 8 FIG4 shows the offset voltage simulation results of a chopper-zero fully differential operational amplifier with digital calibration;

[0199] A Monte Carlo simulation is performed on the operational amplifier of the present invention, i.e., the effects of process and mismatch are added, with 200 simulation points. From the simulation results, it can be seen that the average offset voltage is 13.717 nV. Therefore, the offset voltage of the operational amplifier is as low as nV level, which is very low.

[0200] Those skilled in the art can make various other corresponding changes and deformations based on the technical solutions and concepts described above, and all of these changes and deformations should fall within the scope of protection of the claims of the present invention.

Claims

1. A chopper-zero fully differential operational amplifier circuit with digital calibration, characterized in that: It includes a switch module, a transconductance module, a transresistance amplifier module, a capacitance module, a digital calibration module, a common-mode feedback module and an output module; The first transconductance module and the first transimpedance amplifier module serve as a first main amplifier; the third transconductance module and the second transimpedance amplifier module serve as a second main amplifier; the second transconductance module and the first transimpedance amplifier module serve as a first zeroing amplifier; and the fourth transconductance module and the second transimpedance amplifier module serve as a second zeroing amplifier. The first digital calibration module is used to preliminarily calibrate the offset voltage of the first main amplifier, and the second digital calibration module is used to preliminarily calibrate the offset voltage of the second main amplifier; the common-mode feedback module is used to stabilize the output common-mode voltage of the first transimpedance amplifier module and the second transimpedance amplifier module, and reduce the burrs of the output signal; the output module is used to output a differential signal; After the digital calibration module preliminarily calibrates the offset voltage of the main amplifier, chopping and auto-zeroing are achieved by switching switches in the first switch module, the second switch module, the third switch module, and the fourth switch module.

2. The chopper-zero fully differential operational amplifier circuit with digital calibration according to claim 1, wherein: The first input terminal of the first switch module is connected to the first input signal, the input signal number is VINP, and the second input terminal is connected to the second input signal, the input signal number is VINN; The first output terminal and the second output terminal of the first switch module are connected to the first input terminal and the second input terminal of the first transconductance module respectively, and the connection nodes are numbered N1 and N2 respectively; The first input terminal and the second input terminal of the third switch module are connected to the second input signal and the first input signal respectively; The first output terminal and the second output terminal of the third switch module are connected to the first input terminal and the second input terminal of the third transconductance module respectively, and the connection nodes are numbered N9 and N10 respectively; The first input terminal of the first transimpedance amplification module is connected to the first output terminal of the first transconductance module, the first output terminal of the first digital calibration module, the first output terminal of the second transconductance module, and the first output terminal of the common-mode feedback module, and the connection node is numbered N3; The second input terminal of the first transimpedance amplification module is connected to the second output terminal of the first transconductance module, the second output terminal of the first digital calibration module, the second output terminal of the second transconductance module, and the second output terminal of the common-mode feedback module, and the connection node is numbered N4; The first input terminal of the second transimpedance amplification module is connected to the first output terminal of the third transconductance module, the first output terminal of the second digital calibration module, the first output terminal of the fourth transconductance module, and the third output terminal of the common-mode feedback module, and the connection node is numbered N11; The second input terminal of the second transimpedance amplification module is connected to the second output terminal of the third transconductance module, the second output terminal of the second digital calibration module, the second output terminal of the fourth transconductance module, and the fourth output terminal of the common-mode feedback module, and the connection node is numbered N12; A first input terminal of the second switch module is connected to the first output terminal of the first transresistance amplifier module, the first input terminal of the first digital calibration module, and the first input terminal of the common-mode feedback, and the connection node is numbered N5; The second input terminal of the second switch module is connected to the second output terminal of the first transimpedance amplifier module, the second input terminal of the first digital calibration module, and the second input terminal of the common-mode feedback, and the connection node is numbered N6; The first output terminal and the second output terminal of the second switch module are connected to the first input terminal and the second input terminal of the first capacitor module respectively, and the connection nodes are numbered N19 and N20 respectively; The third output terminal of the second switch module is connected to the third output terminal of the fourth switch module and the first input terminal of the output module, and the connection node is numbered N17; The fourth output terminal of the second switch module is connected to the fourth output terminal of the fourth switch module and the second input terminal of the output module, and the connection node is numbered N18; The first input terminal of the fourth switch module is connected to the first output terminal of the second transimpedance amplifier module, the first input terminal of the second digital calibration module, and the third input terminal of the common-mode feedback, and the connection node is numbered N13; The second input terminal of the fourth switch module is connected to the second output terminal of the second transimpedance amplifier module, the second input terminal of the second digital calibration module, and the fourth input terminal of the common-mode feedback, and the connection node is numbered N14; The first output terminal and the second output terminal of the fourth switch module are connected to the first input terminal and the second input terminal of the second capacitor module respectively, and the connection nodes are numbered N21 and N22 respectively; The first output terminal and the second output terminal of the first capacitor module are connected to the first input terminal and the second input terminal of the second transconductance module respectively, and the connection nodes are numbered N7 and N8 respectively; The first output terminal and the second output terminal of the second capacitor module are connected to the first input terminal and the second input terminal of the fourth transconductance module respectively, and the connection nodes are numbered N15 and N16 respectively; The first output terminal and the second output terminal of the output module are connected to the first output signal and the second output signal respectively. The first output signal is numbered VOUTP and the second output signal is numbered VOUTN.

3. The chopper-zero fully differential operational amplifier circuit with digital calibration according to claim 1, wherein: The first switch module includes: a first switch, a second switch, a third switch, a fourth switch, a fifth switch and a sixth switch; The first end of the first switch, the first end of the second switch, the first end of the third switch, and the first end of the fourth switch are all connected to the first input signal VINP; the first end of the fifth switch and the first end of the sixth switch are all connected to the second input signal VINN; the second end of the first switch, the second end of the fourth switch, and the second end of the sixth switch are all connected to the node N2; the second end of the second switch, the second end of the third switch, and the second end of the fifth switch are all connected to the node N1; The third switch module includes: a sixteenth switch, a seventeenth switch, an eighteenth switch, a nineteenth switch, a twentieth switch, and a twenty-first switch; The first terminal of the sixteenth switch, the first terminal of the seventeenth switch, the first terminal of the eighteenth switch, and the first terminal of the nineteenth switch are all connected to the second input signal VINN; the first terminal of the twentieth switch and the first terminal of the twenty-first switch are all connected to the first input signal VINP; the second terminal of the sixteenth switch, the second terminal of the nineteenth switch, and the second terminal of the twenty-first switch are all connected to the node N10; the second terminal of the seventeenth switch, the second terminal of the eighteenth switch, and the second terminal of the twentieth switch are all connected to the node N9; The second switch module includes: a seventh switch, an eighth switch, a ninth switch, a tenth switch, an eleventh switch and a twelfth switch; The first end of the seventh switch, the first end of the eighth switch, and the first end of the ninth switch are all connected to the node N5; the first end of the tenth switch, the first end of the eleventh switch, and the first end of the twelfth switch are all connected to the node N6; the second end of the ninth switch is connected to the node N19; the second end of the tenth switch is connected to the node N20; the second end of the seventh switch and the second end of the eleventh switch are both connected to the node N18; the second end of the eighth switch and the second end of the twelfth switch are both connected to the node N17; The fourth switch module includes: a twenty-second switch, a twenty-third switch, a twenty-fourth switch, a twenty-fifth switch, a twenty-sixth switch, and a twenty-seventh switch; The first end of the twenty-second switch, the first end of the twenty-third switch, and the first end of the twenty-fourth switch are all connected to the node N13; the first end of the twenty-fifth switch, the first end of the twenty-sixth switch, and the first end of the twenty-seventh switch are all connected to the node N14; the second end of the twenty-fourth switch is connected to the node N21; the second end of the twenty-fifth switch is connected to the node N22; the second end of the twenty-second switch and the second end of the twenty-sixth switch are both connected to the node N18; the second end of the twenty-third switch and the second end of the twenty-seventh switch are both connected to the node N17.

4. The chopper-zero fully differential operational amplifier circuit with digital calibration according to claim 1, wherein: In the first transconductance module, the second transconductance module, the third transconductance module and the fourth transconductance module: The voltage positive input terminal is the first input terminal; The voltage negative input terminal is the second input terminal; The current positive output terminal is the first output terminal; The current negative output terminal is the second output terminal.

5. The chopper-zero fully differential operational amplifier circuit with digital calibration according to claim 1, wherein: In the first transimpedance amplifier module and the second transgroup amplifier module: The current positive input terminal is the first input terminal; The current negative input terminal is the second input terminal; The voltage positive output terminal is the first output terminal; The negative voltage output terminal is the second output terminal.

6. The chopper-zero fully differential operational amplifier circuit with digital calibration according to claim 1, wherein: The first digital calibration module includes a COMP1 module, a SAR LOGIC1 module and an IDAC1 module; The COMP1 module is a comparator module, the SAR LOGIC1 module is a successive approximation logic module, and the IDAC1 module is a current-mode digital-to-analog converter module; The two input terminals of the COMP1 module are respectively the first input terminal and the second input terminal of the first digital calibration module; The output of the COMP1 module is connected to the input of the SAR LOGIC1 module; The input of the IDAC1 module is connected to the output of the SAR LOGIC1 module; The two output terminals of the IDAC1 module are respectively the first output terminal and the second output terminal of the first digital calibration module.

7. The chopper-zeroed fully differential operational amplifier circuit with digital calibration according to claim 1, wherein: The second digital calibration module includes a COMP2 module, a SAR LOGIC2 module and an IDAC2 module; The COMP2 module is a comparator module, the SAR LOGIC2 module is a successive approximation logic module, and the IDAC2 module is a current-mode digital-to-analog converter module; The two input terminals of the COMP2 module are respectively the first input terminal and the second input terminal of the second digital calibration module; The output of the COMP2 module is connected to the input of the SAR LOGIC2 module; The input end of the IDAC2 module is connected to the output end of the SAR LOGIC2 module; The two output terminals of the IDAC2 module are respectively the first output terminal and the second output terminal of the second digital calibration module.

8. The chopper-zeroed fully differential operational amplifier circuit with digital calibration according to claim 1, wherein: The first capacitor module includes a first capacitor and a second capacitor; A first end of the first capacitor is connected to a ground, which is a ground port; The second end of the first capacitor is simultaneously the first input end and the first output end of the first capacitor module; A first terminal of the second capacitor is connected to the ground terminal; The second end of the second capacitor is also the second input end and the second output end of the first capacitor module; The second capacitor module includes a third capacitor and a fourth capacitor; A first terminal of the third capacitor is connected to the ground terminal; The second end of the third capacitor is simultaneously the first input end and the first output end of the second capacitor module; A first terminal of the fourth capacitor is connected to the ground terminal; The second end of the fourth capacitor is simultaneously the second input end and the second output end of the second capacitor module.

9. The chopper-zeroed fully differential operational amplifier circuit with digital calibration according to claim 1, wherein: The common-mode feedback module includes a thirteenth switch, a fourteenth switch, a fifteenth switch, a twenty-eighth switch, a twenty-ninth switch, a thirtieth switch, a fifth capacitor, a sixth capacitor, an OPA1 module, a GM3 module, and a GM6 module; The OPA1 module is a dual-ended input, single-ended output operational amplifier; The GM3 and GM6 modules are single-ended input and double-ended output transconductance amplifiers; The first end of the thirteenth switch is the first input end of the common-mode feedback module; The first end of the fourteenth switch is the second input end of the common-mode feedback module; The first end of the twenty-eighth switch is the fourth input end of the common-mode feedback module; The first end of the twenty-ninth switch is the third input end of the common-mode feedback module; The second end of the thirteenth switch, the second end of the fourteenth switch, the second end of the twenty-eighth switch, and the second end of the twenty-ninth switch are connected to the inverting input terminal of OPA1; The positive input terminal of OPA1 is connected to the reference voltage VREF; The output terminal of OPA1 is connected to the first terminal of the fifteenth switch and the first terminal of the thirtieth switch; The second end of the fifteenth switch is connected to the first end of the fifth capacitor and the input end of GM3; The second terminal of the 30th switch is connected to the first terminal of the sixth capacitor and the input terminal of GM6; The second terminal of the fifth capacitor is grounded; The second terminal of the sixth capacitor is grounded; The two output terminals of GM3 are the first output terminal and the second output terminal of the common mode feedback module respectively; The two output terminals of GM6 are respectively the third output terminal and the fourth output terminal of the common-mode feedback module.

10. The chopper-zeroed fully differential operational amplifier circuit with digital calibration according to claim 1, wherein: The output module includes a seventh capacitor, an eighth capacitor and a DFFOPA module; The DFFOPA module is a fully differential voltage operational amplifier; The positive input terminal of the DFFOPA module is the first input terminal of the output module; The inverting input terminal of the DFFOPA module is the second input terminal of the output module; The reverse output terminal of the DFFOPA module is the first output terminal of the output module; The positive output terminal of the DFFOPA module is the second output terminal of the output module; A first end of the seventh capacitor is connected to the positive input end of the DFFOPA; The second end of the seventh capacitor is connected to the reverse output end of the DFFOPA; A first end of the eighth capacitor is connected to the inverting input end of the DFFOPA; The second end of the eighth capacitor is connected to the positive output end of the DFFOPA.

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