Embedded special high-frequency low-level control system

Abstract

The application discloses an embedded special high-frequency low-level control system, which comprises a digital signal processing board, an ADC / DAC sub-board and a radio frequency front-end board; the radio frequency front-end board comprises two up-conversion channels and six down-conversion channels, and the digital signal processing board comprises an FPGA; wherein the radio frequency front-end board is used for dividing an input reference line RF signal into four RF reference signals and generating an LO signal; the ADC / DAC sub-board is used for ADC analog-digital conversion and DAC digital-analog conversion; and the main functions of the digital signal processing board include clock distribution of the RF reference signal, a motor driving circuit and a piezo ceramic driving circuit, data acquisition and logic control algorithm of a FPGA logic unit PL part, an embedded ARM system of a FPGA processor unit PS part, EPICS-IOC application of a low-level system, network data communication and the like.

Description

Technical Field

[0001] This invention belongs to the field of accelerator technology, specifically relating to an embedded dedicated high-frequency low-level control system for low-level control of high-frequency systems in High Energy Photon Source (HEPS) projects, and can be widely used in related projects involving high-frequency signal data acquisition and control. Background Technology

[0002] High-frequency systems are crucial in accelerator devices, serving as the "engine" of the entire accelerator system. A radio frequency electric field is established within the high-frequency resonant cavity, and charged particles move along a longitudinal trajectory. When they pass through the radio frequency electric field, they gain energy in the acceleration phase and are accelerated, or they are focused longitudinally.

[0003] The high-frequency low-level control system is one of the basic components of the accelerator's high-frequency system. Its main functions include high-frequency cavity field amplitude control and cavity field phase control, high-frequency cavity frequency tuning control, and safety interlock protection, so as to ensure the stable operation of the high-frequency system and even the accelerator system.

[0004] The Institute of High Energy Physics, Chinese Academy of Sciences, developed a dedicated digital low-level control system with basic cavity field amplitude and phase control and cavity frequency tuning control functions. However, the digital signal processing board of this low-level system cannot independently run IOC (Input / Output Controller) applications. It requires an additional server to run IOC applications based on EPICS (Experimental Physics and Industrial Control System). At the same time, the ADC and DAC are integrated on the digital signal board without separating digital and analog circuits, making it difficult to upgrade the ADC / DAC. Moreover, the ADC only has 6 channels and the DAC only has 2 channels, which is relatively few and cannot meet the needs of high-frequency low-level systems for acquiring more RF (Ratio Frequency) signal data. Summary of the Invention

[0005] To address the shortcomings of the aforementioned low-level control systems, this invention provides an embedded, dedicated high-frequency low-level control system. This invention improves upon the low-level control system by designing and manufacturing a dedicated Xilinx embedded FPGA-based Digital Signal Processing (DSP) board, ADC / DAC sub-board, and RF front-end board; and develops a low-level control program, an embedded Linux system, low-level system hardware drivers, and EPICS IOC applications. The improvements to the low-level system mainly focus on the following three aspects:

[0006] 1) Both Xilinx's ZYNQ series FPGAs and Altera's FPGAs with embedded Nios-II soft cores adopt a System-on-Chip (SoC) architecture, integrating the processor and programmable logic units onto a single FPGA chip. The ZYNQ series FPGAs integrate an ARM Cortex-A9 hard-core processor, offering high processing speed and efficiency, making them suitable for applications requiring powerful processing capabilities. Altera's Nios-II, on the other hand, is a soft-core processor running on the FPGA's logic resources, offering high flexibility but lower performance. Therefore, this invention replaces the FPGA on the digital signal processing board with Xilinx's ZYNQ-7000 series ZYNQ7100, which embeds an ARM Cortex-A9 hard-core processor and can independently run a Linux operating system. A new EPICS-IOC application for low-level control systems has been developed on the Linux system, including hardware drivers for low-level devices, log support files, device support files, and a low-level IOC database.

[0007] 2) The analog-to-digital circuits are separated, and the ADC / DAC daughterboard is designed independently. It is connected to the DSP card in a bridging manner through the FMC (FPGA Mezzanine Card) interface, which reduces the noise interference of digital circuits on high-performance ADC / DAC circuits and improves signal integrity. At the same time, this also facilitates fault maintenance, upgrading or improvement of the ADC / DAC circuit chip design, and improves flexibility.

[0008] 3) The microwave components on the RF front-end board mainly include power dividers, mixers, and amplifiers. These microwave components were replaced, expanding the microwave high-frequency operating band to cover the RF frequency range of 100MHz to 2GHz. Furthermore, the bandpass filters for RF (Ratio Frequency), LO (Local Oscillator), and IF (Intermediate Frequency) frequencies were all packaged with identical filters. This means that for different RF operating frequencies, only the corresponding RF frequency bandpass filter, LO local oscillator frequency bandpass filter, and IF intermediate frequency low-pass filter need to be replaced for direct use.

[0009] The technical solution of this invention is as follows:

[0010] The hardware primarily includes a digital signal processing board, an ADC / DAC daughterboard, and an RF front-end board. Both the circuit schematics and PCB layout were completed using Altium Designer. The DSP board uses a Xilinx FPGA as its core chip. Its Programmable Logic (PL) section implements various low-level control algorithms, including cavity field amplitude and phase loop control, cavity frequency tuning control, maximum power protection, and superconducting cavity quench protection. The Processing System (PS) section integrates two ARM Cortex-A9 processors, running an embedded Linux operating system, and independently running low-level IOC applications. The ADC / DAC daughterboard connects to the DSP board via an FMC interface in a bridged manner to complete the conversion between analog and digital signals. The RF front-end board includes functions for generating the LO local oscillator signal, up-converting the IF intermediate frequency excitation analog signal, and down-converting the RF acquisition signal. The control software is based on the EPICS control system; the upper-level control interface is based on CS-Studio.

[0011] The RF front-end board mainly includes:

[0012] 1) RF reference signal power division: The reference line RF signal is used as the input signal. After passing through a 4-way power divider, it outputs 4 RF reference signals. The first RF reference signal output is sent to the clock distribution unit of the DSP board for clock distribution, which will generate an IF intermediate frequency reference signal and return it to the RF front-end board. The second RF reference signal output is mixed with the IF intermediate frequency reference signal output from the clock distribution unit of the DSP board and then filtered by bandpass to obtain the LO local oscillator signal. The third RF reference signal output is sent to each downconversion channel for downconversion and then output to the ADC / DAC sub-board for ADC acquisition. The last RF reference signal is output as an RF spare signal to the front panel of the low-level control chassis.

[0013] 2) Generation of LO signal: The IF intermediate frequency reference signal output from the clock distribution unit of the DSP board is low-pass filtered and then mixed with the RF reference signal. The mixed signal contains two frequencies: RF ± IF. This signal is first amplified by an amplifier, and then passed through a bandpass filter of the LO local oscillator frequency to obtain the LO local oscillator signal. The LO frequency is equal to the RF frequency minus the IF frequency. Then, it is divided by 2 power dividers and then by 4 power dividers to obtain 8 LO frequency signals, which are then sent as LO local oscillator signals to the mixers of 2 upconversion channels and 6 downconversion channels, respectively.

[0014] 3) 6-channel downconversion: The RF acquisition signals, such as cavity forward power signal Pf, cavity reflection power signal Pr, cavity field return signal Pt, etc., and the LO local oscillator signal are mixed by a mixer, amplified by an amplifier, and then filtered by a low-pass filter to obtain the corresponding IF intermediate frequency acquisition analog signal of the RF acquisition signal. The output IF intermediate frequency acquisition analog signal will be connected to the ADC sampling channel of the ADC / DAC sub-board.

[0015] 4) Two-way frequency conversion channel: The IF intermediate frequency excitation analog signal and LO local oscillator signal output from the ADC / DAC sub-board are mixed by a mixer, amplified by an amplifier, and then filtered by a bandpass filter at the RF frequency to obtain a low-level RF excitation signal output. This RF output signal is used as a low-level excitation and sent to a power source for power amplification, and then sent to the high-frequency cavity for field establishment.

[0016] The main changes compared to the first-generation dedicated low-level control system's RF front-end board are:

[0017] 1) Change the 1-channel upconversion to 2-channel upconversion to increase the redundancy of the RF excitation output channels; change the 5-channel downconversion to 6-channel downconversion to increase the number of channels for RF signal acquisition.

[0018] 2) The microwave devices of the RF front-end board, including amplifiers, mixers, power dividers, etc., have been improved. The original microwave devices could only operate within 1 GHz, but after the improvement, the RF frequency can operate within 2 GHz.

[0019] 3) The LDO low dropout linear regulator has been upgraded to a high-performance regulator with lower noise, higher output current, and lower dropout voltage, thereby improving the performance of the RF front-end board.

[0020] The ADC / DAC daughterboard mainly includes:

[0021] This board functions as an ADC (Analog-to-Digital Converter) and a DAC (Digital-to-Analog Converter), acting as a bridge between the RF front-end board and the DSP (Digital Signal Processing) board. It connects to the FPGA (FPGA-based Digital Signal Processing) board via the FMC (Functional Module Control) interface and to the RF front-end board's IF (Intermediate Frequency) signals (including the IF excitation analog signal and the IF sampling analog signal) via the SMA (Simplified Module Control) interface.

[0022] First, the ADC / DAC daughterboard receives the IF intermediate frequency excitation digital signal output by the FPGA through the FMC interface, and outputs the IF intermediate frequency excitation analog signal after digital-to-analog conversion by the DAC, and then outputs it to the RF front-end board through the SMA interface.

[0023] Secondly, the ADC / DAC daughterboard receives the IF intermediate frequency acquisition analog signal output from the RF front-end board through the SMA interface, outputs the IF intermediate frequency acquisition digital signal after analog-to-digital conversion by the ADC, and then outputs it to the FPGA through the FMC interface.

[0024] The clock and power signals for the ADC and DAC are provided by the DSP digital signal processing board through the FMC interface.

[0025] The sub-board is matched with 6 down-conversion channels of the RF front-end board, including 6 high-speed ADC channels; and with 2 up-conversion channels of the RF front-end board, the sub-board includes 2 high-speed DAC channels.

[0026] Digital signal processing boards mainly include:

[0027] Digital signal processing boards are the core of low-level control systems. Their main functions include clock distribution of RF reference signals, motor drive and Piezo ceramic drive circuits, data acquisition and logic control algorithms in the FPGA logic unit PL section, embedded ARM system in the FPGA processor unit PS section, EPICS-IOC application for low-level systems, and network data communication.

[0028] The RF reference signal clock distribution unit takes the RF reference signal as input. After the clock is divided by N, the ADC clock, DAC clock, and FPGA operating clock are obtained. The ADC clock and DAC clock are sent to the ADC / DAC sub-board, and the FPGA operating clock is sent to the FPGA. After the clock is divided by M times, the IF intermediate frequency reference signal is obtained and sent to the RF front-end board.

[0029] The data acquisition and logic control algorithms of the FPGA logic unit PL section mainly complete the amplitude and phase loop control of the high-frequency cavity field and the cavity frequency tuning control. The input signals for the amplitude and phase loop acquisition of the cavity field include the RF reference signal REF and the cavity field sampling signal Pt. REF and Pt are RF signals. These two RF signals are first down-converted to IF intermediate frequency (IF) analog signals by the RF front-end board, then sent to the ADC / DAC sub-board and converted to IF IF digital signals. These signals are then sent to the FPGA for Non-IQ sampling to obtain the quadrature I / Q signals corresponding to REF and Pt. These two pairs of I / Q quadrature signals are then fed into the FPGA's cavity field amplitude and phase loop algorithm, output by the DDS as IF IF excitation digital signals, sent to the ADC / DAC sub-board to obtain the IF IF excitation analog signals, then through the RF front-end board to obtain the RF excitation signals, and finally amplified by the power source before being sent into the high-frequency cavity for field establishment. The input signals for the cavity frequency tuning control acquisition include the high-frequency cavity forward power signal Pf and the cavity field sampling signal Pt. Similarly, the I / Q quadrature of these two signals is obtained, and then the phase of the forward power (forw_pha) and the phase of Pt (cav_pha) are obtained by the Cordic algorithm. The difference between the two (dif_angle) is sent to the frequency control loop algorithm to obtain the motor drive pulse signal (pulse), the direction signal (dir), and the digital signal of the piezo drive (piezo_out). The pulse and dir signals are sent to the motor driver to drive the motor to slowly tune the cavity. The piezo_out signal is output as a piezo drive analog signal by the slow DAC and then sent to the piezo driver for amplification to drive the piezo ceramic on the cavity to achieve fast tuning of the cavity frequency.

[0030] The low-level register units within the FPGA (Digital Signal Processing Board) include low-level write registers and low-level read registers, used to write low-level control quantities and read low-level status quantities, respectively. Low-level control quantities mainly include setting the cavity voltage Vc_Set, setting the phase Pha_Set, setting the detuning angle Load_angle, the cavity field amplitude and phase closed-loop switch Vc_Loop, the frequency control loop closed-loop switch Freq_Loop, and the RF switch RF_ON, etc. These control quantities are written through the FPGA's internal write registers. Low-level status quantities mainly include cavity voltage Vc, phase Vc_Pha, the amplitude and phase of the cavity forward power Pf, and the amplitude and phase of the reflected power Pr, etc. These low-level status quantities are stored in the FPGA's internal low-level read register group for convenient access and retrieval.

[0031] Compared to the first-generation dedicated low-level control system, the main improvements of this DSP board are:

[0032] 1) The digital signal processing board no longer includes high-speed ADC and DAC circuits. It is designed with two FMC interfaces, which can bridge two ADC / DAC daughter boards, enabling a maximum of 12 high-speed ADC sampling channels and 4 high-speed DAC output channels. 2) The clock distribution chip unit uses the same clock distribution chip, but considering the increase in ADC and DAC channels,

[0033] The clock distribution chip was changed from one to two. Each of the two clock distribution chips can be configured independently, allowing for different clock distribution parameters. This enables the board to run two low-level control systems simultaneously, using different clock configurations or even different RF frequencies, increasing system flexibility.

[0034] 3) The motor drive unit and piezo drive unit have also been upgraded to accommodate two low-level systems. 4) The FPGA chip has been changed from the Altera Stratix III series EP3SL150F1152C2 to the Xilinx ZYNQ-7000 series XC7Z100-2FFG900I. The latter has several advantages and differences compared to the former:

[0035] a) The FPGA integrates an embedded ARM Cortex-A9 hard-core processor, can run the Linux operating system independently, and can independently run the EPICS-IOC application of the low-level control system on the Linux system;

[0036] b) It has more logic processing units, DSP data signal processing units, and block memory (BRAM), etc.

[0037] c) Configure DDR3 DRAM and QSPI flash internal memory, as well as external interfaces such as HDMI, Ethernet, UART, JTAG, and SD card slot on the FPGA periphery. This allows the DSP board to be used as an independent server running a Linux system and to develop applications related to low-level systems such as EPICS-IOC.

[0038] d) Using the Petalinux embedded Linux development tool, a custom Linux kernel configuration, low-level register device tree generation, root file system customization, application cross-compilation development and debugging, and system image file generation were completed. The system image files include BOOT.BIN and image.ub. BOOT.BIN is the boot image file for the embedded system, mainly including FSBL (First Stage Boot Loader), FPGA Bitstream for configuring the FPGA logic program, and SSBL (Second Stage Boot Loader) U-Boot. image.ub is a combined image file containing the Linux kernel, device tree, and root file system. It is the main file in BOOT.BIN for U-Boot to load and start the Linux system. The system image files BOOT.BIN and image.ub are stored on the boot media SD card; that is, the SD card contains the bitstream files of the PL part and the operating system files of the PS part, which allows for very convenient copying, porting, and updating of the low-level control system program. 5) Unlike Altera's FPGAs, which are pure programmable logic units, the ZYNQ-7000 series FPGAs integrate programmable logic units (PL) and processor systems (PS), making the communication method of low-level systems completely different. The algorithm programs for writing low-level control parameters and reading status parameters on the FPGA side were redeveloped, a low-level register device driver for Linux system was developed, and a low-level EPICS IOC application running on embedded Linux system was developed.

[0039] a) Writing low-level system control parameters and reading status parameters: The axi_lite_slave module is used to interconnect the PL and PS parts of the FPGA via the axi-lite bus. Memory-mapped communication is used to map the registers on the PL side to the memory address storage space on the PS side. The axi-lite bus mainly includes the write data signal axi_wdata, the write address signal axi_waddr, the read data signal axi_rdata, and the read address signal axi_raddr. When writing control parameters, the PS processor, acting as the master, transmits the written parameter data axi_wdata and the write address axi_waddr to the PL of the slave device. The PL then writes the data axi_wdata into the corresponding register according to the write address axi_waddr, thus setting the low-level control variable. When reading status parameters, the PS processor, acting as the master, transmits the read address axi_raddr to the PL of the slave device. The PL then transmits the register value axi_rdata at the corresponding address to the PS, which writes it into the memory address corresponding to the PS's read address axi_raddr, thus reading the low-level status parameter.

[0040] b) Driver development for low-level register devices: Add the corresponding node for the low-level register device to the device tree, including the device node name, register address range, register address length, etc. Create the driver for the low-level register device to enable the EPICS-IOC application to read and write to the low-level register of the hardware device. The hardware driver for the low-level register device mainly includes: 1. Creating a low-level register device structure, which contains the device node in the device tree; 2. Declaring the device operation function structure `file_operations` for the low-level register device. `file_operations` covers all Linux kernel operation functions, including device open, read, write, control, and close functions, and is the core of the device driver; 3. Creating the device open function `open()` to open the low-level register device; 4. Creating the read operation function `read()` to read data from the low-level register; 5. Creating the write operation function `write()` to write to the low-level register. 6. Create the I / O control operation function ioctl(), used by the application to transmit control commands to the low-level register device; 6. Create the device release operation function release(), used to close the low-level register device; 7. Create the registration module loading function init() and the registration module unloading function exit(). The low-level register device driver needs to be compiled into a driver module file to run in the Linux kernel space. The application needs to load this driver module file to operate the device. The registration module loading function init() is the entry function of the driver function, which loads the registration module. The registration module unloading function exit() is the exit function of the driver function, which unloads the registration module.

[0041] c) Development of EPICS-IOC Applications: 1. First, build the EPICS control system: Download the standard EPICS Base installation package, set the cross-compiler location, add the cross-compilation framework, and then perform cross-compilation to complete the Base installation. 2. Use EPICS instructions to create a standard IOC application, generating the basic IOC application for the low-level control system. 3. Create a low-level register device support file (Device support) for opening low-level register devices. 4. Create a low-level device record support file (Record Support), including ai, ao, bi, bo, etc.

[0042] Supports recording files of various data types, including waveform, and allows calling device operation functions such as read() and write().

[0043] The `ioctl()` function and other methods are used to read from and write to low-level register devices. 5. Create a Device Support Database Definition (DPS Database Definition) file for the low-level register device. This file describes the interface between the device support modules, record types, and the hardware driver for the low-level register device, enabling the EPICS system to interact with the low-level hardware device. 6. Create a database file containing `ai`,

[0044] 7. Cross-compile low-level EIPICS IOC applications. 8. Copy the cross-compiled EPICS Base and EPICS IOC applications to the user file directory of the embedded Linux system running on the PS side of the DSP board FPGA, and run the EPICS IOC application to complete the development of the low-level EPICS IOC application.

[0045] Furthermore, for different RF frequencies, the RF front-end board only needs to modify the corresponding RF filter, LO filter, and low-pass filter, and the digital signal processing board and ADC / DAC sub-board can be used interchangeably.

[0046] Furthermore, in addition to the basic cavity field amplitude and phase loop control and cavity frequency tuning control, the low-level control algorithm has also developed algorithms including DOB (Disturbance Observer) control algorithm, NANC (Narrow-band Active Noise Control) algorithm, and ADRC (Active Disturbance Rejection Control) algorithm.

[0047] Compared to the previous version of the dedicated low-level system, this invention has the following advantages:

[0048] 1) The FPGA uses Xilinx's ZQYN-7000 series chip, with an embedded ARM core and a Linux operating system installed, to independently run the EPICS IOC application for low-level systems.

[0049] 2) High portability: The PL and PS parts of the FPGA are both stored on the SD card.

[0050] 3) An ADC / DAC daughterboard is used, separating the analog and digital circuits. This facilitates the upgrading and updating of the ADC / DAC chip without requiring changes to the DSP board.

[0051] 4) The DSP board has two FMC bridge interfaces, which can set the maximum number of ADC channels to 12 and the maximum number of DAC channels to 4, doubling the number of channels.

[0052] 5) One DSP board is equipped with two clock configuration chips, which enables the operation of two low-level control systems with different RF frequencies.

[0053] 6) The RF band range of the radio frequency front-end board has been expanded to 100MHz to 2GHz. Attached Figure Description

[0054] Figure 1 This is a block diagram of the low-level control system.

[0055] Figure 2 This is a schematic diagram of a digital signal processing board.

[0056] Figure 3 This is the schematic diagram of the ADC / DAC daughterboard.

[0057] Figure 4 This is the schematic diagram of the radio frequency front-end board.

[0058] Figure 5 This is a schematic diagram for FPGA functional development.

[0059] Figure 6 This is a schematic diagram of the principle framework of a low-level software system.

[0060] Figure 7 This is an overall integrated tuning diagram for a high-frequency system. Detailed Implementation

[0061] The present invention will now be described in further detail with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0062] 1. Top-level design

[0063] The block diagram of the low-level control system is as follows: Figure 1 As shown, the system mainly includes a digital signal processing board, an ADC / DAC sub-board, an RF front-end board, and a low-level control chassis. The digital signal processing board performs digital signal acquisition and control algorithm functions, clock distribution, and network communication. The ADC / DAC sub-board performs analog-to-digital signal conversion. The RF front-end board performs up-conversion of the IF intermediate frequency excitation analog signal to obtain the RF excitation signal and down-conversion of the RF acquisition signal to obtain the IF intermediate frequency acquisition analog signal. The low-level control chassis provides power to the boards and interfaces with external devices.

[0064] 2. Hardware Design

[0065] Altium Designer was used for circuit schematic design and PCB layout.

[0066] DSP board hardware design:

[0067] The schematic diagram of the DSP board is as follows: Figure 2 As shown.

[0068] The core of the DSP board is an FPGA chip, specifically the Xilinx ZYNQ-7100-2FFG900I chip. Its power supply (PS) section includes an ARM dual-core Cortex-A9 application processor. The FPGA includes interconnects, internal memory, external memory interfaces, and peripherals. Its PL section has 444K logic cells and 277.4K lookup tables (LUTs). Its ALM and LE counts are 56.8k and 142.5k respectively, and it has 900 I / O pins. For an LLRF low-level system, the number of logic cells and pins is sufficient to meet design requirements. The FPGA's PL and PS sections are interconnected via an AXI bus.

[0069] The FPGA's PS (Power Switch) section is externally configured with two 4Gb DDR3 DRAM chips and two 256Mb Quad-SPI FLASH chips. The DDR3 serves as the main memory for the embedded ARM system, used to run the operating system and applications, store temporary data and cache, and support peripheral data transfer and buffering. The Flash memory is the non-volatile memory in the embedded ARM system, used for permanent storage of program code, configuration data, and user data. It also features a rich set of peripheral interfaces, including one Gigabit Ethernet port, two USB 2.0 ports, one HDMI output port, one UART serial port, one JTAG port, and one SD card slot. The network interface enables network data interaction with external network devices. The USB ports can connect to external USB slave devices such as keyboards and mice; the HDMI port can connect to external display devices such as monitors; the UART serial port can be used to connect to external computers for communication and facilitating debugging of the user's Linux system; the JTAG port is used for downloading and debugging the FPGA program; and the SD card slot can accept SD cards for loading the bitstream files of the FPGA PL (Power Logic) section and the operating system files of the PS section.

[0070] The clock distribution unit mainly includes two AD9520 chips and one CPLD chip. The AD9520 is the clock distribution chip, which takes the RF reference signal as input and generates two sets of output signals, including: FPGA operating clock, ADC clock, DAC clock, IF intermediate frequency reference signal, etc. The CPLD chip serves as the configuration chip for the AD9520, and completes the flexible configuration of the AD9520 parameters based on the serial SPI interface.

[0071] The motor drive circuit is equipped with an optocoupler isolation chip to isolate the FPGA's motor drive pulse signal (pulse) and direction signal (dir) before outputting them through the SCSI interface. This drives the motor to achieve slow tuning of the high-frequency cavity. The upper and lower mechanical limit switch signals of the motor are input through the SCSI interface, converted to TTL signals, and then optically isolated before being input to the FPGA as the motor's mechanical limit signals. The voltage signal of the motor position is sent to a serial slow ADC via an SMA interface, converted into a digital signal, and then sent to the FPGA to achieve electrical limit of the motor position. A serial DAC is configured to convert the FPGA's piezo drive digital signal into a piezo drive analog signal, ultimately achieving fast piezo tuning of the high-frequency cavity.

[0072] Two FMC interfaces are configured to bridge the ADC / DAC daughterboard, sending the ADC clock and DAC clock to the ADC and DAC chips, thus realizing the signal interconnection between the ADC / DAC and the FPGA.

[0073] It is equipped with two reset switches, which can be used as hard reset switches for FPGA programs; two SMA interfaces that pass through the FPGA, which can be used to connect external trigger signals; and 10 I / O expansion ports, which facilitate the expansion of low-level system hardware functions.

[0074] Based on the chip selection and functional requirements, the schematic diagram was designed and the PCB was drawn. Since the digital signal processing board involves complex circuits and a large number of signals, the PCB design adopts a 16-layer stack-up design to ensure signal integrity and good EMC electromagnetic shielding performance.

[0075] ADC / DAC daughterboard hardware design:

[0076] First, based on the FMC interface of the DSP board, determine the size of the ADC / DAC daughterboard and the location of the FMC interface. The ADC configuration includes three dual-channel, 16-bit AD9268-125 chips with a maximum sampling rate of 125 MSPS; the DAC configuration includes one dual-channel, 16-bit AD9788 chip with a maximum sampling rate of 800 MSPS. The block diagram of the ADC / DAC daughterboard is shown below. Figure 3 As shown.

[0077] RF front-end board hardware design:

[0078] The high-frequency RF acquisition information includes the reference signal REF, cavity forward power signal Pf, cavity reflected power signal Pr, cavity field retrieval signal Pt, beam current signal Pb, and the output signal is the RF excitation signal of the power source. Considering redundancy, the RF front-end board includes 6 down-conversion channels and 2 up-conversion channels. Common RF signal frequencies for high-frequency cavities mainly include 166.6MHz, 499.8MHz, and 1.3GHz RF frequencies. The main components involved in the RF front-end board include power dividers, amplifiers, mixers, filters, and voltage regulators. The selection of these RF components first considers their operating bandwidth covering the RF band from 100MHz to 2GHz, then selects them based on the main characteristics of each RF component, and finally completes the schematic design and PCB layout. PCB layout mainly considers channel isolation and, in conjunction with the digital signal processing board, channel layout design, and other aspects to complete the design. The basic principle block diagram of the RF front-end board is shown below. Figure 4 As shown.

[0079] 3. FPGA Function Development

[0080] FPGA functional development schematic diagram as follows Figure 5 As shown.

[0081] The Vivado FPGA integrated development environment platform was used to develop the firmware control algorithm for the PL side and configure the hardware of the embedded ARM processor for the PS part.

[0082] The firmware control algorithm on the PL side is based on the first-generation low-level control firmware algorithm, and incorporates cavity field amplitude and phase loop control algorithm, cavity frequency tuning loop control algorithm, etc. DOB control algorithm, NANC control algorithm, ADRC control algorithm, etc., have also been developed.

[0083] The PS terminal is equipped with DDR3 memory, flash memory, network interface, HDMI interface, USB interface, serial UART interface, SD card interface, etc.

[0084] The PL side develops an axi_lite_slave module based on the axi-lite bus, allocates memory memory address space, and enables the PS's memory memory space to write data to the low-level write register and to write low-level read register data to the PS's memory memory space, thereby realizing the writing of low-level control parameters and the reading of status parameters.

[0085] 4. Software Development

[0086] The schematic diagram of the low-level software system is as follows: Figure 6As shown. The software system is based on the EPICS control system for developing low-level IOC applications, specifically including: 1. Developing hardware drivers for low-level register devices to implement read and write operations on the memory address data corresponding to the low-level registers in the Linux kernel space. 2. Writing device support files, responsible for mapping EPICS record operations (open, read, write, etc.) to the hardware device operations of low-level registers. 3. Writing record support files, including record types such as ai, ao, bi, bo, and waveform, which define the specific logical processing methods for record types and interact with the device support module to implement read and write operations on low-level register devices. 4. Writing device support database definition .dbd files, defining the interfaces of device support modules, record types, and device driver functions, and integrating device driver functions with the EPICS system. 5. Creating database files, all records in the low-level system are created and defined through database files, describing all record types of the low-level EPICS control system, defining record fields, and associating with device support modules to implement read and write operations on low-level register hardware devices. After the EPICS IOC for the low-level system is created and running, Channel Access (CA), as the core communication protocol of EPICS, provides the function of accessing and manipulating process variables (PVs). Channel Access can read and write database records through Database Access, while CA also publishes the PV quantities of the EPICS system through the network. Clients (OPI) and data servers connected to the network can read and write PV quantities through CA, thereby realizing the writing of low-level control parameters and the reading of status parameters. This ultimately enables the EPICS IOC application to read and write to the ARM core's memory storage space, realizes data interaction between the application layer and the digital signal processing board, and enables the reading and writing of the FPGA's internal low-level registers for low-level algorithm control. The upper-layer control interface of the OPI client is based on Control System Studio (CS-Studio).

[0087] 5. System integration and debugging

[0088] After the digital signal processing board, ADC / DAC daughterboard, and RF front-end board are fabricated and the chips are soldered, a low-level chassis design is required to integrate them into a complete low-level control system. The front panel of the chassis mainly includes a power switch, LED status lights, RF signal input interfaces, RF signal excitation output interfaces, and ceramic excitation output interfaces. The rear panel contains motor drive input / output interfaces, a reset switch, a trigger interface, a network port, and a 220V power input.

[0089] Overall integration and debugging of high-frequency systems, such as Figure 7 As shown. The reference line provides a low-level RF reference signal. The low-level control system acquires the cavity field feedback signal Pt, the cavity forward power signal Pf, and the cavity reflection power signal Pr. The low-level RF excitation output signal is sent to the power source through an RF switch. The power source amplifies the RF excitation signal and then sends it to the high-frequency cavity for field establishment after passing through a circulator. The low-level system also controls the frequency by tuning the high-frequency cavity through a tuning driver, including a motor driver and a Piezo ceramic driver. The low-level system interacts with the client OPI and the database server via a network. Multiple clients can be connected to the network, enabling multiple users to operate the low-level device.

[0090] Although specific embodiments of the invention have been disclosed for illustrative purposes to aid in understanding and implementing the invention, those skilled in the art will understand that various substitutions, variations, and modifications are possible without departing from the spirit and scope of the invention and the appended claims. Therefore, the invention should not be limited to the content disclosed in the preferred embodiments, and the scope of protection claimed by the invention is defined by the claims.

Claims

1. An embedded special-purpose high-frequency low-level control system, characterized by, The device comprises a digital signal processing board, an ADC / DAC sub-board, and a radio frequency front-end board; the radio frequency front-end board comprises two up-conversion channels and six down-conversion channels, and the digital signal processing board comprises an FPGA; wherein The radio frequency front-end board is configured to divide an input reference line RF signal into four RF reference signals, send the first RF reference signal to a clock distribution unit of the digital signal processing board to generate an IF intermediate frequency reference signal, return the IF intermediate frequency reference signal to the radio frequency front-end board, mix the second RF reference signal with the IF intermediate frequency reference signal, perform band-pass filtering to obtain an LO local oscillator signal, then divide the LO local oscillator signal into eight signals and send the eight signals into mixers of the two up-conversion channels and the six down-conversion channels respectively, send the third RF reference signal to one of the down-conversion channels for down-conversion, mix an input RF acquisition signal with the LO local oscillator signal in the down-conversion channel, perform filtering to obtain an IF intermediate frequency acquisition analog signal of the corresponding RF acquisition signal, input the IF intermediate frequency acquisition analog signal into an ADC sampling channel of the ADC / DAC sub-board, and use the last RF reference signal as a backup signal; the up-conversion channel mixes an input LO local oscillator signal with an IF intermediate frequency excitation analog signal output by the ADC / DAC sub-board, performs filtering to obtain a low-level RF excitation signal, and outputs the low-level RF excitation signal for field building of a high-frequency cavity; The ADC / DAC sub-board is configured to receive an IF intermediate frequency excitation digital signal output by the digital signal processing board, convert the IF intermediate frequency excitation digital signal into an IF intermediate frequency excitation analog signal, and send the IF intermediate frequency excitation analog signal to the radio frequency front-end board; and receive an IF intermediate frequency acquisition analog signal output by the radio frequency front-end board, convert the IF intermediate frequency acquisition analog signal into an IF intermediate frequency acquisition digital signal, and send the IF intermediate frequency acquisition digital signal to the digital signal processing board; The digital signal processing board is provided with a driver of a low-level register device in the FPGA and an EPICS-IOC application, and is configured to realize reading and writing of the low-level register device by the EPICS-IOC application; and The input IF intermediate frequency acquisition digital signal is subjected to Non-IQ sampling to obtain quadrature I / Q signals corresponding to an RF reference signal REF and quadrature I / Q signals corresponding to a cavity field back acquisition signal Pt, and an IF intermediate frequency excitation digital signal is generated according to the two pairs of I / Q quadrature signals for amplitude and phase loop control of a high-frequency cavity field and is sent to the ADC / DAC sub-board.

2. The system of claim 1, wherein, The FPGA comprises programmable logic units PL and a processor system PS; when writing the control variable, the processor system PS transmits the written parameter data axi_wdata and the write address axi_waddr to the programmable logic units PL, the programmable logic units PL write the parameter data axi_wdata into the corresponding register according to the write address axi_waddr, and the setting of the low-level control variable is completed; when reading the state variable, the processor system PS transmits the read address axi_raddr to the programmable logic units PL, the programmable logic units PL transmit the register value axi_rdata of the corresponding address to the processor system PS according to the read address axi_raddr, and the processor system PS writes the received register value axi_rdata into the memory address corresponding to the read address axi_raddr, and the reading of the low-level state variable is completed.

3. The system of claim 1, wherein, The method for developing the driver is: 1) adding a device node corresponding to the low-level register device in the device tree of the low-level register of the FPGA, including the device node name, register address range and register address length; 2) creating a low-level register device structure body containing the device node of the device tree; 3) declaring a device operation function structure body file_operations of the low-level register device, covering all the linux kernel operation functions; then creating a device opening function open() for opening the low-level register device, a read operation function read() for reading the data of the low-level register, a write operation function write() for writing data into the low-level register, an I / O control operation function ioctl() for transmitting control instructions from the application to the low-level register device, a device release operation function release() for closing the low-level register device, a registration module loading function init() for loading the registration module, and a registration module unloading function exit() for unloading the registration module. The method for developing the EPICS-IOC application is:

4. The system of claim 2, wherein, 1) building the EPICS control system: downloading the standard EPICS Base installation package, setting the position of the cross-compiler, adding a cross-compile framework, and then performing cross-compile to complete the installation of the EPICS Base; 2) creating a standard IOC application by using the EPICS instruction to generate the IOC basic application of the low-level control system; 3) creating a low-level register device support file Device support for opening the low-level register device; 4) creating a low-level device record support file Record Support for reading and writing the low-level register device by calling the device operation function. ​ 5) Create a device support database definition file for the low-level register device, which describes the interface between the device support module, record type, and hardware driver of the low-level register device, enabling the EPICS system to interact with the low-level hardware device. 6) Create the database file; 7) Cross-compile low-level EIPICSIOC applications; 8) Copy the cross-compiled EPICS Base and EPICSIOC applications to the user file directory of the embedded Linux system of the processor system PS, and run the EPICSIOC application to complete the development of the low-level EPICSIOC application.

5. The system of claim 1, wherein, The downconversion channel mixes the input RF acquisition signal and the LO local oscillator signal sequentially through a mixer, an amplifier, and a low-pass filter to obtain the corresponding IF intermediate frequency acquisition analog signal of the RF acquisition signal; the upconversion channel mixes the input LO local oscillator signal and the IF intermediate frequency excitation analog signal output by the ADC / DAC sub-board sequentially through a mixer, an amplifier, and a bandpass filter to obtain a low-level RF excitation signal.

6. The system of claim 1 or 2 or 3, wherein, The digital signal processing board has two FMC interfaces for bridging two ADC / DAC sub-boards to achieve 12-channel ADC sampling and 4-channel DAC output.

7. The system of claim 1 or 2 or 3, wherein, The clock distribution unit divides the input RF reference signal by N to obtain the ADC clock, DAC clock, and FPGA operating clock. The ADC clock and DAC clock are input into the ADC / DAC sub-board, and the FPGA operating clock is sent to the FPGA. The RF reference signal is clocked and divided by M times to obtain the IF intermediate frequency reference signal, which is then sent to the RF front-end board. The clock distribution unit includes two clock distribution chips with different parameter configurations, which are used to run two low-level control systems with different clock configurations and different RF frequencies simultaneously.

8. The system of claim 1 or 2 or 3, wherein, The RF acquisition signals include cavity forward power signal Pf, cavity reflection power signal Pr, and cavity field recovery signal Pt.

9. The system of claim 1, wherein, The RF front-end board uses a 4-power divider to split the input reference line RF signal into 4 RF reference signals; the microwave devices of the RF front-end board include amplifiers, mixers and power dividers, and the high frequency of the microwave devices is within 2 GHz.

10. The system of claim 2, wherein, The FPGA is the XC7Z100-2FFG900I chip under the ZYNQ-7000 series; the programmable logic unit PL and the processor system PS are interconnected via the axi-lite bus, and memory mapping communication is used to realize the mapping of the registers of the programmable logic unit PL to the memory address storage space of the processor system PS.

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