Digital signal processing method and system based on FPGA

By digitizing and analyzing the frequency of analog high-speed signals and dynamically adjusting the CDR loop parameters, FPGA-based fast locking and high-precision analysis are achieved, solving the problem of the trade-off between speed and accuracy in existing CDR designs and improving the versatility and efficiency of the test equipment.

CN121308932APending Publication Date: 2026-01-09广州思林杰科技股份有限公司
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Patent Information

Application Number
CN202511388952.X
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-09-26
Publication Date
2026-01-09

AI Technical Summary

Technical Problem

Existing FPGA-based CDR designs cannot simultaneously balance loop locking speed and measurement accuracy, nor can they be dynamically adjusted for different application scenarios, thus limiting the versatility and efficiency of test and measurement equipment.

Method used

A dynamic adaptive digital signal processing architecture is adopted. By digitizing the analog high-speed signal and performing feedforward frequency analysis, the frequency offset value is obtained. The CDR loop is preset and high bandwidth lock is started. The phase error signal is monitored and the proportional and integral coefficients of the loop filter are smoothly switched after the lock is achieved. The switch is made from high bandwidth mode to low bandwidth mode to achieve high-precision clock recovery and jitter analysis.

Benefits of technology

It achieves the integration of fast locking and high-precision measurement in a single operation, solving the problem of the trade-off between locking speed and measurement accuracy in traditional CDR designs, and improving testing efficiency and adaptability.

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Abstract

The invention discloses a digital signal processing method and system based on an FPGA, relates to the field of digital signal processing, and introduces a staged variable bandwidth CDR strategy. In the initial stage, the signal frequency offset is quickly estimated through feedforward frequency analysis, and a high-bandwidth loop is started on the basis of the signal frequency offset, so that top-speed locking is realized, and the requirements of production testing and other scenes on efficiency are met. When the system confirms that locking is stable through hardware logic, a multi-step interpolation state machine is triggered, the state machine can smoothly switch the coefficient of the loop filter from a high bandwidth mode to a low bandwidth mode without disturbance, and the lock losing risk in the switching process is avoided. Finally, in a stable low-bandwidth mode, the system can perform accurate jitter decomposition and data analysis by using a high-precision recovery clock. In this way, the two modes of rapid capture and high-precision measurement are fused in one operation process, and the static design limitation in the prior art is solved.
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