Transparent display device and tiled display device

Abstract

A transparent display device comprises a circuit substrate, a micro light emitting diode, a protective layer and a water blocking structure. The circuit substrate is provided with a penetrating area and a non-penetrating area. The micro light-emitting diode is arranged on the non-penetrating area and is jointed to the circuit substrate. The protection layer is arranged on the non-penetrating area and covers the top surface and the side wall of the micro light emitting diode. The micro light emitting diode and the water blocking structure are separated by the protective layer, and the water blocking structure comprises an opening overlapped on the top surface of the micro light emitting diode.

Description

Technical Field

[0001] The invention relates to a transparent display device and a spliced ​​display device. Background Art

[0002] Light-emitting diode (LED) displays are a highly efficient light source technology widely used in displays, lighting, and multimedia devices. Their structure typically consists of an array of multiple micro-LEDs (micro-LEDs), each controlled by a driver circuit to produce high-resolution and high-brightness displays. To enhance the stability and lifespan of the device, packaging techniques are often used to isolate it from moisture and impurities in the external environment.

[0003] However, when moisture intrudes into display devices, it can cause a variety of problems, such as corrosion of metal electrodes and reduced luminous efficiency. These issues not only affect display quality but can also shorten the device's lifespan. Therefore, moisture barrier technology has become a key design consideration. Summary of the Invention

[0004] The invention provides a transparent display device and a spliced ​​display device.

[0005] At least one embodiment of the present invention provides a transparent display device comprising a circuit substrate, a micro-LED, a protective layer, and a water-blocking structure. The circuit substrate has a transmissive region and a non-transmissive region. The micro-LED is disposed on the non-transmissive region and bonded to the circuit substrate. The protective layer is disposed on the non-transmissive region and covers the top surface and sidewalls of the micro-LED. The micro-LED is separated from the water-blocking structure by the protective layer, and the water-blocking structure includes an opening that overlaps the top surface of the micro-LED.

[0006] At least one embodiment of the present invention provides a spliced ​​display device, which includes two or more transparent display devices spliced ​​together. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a partial cross-sectional schematic diagram of a transparent display device according to an embodiment of the present invention.

[0008] Figure 2 It is a partial cross-sectional schematic diagram of a transparent display device according to an embodiment of the present invention.

[0009] Figure 3 It is a partial cross-sectional schematic diagram of a transparent display device according to an embodiment of the present invention.

[0010] Figures 4A to 4C It is manufactured Figure 1Schematic cross-sectional views of some stages of a method for manufacturing a transparent display device.

[0011] Figure 5 It is a partial cross-sectional schematic diagram of a transparent display device according to an embodiment of the present invention.

[0012] Figure 6 It is a partial cross-sectional schematic diagram of a transparent display device according to an embodiment of the present invention.

[0013] Figure 7 FIG1 is a top view of a micro light emitting diode and a conductive layer of a transparent display device according to an embodiment of the present invention.

[0014] Figure 8 A schematic top view of a micro light emitting diode and a conductive layer of a transparent display device according to an embodiment of the present invention.

[0015] Figure 9 is a flow chart of a method for manufacturing a transparent display device according to some embodiments of the present invention.

[0016] Figure 10A FIG. 1 is a schematic top view of a spliced ​​display device according to an embodiment of the present invention.

[0017] Figure 10B It is along Figure 10A Schematic cross-sectional view of line AA'.

[0018] The accompanying drawings are described as follows:

[0019] 10A, 10B, 10C, 10D, 10E: Transparent display device

[0020] 100: Circuit board

[0021] 110:Transparent substrate

[0022] 112: buffer layer

[0023] 113: first insulating layer

[0024] 114: Second insulation layer

[0025] 115: first buffer layer

[0026] 116: Second buffer layer

[0027] 117: The third buffer layer

[0028] 118: Fourth buffer layer

[0029] 119: passivation layer

[0030] 120: semiconductor layer

[0031] 130: first conductive pattern layer

[0032] 131: Gate

[0033] 132: Conductive characteristics

[0034] 140: second conductive pattern layer

[0035] 150: third conductive pattern layer

[0036] 151: first source / drain

[0037] 152: Second source / drain

[0038] 153: Conductive characteristics

[0039] 160: fourth conductive pattern layer

[0040] 170: fifth conductive pattern layer

[0041] 180: sixth conductive pattern layer

[0042] 181,182: pads

[0043] 191: The third insulating layer

[0044] 192: Fourth insulation layer

[0045] 193: Fifth insulation layer

[0046] 200: Micro LED

[0047] 200s, 300s: sidewall

[0048] 200t, 300t: Top

[0049] 210:Contact

[0050] 300: Protective layer

[0051] 400: Water-blocking structure

[0052] 400H: Open

[0053] 410: oxide layer

[0054] 420: Nitride layer

[0055] 500: Encapsulation layer

[0056] 600: conductive layer

[0057] 600H:Through hole

[0058] BM: Black Matrix

[0059] S1, S2, S3, S4, S5, S6: Steps

[0060] T: Active Components

[0061] TR: penetration zone

[0062] NTR: Non-penetrating region. DETAILED DESCRIPTION

[0063] Figure 1 is a partial cross-sectional diagram of a transparent display device 10A according to an embodiment of the present invention. Figure 1 The transparent display device 10A includes a circuit substrate 100 , a micro light emitting diode 200 , a protective layer 300 , a water blocking structure 400 and an encapsulation layer 500 .

[0064] The circuit substrate 100 has a transmissive region TR and a non-transmissive region NTR. In some embodiments, the transmissive region TR of the circuit substrate 100 is made of a transparent material, allowing light to pass through the transmissive region TR; while the non-transmissive region NTR of the circuit substrate 100 is made of a non-transmissive material (e.g., a metal material, a semiconductor material, etc.).

[0065] In some embodiments, the circuit substrate 100 includes a transparent substrate 110. Transparent substrate 110 may be made of glass, organic materials, or other suitable materials. Transparent substrate 110 may be a rigid substrate, a flexible substrate, or a stretchable substrate. In some embodiments, a buffer layer 112 is disposed on a surface of transparent substrate 110.

[0066] In this embodiment, the circuit substrate 100 includes multiple conductive pattern layers and multiple insulating layers. For example, the circuit substrate 100 includes a semiconductor layer 120, a first insulating layer 113, a first conductive pattern layer 130, a second insulating layer 114, a second conductive pattern layer 140, a third insulating layer 191, a third conductive pattern layer 150, a fourth insulating layer 192, a first buffer layer 115, a fourth conductive pattern layer 160, a fifth insulating layer 193, a second buffer layer 116, a fifth conductive pattern layer 170, a third buffer layer 117, a black matrix BM, a fourth buffer layer 118, a sixth conductive pattern layer 180, and a passivation layer 119. In some embodiments, the number of semiconductor layers, conductive pattern layers, insulating layers, and buffer layers in the circuit substrate 100 can be adjusted as needed.

[0067] The semiconductor layer 120 is disposed on the buffer layer 112. In some embodiments, the semiconductor layer 120 is a single-layer or multi-layer structure and includes amorphous silicon, polycrystalline silicon, microcrystalline silicon, single-crystalline silicon, an organic semiconductor material, an oxide semiconductor material (e.g., indium zinc oxide, indium gallium zinc oxide, or other suitable materials or combinations thereof), or other suitable materials or combinations thereof. In this embodiment, the semiconductor layer 120 includes a channel region and doped regions located on both sides of the channel region. In some embodiments, the doped regions include lightly doped regions and heavily doped regions.

[0068] The first insulating layer 113 is located on the semiconductor layer 120 .

[0069] The first conductive pattern layer 130 is located on the first insulating layer 113 and includes a gate 131 and a conductive feature 132. The gate 131 overlaps the channel region of the semiconductor layer 120. The conductive feature 132 is, for example, a signal line or other conductive structure.

[0070] The second insulating layer 114 is located on the first conductive pattern layer 130. The second conductive pattern layer 140 is located on the second insulating layer 114. The second conductive pattern layer 140 includes, for example, signal lines or other conductive structures. In some embodiments, the second insulating layer 114 and the second conductive pattern layer 140 may be omitted.

[0071] The third insulating layer 191 is located on the second conductive pattern layer 140 and the second insulating layer 114. In some embodiments, the third insulating layer 191 may also be referred to as an interlayer dielectric layer.

[0072] The third conductive pattern layer 150 is located on the third insulating layer 191 and includes a first source / drain 151, a second source / drain 152, and a conductive feature 153. The first source / drain 151 and the second source / drain 152 pass through the third insulating layer 191, the second insulating layer 114, and the first insulating layer 113 and are connected to the doped regions of the semiconductor layer 120. The conductive feature 153 is, for example, a signal line or other conductive structure.

[0073] In this embodiment, the active device T is located on the transparent substrate 110 and includes a semiconductor layer 120, a gate 131, a first source / drain 151, and a second source / drain 152. In this embodiment, the active device T is exemplified by a top-gate thin-film transistor, but the present invention is not limited thereto. In other embodiments, the active device T may also be a bottom-gate thin-film transistor, a dual-gate thin-film transistor, or another type of thin-film transistor.

[0074] The fourth insulating layer 192 is located on the third conductive pattern layer 150. In some embodiments, the fourth insulating layer 192 may also be referred to as a planarization layer.

[0075] The first buffer layer 115 is located on the fourth insulating layer 192. The fourth conductive pattern layer 160 is located on the first buffer layer 115. A portion of the fourth conductive pattern layer 160 forms a conductive via that passes through the fourth insulating layer 192 and connects to the third conductive pattern layer 150. In this embodiment, the first buffer layer 115 is located only on the top surface of the fourth insulating layer 192 and between the top surface of the fourth insulating layer 192 and the fourth conductive pattern layer 160. In other embodiments, in addition to being located on the top surface of the fourth insulating layer 192, the first buffer layer 115 also fills the via in the fourth insulating layer 192 and laterally surrounds the fourth conductive pattern layer 160 to connect to the conductive via of the third conductive pattern layer 150.

[0076] The fifth insulating layer 193 is located on the fourth conductive pattern layer 160. In some embodiments, the fifth insulating layer 193 may also be referred to as a planarization layer.

[0077] The second buffer layer 116 is located on the fifth insulating layer 193. The fifth conductive pattern layer 170 is located on the second buffer layer 116. A portion of the fifth conductive pattern layer 170 forms a conductive via that passes through the fifth insulating layer 193 and connects to the fourth conductive pattern layer 160. In this embodiment, the second buffer layer 116 is located only on the top surface of the fifth insulating layer 193 and between the top surface of the fifth insulating layer 193 and the fifth conductive pattern layer 170. In other embodiments, in addition to being located on the top surface of the fifth insulating layer 193, the second buffer layer 116 also fills the via in the fifth insulating layer 193 and laterally surrounds the fifth conductive pattern layer 170 to connect to the conductive via of the fourth conductive pattern layer 160.

[0078] The third buffer layer 117 is located on the fifth conductive pattern layer 170 . The black matrix BM is located on the third buffer layer 117 .

[0079] The fourth buffer layer 118 is located on the black matrix BM. The sixth conductive pattern layer 180 is located on the fourth buffer layer 118 and includes a plurality of pads 181 and 182. In this embodiment, the pad 181 is electrically connected to the first source / drain 151 of the active device T through the fifth conductive pattern layer 170 and the fourth conductive pattern layer 160.

[0080] The passivation layer 119 overlies the pads 181 and 182. In some embodiments, the passivation layer 119 is made of silicon oxide, silicon nitride, silicon oxynitride, or other suitable insulating materials.

[0081] In this embodiment, the semiconductor layer 120, the first conductive pattern layer 130, the second conductive pattern layer 140, the third conductive pattern layer 150, the fourth conductive pattern layer 160, the fifth conductive pattern layer 170, the black matrix BM, and the sixth conductive pattern layer 180 are distributed in the non-transmitting region NTR of the circuit substrate 100. The first insulating layer 113, the second insulating layer 114, the third insulating layer 191, the fourth insulating layer 192, the first buffer layer 115, the fifth insulating layer 193, the second buffer layer 116, the third buffer layer 117, the fourth buffer layer 118, and the passivation layer 119 are disposed in the non-transmitting region NTR, and at least a portion of these layers extends from the non-transmitting region NTR to the transmitting region TR. For example, the first insulating layer 113, the second insulating layer 114, the third insulating layer 191, the fourth insulating layer 192, the fifth insulating layer 193, the third buffer layer 117, the fourth buffer layer 118, and the passivation layer 119 extend from the non-transmitting region NTR to the transmitting region TR, while the first buffer layer 115 and the second buffer layer 116 are only provided in the non-transmitting region NTR and do not extend to the transmitting region TR. By removing the first buffer layer 115 and the second buffer layer 116 from the transmitting region TR, the transmittance of the transmitting region TR can be improved.

[0082] The micro-LEDs 200 are disposed on the non-transmitting region NTR of the circuit substrate 100. In this embodiment, the micro-LEDs 200 include horizontal LEDs, but the present disclosure is not limited thereto. In other embodiments, the micro-LEDs 200 include vertical LEDs or other types of LEDs. A black matrix BM is disposed above the transparent substrate 110 and around the micro-LEDs 200. In some embodiments, the black matrix BM does not overlap the micro-LEDs 200.

[0083] Micro-LED 200 is bonded to circuit substrate 100. For example, micro-LED 200 is bonded to pads 181 and 182, and joints 210 between micro-LED 200 and pads 181 and 182 include solder, conductive adhesive, or other suitable conductive structures. Joints 210 pass through passivation layer 119, and passivation layer 119 surrounds joints 210.

[0084] The protective layer 300 is disposed on the non-transmitting region NTR of the circuit substrate 100 and covers the top surface 200t and sidewalls 200s of the micro-LED. In some embodiments, the protective layer 300 is formed on the passivation layer 119 and fills the space between the micro-LED 200 and the passivation layer 119. In some embodiments, the protective layer 300 surrounds the micro-LED 200 and the contacts 210 between the micro-LED 200 and the pads 181 and 182 to protect the micro-LED 200 and the contacts 210. In some embodiments, the protective layer 300 comprises photoresist, transparent optical adhesive, or other suitable material and has a narrow top and wide bottom structure.

[0085] The water-blocking structure 400 is located on the protective layer 300, and the micro-LED 200 is separated from the water-blocking structure 400 by the protective layer 300. The water-blocking structure 400 extends from the top surface 300t of the protective layer 300 along the sidewalls 300s of the protective layer 300 to the passivation layer 119, and covers the boundary between the protective layer 300 and the passivation layer 119, thereby preventing moisture from diffusing from the interface between the protective layer 300 and the passivation layer 119 to the micro-LED 200.

[0086] In some embodiments, the water-blocking structure 400 includes a multi-layer structure, for example, including an oxide layer 410 (e.g., including silicon oxide or other suitable oxides) and a nitride layer 420 (e.g., including silicon nitride or other suitable nitrides) overlapping the oxide layer 410. In some embodiments, the water-blocking structure 400 may further include more insulating layers.

[0087] The water-blocking structure 400 includes an opening 400H that overlaps the top surface 200t of the micro-LED 200, thereby reducing the interference (such as refraction) caused by the water-blocking structure 400 on the light emitted by the micro-LED 200. In the present embodiment, the shapes of the oxide layer 410 and the nitride layer 420 are defined using the same mask pattern. Therefore, the vertical projection shape of the oxide layer 410 on the transparent substrate 110 is substantially equal to the vertical projection shape of the nitride layer 420 on the transparent substrate 110, and the sidewalls of the oxide layer 410 are aligned with the sidewalls of the nitride layer 420. However, in other embodiments, the shapes of the oxide layer 410 and the nitride layer 420 may also be defined by different mask patterns, so that the vertical projection shape of the oxide layer 410 on the transparent substrate 110 is not equal to the vertical projection shape of the nitride layer 420 on the transparent substrate 110, such as Figure 2 In the transparent display device 10B, the nitride layer 420 may cover the sidewalls of the oxide layer 410 .

[0088] Back to Figure 1In this embodiment, the water-blocking structure 400 is disposed on the non-transmission region NTR and does not overlap with the transmission region TR, thereby increasing the transmittance of the transmission region TR. However, in other embodiments, the water-blocking structure 400 overlaps with the transmission region TR, such as Figure 3 As shown in the transparent display device 10C.

[0089] Back to Figure 1 The encapsulation layer 500 covers the water-blocking structure 400 and the protective layer 300. In this embodiment, the encapsulation layer 500 fills the opening 400H of the water-blocking structure 400 and contacts the protective layer 300 through the opening 400H. In some embodiments, the encapsulation layer 500 is made of a transparent resin, transparent adhesive, transparent silicone, or other suitable material.

[0090] Figures 4A to 4C It is manufactured Figure 1 Schematic cross-sectional view of some stages of the manufacturing method of the transparent display device 10A. Figure 4A , bonding the micro LED 200 to the pads 181, 182 of the circuit substrate 100. For example, the micro LED 200 is transferred from the growth substrate or the interposer substrate to the circuit substrate 100 through a mass transfer process, and then the micro LED 200 is connected to the circuit substrate 100 through solder, conductive adhesive, or other connecting structures.

[0091] Please refer to Figure 4B , a protective layer 300 is formed on the micro-LEDs 200. For example, a photoresist material is coated on the circuit substrate 100, and then an exposure process and a development process are performed to form the protective layer 300 covering the micro-LEDs 200. In some embodiments, each protective layer 300 covers one or more micro-LEDs 200.

[0092] Please refer to Figure 4C , forming a water-blocking structure 400 on the protective layer 300. For example, an oxide material layer and a nitride material layer are sequentially deposited, and then the deposited oxide material layer and the nitride material layer are etched using a mask pattern to form an oxide layer 410 and a nitride layer 420. Because the oxide layer 410 and the nitride layer 420 are defined using the same mask pattern, the oxide layer 410 and the nitride layer 420 have the same vertical projection shape, and the sidewalls of the oxide layer 410 are aligned with the sidewalls of the nitride layer 420.

[0093] In other embodiments, the oxide material layer and the nitride material layer may also be defined using different mask patterns. For example, after depositing the oxide material layer, the oxide material layer is first etched using a first mask pattern to obtain an oxide layer 410. Then, a nitride material layer is deposited on the oxide layer 410. Then, a second mask pattern is used to etch the nitride material layer to obtain a nitride layer 420, as shown in FIG. Figure 2 The water blocking structure 400 is shown.

[0094] Finally, a packaging layer 500 is formed on the water-blocking structure 400 and the protective layer 300. Figure 1 shown.

[0095] Figure 5 is a partial cross-sectional diagram of a transparent display device 10D according to an embodiment of the present invention. It must be noted that Figure 5 The implementation examples follow Figure 1 The component numbers and partial contents of the embodiments are the same or similar components, and the description of the same technical contents is omitted. For the description of the omitted parts, please refer to the above embodiments and will not be repeated here.

[0096] Figure 5 The transparent display device 10D and Figure 1 Display device Figure 10A The difference is that the transparent display device 10D further includes a conductive layer 600 .

[0097] The conductive layer 600 is sandwiched between the protective layer 300 and the water-blocking structure 400, and is located between the sidewalls 200s of the micro-LED 200 and the water-blocking structure 400. The conductive layer 600 extends from the top surface 300t of the protective layer 300 along the sidewalls 300s of the protective layer 300 to the passivation layer 119. In some embodiments, the conductive layer 600 is formed by evaporation, coating, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable processes.

[0098] In this embodiment, the conductive layer 600 is located on the non-transmitting region NTR and does not overlap the transmitting region TR. The conductive layer 600 can serve as an anti-static structure to reduce damage to components caused by static electricity. Since the anti-static structure is disposed around the micro-LEDs 200, it is unnecessary to provide additional anti-static structures (such as anti-static rings) around the perimeter of the transparent display device 10D. This can reduce the bezel size of the transparent display device 10D. In some embodiments, the conductive layer 600 is connected to a ground voltage or other DC voltage.

[0099] In some embodiments, the conductive layer 600 includes a transparent conductive material, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide, or other suitable materials. In embodiments where the conductive layer 600 includes a transparent conductive material, the conductive layer 600 may extend from the non-transmitting region NTR to the transmitting region TR and overlap the transmitting region TR.

[0100] In some embodiments, the conductive layer 600 includes a through hole 600H that overlaps the top surface 200t of the micro-LED 200. In this embodiment, the conductive layer 600 and the oxide layer 410 and nitride layer 420 of the water-blocking structure 400 are defined using the same mask pattern. Therefore, the conductive layer 600, the oxide layer 410, and the nitride layer 420 have the same vertical projection shape on the transparent substrate 110, and the sidewalls of the through hole 600H are aligned with the sidewalls of the opening 400H. However, in other embodiments, the conductive layer 600 and the water-blocking structure 400 may be defined using different mask patterns. For example, the mask pattern is first used to etch the conductive material layer to obtain the conductive layer 600 including the through hole 600H. The water-blocking structure 400 is then formed on the conductive layer 600. In this case, the vertical projection shape of the conductive layer 600 on the transparent substrate 110 may be different from the vertical projection shape of the oxide layer 410 on the transparent substrate 110 and the vertical projection shape of the nitride layer 420 on the transparent substrate 110, such as Figure 6 As shown in the transparent display device 10E.

[0101] The encapsulation layer 500 covers the water-blocking structure 400 and the protection layer 300 , fills the opening 400H of the water-blocking structure 400 and the through hole 600H of the shielding structure 600 , and contacts the protection layer 300 .

[0102] Figure 7 FIG. 1 is a top view of a micro-LED 200 and a conductive layer 600 of a transparent display device according to an embodiment of the present invention. It should be noted that Figure 7 The implementation examples follow Figure 6 The component numbers and partial contents of the embodiments are the same or similar components, and the description of the same technical contents is omitted. For the description of the omitted parts, please refer to the above embodiments and will not be repeated here.

[0103] Please refer to Figure 7 In this embodiment, each pixel includes a plurality of micro-LEDs 200. For example, three adjacent micro-LEDs 200 constitute a pixel, and are respectively a red micro-LED, a green micro-LED, and a blue micro-LED. The micro-LEDs 200 are bonded to pads 181 and 182.

[0104] The conductive layer 600 includes a mesh structure 610 and a shielding structure 620 in a top view. The mesh structure 610 overlaps the non-penetrating region NTR, and the mesh structure 610 includes a black matrix, a plurality of signal lines and other conductive features ( Figure 7 Not shown, please refer to Figure 5 The shielding structure 620 extends from the mesh structure 610 toward the micro-LED 200 and has a through hole 600H overlapping the top surface of the micro-LED 200. The water-blocking structure 400 ( Figure 7 Not shown, please refer to Figure 5 ) is formed on the shielding structure 620 , and the through hole 600H of the shielding structure 620 overlaps the opening 400H of the water-blocking structure 400 .

[0105] In this embodiment, each shielding structure 620 overlaps one micro-LED 200, but the present disclosure is not limited thereto. In other embodiments, a single micro-LED 200 overlaps multiple micro-LEDs 200, such as Figure 8 shown.

[0106] Figure 9 is a flow chart of a method for manufacturing a transparent display device according to some embodiments of the present invention. Figure 9 In step S1, the micro-LED is bonded to the circuit substrate. Figure 4A shown.

[0107] Optionally, in step S2, the micro-LEDs are tested and faulty micro-LEDs are repaired.

[0108] In step S3, a protective layer is formed to cover the micro-LEDs, such as Figure 4B In some embodiments, the micro-LED covered by the protective layer can be a repaired micro-LED or an unrepaired micro-LED.

[0109] Optionally, in step S4, a conductive layer is formed. A transparent display device including a conductive layer is as follows Figure 5 or Figure 6 shown.

[0110] In step S5, a water-blocking structure is formed, such as Figure 4C shown.

[0111] Finally, in step S6, an encapsulation layer is formed, such as Figure 1 shown.

[0112] Figure 10A FIG. 1 is a schematic top view of a spliced ​​display device according to an embodiment of the present invention. Figure 10B It is along Figure 10A Please refer to the cross-sectional diagram of the line A-A'. Figure 10A and Figure 10B In this embodiment, two or more transparent display devices 10A are spliced ​​together to form a spliced ​​display device. Figure 1 The transparent display device 10A described in the related paragraphs is taken as an example, but the present invention is not limited thereto. In other embodiments, multiple transparent display devices described in other embodiments are spliced ​​together to form a spliced ​​display device.

[0113] In this embodiment, the provision of the protective layer 300 and the water-blocking structure 400 prevents moisture entering from the edge of the transparent display device 10A from damaging the micro-LEDs 200. Therefore, the micro-LEDs 200 can be positioned very close to the edge of the transparent display device 10A, thereby achieving a narrow bezel or seamless connection.

Claims

1. A transparent display device, comprising: A circuit substrate having a penetration area and a non-penetration area; a micro light emitting diode disposed on the non-transmitting area and bonded to the circuit substrate; a protective layer disposed on the non-transmitting region and covering the top surface and sidewalls of the micro-LED; and A water-blocking structure is provided, wherein the micro-LED and the water-blocking structure are separated by the protective layer, and the water-blocking structure comprises an opening overlapping the top surface of the micro-LED. 2 . The transparent display device as claimed in claim 1 , wherein the water-blocking structure does not overlap the penetration region. The transparent display device as claimed in claim 1 , wherein the water-blocking structure overlaps the penetration region.

4. The transparent display device according to claim 1, further comprising: A conductive layer is sandwiched between the protective layer and the water-blocking structure, and the conductive layer is located between the side wall of the micro-LED and the water-blocking structure, wherein the conductive layer includes a mesh structure in a top view. The transparent display device as claimed in claim 4 , wherein the conductive layer is connected to a ground voltage. 6 . The transparent display device as claimed in claim 1 , wherein the protective layer comprises a photoresist or a transparent optical adhesive and surrounds the connection point between the micro light emitting diode and the circuit substrate. The transparent display device as claimed in claim 1 , wherein the water-blocking structure comprises a multi-layer structure.

8. The transparent display device as claimed in claim 1, wherein the circuit substrate comprises: a transparent substrate; a black matrix located above the transparent substrate and around the micro-LEDs; a pad located above the transparent substrate, wherein the micro light emitting diode is bonded to the pad; a passivation layer overlying the pad and surrounding the contact between the micro-LED and the pad, wherein the protective layer is formed on the passivation layer and surrounds the micro-LED and the contact, wherein the water-blocking structure extends from a top surface of the protective layer along a side surface of the protective layer to the passivation layer, wherein the water-blocking structure includes an oxide layer and a nitride layer overlapping the oxide layer, and a vertical projection shape of the oxide layer on the transparent substrate is substantially equal to a vertical projection shape of the nitride layer on the transparent substrate; as well as A packaging layer covers the water-blocking structure and the protection layer, wherein the packaging layer fills the opening of the water-blocking structure and contacts the protection layer.

9. The transparent display device according to any one of claims 1 to 8, wherein the circuit substrate comprises: a transparent substrate; a black matrix located above the transparent substrate and around the micro-LEDs; a pad located above the transparent substrate, wherein the micro light emitting diode is bonded to the pad; a passivation layer covering the pad and surrounding the contact between the micro-LED and the pad, wherein the protection layer is formed on the passivation layer and surrounding the micro-LED and the contact; a conductive layer extending from a top surface of the protective layer along a side surface of the protective layer to the passivation layer, and comprising: a mesh structure overlapping the non-penetrating area; a shielding structure extending from the mesh structure toward the micro-LED and having a through hole overlapping the top surface of the micro-LED, wherein the water-blocking structure is formed on the shielding structure, and the through hole of the shielding structure overlaps the opening of the water-blocking structure; and A packaging layer covers the water-blocking structure and the protective layer, wherein the packaging layer fills the opening of the water-blocking structure and the through hole of the shielding structure and contacts the protective layer.

10. A spliced ​​display device, comprising: Two or more transparent display devices according to claim 1 are spliced ​​together.

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