Display device, method for manufacturing display device, and head-mounted display device including display device

Abstract

The invention relates to a display device, a method for manufacturing the display device, and a head-mounted display device including the display device. The display device includes a substrate including a display area and a non-display area; first electrodes spaced apart from each other on the substrate in the display area; a power connection electrode on the substrate in the non-display area; a pixel defining film in the display area and the non-display area and including a first opening overlapping the first electrode and a second opening overlapping the power connection electrode; a light emitting stack on the first electrode in the display area; and a second electrode on the pixel defining film and the light emitting stack, the pixel defining film including a first pixel defining film, a second pixel defining film on the first pixel defining film, and a third pixel defining film on the second pixel defining film.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0026231 filed on February 23, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a display device, a method for manufacturing the display device, and a head-mounted display device including the display device. Background Art

[0003] A head-mounted display (HMD) is a device worn on the user's head in the form of glasses or a helmet, with an image display focused at a close distance in front of the user's eyes. This device can enable virtual reality (VR) or augmented reality (AR).

[0004] Head-mounted display devices use multiple lenses to magnify an image displayed on a small display device and display the magnified image. Therefore, the display device used in head-mounted display devices needs to provide high-resolution images, for example, images with a resolution of 3,000 pixels per inch (PPI) or higher. To this end, organic light-emitting diodes on silicon (OLEDoS), which are small, high-resolution organic light-emitting display devices, are used as display devices for head-mounted display devices. OLEDoS is an image display device in which organic light-emitting diodes (OLEDs) are provided on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is provided. Summary of the Invention

[0005] Aspects of the present disclosure provide a display device including openings of different shapes in a pixel-defining film.

[0006] According to one or more embodiments of the present disclosure, a display device includes: a substrate including a display area and a non-display area around the display area; a plurality of first electrodes spaced apart from each other on the substrate in the display area; a power connection electrode located on the substrate in the non-display area; a pixel defining film in the display area and the non-display area, and including a plurality of first openings overlapping with the first electrodes and a second opening overlapping with the power connection electrodes; a plurality of light-emitting stacks located on the first electrode in the display area; and a second electrode on the pixel defining film and the light-emitting stack, wherein the pixel defining film includes a first pixel defining film, a second pixel defining film on the first pixel defining film, and a third pixel defining film on the second pixel defining film, and in the first opening, the second pixel defining film is more recessed inward than the third pixel defining film, and in the second opening, the lateral sides of the first pixel defining film, the lateral sides of the second pixel defining film, and the lateral sides of the third pixel defining film are in the same plane.

[0007] In one or more embodiments, a thickness of a portion of the first electrode overlapping the first opening is smaller than a thickness of a portion of the power connection electrode overlapping the second opening.

[0008] In one or more embodiments, a first thickness of a portion of the first electrode overlapping the first opening is smaller than a second thickness of an edge portion of the first electrode.

[0009] In one or more embodiments, an area of ​​a portion of the first electrode having the first thickness is greater than an area of ​​a portion of the first electrode penetrated by the first opening of the first pixel defining film, and the first pixel defining film includes a tip structure on the first electrode.

[0010] In one or more embodiments, the first electrode includes a base layer, an intermediate layer on the base layer, and an upper layer on the intermediate layer, wherein a fourth thickness of a portion of the upper layer overlapping the first opening is less than a fifth thickness of an edge portion of the upper layer.

[0011] In one or more embodiments, the base layer includes Ti and / or ITO, the middle layer includes Al and / or Ag, and the upper layer includes TiN and / or ITO.

[0012] In one or more embodiments, the display device further includes an insulating layer on the substrate, wherein the first electrode and the power connection electrode are directly on the insulating layer.

[0013] In one or more embodiments, the pixel defining film also includes a fourth pixel defining film on the third pixel defining film, and a fifth pixel defining film on the fourth pixel defining film, wherein, in the first opening, the fourth pixel defining film is more recessed inward than the fifth pixel defining film.

[0014] In one or more embodiments, a sidewall of the second opening of the pixel defining film has a smooth surface, and the second electrode covers the second opening and is connected to the power connection electrode.

[0015] In one or more embodiments, the light-emitting stack includes a first light-emitting stack, a second light-emitting stack on the first light-emitting stack, and a third light-emitting stack on the second light-emitting stack, wherein the first light-emitting stack and the second light-emitting stack are in a first opening, and the first light-emitting stack and the second light-emitting stack located in a plurality of first openings adjacent to each other and different from each other are not connected to each other.

[0016] In one or more embodiments, each of the first pixel defining film, the second pixel defining film, and the third pixel defining film includes a silicon oxide or silicon nitride-based inorganic insulating material, and the pixel defining film includes alternately stacked layers including different materials.

[0017] In one or more embodiments, the display device further includes a plurality of dam structures in the non-display area and an encapsulation layer on the second electrode, the plurality of dam structures surrounding the display area, wherein each of the plurality of dam structures has a groove shape penetrating the pixel defining film.

[0018] In one or more embodiments, the encapsulation layer includes a first inorganic encapsulation layer on the second electrode and beyond the dam structure, an organic encapsulation layer on the first inorganic encapsulation layer but not covering the outermost dam structure among the multiple dam structures, and a second inorganic encapsulation layer on the organic encapsulation layer and the first inorganic encapsulation layer.

[0019] In one or more embodiments, the display device further includes: a plurality of color filters on the encapsulation layer and each overlapping the first electrode; a plurality of lenses on the color filters and in the display area; and a cover layer on the lenses.

[0020] According to one or more embodiments of the present disclosure, a method for manufacturing a display device includes: forming a first electrode and a power connection electrode on a substrate, and forming a first pixel defining film, a second pixel defining film, and a third pixel defining film covering the first electrode and the power connection electrode; performing a first etching process to partially etch the portions of the second pixel defining film and the third pixel defining film overlapping with the first electrode; performing a second etching process to etch the remaining portions of the second pixel defining film in the first etching process and form a tip structure, in which the lateral side of the third pixel defining film protrudes beyond the second pixel defining film; and performing a third etching process to etch the first pixel defining film, the second pixel defining film, and the third pixel defining film to form a first opening exposing the top surface of the first electrode and a second opening exposing the top surface of the power connection electrode, wherein the thickness of the portion of the first electrode overlapping with the first opening is less than the thickness of the portion of the power connection electrode overlapping with the second opening.

[0021] In one or more embodiments, the tip structures of the first pixel defining film and the third pixel defining film are located in the first opening, and the lateral sides of the first pixel defining film, the lateral sides of the second pixel defining film, and the lateral sides of the third pixel defining film are located in the same plane in the second opening.

[0022] In one or more embodiments, the first electrode includes a base layer, an intermediate layer on the base layer, and an upper layer on the intermediate layer, and a portion of the upper layer overlapping the first opening has a thickness thinner than an edge portion of the upper layer.

[0023] In one or more embodiments, the second etching process is performed as a wet etching process.

[0024] In one or more embodiments, in the third etching process, while etching the first pixel defining film, the second pixel defining film, and the third pixel defining film overlapping the power connection electrode, a portion of the first electrode and the first pixel defining film overlapping the first electrode are etched.

[0025] According to one or more embodiments of the present disclosure, a head-mounted display device includes: a frame mounted on a user's body and corresponding to the user's left eye and right eye; a plurality of display devices in the frame; and an eyepiece on each of the plurality of display devices, wherein the display device includes: a substrate including a display area and a non-display area surrounding the display area; a plurality of first electrodes spaced apart from each other on the substrate in the display area; a power connection electrode located on the substrate in the non-display area; a pixel defining film in the display area and the non-display area, and including a plurality of first openings overlapping with the first electrodes and a second opening overlapping with the power connection electrodes; a plurality of light-emitting diodes; and a plurality of light-emitting diodes. A stack, located on a first electrode in a display area; and a second electrode, on a pixel-defining film and a light-emitting stack, wherein the pixel-defining film includes a first pixel-defining film, a second pixel-defining film on the first pixel-defining film, and a third pixel-defining film on the second pixel-defining film, in the first opening, the second pixel-defining film is more recessed inward than the third pixel-defining film, and in the second opening, the lateral sides of the first pixel-defining film, the lateral sides of the second pixel-defining film, and the lateral sides of the third pixel-defining film are in the same plane, and the thickness of the portion of the first electrode overlapping with the first opening is less than the thickness of the portion of the power connection electrode overlapping with the second opening.

[0026] Aspects of the present disclosure provide a method for manufacturing a display device, in which openings of different shapes of a pixel defining film are formed in the same process without an additional mask.

[0027] However, the aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0028] In a display device according to one or more embodiments, a pixel defining film may include an opening formed in a display region and having a pointed structure, and an opening formed in a non-display region and having smooth lateral sides. The light-emitting stacks of different adjacent sub-pixels may be separated by the opening in the display region, and the opening in the non-display region may prevent disconnection of the electrode layer.

[0029] Furthermore, the method for manufacturing a display device according to one or more embodiments may shorten a manufacturing process by concurrently (eg, simultaneously) forming openings of different shapes without an additional mask.

[0030] However, the effects, aspects, and features according to the embodiments of the present disclosure are not limited to the above-discussed effects, aspects, and features, and various other effects, aspects, and features are included herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects and features of the embodiments of the present disclosure will become more apparent by describing in detail the embodiments of the present disclosure with reference to the accompanying drawings, in which: Figure 1 is an exploded perspective view of a display device according to one or more embodiments; Figure 2 is a block diagram illustrating a display device according to one or more embodiments; Figure 3 is an equivalent circuit diagram of a sub-pixel according to one or more embodiments; Figure 4 is a diagram illustrating a display panel according to one or more embodiments; Figure 5 It shows the settings Figure 4 A plan view of first electrodes and emission regions of a plurality of pixels and a pixel defining film in a display area; Figure 6 is a plan view illustrating first electrodes and emission regions of a plurality of sub-pixels and a pixel-defining film according to one or more embodiments; Figure 7 It is along Figure 5 A schematic cross-sectional view taken along line AA'; Figure 8 It shows Figure 4 An enlarged view of region X; Figure 9 It is along Figure 8 A schematic cross-sectional view taken along line BB'; Figure 10 is a cross-sectional view illustrating a first electrode and a power connection electrode of a display device according to one or more embodiments; Figure 11 is a diagram illustrating a first electrode of a display device according to one or more embodiments in more detail; Figures 12 to 18 is a diagram partially illustrating a manufacturing process of a display device according to one or more embodiments; Figure 19 is a cross-sectional view illustrating a first electrode and a power connection electrode of a display device according to one or more embodiments; Figure 20 is a perspective view illustrating a head-mounted display device according to one or more embodiments; Figure 21 It shows Figure 20an exploded perspective view of an example of a head-mounted display device; and Figure 22 is a perspective view illustrating a head-mounted display device according to one or more embodiments. DETAILED DESCRIPTION

[0032] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. However, the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the disclosure to those skilled in the art.

[0033] It will also be understood that when a layer is referred to as being "on" another layer or substrate, the layer can be directly on the other layer or substrate, or intervening layers may also be present. Throughout the specification and drawings, like reference numerals may indicate identical or substantially similar components. In the drawings, the thickness of layers and regions are exaggerated for clarity.

[0034] Although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms can be used to distinguish one element from another. Therefore, without departing from the teachings of one or more embodiments, the first element discussed below can be referred to as the second element. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first", "second", etc. can also be used herein to distinguish different categories or sets of elements. For simplicity, the terms "first", "second", etc. can respectively represent "first category (or first group)", "second category (or second group)", etc.

[0035] The features of the various embodiments of the present disclosure may be combined in part or in whole. As will be clearly understood by those skilled in the art, various interlocks and operations are technically feasible. The various embodiments may be practiced individually or in combination.

[0036] As used herein, the phrase “element A on element B” means that element A may be directly disposed on element B and / or element A may be indirectly disposed on element B via another element C. As used herein, “at least one of A, B, and C” may refer to A, B, C, AB, AC, BC, or ABC.

[0037] It will be understood by those skilled in the art that, in view of the overall content of the present disclosure, each suitable feature of the various embodiments of the present disclosure may be combined or combined with each other in part or in whole, and may be technically interlocked and operated in various suitable manners, and unless otherwise stated or implied, each embodiment may be implemented independently of each other or in combination with each other in any suitable manner.

[0038] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0039] Figure 1 is an exploded perspective view of a display device according to one or more embodiments.

[0040] Reference Figure 1 The display device 10 according to one or more embodiments is a device for displaying moving images and / or still images. The display device 10 according to one or more embodiments can be applied to portable electronic devices such as mobile phones, smartphones, tablet personal computers, mobile communication terminals, electronic organizers, e-books, portable multimedia players (PMPs), navigation systems, ultra-mobile personal computers (UMPCs), and the like. For example, the display device 10 can be applied as a display unit for a television, laptop computer, monitor, billboard, or Internet of Things (IoT) device. Alternatively, the display device 10 can be applied to smart watches, watch phones, head-mounted displays (HMDs) for implementing virtual reality and augmented reality, and the like.

[0041] The display device 10 according to one or more embodiments includes a display panel 100 , a heat dissipation layer 200 , a circuit board 300 , a timing control circuit 400 , and a power supply circuit 500 .

[0042] The display panel 100 may have a planar shape similar to a quadrilateral. For example, the display panel 100 may have a planar shape similar to a quadrilateral having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1. In the display panel 100, the corner where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be a right angle or rounded with a suitable curvature (e.g., a predetermined curvature). The planar shape of the display panel 100 is not limited to a quadrilateral and may be a shape similar to another polygonal shape, a circular shape, and / or an elliptical shape. The planar shape of the display device 10 may conform to the planar shape of the display panel 100, but is not limited thereto.

[0043] The heat dissipation layer 200 may overlap the display panel 100 in the third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be provided on one surface of the display panel 100, for example, on the rear surface of the display panel 100. The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a layer containing a material having high thermal conductivity, such as graphite, silver (Ag), copper (Cu), or aluminum (Al).

[0044] The circuit board 300 can be electrically connected to a pad portion PDA (see FIG. 1 ) of the display panel 100 by using a conductive adhesive member such as an anisotropic conductive film. Figure 4 ) of multiple pads PD (see Figure 4 ). The circuit board 300 may be a flexible printed circuit board (FPCB) having a flexible material and / or a flexible film. Although the circuit board 300 is Figure 1 100, but the circuit board 300 may be bent. In this case, one end of the circuit board 300 may be disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. One end of the circuit board 300 may be a pad portion of the circuit board 300 connected to the display panel 100 by using a conductive adhesive member (see FIG. Figure 4 ) of multiple pads PD (see Figure 4 ) at the opposite end of the other end.

[0045] The timing control circuit 400 may receive digital video data and a timing signal inputted from the outside. The timing control circuit 400 may generate a scanning timing control signal SCS (see FIG. 1 ) for controlling the display panel 100 in response to the timing signal. Figure 2 ), transmit timing control signal ECS (see Figure 2 ) and the data timing control signal DCS (see Figure 2 The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 (see Figure 2 ), and outputs the emission timing control signal ECS to the emission driver 620 (see Figure 2 The timing control circuit 400 can output the digital video data DATA and the data timing control signal DCS to the data driver 700 (see Figure 2 ).

[0046] The power supply circuit 500 can generate a plurality of panel driving voltages according to the power voltage from the outside. For example, the power supply circuit 500 can generate a first driving voltage VSS (see Figure 2 ), the second driving voltage VDD (see Figure 2 ), reference voltage VREF (see Figure 2 ) and the third driving voltage VINT (see Figure 2 ), and supply them to the display panel 100. Figure 3 The first driving voltage VSS, the second driving voltage VDD, the reference voltage VREF, and the third driving voltage VINT are described.

[0047] Each of the timing control circuit 400 and the power supply circuit 500 may be formed as an integrated circuit (IC) and attached to one surface of the circuit board 300. In this case, the scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 may be supplied to the display panel 100 through the circuit board 300. In addition, the first driving voltage VSS, the second driving voltage VDD, the reference voltage VREF, and the third driving voltage VINT of the power supply circuit 500 may be supplied to the display panel 100 through the circuit board 300.

[0048] Alternatively, similar to the scan driver 610, the emission driver 620, and the data driver 700, each of the timing control circuit 400 and the power supply circuit 500 may be provided in the non-display area NDA (see FIG. Figure 2 ). In this case, the timing control circuit 400 may include a plurality of timing transistors, and each power supply circuit 500 may include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors may be formed on a semiconductor substrate SSUB (see FIG. 1 ) by a semiconductor process. Figure 7 ). For example, a plurality of timing transistors and a plurality of power transistors may be formed by CMOS. Each of the timing control circuit 400 and the power supply circuit 500 may be provided between the data driver 700 and the pad portion PDA (see Figure 4 )between.

[0049] Figure 2 is a block diagram illustrating a display device according to one or more embodiments.

[0050] Reference Figure 2 The display panel 100 may include a display area DAA and a non-display area NDA disposed around the display area DAA along an edge or periphery of the display area DAA. In the display area DAA, a plurality of pixels PX are configured to emit light and / or display an image, and in the non-display area NDA, light may not be emitted and / or an image may not be displayed.

[0051] The display panel 100 may include a plurality of pixels PX disposed in a display area DAA, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL.

[0052] The plurality of pixels PX may be arranged along a first direction DR1 and a second direction DR2. The plurality of pixels PX may be arranged in a matrix in the display area DAA. For example, the plurality of pixels PX may be arranged along rows and columns of the matrix along the first direction DR1 and the second direction DR2. The plurality of scan lines SL and the plurality of emission control lines EL may extend in the first direction DR1 and may be spaced apart (e.g., spaced apart) along the second direction DR2. The plurality of data lines DL may extend in the second direction DR2 and may be spaced apart (e.g., spaced apart) along the first direction DR1.

[0053] The plurality of scan lines SL may include a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines GBL. The plurality of emission control lines EL include a plurality of first emission control lines EL1 and a plurality of second emission control lines EL2.

[0054] The plurality of pixels PX may include a plurality of sub-pixels SP1, SP2, and SP3. The plurality of sub-pixels SP1, SP2, and SP3 may include Figure 3 The plurality of pixel transistors shown in FIG. The plurality of pixel transistors can be formed by a semiconductor process to be disposed on a semiconductor substrate SSUB (see FIG. Figure 7 For example, the plurality of pixel transistors may be formed of a complementary metal oxide semiconductor (CMOS).

[0055] Each of the plurality of sub-pixels SP1, SP2, and SP3 can be connected to one write scan line GWL among a plurality of write scan lines GWL, one control scan line GCL among a plurality of control scan lines GCL, one bias scan line GBL among a plurality of bias scan lines GBL, one first emission control line EL1 among a plurality of first emission control lines EL1, one second emission control line EL2 among a plurality of second emission control lines EL2, and one data line DL among a plurality of data lines DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 can receive a data voltage of the data line DL in response to a write scan signal of the write scan line GWL and emit light from the light-emitting element according to the data voltage.

[0056] The display panel 100 may include a scan driver 610 , an emission driver 620 , and a data driver 700 disposed in the non-display area NDA.

[0057] The scan driver 610 includes a plurality of scan transistors, and the emission driver 620 includes a plurality of light emitting transistors. The plurality of scan transistors and the plurality of light emitting transistors may be formed on a semiconductor substrate SSUB (see FIG. Figure 7 ). For example, a plurality of scanning transistors and a plurality of light emitting transistors can be formed by CMOS. Although Figure 2, the scan driver 610 is disposed on the left side of the display area DAA and the emission driver 620 is disposed on the right side of the display area DAA, but the present disclosure is not limited thereto. For example, the scan driver 610 and the emission driver 620 may be disposed on both the left and right sides of the display area DAA.

[0058] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate a write scan signal based on the scan timing control signal SCS from the timing control circuit 400 and sequentially output the write scan signal to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal in response to the scan timing control signal SCS and sequentially output the control scan signal to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal based on the scan timing control signal SCS and sequentially output the bias scan signal to the bias scan line GBL.

[0059] The emission driver 620 includes a first emission control driver 621 and a second emission control driver 622. Each of the first emission control driver 621 and the second emission control driver 622 can receive an emission timing control signal ECS from the timing control circuit 400. The first emission control driver 621 generates a first emission control signal based on the emission timing control signal ECS and sequentially outputs the first emission control signal to the first emission control line EL1. The second emission control driver 622 generates a second emission control signal based on the emission timing control signal ECS and sequentially outputs the second emission control signal to the second emission control line EL2.

[0060] The data driver 700 may include a plurality of data transistors, and the plurality of data transistors may be formed on a semiconductor substrate SSUB (see FIG. Figure 7 For example, the plurality of data transistors may be formed of CMOS.

[0061] The data driver 700 may receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, the sub-pixels SP1, SP2, and SP3 are selected by the write scan signal of the scan driver 610, and the data voltage may be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0062] Figure 3 is an equivalent circuit diagram of a sub-pixel according to one or more embodiments.

[0063] Reference Figure 3 Subpixel SP1 can be connected to a write scan line GWL, a control scan line GCL, a bias scan line GBL, a first emission control line EL1, a second emission control line EL2, and a data line DL. Furthermore, subpixel SP1 can be connected to a first drive voltage line VSL to which a first drive voltage VSS corresponding to a low potential voltage is applied, a second drive voltage line VDL to which a second drive voltage VDD corresponding to a high potential voltage is applied, and a third drive voltage line VIL to which a third drive voltage VINT corresponding to an initialization voltage is applied. That is, the first drive voltage line VSL can be a low potential voltage line, the second drive voltage line VDL can be a high potential voltage line, and the third drive voltage line VIL can be an initialization voltage line. In this case, the first drive voltage VSS can be lower than the third drive voltage VINT. The second drive voltage VDD can be higher than the third drive voltage VINT.

[0064] The sub-pixel SP1 includes a plurality of transistors T1 to T6 , a light emitting element LE, a first capacitor C1 , and a second capacitor C2 .

[0065] The light-emitting element LE emits light in response to a drive current Ids flowing through the channel of the first transistor T1. The amount of light emitted by the light-emitting element LE may be proportional to the drive current Ids. The light-emitting element LE may be disposed between the fourth transistor T4 and the first drive voltage line VSL. A first electrode of the light-emitting element LE may be connected to the drain electrode of the fourth transistor T4, and a second electrode of the light-emitting element LE may be connected to the first drive voltage line VSL. The first electrode of the light-emitting element LE may be an anode electrode, and the second electrode of the light-emitting element LE may be a cathode electrode. The light-emitting element LE may be, but is not limited to, an organic light-emitting diode (OLED) including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first and second electrodes. For example, the light-emitting element LE may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first and second electrodes. In this case, the light-emitting element LE may be a micro light-emitting diode.

[0066] The first transistor T1 may be a driving transistor that controls a source-drain current Ids (i.e., a "driving current") flowing between a source electrode and a drain electrode of the first transistor T1 according to a voltage applied to the gate electrode of the first transistor T1. The first transistor T1 includes a gate electrode connected to a first node N1, a source electrode connected to a drain electrode of the sixth transistor T6, and a drain electrode connected to a second node N2.

[0067] The second transistor T2 can be disposed between one electrode of the first capacitor C1 and the data line DL. The second transistor T2 is turned on by a write scan signal from the write scan line GWL to connect one electrode of the first capacitor C1 to the data line DL. Therefore, a data voltage of the data line DL can be applied to one electrode of the first capacitor C1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor C1.

[0068] The third transistor T3 can be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal from the control scan line GCL to connect the first node N1 to the second node N2. To this end, because the gate and drain electrodes of the first transistor T1 are connected, the first transistor T1 can operate like a diode (e.g., the first transistor T1 can be diode-connected). The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0069] The fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emission control signal of the first emission control line EL1 to connect the second node N2 to the third node N3. Thus, the driving current Ids of the first transistor T1 may be supplied to the light-emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0070] The fifth transistor T5 can be disposed between the third node N3 and the third drive voltage line VIL. The fifth transistor T5 is turned on by a bias scan signal from the bias scan line GBL to connect the third node N3 to the third drive voltage line VIL. Therefore, the third drive voltage VINT of the third drive voltage line VIL can be applied to the first electrode of the light-emitting element LE. The fifth transistor T5 includes a gate electrode connected to the bias scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third drive voltage line VIL.

[0071] The sixth transistor T6 can be disposed between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by the second emission control signal of the second emission control line EL2 to connect the source electrode of the first transistor T1 to the second drive voltage line VDL. Therefore, the second drive voltage VDD of the second drive voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emission control line EL2, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0072] The first capacitor C1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor C1 includes one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0073] The second capacitor C2 is formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor C2 includes one electrode connected to the gate electrode of the first transistor T1 or the first node N1 and the other electrode connected to the second driving voltage line VDL.

[0074] The first node N1 is a junction between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor C1, and one electrode of the second capacitor C2. The second node N2 is a junction between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a junction between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0075] Each of the first to sixth transistors T1 to T6 may be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first to sixth transistors T1 to T6 may be a P-type MOSFET, but is not limited thereto. Each of the first to sixth transistors T1 to T6 may be an N-type MOSFET. Alternatively, some of the first to sixth transistors T1 to T6 may be P-type MOSFETs, and each of the remaining transistors may be an N-type MOSFET.

[0076] although Figure 3 The sub-pixel SP1 is shown to include six transistors T1 to T6 and two capacitors C1 and C2, but it should be noted that the equivalent circuit diagram of the sub-pixel SP1 is not limited to Figure 3 For example, the number of transistors and the number of capacitors of the sub-pixel SP1 are not limited to Figure 3 The example shown in .

[0077] Figure 4 is a diagram illustrating a display panel according to one or more embodiments.

[0078] Reference Figure 4 According to one or more embodiments, the display panel 100 may include a plurality of pixels PX arranged in a matrix in a display area DAA. For example, the plurality of pixels PX may be arranged along rows and columns of the matrix along a first direction DR1 and a second direction DR2. The display panel 100 may include a scan driver 610, an emission driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a pad portion PDA, a power connection portion PCA, and a dam structure DAM, disposed in a non-display area NDA. In addition, in one or more embodiments, the display panel 100 may further include an electrostatic protection portion, a moisture permeation prevention portion, and / or a crack prevention portion disposed outside the dam structure DAM.

[0079] The scan driver 610 may be provided on a first side of the display area DAA, and the emission driver 620 may be provided on a second side of the display area DAA. For example, the scan driver 610 may be provided on one side of the display area DAA in the first direction DR1, and the emission driver 620 may be provided on the other side of the display area DAA in the first direction DR1. That is, the scan driver 610 may be provided on the left side of the display area DAA, and the emission driver 620 may be provided on the right side of the display area DAA. However, the present disclosure is not limited thereto, and the scan driver 610 and the emission driver 620 may be provided on both the first side and the second side of the display area DAA.

[0080] The pad portion PDA may include a plurality of pads PD connected to pads or bumps of the circuit board 300 via a conductive adhesive member. The pad portion PDA may be disposed on a third side of the display area DAA. For example, the pad portion PDA may be disposed on one side of the display area DAA in the second direction DR2. In other words, the pad portion PDA may be disposed on the lower side of the display area DAA. The pad portion PDA may be disposed outside the data driver 700 in the second direction DR2. In other words, the pad portion PDA may be disposed closer to the edge of the display panel 100 than the data driver 700.

[0081] In one or more embodiments, the display panel 100 may further include an inspection pad to inspect whether the display panel 100 is operating normally. The inspection pad may be connected to a fixture and / or probe pins during the inspection process, or may be connected to a circuit board for inspection. The circuit board for inspection may be a printed circuit board (PCB) made of a rigid material and / or a flexible printed circuit board (FPCB) made of a flexible material.

[0082] The first distribution circuit 710 distributes the data voltage applied through the pad portion PDA to multiple data lines DL. For example, the first distribution circuit 710 can distribute the data voltage applied through one pad PD of the pad portion PDA to P (P is a positive integer of 2 or greater) data lines DL, thereby reducing the number of pads PD. The first distribution circuit 710 can be disposed on a third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be disposed on one side of the display area DAA in the second direction DR2. In other words, the first distribution circuit 710 can be disposed on the lower side of the display area DAA.

[0083] The second distribution circuit 720 distributes the signal applied through the pad portion PDA to the scan driver 610, the emission driver 620, and the data lines DL. The second distribution circuit 720 can be configured to check the operation of each of the pixels PX in the display area DAA. The second distribution circuit 720 can be arranged on the fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be arranged on the other side of the display area DAA in the second direction DR2. In other words, the second distribution circuit 720 can be arranged on the upper side of the display area DAA. However, the second distribution circuit 720 can be omitted.

[0084] The power connection part PCA refers to the light emitting element LE (see Figure 3 ) and is applied with a first driving voltage VSS (see Figure 2 ) of the power connection electrode therein to connect the first driving voltage VSS (see Figure 2 ) is applied to the light emitting element LE (see Figure 3 ) in the area of ​​the second electrode.

[0085] The power connection portion PCA may be disposed around the display area DAA (e.g., disposed so as to surround the display area DAA). Furthermore, the power connection portion PCA may be disposed outside the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720. For example, the power connection portion PCA may be disposed closer to the edge of the display panel 100 than the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720. The power connection portion PCA may be disposed around the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720 (e.g., disposed so as to surround the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720). However, the present disclosure is not limited thereto, and the power connection portion PCA may overlap at least one of the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720 in the third direction DR3.

[0086] The dam structure DAM can be used to prevent the light emitting element LE from being packaged (see Figure 3 ) encapsulation layer TFE (see Figure 7 ) The organic encapsulation layer TFE2 overflows into the pad portion of the PDA structure.

[0087] The dam structure DAM may be disposed around the display area DAA (e.g., disposed so as to surround the display area DAA). Furthermore, the dam structure DAM may be disposed outside the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720. For example, the dam structure DAM may be disposed closer to the edge of the display panel 100 than the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720. The dam structure DAM may be disposed around the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720 (e.g., disposed so as to surround the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720). However, the present disclosure is not limited thereto, and the dam structure DAM may overlap at least one of the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720 in the third direction DR3.

[0088] In addition, the dam structure DAM may be provided outside the power connection portion PCA. For example, the dam structure DAM may be provided closer to the edge of the display panel 100 than the power connection portion PCA. The dam structure DAM may be provided around the power connection portion PCA (for example, around the power connection portion PCA).

[0089] Figure 5 It shows the settings Figure 4 A plan view of the first electrodes and emission regions of multiple pixels and the pixel defining film in the display area.

[0090] Reference Figure 5 Each of the plurality of pixels PX may include a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3. The first to third subpixels SP1, SP2, and SP3 may include emission areas EA1, EA2, and EA3, respectively. For example, the first subpixel SP1 may include a first emission area EA1, the second subpixel SP2 may include a second emission area EA2, and the third subpixel SP3 may include a third emission area EA3.

[0091] Each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be a region defined by the pixel defining film PDL. For example, each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be a region defined by the first pixel defining film PDL1.

[0092] The length of the third emission area EA3 in the first direction DR1 may be smaller than the length of the first emission area EA1 in the first direction DR1 and may be smaller than the length of the second emission area EA2 in the first direction DR1. The length of the first emission area EA1 in the first direction DR1 and the length of the second emission area EA2 in the first direction DR1 may be substantially the same.

[0093] In each of the plurality of pixels PX, the first emission area EA1 and the second emission area EA2 may be adjacent to each other in the second direction DR2. Furthermore, the first emission area EA1 and the third emission area EA3 may be adjacent to each other in the first direction DR1. Furthermore, the second emission area EA2 and the third emission area EA3 may be adjacent to each other in the first direction DR1. The areas of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be different.

[0094] The first emission area EA1 may emit light of a first color, the second emission area EA2 may emit light of a second color, and the third emission area EA3 may emit light of a third color. Here, the first color light may be light of a red wavelength band, the second color light may be light of a green wavelength band, and the third color light may be light of a blue wavelength band. For example, the blue wavelength band may be a wavelength band of light having a main peak wavelength in the range of approximately 370 nm to approximately 460 nm, the green wavelength band may be a wavelength band of light having a main peak wavelength in the range of approximately 480 nm to approximately 560 nm, and the red wavelength band may be a wavelength band of light having a main peak wavelength in the range of approximately 600 nm to approximately 750 nm.

[0095] The first electrode AND of the light emitting element LE (for example, see Figure 7) may have a rectangular shape in plan view. The planar shape of the first electrode AND of the light-emitting element LE may be different in the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3. For example, the first electrode AND of the first subpixel SP1 and the first electrode AND of the second subpixel SP2 may have a rectangular planar shape having a long side in the first direction DR1 and a short side in the second direction DR2. The first electrode AND of the third subpixel SP3 may have a rectangular planar shape having a short side in the first direction DR1 and a long side in the second direction DR2 in plan view. The length of the first electrode AND of the third subpixel SP3 in the first direction DR1 may be shorter than the length of the first electrode AND of each of the first subpixel SP1 and the second subpixel SP2 in the first direction DR1. The length of the first electrode AND of the first subpixel SP1 in the second direction DR2 may be longer than the length of the first electrode AND of the second subpixel SP2 in the second direction DR2.

[0096] In one or more embodiments, the first electrode AND of the light emitting element LE may be connected to the first electrode AND of the light emitting element LE through the tenth via hole VA10 (see FIG. Figure 7 ) is connected to the reflective electrode layer RL (see Figure 7 In one or more embodiments, the tenth via hole VA10 may overlap the first pixel defining film PDL1 , the second pixel defining film PDL2 , and the third pixel defining film PDL3 in the third direction DR3 .

[0097] Figure 6 is a plan view illustrating first electrodes and emission regions of a plurality of sub-pixels and a pixel-defining film according to one or more embodiments.

[0098] Because except for the plane shape of the first emission area EA1, the plane shape of the second emission area EA2 and the plane shape of the third emission area EA3 Figure 5 In addition to the differences in the planar shapes of the first emission area EA1, the second emission area EA2, and the third emission area EA3, Figure 6 Examples and Figure 5 The embodiments are basically the same, so the Figure 5 The description of the embodiment is repeated.

[0099] Reference Figure 6, the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be arranged in a hexagonal structure having a hexagonal shape in a plan view. In this case, the first emission area EA1 and the second emission area EA2 may be adjacent to each other in the first direction DR1, but the second emission area EA2 and the third emission area EA3 may be adjacent to each other in the first oblique direction DD1, and the first emission area EA1 and the third emission area EA3 may be adjacent to each other in the second oblique direction DD2. The first oblique direction DD1 may be a direction between the first direction DR1 and the second direction DR2 and may refer to a direction inclined 45 degrees relative to the first direction DR1 and the second direction DR2, and the second oblique direction DD2 may be a direction perpendicular to the first oblique direction DD1.

[0100] Despite Figure 5 and Figure 6 , each of the plurality of pixels PX includes three emission areas EA1, EA2, and EA3, but the present disclosure is not limited thereto. That is, each of the plurality of pixels PX may include four emission areas.

[0101] In addition, the arrangement of the emission areas EA1, EA2 and EA3 of the plurality of pixels PX is not limited to Figure 5 and Figure 6 For example, the emission regions of the plurality of pixels PX may be arranged in a stripe structure in which the emission regions are arranged along the first direction DR1, a PENTILE structure in which the emission regions are arranged in a diamond shape, or a PENTILE structure in which the emission regions are arranged in a diamond shape. ® Structure, etc. PENTILE ® The pixel arrangement structure may be referred to as an RGBG matrix structure (eg, PENTILE ® Matrix structure or RGBG structure (for example, PENTILE ® structure)). PENTILE ® is a registered trademark of Samsung Display Co., Ltd. of South Korea.

[0102] Figure 7 It is along Figure 5 Schematic cross-sectional view taken along line AA'.

[0103] Reference Figure 7 The display panel 100 may include a semiconductor backplane SBP, a light emitting element backplane EBP, a display element layer EML, an encapsulation layer TFE, an adhesive layer ADL, a color filter layer CFL, a lens array layer LNS, and a cover layer DCL. In one or more embodiments, the display panel 100 may further include a polarizing plate disposed on the cover layer DCL.

[0104] The semiconductor backplane SBP includes a semiconductor substrate SSUB, the semiconductor substrate SSUB includes a plurality of pixel transistors PTR, a plurality of semiconductor insulating films covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR. The plurality of pixel transistors PTR may be a reference Figure 3 The first transistor T1 to the sixth transistor T6 are described.

[0105] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. The semiconductor substrate SSUB may be a substrate doped with first-type impurities. A plurality of well regions WA may be provided on the top surface of the semiconductor substrate SSUB. The plurality of well regions WA may be regions doped with second-type impurities. The second-type impurities may be different from the aforementioned first-type impurities. For example, when the first-type impurities are p-type impurities, the second-type impurities may be n-type impurities. Alternatively, when the first-type impurities are n-type impurities, the second-type impurities may be p-type impurities.

[0106] Each of the plurality of well regions WA includes a source region SA corresponding to a source electrode of the pixel transistor PTR, a drain region DA corresponding to a drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region SA and the drain region DA.

[0107] The lower insulating film BINS may be provided between the gate electrode GE and the well area WA. The side insulating film SINS may be provided on the side surface of the gate electrode GE. The side insulating film SINS may be provided on the lower insulating film BINS.

[0108] Each of the source region SA and the drain region DA may be a region doped with first-type impurities. The gate electrode GE of the pixel transistor PTR may overlap the well region WA in the third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region SA may be provided on one side of the gate electrode GE, and the drain region DA may be provided on the other side of the gate electrode GE.

[0109] Each of the plurality of well regions WA further includes a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may be a region having an impurity concentration lower than that of the source region SA due to the lower insulating film BINS. The second low-concentration impurity region LDD2 may be a region having an impurity concentration lower than that of the drain region DA due to the lower insulating film BINS. The distance between the source region SA and the drain region DA may be increased due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2. Therefore, the length of the channel region CH of each of the pixel transistors PTR may be increased, thereby reducing or preventing punch-through and hot carrier phenomena that may be caused by a short channel.

[0110] The first semiconductor insulating film SINS1 may be provided on the semiconductor substrate SSUB to cover the gate electrode GE. The first semiconductor insulating film SINS1 may be made of silicon carbonitride (SiCN) and / or silicon oxide (SiO x ) type inorganic film formation, but not limited to this.

[0111] The second semiconductor insulating film SINS2 may be provided on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 may be made of silicon oxide (SiO x ) type inorganic film formation, but not limited to this.

[0112] A plurality of contact terminals CTE may be disposed on the second semiconductor insulating film SINS2. Each of the plurality of contact terminals CTE may be connected to one of the gate electrode GE, source area SA, and drain area DA of each of the pixel transistors PTR via a hole penetrating the first semiconductor insulating film SINS1 and the second semiconductor insulating film SINS2. The plurality of contact terminals CTE may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or alloys and / or compounds including one or more of these.

[0113] The third semiconductor insulating film SINS3 may be provided on the second semiconductor insulating film SINS2. The third semiconductor insulating film SINS3 may also be provided on the side surface of each of the portions of the plurality of contact terminals CTE provided on the second semiconductor insulating film SINS2. The top surface of each of the plurality of contact terminals CTE may be exposed without being covered by the third semiconductor insulating film SINS3. The third semiconductor insulating film SINS3 may be made of silicon oxide (SiO x ) type inorganic film formation, but not limited to this.

[0114] The semiconductor substrate SSUB may be replaced with a glass substrate and / or a polymer resin substrate such as polyimide. In this case, the thin film transistor may be provided on the glass substrate and / or the polymer resin substrate. The glass substrate may be a rigid substrate that does not bend, and the polymer resin substrate may be a flexible substrate that can be bent and / or curved.

[0115] The light-emitting element backplane EBP includes first to eighth metal layers ML1 to ML8 and a plurality of vias VA1 to VA9. Furthermore, the light-emitting element backplane EBP includes a plurality of interlayer insulating layers INS1 to INS9 disposed between the third semiconductor insulating film SINS3 and the first metal layer ML1, between the first to eighth metal layers ML1 to ML8, and between the eighth metal layer ML8 and the display element layer EML.

[0116] The first to eighth metal layers ML1 to ML8 may connect a plurality of contact terminals CTE exposed from the semiconductor backplane SBP to form Figure 3 . The first to sixth transistors T1 to T6 may be formed in the semiconductor backplane SBP, and the first to sixth transistors T1 to T6 may be connected to the first capacitor C1 and the second capacitor C2 via the first to eighth metal layers ML1 to ML8. Furthermore, the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE may also be connected via the first to eighth metal layers ML1 to ML8.

[0117] A first interlayer insulating layer INS1 may be provided on the semiconductor backplane SBP. Each of the first via holes VA1 may penetrate the first interlayer insulating layer INS1 to connect to the contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first metal layers ML1 may be provided on the first interlayer insulating layer INS1 and may be connected to the first via holes VA1.

[0118] The second interlayer insulating layer INS2 may be disposed on the first interlayer insulating layer INS1 and the first metal layer ML1. Each of the second via holes VA2 may penetrate the second interlayer insulating layer INS2 and may be connected to the exposed first metal layer ML1. Each of the second metal layers ML2 may be disposed on the second interlayer insulating layer INS2 and may be connected to the second via holes VA2.

[0119] The third interlayer insulating layer INS3 may be disposed on the second interlayer insulating layer INS2 and the second metal layer ML2. Each of the third via holes VA3 may penetrate the third interlayer insulating layer INS3 and may be connected to the exposed second metal layer ML2. Each of the third metal layers ML3 may be disposed on the third interlayer insulating layer INS3 and may be connected to the third via holes VA3.

[0120] The fourth interlayer insulating layer INS4 may be disposed on the third interlayer insulating layer INS3 and the third metal layer ML3. Each of the fourth via holes VA4 may penetrate the fourth interlayer insulating layer INS4 and may be connected to the exposed third metal layer ML3. Each of the fourth metal layers ML4 may be disposed on the fourth interlayer insulating layer INS4 and may be connected to the fourth via hole VA4.

[0121] A fifth interlayer insulating layer INS5 may be disposed on the fourth interlayer insulating layer INS4 and the fourth metal layer ML4. Each of the fifth via holes VA5 may penetrate the fifth interlayer insulating layer INS5 and may be connected to the exposed fourth metal layer ML4. Each of the fifth metal layers ML5 may be disposed on the fifth interlayer insulating layer INS5 and may be connected to the fifth via hole VA5.

[0122] The sixth interlayer insulating layer INS6 may be disposed on the fifth interlayer insulating layer INS5 and the fifth metal layer ML5. Each of the sixth via holes VA6 may penetrate the sixth interlayer insulating layer INS6 and may be connected to the exposed fifth metal layer ML5. Each of the sixth metal layers ML6 may be disposed on the sixth interlayer insulating layer INS6 and may be connected to the sixth via hole VA6.

[0123] The seventh interlayer insulating layer INS7 may be disposed on the sixth interlayer insulating layer INS6 and the sixth metal layer ML6. Each of the seventh via holes VA7 may penetrate the seventh interlayer insulating layer INS7 and may be connected to the exposed sixth metal layer ML6. Each of the seventh metal layers ML7 may be disposed on the seventh interlayer insulating layer INS7 and may be connected to the seventh via hole VA7.

[0124] The eighth interlayer insulating layer INS8 may be disposed on the seventh interlayer insulating layer INS7 and the seventh metal layer ML7. Each of the eighth via holes VA8 may penetrate the eighth interlayer insulating layer INS8 and may be connected to the exposed seventh metal layer ML7. Each of the eighth metal layers ML8 may be disposed on the eighth interlayer insulating layer INS8 and may be connected to the eighth via hole VA8.

[0125] The first to eighth metal layers ML1 to ML8 and the first to eighth vias VA1 to VA8 may be formed of substantially the same material. The first metal layers ML1 to ML8 and the first to eighth vias VA1 to VA8 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and / or neodymium (Nd), and / or alloys and / or compounds including one or more thereof. The first to eighth vias VA1 to VA8 may be made of substantially the same material. The first to eighth interlayer insulating layers INS1 to INS8 may be made of silicon oxide (SiO x ) type inorganic film formation, but not limited to this.

[0126] In one or more embodiments, the thickness of the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6 may be respectively greater than the thickness of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. In one or more embodiments, the thickness of each of the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6 may be greater than the thickness of the first metal layer ML1. In one or more embodiments, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be substantially the same. For example, the thickness of the first metal layer ML1 may be approximately 1360Å, the thickness of each of the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5 and the sixth metal layer ML6 may be approximately 1440Å, and the thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5 and the sixth via VA6 may be approximately 1150Å.

[0127] The thickness of each of the seventh metal layer ML7 and the eighth metal layer ML8 may be greater than the thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6. The thickness of each of the seventh metal layer ML7 and the eighth metal layer ML8 may be greater than the thickness of the seventh via VA7 and the thickness of the eighth via VA8. The thickness of each of the seventh via VA7 and the eighth via VA8 may be greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be substantially the same. For example, the thickness of each of the seventh metal layer ML7 and the eighth metal layer ML8 may be approximately 9000 Å. The thickness of each of the seventh via VA7 and the eighth via VA8 may be approximately 6000 Å.

[0128] The ninth interlayer insulating layer INS9 may be disposed on the eighth interlayer insulating layer INS8 and the eighth metal layer ML8. The ninth interlayer insulating layer INS9 may be made of silicon oxide (SiO x ) type inorganic film formation, but not limited to this.

[0129] Each of the ninth vias VA9 may penetrate the ninth interlayer insulating layer INS9 and may be connected to the exposed eighth metal layer ML8. The ninth via VA9 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or alloys and / or compounds including one or more thereof. The thickness of the ninth via VA9 may be approximately 16,500 Å.

[0130] The display element layer EML may be disposed on the ninth interlayer insulating layer INS9 of the light emitting element backplane EBP. The display element layer EML may include light emitting elements LE and a pixel defining layer PDL. Each light emitting element LE includes a reflective electrode layer RL, a tenth interlayer insulating layer INS10, an eleventh interlayer insulating layer INS11, a tenth via hole VA10, a first electrode AND, a light emitting stack IL, and a second electrode CAT.

[0131] The reflective electrode layer RL may be disposed on the ninth interlayer insulating layer INS9. The reflective electrode layer RL may include at least one of the reflective electrodes RL1, RL2, RL3, and RL4. For example, the reflective electrode layer RL may include: Figure 7 1 to the fourth reflective electrodes RL1 , RL2 , RL3 and RL4 shown in FIG.

[0132] Each of the first reflective electrodes RL1 may be disposed on the ninth interlayer insulating layer INS9 and may be connected to the ninth via hole VA9. The first reflective electrodes RL1 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or alloys and / or compounds including one or more thereof. For example, the first reflective electrodes RL1 may include titanium nitride (TiN).

[0133] Each of the second reflective electrodes RL2 may be disposed on the first reflective electrode RL1. The second reflective electrodes RL2 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or alloys and / or compounds including one or more thereof. For example, the second reflective electrodes RL2 may include aluminum (Al).

[0134] Each of the third reflective electrodes RL3 may be disposed on the second reflective electrode RL2. The third reflective electrodes RL3 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or alloys and / or compounds including one or more thereof. For example, the third reflective electrodes RL3 may include titanium nitride (TiN).

[0135] The fourth reflective electrode RL4 may be disposed on each of the third reflective electrodes RL3. The fourth reflective electrode RL4 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or alloys and / or compounds including one or more of these. For example, the fourth reflective electrode RL4 may include titanium (Ti).

[0136] Because the second reflective electrode RL2 is an electrode that substantially reflects light from the light-emitting element LE, in one or more embodiments, the thickness of the second reflective electrode RL2 may be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, in one or more embodiments, the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 may be approximately 100 Å, and the thickness of the second reflective electrode RL2 may be approximately 850 Å. However, in one or more other embodiments, the thickness of the second reflective electrode RL2 may be substantially the same as the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4.

[0137] The tenth interlayer insulating layer INS10 may be disposed on the ninth interlayer insulating layer INS9. The tenth interlayer insulating layer INS10 may be disposed between the reflective electrode layers RL adjacent to each other. The tenth interlayer insulating layer INS10 may be disposed on the reflective electrode layer RL in the third sub-pixel SP3. The tenth interlayer insulating layer INS10 may be made of silicon oxide (SiO x ) type inorganic film formation, but not limited to this.

[0138] The eleventh interlayer insulating layer INS11 may be disposed on the tenth interlayer insulating layer INS10 and the reflective electrode layer RL in the second and third sub-pixels SP2 and SP3. The eleventh interlayer insulating layer INS11 may be made of silicon oxide (SiO x ) type inorganic film formation, but not limited to this.

[0139] Considering the resonance distance of light emitted from the light emitting element LE, the tenth and eleventh interlayer insulating layers INS10 and INS11 may not be disposed under the first electrode AND in at least one of the first, second, and third subpixels SP1, SP2, and SP3.

[0140] For example, the first electrode AND of the first subpixel SP1 may be directly disposed on the fourth reflective electrode RL4, and the first electrode AND of the first subpixel SP1 may not overlap the tenth interlayer insulating layer INS10 and the eleventh interlayer insulating layer INS11. The first electrode AND of the second subpixel SP2 may be disposed on the eleventh interlayer insulating layer INS11, and the eleventh interlayer insulating layer INS11 may be directly disposed on the fourth reflective electrode RL4. In other words, the first electrode AND of the second subpixel SP2 may not overlap the tenth interlayer insulating layer INS10. The first electrode AND of the third subpixel SP3 may be disposed on the eleventh interlayer insulating layer INS11 and may overlap the tenth interlayer insulating layer INS10.

[0141] In one or more embodiments, the distance between the first electrode AND and the reflective electrode layer RL may be different in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. In order to adjust the distance from the reflective electrode layer RL to the second electrode CAT according to the main wavelength of light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the presence or absence of the tenth interlayer insulating layer INS10 and the eleventh interlayer insulating layer INS11 may be set in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, Figure 7In the embodiment of the present invention, the distance between the first electrode AND and the reflective electrode layer RL in the third subpixel SP3 may be greater than the distance between the first electrode AND and the reflective electrode layer RL in the second subpixel SP2 and the distance between the first electrode AND and the reflective electrode layer RL in the first subpixel SP1, and the distance between the first electrode AND and the reflective electrode layer RL in the second subpixel SP2 may be greater than the distance between the first electrode AND and the reflective electrode layer RL in the first subpixel SP1. However, the present disclosure is not limited thereto. The distance between the first electrode AND and the reflective electrode layer RL in each of the subpixels SP1, SP2, and SP3 may be variously modified and designed.

[0142] In addition, although the tenth interlayer insulating layer INS10 and the eleventh interlayer insulating layer INS11 are shown in the drawings, a twelfth interlayer insulating layer may be further provided below the first electrodes AND of the sub-pixels SP1, SP2, and SP3. In this case, the eleventh interlayer insulating layer INS11 and the twelfth interlayer insulating layer may be provided below the first electrode AND of the second sub-pixel SP2, and the tenth interlayer insulating layer INS10, the eleventh interlayer insulating layer INS11, and the twelfth interlayer insulating layer may be provided below the first electrode AND of the third sub-pixel SP3. Alternatively, the eleventh interlayer insulating layer INS11 may be omitted.

[0143] Each of the tenth via holes VA10 may penetrate the tenth interlayer insulating layer INS10 and / or the eleventh interlayer insulating layer INS11 in the second subpixel SP2 and the third subpixel SP3 and may be connected to the exposed fourth reflective electrode RL4. The tenth via hole VA10 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or alloys and / or compounds including one or more thereof. The thickness of the tenth via hole VA10 in the second subpixel SP2 may be thinner than the thickness of the tenth via hole VA10 in the third subpixel SP3.

[0144] In one or more embodiments, the first electrode AND of each light-emitting element LE may be disposed on the fourth reflective electrode RL4, the tenth interlayer insulating layer INS10, or the eleventh interlayer insulating layer INS11 and may be connected to the tenth via VA10. The first electrode AND of each light-emitting element LE may be connected to the drain region DA or the source region SA of the pixel transistor PTR via the tenth via VA10, the first to fourth reflective electrodes RL1 to RL4, the first to ninth vias VA1 to VA9, the first to eighth metal layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each light-emitting element LE may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or alloys and / or compounds including one or more of these. For example, the first electrode AND of each light-emitting element LE may be titanium nitride (TiN).

[0145] The pixel defining film PDL may be disposed on a portion of the first electrode AND of each of the light emitting elements. The pixel defining film PDL may cover edges of the first electrode AND. The pixel defining film PDL may partition the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0146] The first emission area EA1 may be defined as a region where the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emission area EA2 may be defined as a region where the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third emission area EA3 may be defined as a region where the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0147] The pixel definition film PDL may include first to third pixel definition films PDL1, PDL2, and PDL3. The first pixel definition film PDL1 may be provided on the edge of the first electrode AND of each of the light emitting elements, the second pixel definition film PDL2 may be provided on the first pixel definition film PDL1, and the third pixel definition film PDL3 may be provided on the second pixel definition film PDL2. The first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 may be made of silicon oxide (SiO x ) and / or silicon nitride (SiN x The first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may each have a thickness of about 500 Å.

[0148] According to one or more embodiments, the pixel defining film PDL provided in the display area DAA is constructed so that the second pixel defining film PDL2 may be more recessed inwardly than the first pixel defining film PDL1 and the third pixel defining film PDL3 at the openings forming the emission areas EA1, EA2, and EA3. The first pixel defining film PDL1 and the third pixel defining film PDL3 of the pixel defining film PDL may protrude further into the openings from the lower and upper portions of the second pixel defining film PDL2. The third pixel defining film PDL3, which is the uppermost layer of the pixel defining film PDL, may include a tip that protrudes more than the lower layer of the pixel defining film PDL. Since the third pixel defining film PDL3 has a shape that protrudes more from the inner sidewall of the opening than the second pixel defining film PDL2, an undercut structure of the second pixel defining film PDL2 may be formed below the tip of the third pixel defining film PDL3.

[0149] The portion of the top surface of the first electrode AND that overlaps the first pixel-defining film PDL1 may be partially recessed. During the process of forming the opening of the pixel-defining film PDL, a portion of the top surface of the first electrode AND is recessed, and the first pixel-defining film PDL1 may form a pointed structure. A portion of the top surface of the first electrode AND may be spaced apart (e.g., separated) from the first pixel-defining film PDL1, but an edge portion may be in direct contact with the first pixel-defining film PDL1.

[0150] The light emitting stack IL may include a plurality of intermediate layers. Figure 7 , the light emitting stack IL has a triple series structure including a first light emitting stack IL1, a second light emitting stack IL2, and a third light emitting stack IL3, but the present disclosure is not limited thereto. For example, the light emitting stack IL may have a double series structure including two intermediate layers.

[0151] In the triple-series structure, the light-emitting stack IL may have a series structure including a plurality of light-emitting stacks IL1, IL2, and IL3 that emit different lights. For example, the light-emitting stack IL may include a first light-emitting stack IL1 that emits light of a first color, a second light-emitting stack IL2 that emits light of a third color, and a third light-emitting stack IL3 that emits light of a second color. The first light-emitting stack IL1, the second light-emitting stack IL2, and the third light-emitting stack IL3 may be stacked sequentially.

[0152] The first light-emitting stack IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second light-emitting stack IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer emitting light of a third color, and a second electron transport layer are sequentially stacked. The third light-emitting stack IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer emitting light of a second color, and a third electron transport layer are sequentially stacked.

[0153] A first charge generation layer for supplying holes to the second light emitting stack IL2 and electrons to the first light emitting stack IL1 may be provided between the first light emitting stack IL1 and the second light emitting stack IL2. The first charge generation layer may include an N-type charge generation layer for supplying electrons to the first light emitting stack IL1 and a P-type charge generation layer for supplying holes to the second light emitting stack IL2. The N-type charge generation layer may include a dopant of a metal material.

[0154] A second charge generation layer for supplying holes to the third light emitting stack IL3 and electrons to the second light emitting stack IL2 may be provided between the second light emitting stack IL2 and the third light emitting stack IL3. The second charge generation layer may include an N-type charge generation layer for supplying electrons to the second light emitting stack IL2 and a P-type charge generation layer for supplying holes to the third light emitting stack IL3.

[0155] The first light-emitting stack IL1 may be disposed on the first electrode AND and may be disposed on the first pixel-defining film PDL1. For example, the first light-emitting stack IL1 may be disposed on the inner sidewall of the first pixel-defining film PDL1. The second light-emitting stack IL2 may be disposed on the first light-emitting stack IL1. The second light-emitting stack IL2 may cover the first light-emitting stack IL1 and may be disposed on the first pixel-defining film PDL1 in the opening of the pixel-defining film PDL. Each of the first light-emitting stack IL1 and the second light-emitting stack IL2 may be disconnected by the tip structure of the third pixel-defining film PDL3 between adjacent sub-pixels SP1, SP2, and SP3. The third light-emitting stack IL3 may be disposed on the second light-emitting stack IL2. The third light-emitting stack IL3 may not be disconnected by the tip structure of the third pixel-defining film PDL3 and may be disposed on the pixel-defining film PDL. A gap or empty space may be provided between the third light-emitting stack IL3 and the second pixel-defining film PDL2. That is, the first and second light emitting stacks IL1 and IL2 may be layers disposed in the openings of the pixel defining film PDL, and the third light emitting stack IL3 may be a layer entirely disposed in and on the openings of the pixel defining film PDL.

[0156] For example, in a three-series structure, the tip structure of the pixel-defining film PDL may be a structure for disconnecting the first light-emitting stack IL1 and the second light-emitting stack IL2, and the first charge generation layer and the second charge generation layer between adjacent sub-pixels SP1, SP2, and SP3. In a two-series structure, the tip structure of the pixel-defining film PDL may be a structure for disconnecting the charge generation layer and the lower intermediate layer provided between the lower intermediate layer and the upper intermediate layer.

[0157] The pixel defining film PDL may have a structure in which a plurality of inorganic insulating layers are stacked, and, in some embodiments, may have a structure in which inorganic insulating layers of different materials are alternately stacked. In the process of forming the opening of the pixel defining film PDL, there may be a layer that is etched at a rate faster than the rate of other layers of the contact stack according to the etching selectivity of the etchant. For example, when the first pixel defining film PDL1 and the third pixel defining film PDL3 include inorganic insulating materials of the same material, and the second pixel defining film PDL2 includes inorganic insulating materials of different materials, the second pixel defining film PDL2 may be etched at a rate faster than the rate of the third pixel defining film PDL3 in the process of etching the second pixel defining film PDL2 and the third pixel defining film PDL3, and may be recessed more inward than the third pixel defining film PDL3 to form a tip. Due to the tip structure formed inside the opening of the pixel defining film PDL, the light emitting stack IL may be disconnected between different adjacent emission areas EA1, EA2 and EA3.

[0158] Similarly, during the etching process of the first pixel defining film PDL1, a portion of the top surface of the first electrode AND may be etched depending on the etchant. The portion of the top surface of the first electrode AND overlapping the first pixel defining film PDL1 may be partially recessed, and the first pixel defining film PDL1 may form a tip structure.

[0159] The number of light emitting stacks IL1, IL2, and IL3 emitting different lights is not limited to Figure 7 . For example, the light-emitting stack IL may include two intermediate layers. In this case, one of the two intermediate layers may be substantially the same as the first light-emitting stack IL1, and the other may include a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron transport layer. In this case, a charge generation layer for supplying electrons to one intermediate layer and holes to the other intermediate layer may be provided between the two intermediate layers.

[0160] also, Figure 7It is shown that the first to third light-emitting stacks IL1, IL2 and IL3 are all arranged in the first emission area EA1, the second emission area EA2 and the third emission area EA3, but the present disclosure is not limited to this. For example, the first light-emitting stack IL1 can be arranged in the first emission area EA1, and may not be arranged in the second emission area EA2 and the third emission area EA3. In addition, the second light-emitting stack IL2 can be arranged in the second emission area EA2, and may not be arranged in the first emission area EA1 and the third emission area EA3. In addition, the third light-emitting stack IL3 can be arranged in the third emission area EA3, and may not be arranged in the first emission area EA1 and the second emission area EA2. In this case, the first to third color filters CF1, CF2 and CF3 of the optical layer can be omitted, but it is not necessarily required to be omitted.

[0161] The second electrode CAT may be disposed on the third light-emitting stack IL3. The second electrode CAT may be formed of a transparent conductive material (TCO) that transmits light, such as ITO and / or IZO, or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), and / or an alloy of Mg and Ag. When the second electrode CAT is formed of a semi-transmissive conductive material, light emission efficiency may be improved in each of the first to third subpixels SP1, SP2, and SP3 due to a microcavity effect.

[0162] The encapsulation layer TFE may be disposed on the display element layer EML. The encapsulation layer TFE may include at least one inorganic encapsulation layer TFE1 and TFE3 to prevent oxygen or moisture from penetrating into the display element layer EML. Furthermore, the encapsulation layer TFE may include at least one organic layer to protect the display element layer EML from foreign matter such as dust. For example, the encapsulation layer TFE may include a first inorganic encapsulation layer TFE1, an organic encapsulation layer TFE2, and a second inorganic encapsulation layer TFE3.

[0163] The first inorganic encapsulation layer TFE1 may be disposed on the second electrode CAT, the organic encapsulation layer TFE2 may be disposed on the first inorganic encapsulation layer TFE1, and the second inorganic encapsulation layer TFE3 may be disposed on the organic encapsulation layer TFE2. The first inorganic encapsulation layer TFE1 and the second inorganic encapsulation layer TFE3 may be formed of silicon nitride (SiN x ) layer, silicon oxynitride (SiO x N y ) layer, silicon oxide (SiO x ) layer, titanium oxide (TiO x ) layer and / or aluminum oxide (AlO xThe organic encapsulation layer TFE2 may be a single layer. Alternatively, the organic encapsulation layer TFE2 may be an organic layer including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0164] The adhesive layer ADL may be provided on the encapsulation layer TFE. The adhesive layer ADL may be a layer for bonding the encapsulation layer TFE to the layer provided thereon. The adhesive layer ADL may be a double-sided adhesive member. In addition, the adhesive layer ADL may be a transparent adhesive member such as a transparent adhesive and / or a transparent adhesive resin.

[0165] The color filter layer CFL, the lens array layer LNS, and the cover layer DCL may be disposed on the adhesive layer ADL. The color filter layer CFL, the lens array layer LNS, and the cover layer DCL may constitute an optical layer of the display panel 100.

[0166] The color filter layer CFL may include a plurality of color filters CF1, CF2, and CF3 and may be disposed on the adhesive layer ADL. The first color filter CF1 may overlap the first emission area EA1 of the first subpixel SP1. The first color filter CF1 may transmit light of a first color, i.e., light of a red wavelength band. The first color filter CF1 may transmit light of the first color among the light emitted from the first emission area EA1.

[0167] The second color filter CF2 may overlap the second emission area EA2 of the second sub-pixel SP2. The second color filter CF2 may transmit light of the second color, that is, light of the green wavelength band. Therefore, the second color filter CF2 may transmit light of the second color among the light emitted from the second emission area EA2.

[0168] The third color filter CF3 may overlap the third emission area EA3 of the third subpixel SP3. The third color filter CF3 may transmit light of a third color, that is, light of a blue wavelength band. Therefore, the third color filter CF3 may transmit light of the third color among the light emitted from the third emission area EA3.

[0169] The lens array layer LNS may be disposed on the color filter layer CFL in the display area DAA. The lens array layer LNS may include a plurality of lenses disposed in the display area DAA. The plurality of lenses may be disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the plurality of lenses may be a structure for increasing the ratio of light directed to the front of the display device 10. Each of the plurality of lenses may have a cross-sectional shape that is convex in an upward direction.

[0170] The cover layer DCL may be disposed on the lens array layer LNS. The cover layer DCL may be disposed directly on the multiple lenses of the lens array layer LNS. The cover layer DCL may have a suitable refractive index (e.g., a predetermined refractive index) such that light travels along the third direction DR3 at the interface between the multiple lenses and the cover layer DCL. Furthermore, the cover layer DCL may be a planarization layer. The cover layer DCL may be an organic layer including, for example, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0171] In one or more embodiments, a polarizing plate may be provided on the cover layer DCL. The polarizing plate may be a structure used to prevent visibility degradation caused by external light reflection. The polarizing plate may include a linear polarizing plate and a phase retarder film. For example, the phase retarder film may be a λ / 4 plate (quarter-wave plate), but is not limited thereto. However, the polarizing plate may be omitted if visibility degradation caused by external light reflection is sufficiently overcome by the first to third color filters CF1, CF2, and CF3.

[0172] like Figure 7 As shown in , by forming a light emitting element backplane EBP and a display element layer EML on a semiconductor substrate SSUB on which a plurality of transistors are formed, the size of a plurality of pixels PX can be greatly reduced, thereby providing a display device 10 that displays high-resolution images.

[0173] Figure 8 It shows Figure 4 Magnified view of area X. Figure 9 It is along Figure 8 A schematic cross-sectional view taken along line BB'.

[0174] Figure 4 The region X may be a region disposed at a lower side as one side of the display area DAA in the second direction DR2. Figure 8 and Figure 9 The first distribution circuit 710 , the power connection portion PCA, the dam structure DAM, the data driver 700 , and the pad PD disposed at the lower side of the display area DAA are shown.

[0175] Reference Figure 8 and Figure 9The first distribution circuit 710, the power connection portion PCA, the dam structure DAM, the data driver 700, and the pad PD may be sequentially arranged along the second direction DR2 on the lower side of the display area DAA. However, the present disclosure is not limited thereto. In one or more embodiments, the power connection portion PCA may overlap the first distribution circuit 710 or the data driver 700 in the thickness direction (e.g., the third direction DR3), and the dam structure DAM may overlap the first distribution circuit 710 or the data driver 700 in the thickness direction (e.g., the third direction DR3).

[0176] The first distribution circuit 710 may include a plurality of first distribution transistors DBTR1. Since each of the plurality of first distribution transistors DBTR1 may be formed in combination with Figure 7 The pixel transistors PTR described are substantially the same, so a detailed description of the plurality of first distribution transistors DBTR1 will be omitted. In addition, since the first metal layer ML1 to the eighth metal layer ML8 and the first via holes VA1 to the eighth via holes VA8 electrically connected to the plurality of first distribution transistors DBTR1 are also combined with Figure 7 The described first to eighth metal layers ML1 to ML8 and the first to eighth vias VA1 to VA8 are substantially the same, so descriptions thereof will be omitted.

[0177] The power connection portion PCA includes a first power connection area PCAA1 of the semiconductor substrate SSUB, a first power connection electrode PCE1, and a second power connection electrode PCE2.

[0178] The first driving voltage VSS (see Figure 2 ) may be applied to the first power connection area PCAA1 of the semiconductor substrate SSUB.

[0179] The first power connection electrode PCE1 may be disposed on the ninth interlayer insulating layer INS9 and connected to the first power connection area PCAA1 of the semiconductor substrate SSUB through the first to eighth metal layers ML1 to ML8 and the first to ninth vias VA1 to VA9 .

[0180] The first power connection electrode PCE1 may include first to fourth sub-power connection electrodes SPCE1 to SPCE4. The first to fourth sub-power connection electrodes SPCE1 to SPCE4 of the first power connection electrode PCE1 may be substantially the same as the first to fourth reflective electrodes RL1 to RL4 of the reflective electrode layer RL. That is, the first sub-power connection electrode SPCE1 may correspond to the first reflective electrode RL1, the second sub-power connection electrode SPCE2 may correspond to the second reflective electrode RL2, the third sub-power connection electrode SPCE3 may correspond to the third reflective electrode RL3, and the fourth sub-power connection electrode SPCE4 may correspond to the fourth reflective electrode RL4.

[0181] The second power connection electrode PCE2 may be disposed on the eleventh interlayer insulating layer INS11. The second power connection electrode PCE2 may be connected to the first power connection electrode PCE1 through the tenth via hole VA10.

[0182] The second power connection electrode PCE2 may include substantially the same material as the first electrode AND of the light-emitting element. A portion of the top surface of the second power connection electrode PCE2 may be exposed through an opening in the pixel-defining film PDL. The second electrode CAT of the light-emitting element may extend to the power connection portion PCA and may be connected to the second power connection electrode PCE2 exposed through the pixel-defining film PDL.

[0183] The dam structure DAM may include a first dam DM1 and a second dam DM2. Each of the first dam DM1 and the second dam DM2 may have a groove shape that penetrates at least the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3. The first dam DM1 and the second dam DM2 may penetrate the pixel defining film PDL and the eleventh interlayer insulating layer INS11, respectively.

[0184] In the first dam DM1, the first inorganic encapsulating layer TFE1 may be disposed on the bottom surface of the first dam DM1, the organic encapsulating layer TFE2 may be disposed on the first inorganic encapsulating layer TFE1, and the second inorganic encapsulating layer TFE3 may be disposed on the organic encapsulating layer TFE2. The organic encapsulating layer TFE2 may be disposed to partially fill the first dam DM1. In the second dam DM2, the first inorganic encapsulating layer TFE1 may be disposed on the bottom surface of the second dam DM2, and the second inorganic encapsulating layer TFE3 may be disposed on the first inorganic encapsulating layer TFE1. The organic encapsulating layer TFE2 may not be disposed in the second dam DM2. In the display device 10, the dam structure DAM is composed of two or more dams DM1 and DM2, and the organic encapsulating layer TFE2 may be disposed in the innermost dam (e.g., the first dam DM1) to cover the innermost dam. However, the organic encapsulating layer TFE2 may not be disposed in the outermost dam (e.g., the second dam DM2) and may not cover the outermost dam. Due to the presence of the first and second dams DM1 and DM2 , the organic encapsulation layer TFE2 is prevented from flowing to the pad portion PDA to cover the pad PD. The organic encapsulation layer TFE2 is prevented from covering the pad PD, thereby preventing the pad PD from being electrically connected to the circuit board 300.

[0185] The data driver 700 may include a plurality of data transistors DTR. Since each of the plurality of data transistors DTR may be formed in conjunction with Figure 7 The pixel transistors PTR described are substantially the same, so a detailed description of the plurality of data transistors DTR will be omitted. In addition, since the first metal layer ML1 to the eighth metal layer ML8 and the first via holes VA1 to the eighth via holes VA8 electrically connected to the plurality of data transistors DTR are also combined with Figure 7 The described first to eighth metal layers ML1 to ML8 and the first to eighth vias VA1 to VA8 are substantially the same, so descriptions thereof will be omitted.

[0186] Each of the pads PD may include a pad metal layer PML. The pad metal layer PML may include a first sub-pad metal layer SPML1 and a second sub-pad metal layer SPML2. The first sub-pad metal layer SPML1 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or alloys and / or compounds including one or more of these. The second sub-pad metal layer SPML2 may be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or alloys and / or compounds including one or more of these. For example, the first sub-pad metal layer SPML1 may be made of aluminum (Al) and may have a thickness of approximately 12,000 Å. Furthermore, the second sub-pad metal layer SPML2 may be made of titanium nitride (TiN) and may have a thickness of approximately 600 Å. The thickness of the pad metal layer PML may be greater than the thickness of the reflective electrode layer RL.

[0187] A portion of the top surface of the pad metal layer PML of each pad PD may be exposed without being covered by the tenth interlayer insulating layer INS10 and / or the eleventh interlayer insulating layer INS11. The first sub-pad metal layer SPML1 may be connected to a pad via PVA9 penetrating the ninth interlayer insulating layer INS9 to be connected to the eighth metal layer ML8.

[0188] The encapsulation layer TFE may also be provided in a portion of the non-display area NDA located below the display area DAA in a plan view. While the organic encapsulation layer TFE2 of the encapsulation layer TFE is provided up to the first dam DM1, the inorganic encapsulation layers TFE1 and TFE3 of the encapsulation layer TFE may be provided up to the outside of the dam structure DAM to form an inorganic bonding region.

[0189] Figure 10 is a cross-sectional view illustrating a first electrode and a power connection electrode of a display device according to one or more embodiments.

[0190] Reference Figure 10 , the pixel defining film PDL may include a first opening OP1 overlapping the first electrode AND of the display area DAA, and a second opening OP2 overlapping the power connection electrode PCE of the non-display area NDA. Figure 10 The electrical connection electrodes PCE can be connected with Figure 9 The second power connection electrode PCE2 is substantially the same.

[0191] Each of the first electrode AND and the power connection electrode PCE may be provided on the same layer (e.g., at the same layer) and include the same material. For example, each of the first electrode AND and the power connection electrode PCE may be provided on the eleventh interlayer insulating layer INS11. They may be formed together in the same process and have substantially the same structure.

[0192] In the first opening OP1 of the pixel-defining film PDL, the second pixel-defining film PDL2 may be more recessed than the first and third pixel-defining films PDL1 and PDL3, and the third pixel-defining film PDL3 may form a tip structure TIP. Meanwhile, in the second opening OP2 of the pixel-defining film PDL, the sidewalls of the first to third pixel-defining films PDL1, PDL2, and PDL3 may be coplanar (e.g., at the same level), and the sidewalls of the second opening OP2 may form a smooth surface.

[0193] Unlike the light-emitting stack IL, the second electrode CAT may be provided throughout the entire display area DAA and may extend to the power connection portion PCA to contact the power connection electrode PCE. In the display area DAA, the second electrode CAT may be provided on the third light-emitting stack IL3 and may not be disconnected due to the tip structure TIP of the pixel-defining film PDL. However, because the light-emitting stack IL is not provided on the power connection electrode PCE, the second electrode CAT may be disconnected when the tip structure is formed in the opening of the pixel-defining film PDL.

[0194] In the display device 10, during the process of forming the openings in the pixel-defining film PDL, the openings formed in the display area DAA and the openings formed in the power connection portion PCA in the non-display area NDA can be formed by different processes. Therefore, in the display area DAA, a sharp structure can be formed in the inner sidewalls of the openings to disconnect the light-emitting stack IL between the different sub-pixels SP1, SP2, and SP3. In the non-display area NDA, the inner sidewalls of the openings can be formed smooth to prevent disconnection of the second electrode CAT.

[0195] Each of the first electrode AND and the power connection electrode PCE may be disposed on the same layer (e.g., at the same layer) and comprise substantially the same material. Due to differences in the manufacturing process, a portion of the top surface of the first electrode AND disposed in the display area DAA may be recessed. According to one or more embodiments, a first thickness TH1 of the portion of the first electrode AND overlapping the first opening OP1 may be thinner than a second thickness TH2 of an edge portion of the first electrode AND and a third thickness TH3 of the power connection electrode PCE. During the process of forming the first opening OP1, a portion of the top surface of the first electrode AND may be recessed, and the thickness of the recessed portion may be thinner than the thickness of the edge portion of the first electrode AND. Furthermore, the first thickness TH1 of the first electrode AND may be thinner than the third thickness TH3 of the power connection electrode PCE disposed on the same layer (e.g., at the same layer). The thinner portion of the first electrode AND may have an area larger than the opening of the first pixel defining film PDL1. In other words, the portion of the first electrode AND overlapping the first pixel defining film PDL1 may be partially thinner, and the first pixel defining film PDL1 may form a pointed structure on the first electrode AND.

[0196] Figure 11 is a diagram illustrating a first electrode of a display device according to one or more embodiments in more detail.

[0197] Reference Figure 11 , the first electrode AND may include a plurality of layers ANL1, ANL2, and ANL3. The first electrode AND may include a base layer ANL1, an intermediate layer ANL2, and an upper layer ANL3, and a portion of its top surface recessed while forming the opening of the pixel-defining film PDL may be the upper layer ANL3. A fourth thickness TH4 of a portion of the upper layer ANL3 of the first electrode AND overlapping the first opening OP1 of the pixel-defining film PDL may be less than a fifth thickness TH5 of an edge portion of the upper layer ANL3 of the first electrode AND.

[0198] The intermediate layer ANL2 of the first electrode AND may include a metal material with high reflectivity. In one or more embodiments, the base layer ANL1 of the first electrode AND may include Ti and / or ITO, the intermediate layer ANL2 may include Al and / or Ag, and the upper layer ANL3 may include TiN and / or ITO. The intermediate layer ANL2 may have a thickness greater than that of the base layer ANL1 and the upper layer ANL3, and may reflect light emitted from the light-emitting stack IL and serve as wiring through which electrical signals can flow smoothly. Since a portion of the top surface of the first electrode AND is recessed, the thickness of the upper layer ANL3 may be reduced, and the reflectivity of light emitted from the light-emitting stack IL may be increased.

[0199] In the display device 10 according to one or more embodiments, the sidewall shapes of the openings OP1 and OP2 of the pixel-defining film PDL can differ between the display area DAA and the non-display area NDA. The openings OP1 and OP2 of the pixel-defining film PDL can be formed concurrently (e.g., simultaneously), but can have different sidewall shapes through a partial patterning process. Therefore, in the display area DAA, the light-emitting stack IL between the sub-pixels SP1, SP2, and SP3 can be disconnected, while improving brightness due to the increased light reflectivity of the first electrode AND. Furthermore, in the non-display area NDA, disconnection of the second electrode CAT can be prevented.

[0200] Hereinafter, a manufacturing process of the pixel defining layer PDL of the display device 10 will be described with reference to other drawings.

[0201] Figures 12 to 18 is a diagram partially illustrating a manufacturing process of a display device according to one or more embodiments.

[0202] Reference Figure 12 , forming the first electrode AND and the power connection electrode PCE, and forming the first pixel definition film PDL1, the second pixel definition film PDL2 and the third pixel definition film PDL3 to be sequentially stacked on the first electrode AND and the power connection electrode PCE. Each of the first pixel definition film PDL1, the second pixel definition film PDL2 and the third pixel definition film PDL3 may include silicon oxide (SiO x ) and / or silicon nitride (SiN x ) type inorganic insulating material, and a structure in which different materials are alternately stacked may be formed. For example, the first pixel defining film PDL1 and the third pixel defining film PDL3 may include silicon oxide (SiO x ) type inorganic insulating material, and the second pixel definition film PDL2 may include silicon nitride (SiN x ) type inorganic insulating material. The pixel definition film PDL may have SiO x / SiN x / SiO x However, the present disclosure is not limited thereto, and the materials of the alternately stacked inorganic insulating materials may be opposite. In this case, the pixel definition film PDL may have SiN x / SiO x / SiN x stacking structure.

[0203] Reference Figure 13 and Figure 14A first photoresist PR1 is formed on the third pixel-defining film PDL3, excluding a portion partially overlapping the first electrode AND. A first etching process (first etching) is then performed to etch a portion of the second pixel-defining film PDL2 and the third pixel-defining film PDL3. The first etching process (first etching) can be performed as a dry etching process and / or a wet etching process. During the first etching process (first etching), the second pixel-defining film PDL2 exposed by the first photoresist PR1 may not be completely removed, and a portion of the second pixel-defining film PDL2 may remain.

[0204] Reference Figure 15 and Figure 16 , a second etching process (second etching) is performed to remove the remaining portion of the second pixel defining film PDL2 exposed by the first photoresist PR1, and the first photoresist PR1 is removed. The second etching process (second etching) can be performed as a wet etching process using an etchant having a selectivity for etching the second pixel defining film PDL2 that is faster than the selectivity for etching the third pixel defining film PDL3. For example, when the second pixel defining film PDL2 includes silicon nitride (SiN x ) type inorganic insulating material and the third pixel definition film PDL3 includes silicon oxide (SiO x ) type inorganic insulating material, the etchant of the second etching process (second etching) may be a phosphoric acid (H3PO4) type etchant. The present disclosure is not limited thereto, and as described above, when the second pixel definition film PDL2 includes silicon oxide (SiO x ) type inorganic insulating material, and the third pixel definition film PDL3 includes silicon nitride (SiN x When using inorganic insulating materials such as α-D-type ...

[0205] The accompanying drawings illustrate the second etching process (second etching) being performed while the first photoresist PR1 remains, but the present disclosure is not limited thereto. To prevent peeling of the first photoresist PR1, the second etching process (second etching) may be performed at a high temperature after the first photoresist PR1 is completely removed. In this case, the etching process is performed across the entire third pixel-defining film PDL3. However, depending on the etching selectivity of the etchant, the third pixel-defining film PDL3 covering the power connection electrode PCE may be substantially unetched.

[0206] Reference Figure 17 and Figure 18 A second photoresist PR2 is formed on the third pixel-defining film PDL3, and a third etching process (third etching) is performed to etch a portion of the pixel-defining film PDL and the first electrode AND. The second photoresist PR2 may be provided in an area other than the portion overlapping the first electrode AND and the power connection electrode PCE, and may penetrate the pixel-defining film PDL in the third etching process (third etching) to form the first opening OP1 and the second opening OP2. In one or more embodiments, the third etching process (third etching) may be performed as a dry etching process and / or a wet etching process.

[0207] Since the third etching process (third etching) is performed on the third pixel defining film PDL3 on the power connection electrode PCE, the first to third pixel defining films PDL1, PDL2, and PDL3 may be etched concurrently (e.g., simultaneously). The sidewalls of the second opening OP2 formed by concurrently (e.g., simultaneously) etching the first to third pixel defining films PDL1, PDL2, and PDL3 may have a smooth surface, and the top surface of the power connection electrode PCE may be exposed.

[0208] Because a third etching process (third etching) is performed on the first electrode AND with the second pixel-defining film PDL2 recessed inward, the remaining first pixel-defining film PDL1 can be penetrated to form a first opening OP1. Furthermore, because the etching process is performed for a sufficiently long period of time to penetrate the first pixel-defining film on the power connection electrode PCE to the third pixel-defining films PDL1, PDL2, and PDL3, a portion of the top surface of the first electrode AND can be etched. In this process, in the first electrode AND, the etching rate of the upper layer of the first electrode AND can be faster than the etching rate of the first pixel-defining film PDL1, and the thickness of the first electrode AND can be thinner in an area larger than the area penetrated through the first pixel-defining film PDL1. Therefore, the first pixel-defining film PDL1 can also form a pointed structure on the first electrode AND.

[0209] Next, in one or more embodiments, a light emitting stack IL and a second electrode CAT may be formed on the pixel definition film PDL to form a plurality of light emitting elements in the display area DAA. The second electrode CAT of the light emitting element may be connected to the power connection electrode PCE at the power connection portion PCA.

[0210] In the display device 10 according to one or more embodiments, the pixel-defining film PDL may be patterned concurrently (e.g., simultaneously) in the display area DAA and the non-display area NDA during a manufacturing process, and the shapes of the openings OP1 and OP2 formed in each area may vary. Therefore, although the openings OP1 and OP2 of the pixel-defining film PDL are concurrently (e.g., simultaneously) formed without an additional mask, they may perform different functions depending on their positions.

[0211] Figure 19 is a cross-sectional view illustrating a first electrode and a power connection electrode of a display device according to one or more embodiments.

[0212] Reference Figure 19 The display device 10_a may have a five-layer stacked structure in which the pixel defining film PDL further includes a fourth pixel defining film PDL4 and a fifth pixel defining film PDL5. In this case, each of the first to fifth pixel defining films PDL1, PDL2, PDL3, PDL4, and PDL5 may include silicon oxide (SiO x ) and / or silicon nitride (SiN x ) type inorganic insulating material, and a structure in which layers of different materials are alternately stacked can be formed. The first pixel defining film PDL1, the third pixel defining film PDL3, and the fifth pixel defining film PDL5 can include the same material, and the second pixel defining film PDL2 and the fourth pixel defining film PDL4 can also include the same material. For example, the pixel defining film PDL can have SiO x / SiN x / SiO x / SiN x / SiO x stacked structure or SiN x / SiO x / SiN x / SiO x / SiN x Since the pixel-defining film PDL has a structure in which a greater number of layers are stacked, a double-tip structure can be formed in the first opening OP1 of the pixel-defining film PDL. On the other hand, since the lateral sides of the five pixel-defining films PDL1, PDL2, PDL3, PDL4, and PDL5 are formed to be located on the same plane (e.g., at the same level), the second opening OP2 can have a smooth surface.

[0213] Figure 20 is a perspective view illustrating a head-mounted display device according to one or more embodiments. Figure 21 It shows Figure 20 An exploded perspective view of an example of a head-mounted display device.

[0214] Reference Figure 20 and Figure 21 According to one or more embodiments, the head-mounted display device 1000 includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head-mounted strap 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, a control circuit board 1600, and a connector.

[0215] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Figure 1 The display devices 10 described are substantially the same, so descriptions of the first display device 10_1 and the second display device 10_2 will be omitted.

[0216] The first optical member 1510 may be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical member 1520 may be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0217] The middle frame 1400 may be disposed between the first display device 10_1 and the control circuit board 1600 and between the second display device 10_2 and the control circuit board 1600. The middle frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0218] The control circuit board 1600 may be provided between the middle frame 1400 and the display device housing 1100. The control circuit board 1600 may be connected to the first display device 10_1 and the second display device 10_2 through a connector. The control circuit board 1600 may convert an image source input from the outside into digital video data DATA (see FIG. Figure 2 ), and the digital video data DATA may be transmitted to the first display device 10_1 and the second display device 10_2 through the connector.

[0219] The control circuit board 1600 may transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and may transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. Alternatively, the control circuit board 1600 may transmit the same digital video data DATA to both the first display device 10_1 and the second display device 10_2.

[0220] The display device housing 1100 is used to accommodate the first display device 10_1, the second display device 10_2, the intermediate frame 1400, the first optical member 1510, the second optical member 1520, the control circuit board 1600, and the connector. The housing cover 1200 is provided to cover the surface of an opening of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for the user's left eye and a second eyepiece 1220 for the user's right eye. Figure 20 and Figure 21 It is shown that the first eyepiece 1210 and the second eyepiece 1220 are separately provided, but the present disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be combined into one.

[0221] The first eyepiece 1210 may be aligned with the first display device 10_1 and the first optical member 1510, and the second eyepiece 1220 may be aligned with the second display device 10_2 and the second optical member 1520. Therefore, the user can view the image of the first display device 10_1 magnified into a virtual image by the first optical member 1510 through the first eyepiece 1210, and can view the image of the second display device 10_2 magnified into a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0222] The head-mounted display device 1000 is fixed to the user's head so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are respectively placed on the user's left eye and right eye. Figure 22 The eyeglass frame shown in FIG. 1 is not a headband 1300 .

[0223] The head-mounted display device 1000 may also include a battery for supplying power, an external memory slot for accommodating an external memory, an external connection port for receiving an image source, and a wireless communication module. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, and / or a Bluetooth module.

[0224] Figure 22 is a perspective view illustrating a head-mounted display device according to one or more embodiments.

[0225] Reference Figure 22The head-mounted display device 1000_1 according to one or more embodiments may be a glasses-type display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. The head-mounted display device 1000_1 according to one or more embodiments may include a display device 10_3, a left-eye lens 1010, a right-eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical member 1060, an optical path changing member 1070, and a display device housing 1200_1.

[0226] The display device housing 1200_1 may house the display device 10_3, the optical member 1060, and the optical path changing member 1070. The image displayed on the display device 10_3 may be magnified by the optical member 1060, and the optical path may be changed by the optical path changing member 1070 to provide the image to the user's right eye through the right-eye lens 1020. As a result, the user may view, through the right eye, an augmented reality image in which the virtual image displayed on the display device 10_3 and the real image viewed through the right-eye lens 1020 are combined.

[0227] Figure 22 The display device housing 1200_1 is shown as being disposed at the right end of the support frame 1030, but the present disclosure is not limited thereto. For example, the display device housing 1200_1 may be disposed at the left end of the support frame 1030, in which case the image of the display device 10_3 may be provided to the user's left eye. Alternatively, the display device housing 1200_1 may be disposed at both the left and right ends of the support frame 1030, in which case the user may view the image displayed on the display device 10_3 with both the left and right eyes.

[0228] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the embodiments without departing substantially from the principles, spirit and scope of the present disclosure. Therefore, the embodiments of the present disclosure are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A display device, comprising: a substrate comprising a display area and a non-display area surrounding the display area; a plurality of first electrodes spaced apart from each other on the substrate in the display area; a power connection electrode located on the substrate in the non-display area; a pixel defining film in the display area and the non-display area, and including a plurality of first openings overlapping the first electrode and a second opening overlapping the power connection electrode; a plurality of light-emitting stacks located on the first electrode in the display area; as well as A second electrode is provided on the pixel defining film and the light emitting stack. The pixel defining film includes a first pixel defining film, a second pixel defining film on the first pixel defining film, and a third pixel defining film on the second pixel defining film, and In which, in the first opening, the second pixel defining film is more recessed inward than the third pixel defining film, and in the second opening, the lateral side of the first pixel defining film, the lateral side of the second pixel defining film and the lateral side of the third pixel defining film are in the same plane.

2. The display device according to claim 1, wherein A thickness of a portion of the first electrode overlapping the first opening is smaller than a thickness of a portion of the power connection electrode overlapping the second opening.

3. The display device according to claim 1, wherein A first thickness of a portion of the first electrode overlapping the first opening is smaller than a second thickness of an edge portion of the first electrode.

4. The display device according to claim 3, wherein An area of ​​the portion of the first electrode having the first thickness is greater than an area of ​​a portion of the first electrode penetrated by the first opening of the first pixel defining film, and wherein the first pixel defining film includes a tip structure on the first electrode.

5. The display device according to claim 3, wherein The first electrode includes a base layer, an intermediate layer on the base layer, and an upper layer on the intermediate layer, and wherein a fourth thickness of a portion of the upper layer overlapping the first opening is smaller than a fifth thickness of an edge portion of the upper layer. The display device according to claim 5 , wherein: The base layer includes Ti and / or ITO, the intermediate layer includes Al and / or Ag, and the upper layer includes TiN and / or ITO.

7. The display device according to claim 1, further comprising an insulating layer on the substrate, in, The first electrode and the power connection electrode are directly on the insulating layer.

8. The display device according to claim 1, wherein The pixel defining film also includes a fourth pixel defining film on the third pixel defining film, and a fifth pixel defining film on the fourth pixel defining film, and wherein, in the first opening, the fourth pixel defining film is more recessed inward than the fifth pixel defining film.

9. The display device according to claim 1, wherein A sidewall of the second opening of the pixel defining film has a smooth surface, and the second electrode covers the second opening and is connected to the power connection electrode.

10. The display device according to claim 1, wherein The light emitting stack includes a first light emitting stack, a second light emitting stack on the first light emitting stack, and a third light emitting stack on the second light emitting stack, and The first light emitting stack and the second light emitting stack are in the first opening, and the first light emitting stack and the second light emitting stack disposed in the plurality of first openings that are adjacent to and different from each other are not connected to each other.

11. The display device according to claim 1, wherein Each of the first pixel defining layer, the second pixel defining layer, and the third pixel defining layer includes a silicon oxide or silicon nitride-based inorganic insulating material, and the pixel defining layer includes alternately stacked layers including different materials.

12. The display device according to claim 1 , further comprising a plurality of dam structures in the non-display area and an encapsulation layer on the second electrode, the plurality of dam structures surrounding the display area, in, Each of the plurality of dam structures has a groove shape penetrating the pixel defining film.

13. The display device according to claim 12, wherein: The encapsulation layer includes a first inorganic encapsulation layer on the second electrode and beyond the multiple dam structures, an organic encapsulation layer on the first inorganic encapsulation layer but not covering the outermost dam structure among the multiple dam structures, and a second inorganic encapsulation layer on the organic encapsulation layer and the first inorganic encapsulation layer.

14. The display device according to claim 12, further comprising: a plurality of color filters on the encapsulation layer and each overlapping the first electrode; a plurality of lenses on the color filter and in the display area; and a covering layer on the lens.

15. A method for manufacturing a display device, the method comprising: forming a first electrode and a power connection electrode on a substrate, and forming a first pixel definition layer, a second pixel definition layer, and a third pixel definition layer covering the first electrode and the power connection electrode; performing a first etching process to partially etch portions of the second pixel defining layer and the third pixel defining layer overlapping the first electrode; performing a second etching process to etch the portion of the second pixel defining film remaining in the first etching process and form a tip structure in which a lateral side of the third pixel defining film protrudes beyond the second pixel defining film; as well as performing a third etching process of etching the first pixel defining film, the second pixel defining film, and the third pixel defining film to form a first opening exposing the top surface of the first electrode and a second opening exposing the top surface of the power connection electrode, The thickness of a portion of the first electrode overlapping the first opening is smaller than the thickness of a portion of the power connection electrode overlapping the second opening.

16. The method according to claim 15, wherein The tip structures of the first pixel defining film and the third pixel defining film are located in the first opening, and the lateral sides of the first pixel defining film, the lateral sides of the second pixel defining film, and the lateral sides of the third pixel defining film are located in the same plane in the second opening.

17. The method according to claim 15, wherein: The first electrode includes a base layer, an intermediate layer on the base layer, and an upper layer on the intermediate layer, and a thickness of a portion of the upper layer overlapping the first opening is smaller than a thickness of an edge portion of the upper layer.

18. The method according to claim 15, wherein The second etching process is performed as a wet etching process.

19. The method according to claim 15, wherein In the third etching process, while etching the first pixel defining film, the second pixel defining film and the third pixel defining film overlapping the power connection electrode, a portion of the first electrode and the first pixel defining film overlapping the first electrode are etched.

20. A head-mounted display device, comprising: a frame mounted on a user's body and corresponding to the user's left and right eyes; a plurality of display devices in the frame; as well as an eyepiece, on each of said plurality of display devices, Wherein, the display device includes: a substrate comprising a display area and a non-display area surrounding the display area; a plurality of first electrodes spaced apart from each other on the substrate in the display area; a power connection electrode located on the substrate in the non-display area; a pixel defining film in the display area and the non-display area, and including a plurality of first openings overlapping the first electrode and a second opening overlapping the power connection electrode; a plurality of light-emitting stacks located on the first electrode in the display area; and A second electrode is provided on the pixel defining film and the light emitting stack. The pixel defining film includes a first pixel defining film, a second pixel defining film on the first pixel defining film, and a third pixel defining film on the second pixel defining film. wherein, in the first opening, the second pixel defining film is more recessed inward than the third pixel defining film, and in the second opening, the lateral sides of the first pixel defining film, the lateral sides of the second pixel defining film, and the lateral sides of the third pixel defining film are in the same plane, and The thickness of a portion of the first electrode overlapping the first opening is smaller than the thickness of a portion of the power connection electrode overlapping the second opening.

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