Display device

Abstract

Disclosed is a display device including: a substrate including a non-display area surrounding a display area; a plurality of signal lines on the display area of the substrate; and a plurality of link wirings electrically connected to the signal lines and on a link area of the non-display area of the substrate, the plurality of link wirings including intersection points at which adjacent link wirings are arranged to intersect each other.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] Display devices are used in various electronic devices such as televisions (TVs), smartphones, laptops, and tablet computers. For this reason, research on developing thinner, lighter, and lower-power-consuming display devices continues.

[0003] Examples of the display device may include a liquid crystal display device (LCD), a field emission display device (FED), and an organic light emitting display device (OLED). Summary of the Invention

[0004] An object of the solution according to an embodiment of the present disclosure is to provide a display device having a dual link wiring structure, in which a plurality of link wirings are provided in different layers so that the plurality of link wirings can be provided in a limited bezel area.

[0005] Furthermore, an object of an embodiment according to the present disclosure is to provide a display device in which an electric field generated between link wirings adjacent to each other in a dual link wiring structure can be reduced to prevent generation of an unnecessary DC voltage, thereby preventing a flicker phenomenon of an image.

[0006] The purpose according to the present disclosure is not limited to the purpose mentioned above. Other purposes and advantages not mentioned according to the present disclosure can be understood based on the following description, and can be more clearly understood based on the embodiments according to the present disclosure. In addition, it will be easily understood that the means described in the present disclosure or their combination can be used to achieve the purposes and advantages according to the present disclosure.

[0007] To achieve the above purpose, in one embodiment, a display device includes: a substrate including a display area and a non-display area surrounding the display area; a plurality of signal lines on the display area of ​​the substrate; and a plurality of link wirings electrically connected to the plurality of signal lines, the plurality of link wirings being on the link area of ​​the non-display area of ​​the substrate, wherein the plurality of link wirings are arranged in different layers, and in a plan view of the display device, a pair of link wirings adjacent to each other among the plurality of link wirings intersect each other at an intersection point.

[0008] In one embodiment, a display device includes: a substrate including a display area, a non-display area surrounding the display area, a link area in the non-display area, and a pad area in the link area; a plurality of signal lines on the display area of ​​the substrate; and a plurality of link wirings on the link area, the plurality of link wirings being electrically connected to the plurality of signal lines, wherein, in a plan view of the display device, a pair of link wirings adjacent to each other in the link area intersect with each other at a first point closer to the display area than the pad area, and intersect with each other at a second point closer to the pad area than the display area in the plan view.

[0009] According to an embodiment of the present disclosure, due to the dual-link wiring structure, the design of a narrow bezel area can be facilitated, so that a display device having high resolution and operating in a VRR (Variable Refresh Rate) mode can be realized.

[0010] According to embodiments of the present disclosure, the electric field generated between adjacent link wirings in a dual-link wiring structure can be reduced, thereby preventing the generation of unnecessary DC voltage and thereby preventing image flickering below the bezel area. Consequently, a display device that can operate at a low power level and thus has reduced power consumption can be realized.

[0011] Effects of the present disclosure are not limited to the above-mentioned effects, but other effects not mentioned will be clearly understood by those skilled in the art from the following description.

[0012] In addition to the above effects, specific effects of the present disclosure will be described together with specific details for implementing the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a diagram illustrating a schematic configuration of a display device according to an embodiment of the present disclosure.

[0014] Figure 2 is a plan view of a display panel according to some embodiments of the present disclosure.

[0015] Figure 3 According to the embodiment of the present disclosure Figure 2 An enlarged plan view of area 3 in FIG.

[0016] Figure 4 According to the embodiment of the present disclosure Figure 2 An enlarged plan view of area 4 in FIG.

[0017] Figure 5 According to the embodiment of the present disclosure Figure 4 A cross-sectional view taken along line 5-5 in FIG.

[0018] Figure 6 is a cross-sectional view illustrating electric field generation of a dual link wiring according to an embodiment of the present disclosure.

[0019] Figure 7 According to the embodiment of the present disclosure Figure 2 An enlarged plan view of area 7 in FIG.

[0020] Figure 8 According to the embodiment of the present disclosure Figure 2 An enlarged plan view of area 8 in FIG.

[0021] Figure 9 According to the embodiment of the present disclosure Figure 8 A cross-sectional view taken along line 9-9 in FIG.

[0022] Figure 10 is a graph of measured flicker according to an example of the present disclosure. DETAILED DESCRIPTION

[0023] The advantages and features of the present disclosure and the methods for achieving the advantages and features will be described later with reference to the accompanying drawings. Figure 1 The embodiments described in detail below will become apparent. However, the present disclosure is not limited to the embodiments disclosed below, but can be implemented in a variety of different forms. Therefore, these embodiments are set forth only to complete the present disclosure and to fully inform those of ordinary skill in the art of the present disclosure of the scope of the present disclosure.

[0024] For simplicity and clarity of explanation, the elements in the accompanying drawings are not necessarily drawn to scale. The same reference numerals in different figures represent the same or similar elements and therefore perform similar functions. In addition, in order to simplify the description, the description and details of well-known steps and elements are omitted. In addition, in the following detailed description of the present disclosure, many specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be understood that the present disclosure can be practiced without these specific details. In other cases, well-known methods, processes, components and circuits are not described in detail to avoid unnecessarily blurring the various aspects of the present disclosure. Examples of various embodiments are further shown and described below. It will be understood that the description herein is not intended to limit the claims to the specific embodiments described. On the contrary, the description herein is intended to cover alternatives, modifications and equivalents as may be included in the subject matter and scope of the present disclosure as defined by the appended claims.

[0025] The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings illustrating the embodiments of the present disclosure are illustrative, and the present disclosure is not limited thereto.

[0026] The terms used herein are only intended to describe the purpose of specific embodiments, and are not intended to limit the present disclosure. As used herein, the singular constitutes "one" and "an" and is also intended to include plural constitutes, unless the context clearly indicates otherwise. It will also be understood that the terms "comprise", "comprises", "comprising" and "comprising" specify the existence of the features, integers, operations, elements and / or parts when used in this specification, but do not exclude the existence or addition of one or more other features, integers, operations, elements, parts and / or parts thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one" can modify the entire element list before the element list, and the individual elements in the list cannot be modified. When explaining numerical value, even if there is no clear description thereof, error or tolerance may also occur therein.

[0027] Furthermore, it will be understood that when a first element or layer is referred to as being "on" a second element or layer, the first element can be directly disposed on the second element, or can be indirectly disposed on the second element with a third element or layer disposed between the first and second elements or layers. It will be understood that when an element or layer is referred to as being "connected to" or "coupled to" another element or layer, the element or layer can be directly connected to or coupled to the other element or layer, or one or more intervening elements or layers can be present. It will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers can also be present.

[0028] Furthermore, as used herein, when a layer, film, region, plate, etc. is disposed “on” or “on top of” another layer, film, region, plate, etc., the former may be in direct contact with the latter, or another layer, film, region, plate, etc. may be disposed between the former and the latter. As used herein, when a layer, film, region, plate, etc. is disposed directly “on” or “on top of” another layer, film, region, plate, etc., the former is in direct contact with the latter, and no other layer, film, region, plate, etc. is disposed between the former and the latter. Furthermore, as used herein, when a layer, film, region, plate, etc. is disposed “below” or “beneath” another layer, film, region, plate, etc., the former may be in direct contact with the latter, or another layer, film, region, plate, etc. may be disposed between the former and the latter. As used herein, when a layer, film, region, plate, etc. is disposed directly “below” or “beneath” another layer, film, region, plate, etc., the former is in direct contact with the latter, and no other layer, film, region, plate, etc. is disposed between the former and the latter.

[0029] In the description of a temporal relationship, for example, a temporal precedence relationship between two events such as "after", "subsequently", "before", etc., unless "directly after", "directly after", or "directly before" is not indicated, another event may occur between the two events.

[0030] When a certain embodiment can be implemented differently, the function or operation specified in a specific block can occur in an order different from the order specified in the flow chart. For example, two consecutive blocks can actually be executed substantially simultaneously, or the two blocks can be executed in reverse order according to the functions or operations involved.

[0031] It will be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or time periods, these elements, components, regions, layers, and / or time periods should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or time period. Therefore, a first element, component, region, layer, or portion as described below may be referred to as a second element, component, region, layer, or time period without departing from the spirit and scope of the present disclosure.

[0032] The features of the various embodiments of the present disclosure may be combined with each other in part or in whole, and may be technically related to each other or operate with each other. The embodiments may be implemented independently of each other, and may be implemented together in a related relationship.

[0033] When interpreting numerical values, unless there is a separate explicit description, the value is interpreted as including the error range.

[0034] It will be understood that when an element or layer is referred to as being “connected to” or “connected to” another element or layer, it can be directly on, directly connected to, or directly connected to the other element or layer, or one or more intervening elements or layers may be present. Additionally, it will be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0035] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0036] As used herein, "embodiment," "example," "aspect," etc. should not be construed to render any aspect or design described preferred or advantageous over other aspects or designs.

[0037] Furthermore, the term "or" is intended to mean an inclusive or, not an exclusive or. That is, unless stated otherwise or clear from the context, the statement "x employs a or b" means any of the natural inclusive permutations.

[0038] The terms used in the following description have been selected to be general and commonly used in the relevant technical fields. However, other terms may exist in addition to these terms due to the development and / or changes of technology, conventions, preferences of technicians, etc. Therefore, the terms used in the following description should not be understood as limiting the technical ideas, but should be understood as examples of terms used to illustrate the embodiments.

[0039] In addition, in specific cases, the terms may be arbitrarily selected by the applicant, and in this case, their detailed meanings will be described in the corresponding description paragraphs. Therefore, the terms used in the following description should be understood not only based on the names of the terms, but also based on the meanings of the terms and the content throughout the specific embodiments.

[0040] In describing a signal flow, for example, when a signal is delivered from node A to node B, this may include a case where the signal is transmitted from node A to node B via another node unless the phrases "immediately thereafter" or "directly" are used.

[0041] Hereinafter, a display device according to aspects of the present disclosure will be described with reference to the accompanying drawings.

[0042] Figure 1 is a diagram illustrating a schematic configuration of a display device according to an embodiment of the present disclosure. Figure 2 is a plan view of a display panel according to some embodiments of the present disclosure. Figure 3 According to the embodiment of the present disclosure Figure 2 An enlarged plan view of area 3 in FIG. Figure 4 According to the embodiment of the present disclosure Figure 2 An enlarged plan view of area 4 in FIG.

[0043] Reference Figure 1 and Figure 2 The display device 10 may include: a display panel 20 including a display area AA and a non-display area NAA surrounding the display area AA; and panel drivers 30 , 40 and 50 for driving the display panel 20 .

[0044] The panel drivers 30 , 40 and 50 may include a gate driver 30 , a data driver 40 and a timing controller 50 .

[0045] A plurality of signal lines GL and DL may be provided in the display panel 20. The signal lines GL and DL may include a plurality of gate lines GL and a plurality of data lines DL. The plurality of gate lines GL may transmit scan signals from the gate driver 30 to the display area AA, and the plurality of data lines DL may transmit data signals from the data driver 40 to the display area AA.

[0046] The display area AA may include a plurality of pixels P, each of which is disposed at the intersection of a plurality of gate lines GL and a plurality of data lines DL and arranged in a matrix. The plurality of pixels P arranged in the display area AA may operate in an active matrix manner. Each of the plurality of pixels P may include a thin film transistor TFT disposed at each intersection of the plurality of data lines DL and the plurality of gate lines GL, and a pixel electrode electrically connected to the thin film transistor TFT.

[0047] The display area AA can use each of the multiple pixels P to emit light of a wavelength region corresponding to one of the multiple different colors. In this regard, the multiple colors may include red, green, and blue. Alternatively, the multiple colors may also include white. For example, each of the multiple pixels P operating in an active matrix manner may include a liquid crystal cell. However, the embodiments of the present disclosure are not limited thereto. In another example, each of the multiple pixels may include an organic light emitting diode (OLED).

[0048] The timing controller 50 may control the operation timing of each of the gate driver 30 and the data driver 40 .

[0049] For example, the timing controller 50 may transmit a data control signal 70 for controlling the operation timing of the data driver 40 and a gate control signal 80 for controlling the operation timing of the gate driver 30 based on various timing signals received from an external source.

[0050] The gate driver 30 can sequentially supply scan signals to the plurality of gate lines GL during one frame period for image display based on the gate control signal 80 to control the operation timing of each of the plurality of pixels. The gate driver 30 can be located on only one side of the display panel 20, or on each of two opposite sides of the display panel 20.

[0051] The data driver 40 may convert image data received from the timing controller 50 into analog data voltages based on the data control signal 70. The data driver 40 may supply a data voltage to each data line DL according to a timing at which a scan signal is applied to each pixel corresponding to each gate line GL.

[0052] The timing controller 50 may be mounted on a printed circuit board or a flexible printed circuit board and may be electrically connected to the gate driver 30 and the data driver 40 .

[0053] Reference Figures 1 to 4 , the display panel 20 according to an embodiment of the present disclosure may include a substrate 100 including a display area AA and a non-display area NAA surrounding the display area AA.

[0054] A plurality of pixels P may be provided on a display area AA of the substrate. Video or images may be displayed in the display area AA via the plurality of pixels P. In the non-display area NAA of the substrate, a plurality of drivers may be provided to drive the plurality of pixels P provided in the display area AA. For example, the drivers may include, but are not limited to, a gate driver 30, a data driver 40, and a timing controller 50.

[0055] A plurality of data lines DL and a plurality of gate lines GL may be provided on the display area AA of the base substrate 100. The plurality of data lines DL may be arranged to intersect with the plurality of gate lines GL. Each pixel P region may be defined by each data line DL and each gate line GL intersecting with each other. The pixel P may be electrically connected to the gate line GL and the data line DL. The plurality of pixels P may be provided on the display area AA of the base substrate 100 and may be arranged in a matrix manner (M*N, where M and N are natural numbers). Therefore, the plurality of gate lines GL and the plurality of data lines DL electrically connected to the pixel P may be arranged in a matrix form.

[0056] The link region 215 and the pad region 210 may be located on the non-display region NAA of the base substrate 100. The pad region 210 may be located on one edge of the non-display region NAA and may include a plurality of link pads 305P2 (see FIG. Figure 4 ). For example, the pad area 210 may be provided at a lower edge of the non-display area NAA. The link area 215 may overlap with the pad area 210. The non-display area NAA may be referred to as a bezel area.

[0057] The plurality of gate lines GL extending from the display area AA to the non-display area NAA may be connected to the plurality of electrode pads 305P1 (see FIG. Figure 3Each of the plurality of gate lines GL may be electrically connected to each of the plurality of link wirings LL disposed in the non-display area NAA via each of the first connection electrodes 300a.

[0058] Each of the plurality of link wirings LL can extend toward the pad area 210 of the non-display area NAA so as to be connected to each link pad 305P2. In other words, one end of the gate line GL can be connected to the electrode pad 305P1 via the first connection electrode 300a, and the other end of the gate line GL can be connected to the link pad 305P2 via the second connection electrode 300b. In the present disclosure, the gate line GL is described by way of example. The principles applied to the gate line can be applied to the data line DL in the same manner. For example, one end of the data line DL can be connected to the electrode pad 305P1, and the other end of the data line DL can be connected to the link pad 305P2.

[0059] A plurality of link pads 305P2 (see FIG. Figure 4 ) can be attached to the flexible circuit board 200 including the integrated circuit 205 and electrically connected to the printed circuit board. The printed circuit board may include an integrated circuit chip and may provide various power and various signals to the display area AA to drive the pixels P arranged on the display area AA. For example, the various signals may include a high potential voltage, a low potential voltage, a scan signal, and a data signal. The flexible circuit board 200 can be implemented as a chip on film (COF), which includes a circuit film on which an integrated circuit chip IC is mounted. However, the embodiments of the present disclosure are not limited thereto. For example, the integrated circuit chip IC can be mounted on a TCP (tape carrier package) and bonded to the edge of the display panel 20 in a TAB (tape automated bonding) process.

[0060] In order to provide a user with a display area AA as wide as possible in a display device of limited size, the area size of the non-display area NAA (ie, the frame area) is reduced. A display device having high resolution and operating in VRR (variable refresh rate) mode is required.

[0061] Display devices with high resolution and operating in VRR (variable refresh rate) mode require a larger number of signal lines. Consequently, the number of signal lines and the corresponding link wiring are also increasing. However, as the number of link wiring increases, various problems also arise. For example, when the number of link wiring increases and the border area decreases, it becomes difficult to place multiple link wirings in the same layer.

[0062] Therefore, in order to place a plurality of link wirings in a narrow bezel area, the display device according to an embodiment of the present disclosure may include a dual link wiring structure.

[0063] Figure 5 According to the embodiment of the present disclosure Figure 4 A cross-sectional view taken along line 5-5 in FIG. Figure 6 is a cross-sectional view illustrating electric field generation of a dual link wiring according to an embodiment of the present disclosure.

[0064] Reference Figures 3 to 5 The dual-link wiring structure may be a structure in which adjacent link wirings LL1 and LL2 are formed in different layers. In one embodiment, in a plan view of the display device, a first link wiring LL1 is adjacent to a second link wiring LL2, with no intermediate link wiring LL between the first link wiring LL1 and the second link wiring LL2. The adjacent link wirings LL1 and LL2 may include an odd-numbered first link wiring LL1 and an even-numbered second link wiring LL2.

[0065] For example, odd-numbered first link wirings LL1 may be provided in a first layer, and even-numbered second link wirings LL2 adjacent to the odd-numbered first link wirings LL1 may be provided in a second layer, which is a layer different from the first layer. In one embodiment, the first layer is closer to the substrate than the second layer.

[0066] Reference Figure 3 and Figure 4 In the first region adjacent to the display area AA of the link region 215, the odd-numbered first link wirings LL1 may be electrically connected to the gate lines GL, and the even-numbered second link wirings LL2 may be electrically connected to the data lines DL. However, embodiments of the present disclosure are not limited thereto. The odd-numbered first link wirings LL1 and the even-numbered second link wirings LL2 arranged in the first region may extend to the pad region 210 of the link region 215.

[0067] The dual link wiring structure can reduce the width between the adjacent first link wiring LL1 and second link wiring LL2 , thereby achieving a narrow or zero border by reducing the area occupied by the first link wiring LL1 and the second link wiring LL2 in the border area.

[0068] The odd-numbered first link wirings LL1 may be located in a first layer and on the base substrate 100, and may be made of the same material as the gate electrode GE and formed in the same process as the gate electrode GE. The even-numbered second link wirings LL2 may be located in a second layer different from the first layer, and may be made of the same material as the source / drain electrode SD and formed in the same process as the source / drain electrode SD. A gate insulating layer 113 may be provided between the odd-numbered first link wirings LL1 and the even-numbered second link wirings LL2.

[0069] Reference Figure 6 , according to an embodiment of the present disclosure, the signal A1 of the first polarity may be transmitted to the odd-numbered first link wiring LL1, and the signal B1 of the second polarity may be transmitted to the even-numbered second link wiring LL2. The first polarity and the second polarity may be opposite to each other. For example, the first polarity may be positive polarity (+), and the second polarity may be negative polarity (-). Therefore, the signal of the first polarity may be a positive polarity signal, and the signal of the second polarity may be a negative polarity signal. In one example, the signal of the first polarity may be a positive polarity (+) data voltage, and the signal of the second polarity may be a negative polarity (-) data voltage. Alternatively, the second polarity may be a positive polarity (+), and the first polarity may be a negative polarity (-). In this case, the signal of the second polarity may be a positive polarity (+) data voltage, and the signal of the first polarity may be a negative polarity (-) data voltage.

[0070] A horizontal electric field EF may be generated between the odd-numbered first link wirings LL1 and the even-numbered second link wirings LL2. A signal A1 of a first polarity is transmitted to the odd-numbered first link wirings LL1, and a signal B1 of a second polarity opposite to the first polarity is transmitted to the even-numbered second link wirings LL2 adjacent to the odd-numbered first link wirings LL1. The electric field EF may increase as the distance between the first link wirings LL1 and the second link wirings LL2 becomes smaller.

[0071] When an electric field is generated, the ion component I may be trapped between the first link wiring LL1 and the second link wiring LL2. As the electric field is generated between each of the plurality of odd-numbered first link wirings LL1 and each of the plurality of even-numbered second link wirings LL2 adjacent to each other, the amount of the ion component I trapped therebetween may increase.

[0072] An increase in the amount of trapped ion component I may cause a residual DC voltage DC. This residual DC voltage DC may cause a change in the common voltage Vcom, which should be applied to each pixel at a constant level. When there is a change in the common voltage Vcom, the amount of voltage charged to each pixel may change from frame to frame. As a result, a flickering phenomenon may occur, in which the image or video emitted from the display area AA flickers, which is visible to the user.

[0073] The flicker phenomenon may reduce a user's immersion in an image or video, thereby degrading the reliability of the display device.

[0074] Figure 7 According to the embodiment of the present disclosure Figure 2 An enlarged plan view of area 7 in FIG. Figure 8 According to the embodiment of the present disclosure Figure 2 An enlarged plan view of area 8 in FIG. Figure 9 According to the embodiment of the present disclosure Figure 8 A cross-sectional view taken along line 9-9 in FIG. Figure 10 is a graph of measured flicker levels according to an embodiment of the present disclosure. In this regard, Figure 9 Electric field generation of dual-link wiring according to another embodiment of the present disclosure is shown.

[0075] Reference Figures 7 to 9 The dual-link wiring structure may be a structure in which adjacent link wirings LL are formed in different layers. The link wirings LL may include a first link wiring LL1 and a second link wiring LL2. For example, the first link wiring LL1 may be provided in a first layer, and the second link wiring LL2 may be provided in a second layer different from the first layer. In one example, an odd-numbered first link wiring LL1-0 may be provided in the first layer, and an even-numbered second link wiring LL2-0 adjacent to the odd-numbered first link wiring LL1-0 may be provided in the second layer.

[0076] In a plan view of the display device, the first and second regions of the link region 215 may include a plurality of intersection points C1 and C2, respectively, at which the first link wiring LL1 and the second link wiring LL2 (e.g., a pair of link wirings) intersect with each other. In the plan view, a portion of the first link wiring LL1 and a portion of the second link wiring LL2 are spaced apart from each other at locations other than the intersection points C1 and C2. In one embodiment, the first region may be adjacent to the display region AA, and the second region may be adjacent to the pad region 210. The first region may be one side edge of the link region 215, and the second region may be another side edge opposite to the one side edge of the link region 215.

[0077] Reference Figure 7 In the first region adjacent to the display region AA of the link region 215, the odd-numbered second link wirings LL2-O may be electrically connected to the gate lines GL, and the even-numbered first link wirings LL1-E may be electrically connected to the data lines DL. However, embodiments of the present disclosure are not limited thereto.

[0078] The first area of ​​the link area 215 may include a first intersection C1 at which the even-numbered first link wirings LL1-E and the odd-numbered second link wirings LL2-O intersect with each other. Figure 8 As shown, the even-numbered first link wirings LL1 -E and the odd-numbered second link wirings LL2 -O intersecting each other at the first intersection point C1 of the first area of ​​the link area 215 may extend toward the second area of ​​the link area 215 .

[0079] The plurality of first link wirings LL1 -O and LL1 -E may be located in the first layer on the base substrate 100 , and may be made of the same material as that of the gate electrode GE and may be formed in the same process as that of forming the gate electrode.

[0080] The plurality of second link wirings LL2 -O and LL2 -E may be located in a second layer different from the first layer, may be made of the same material as that of the source / drain electrodes SD, and may be formed in the same process as that of forming the source / drain electrodes SD.

[0081] A gate insulating layer 113 may be provided between the plurality of first link wirings LL1-O and LL1-E and the plurality of second link wirings LL2-O and LL2-E. However, embodiments of the present disclosure are not limited thereto. For example, a plurality of insulating layers may be provided between the plurality of first link wirings LL1-O and LL1-E and the plurality of second link wirings LL2-O and LL2-E.

[0082] Reference Figure 7 and Figure 8 The even-numbered first link wirings LL1 -E and the odd-numbered second link wirings LL2 -O intersecting each other at the first intersection point C1 of the first area of ​​the link area 215 may extend toward the second area of ​​the link area 215 .

[0083] Since the even-numbered first link wiring LL1-E and the odd-numbered second link wiring LL2-O intersect each other at the first intersection C1, the odd-numbered second link wiring LL2-O can be arranged adjacent to the odd-numbered first link wiring LL1-O. For example, the odd-numbered second link wiring LL2-O can be arranged between the odd-numbered first link wiring LL1-O and the even-numbered first link wiring LL1-E. The even-numbered first link wiring LL1-E can be arranged between the odd-numbered second link wiring LL2-O and the even-numbered second link wiring LL2-E.

[0084] The even-numbered first link wiring LL1 -E and the odd-numbered second link wiring LL2 -O intersecting each other at the first intersection C1 of the first area of ​​the link area 215 may intersect each other again at the second intersection C2 of the second area of ​​the link area 215 .

[0085] The even-numbered first link wirings LL1 -E and the odd-numbered second link wirings LL2 -O intersecting each other at the second intersection point C2 may extend to the pad region 210 and may be electrically connected to the link pad 305P2 via the second connection electrode 300 b .

[0086] Since the even-numbered first link wiring LL1-E and the odd-numbered second link wiring LL2-O intersect each other at the second intersection point C2, the even-numbered first link wiring LL1-E may be disposed adjacent to the odd-numbered first link wiring LL1-O in the pad region 210. Furthermore, the even-numbered second link wiring LL2-E may be disposed adjacent to the odd-numbered second link wiring LL2-O.

[0087] Therefore, one link wiring group LL may include odd-numbered first link wirings LL1-O, even-numbered first link wirings LL1-E, odd-numbered second link wirings LL2-O, and even-numbered second link wirings LL2-E arranged along the first direction in the pad region 210.

[0088] For example, the first direction may be the X-axis direction of the base substrate 100 (see Figure 2 In one example, the first direction may be a horizontal direction. A plurality of link wiring groups LL may be arranged on the base substrate 100 .

[0089] The odd-numbered second link wiring LL2-O may be disposed adjacent to the odd-numbered first link wiring LL1-O. For example, the odd-numbered second link wiring LL2-O may be disposed between the odd-numbered first link wiring LL1-O and the even-numbered first link wiring LL1-E. The even-numbered first link wiring LL1-E may be disposed between the odd-numbered second link wiring LL2-O and the even-numbered second link wiring LL2-E.

[0090] Reference Figure 8 and Figure 9 , according to another embodiment of the present disclosure, the signal A1 of the first polarity may be transmitted to the odd-numbered first link wirings LL1 -O disposed in the first layer in the link region 215 of the non-display area NAA.

[0091] A signal A1 having the same first polarity as the signal transmitted to the odd-numbered first link wiring LL1-O may also be transmitted to the odd-numbered second link wiring LL2-O, which is adjacent to the odd-numbered first link wiring LL1-O and disposed in the second layer. The first layer and the second layer may be different layers. In one example, the second layer may be located on top of the first layer. For example, the first polarity may be a positive polarity signal. In one example, the positive polarity signal may be a positive data voltage.

[0092] A signal B1 of a second polarity may be transmitted to the even-numbered first link wiring LL1-E disposed in the first layer. A signal B1 of a second polarity identical to the second polarity of the signal transmitted to the even-numbered first link wiring LL1-E may be transmitted to the even-numbered second link wiring LL2-E disposed in the second layer and adjacent to the even-numbered first link wiring LL1-E. For example, the second polarity may be negative. In one example, the negative polarity signal may be a negative data voltage.

[0093] Since the same first polarity signal A1 is transmitted to the odd-numbered first link wirings LL1-O provided in the first layer and the even-numbered second link wirings LL2-O provided in the second layer, no electric field is generated between them. Furthermore, when the same second polarity signal B1 is transmitted to the even-numbered first link wirings LL1-E provided in the first layer and the even-numbered second link wirings LL2-E provided in the second layer, no electric field is generated between them.

[0094] When a signal A1 of a first polarity and a signal B1 of a second polarity opposite to each other are applied to the even-numbered first link wirings LL1-E arranged in the first layer and intersecting each other at multiple intersections C1 and C2, and the odd-numbered second link wirings LL2-O adjacent to the even-numbered link wirings LL1-E and arranged in the second layer, an electric field can be generated between them.

[0095] Therefore, when an electric field is generated therebetween, the ion component I may be trapped between the even-numbered first link wiring LL1-E and the odd-numbered second link wiring LL2-0. However, the amount of trapped ion component I may be reduced compared to previous embodiments described herein.

[0096] As the amount of trapped ion component I decreases, the residual DC voltage DC can be prevented from occurring. Therefore, the common voltage Vcom applied to each pixel can be kept constant. Therefore, the amount of voltage charged to each pixel can be kept constant, thereby preventing or reducing flickering.

[0097] At high refresh rates such as 120Hz or 60Hz, the flicker phenomenon is not recognizable to the user. However, since a display device operating in a variable refresh rate (VRR) mode operates at various refresh rates (e.g., 40Hz to 120Hz), the flicker phenomenon should not be visible to the user even at low refresh rates below 40Hz.

[0098] To measure whether flicker occurs, the flicker level value can be measured at a refresh rate as low as 24Hz. When measuring the flicker level value at a refresh rate of 24Hz, the flicker level value at a refresh rate of 12Hz is also measured. Therefore, based on the flicker level value measured at a refresh rate of 12Hz, it is possible to determine whether the flicker level at a refresh rate of 24Hz is within a normal range. For example, the reference value R for determining that the flicker level value is normal can be -55dB. When the flicker level value is greater than -55dB, it can be determined as a flicker defect.

[0099] The flicker level value measured at a refresh rate of 12 Hz is lower than the flicker level value measured at a refresh rate of 24 Hz. For example, when the flicker level value measured at a refresh rate of 24 Hz is -55 dB, the flicker level value measured at a refresh rate of 12 Hz is -80 dB, which is lower than -55 dB.

[0100] Therefore, when the flicker level value measured at a refresh rate of 12 Hz is, for example, -80 dB or less, it can be determined that the flicker level value measured at a refresh rate of 24 Hz is within the normal range. In addition, if the flicker level value measured at a refresh rate of 12 Hz is, for example, -55 dB or more, it can be determined that the flicker level value measured at a refresh rate of 24 Hz is a flicker defect.

[0101] Reference Figure 10 In comparative example EX1, the flicker level value measured at a refresh rate of 12 Hz is greater than -55 dB. Accordingly, it can be determined that the flicker level value measured at a refresh rate of 24 Hz is greater than -55 dB (which is the reference value R for determining that the flicker level is normal). Therefore, it can be determined that comparative example EX1 has a flicker defect. In this regard, comparative example EX1 has a configuration in which the first link wiring LL1 and the second link wiring LL2 do not intersect each other in the link area 215.

[0102] Compared to the comparative example, in this example EX2, the flicker level value measured at a refresh rate of 12 Hz is less than -55 dB. For example, the flicker level value may have a value less than -80 dB. Therefore, it can be determined that the flicker level value measured at a refresh rate of 24 Hz has a value less than -55 dB (which is a reference value R for determining that the flicker level is normal). Therefore, it can be determined that no flicker defect occurs in this example EX2. In this regard, this example EX2 has a configuration according to another embodiment of the present disclosure, namely, the first link wiring LL1 and the second link wiring LL2 intersect each other at multiple intersection points C1 and C2 in the first area and the second area of ​​the link area 215.

[0103] Therefore, according to another embodiment of the present disclosure, the flicker level value at a refresh rate of 12 Hz is less than -80 dB. Therefore, flicker defects can be prevented or reduced. For example, the link area 215 may include an intersection point where the first link wiring and the second link wiring intersect each other in at least the first and second areas thereof.

[0104] Therefore, preventing or reducing the occurrence of flicker can increase the user's immersion in the image or video. Therefore, the reliability of the display device can be improved. In addition, the increase in the electric field generated between adjacently arranged link wiring can be prevented.

[0105] Therefore, it is possible to prevent unnecessary direct current voltage from being generated, thereby enabling the display device to operate at low power, thereby reducing its power consumption.

[0106] A display device according to various aspects and embodiments of the present disclosure may be described as follows.

[0107] One aspect of the present disclosure provides a display device, comprising: a substrate including a non-display area surrounding a display area; a plurality of signal lines arranged on the display area of ​​the substrate; and a plurality of link wirings, the plurality of link wirings being electrically connected to the signal lines, respectively, and being arranged on the link area of ​​the non-display area of ​​the substrate, wherein the plurality of link wirings include intersections at which adjacent link wirings are arranged to intersect with each other.

[0108] According to some embodiments of the display device, the intersection point includes: a first intersection point, which is arranged in a first area adjacent to one end of the link area; and a second intersection point, which is arranged in a second area adjacent to the other end opposite to the one end of the link area.

[0109] According to some embodiments of the display device, the first area is adjacent to the display area, and the second area is adjacent to a pad area of ​​the non-display area.

[0110] According to some embodiments of the display device, the plurality of signal lines include data lines or gate lines.

[0111] According to some embodiments of the display device, the link wiring includes: a first link wiring disposed in a first layer on the substrate; and a second link wiring disposed in a second layer different from the first layer.

[0112] According to some embodiments of the display device, the first link wiring and the second link wiring intersect each other at at least one intersection point in the link area.

[0113] According to some embodiments of the display device, the link wiring includes a link wiring group, the link wiring group including: odd-numbered first link wirings and even-numbered first link wirings arranged in a first layer on the substrate; and odd-numbered second link wirings and even-numbered second link wirings arranged in a second layer different from the first layer.

[0114] According to some embodiments of the display device, the even-numbered first link wirings and the odd-numbered second link wirings intersect each other at a first intersection point in a first area of ​​the link area, and intersect each other at a second intersection point in a second area of ​​the link area, wherein the first area and the second area are spaced apart from each other.

[0115] According to some embodiments of the display device, in the link wiring group, the odd-numbered first link wirings, the odd-numbered second link wirings, the even-numbered first link wirings, and the even-numbered second link wirings are arranged in this order in one direction and are spaced apart from each other in an area between the first intersection point and the second intersection point.

[0116] According to some embodiments of the display device, in the link wiring group, the odd-numbered first link wirings, the even-numbered first link wirings, the odd-numbered second link wirings, and the even-numbered second link wirings are arranged in this order in one direction and are spaced apart from each other in an area between the second intersection point and the pad area of ​​the non-display area.

[0117] According to some embodiments of the display device, a signal of a first polarity is transmitted to the odd-numbered first link wirings arranged in the first layer, and the odd-numbered second link wirings adjacent to the odd-numbered first link wirings and arranged in the second layer, wherein a signal of a second polarity is transmitted to the even-numbered first link wirings arranged in the first layer, and the even-numbered second link wirings adjacent to the even-numbered first link wirings and arranged in the second layer, wherein the first polarity and the second polarity are opposite to each other.

[0118] According to some embodiments of the display device, the signal of the first polarity includes a positive data voltage, and the signal of the second polarity includes a negative data voltage.

[0119] According to some embodiments of the display device, the first link wiring includes the same material as the gate electrode on the display area and is formed in the same process as the process of forming the gate electrode, wherein the second link wiring includes the same material as the source electrode / drain electrode set on the display area and is formed in the same process as the process of forming the source electrode / drain electrode, wherein an insulating layer is set between the first link wiring and the second link wiring.

[0120] Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the above embodiments, but can be implemented in various forms. It will be understood by those skilled in the art that the present disclosure can be practiced in other specific forms without changing the technical spirit or basic features of the present disclosure. Therefore, it should be understood that the embodiments described above are not restrictive, but illustrative in all aspects.

Claims

1. A display device comprising: a substrate comprising a display area and a non-display area surrounding the display area; a plurality of signal lines on the display area of ​​the substrate; as well as a plurality of link wirings electrically connected to the plurality of signal lines, the plurality of link wirings being located in a link region of the non-display region of the substrate, wherein the plurality of link wirings are arranged in different layers, and In a plan view of the display device, a pair of link wirings adjacent to each other among the plurality of link wirings intersect with each other at an intersection point.

2. The display device according to claim 1, wherein The intersection points include: a first intersection point in a first region, the first intersection point being closer to a first end of the link region than to a second end of the link region opposite the first end of the link region; and; The second intersection point in the second area is closer to the second end of the link area than to the first end of the link area.

3. The display device according to claim 2, wherein: The first area is adjacent to the display area, and the second area is adjacent to a pad area of ​​the non-display area.

4. The display device according to claim 1, wherein The plurality of signal lines include at least one of a data line and a gate line.

5. The display device according to claim 1, wherein The plurality of link wirings include: a first link routing in a first layer on the substrate; and A second link routing is provided in a second layer on the substrate that is different from the first layer. The display device according to claim 5 , wherein: The first link wiring and the second link wiring intersect each other at one or more intersection points in the link area.

7. The display device according to claim 1, wherein The plurality of link wirings include at least one link wiring group, each link wiring group including: odd-numbered first link wirings and even-numbered first link wirings in a first layer on the substrate; and Odd-numbered second link wirings and even-numbered second link wirings are provided in a second layer different from the first layer on the substrate.

8. The display device according to claim 7, wherein: The even-numbered first link wiring and the odd-numbered second link wiring intersect each other at a first intersection point in the first area of ​​the link area and extend toward the second area of ​​the link area, and intersect each other at a second intersection point in the second area of ​​the link area, The first region and the second region are spaced apart from each other.

9. The display device according to claim 8, wherein In the at least one link wiring group, the odd-numbered first link wirings, the odd-numbered second link wirings, the even-numbered first link wirings, and the even-numbered second link wirings are sequentially arranged in one direction and spaced apart from each other in a region between the first intersection point and the second intersection point.

10. The display device according to claim 8, wherein In the at least one link wiring group, the odd-numbered first link wirings, the even-numbered first link wirings, the odd-numbered second link wirings, and the even-numbered second link wirings are sequentially arranged in one direction and are spaced apart from each other in an area between the second intersection point and the pad area of ​​the non-display area.

11. The display device according to claim 8, wherein The odd-numbered first link wirings in the first layer and the odd-numbered second link wirings adjacent to the odd-numbered first link wirings and in the second layer receive signals of a first polarity, The even-numbered first link wirings in the first layer and the even-numbered second link wirings adjacent to the even-numbered first link wirings in the second layer receive signals of a second polarity opposite to the first polarity.

12. The display device according to claim 11, wherein The signal of the first polarity includes a positive data voltage, and the signal of the second polarity includes a negative data voltage.

13. The display device according to claim 5, wherein The material of the first link wiring is the same as that of the gate electrode on the display area, and the first link wiring is on the same layer as the gate electrode, The material of the second link wiring is the same as that of the source electrode or the drain electrode on the display area, and the second link wiring is on the same layer as the source electrode or the drain electrode. Wherein, the display device further includes an insulating layer between the first link wiring and the second link wiring.

14. A display device comprising: a substrate comprising a display area, a non-display area surrounding the display area, a link area in the non-display area, and a pad area in the link area; a plurality of signal lines on the display area of ​​the substrate; as well as a plurality of link wirings on the link area, the plurality of link wirings being electrically connected to the plurality of signal lines, In which, in the plan view of the display device, a pair of link wirings adjacent to each other in the link area intersect with each other at a first point closer to the display area than the pad area, and intersect with each other at a second point closer to the pad area than the display area in the plan view.

15. The display device according to claim 14, wherein The pair of link wirings includes a first link wiring on a first layer and a second link wiring on a second layer different from the first layer.

16. The display device according to claim 15, wherein The first link wiring receives a signal of a first polarity, and the second link wiring receives a signal of a second polarity different from the first polarity.

17. The display device according to claim 16, wherein: The signal of the first polarity includes a positive voltage, and the signal of the second polarity includes a negative voltage.

18. The display device according to claim 15, wherein The material of the first link wiring is the same as that of the gate electrode on the display area, and the first link wiring is on the same layer as the gate electrode, The material of the second link wiring is the same as that of the source electrode or the drain electrode on the display area, and the second link wiring is on the same layer as the source electrode or the drain electrode.

19. The display device according to claim 16, wherein: A portion of the first link wiring and a portion of the second link wiring are spaced apart from each other in the plan view.

20. The display device according to claim 14, wherein The plurality of signal lines include at least one of a data line and a gate line.

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