Dynamic on-resistance testing device and testing method for wide-bandgap semiconductor device

Abstract

The application provides a kind of wide band gap semiconductor device dynamic on resistance test device and test method, the device includes: interactive control system, signal generating unit, waveform acquisition unit, power supply unit and dynamic on resistance test unit;Dynamic on resistance test unit includes test loop and gate drive circuit, gate drive circuit includes gate drive chip, first adjustable voltage regulator and second adjustable voltage regulator;First adjustable voltage regulator and second voltage regulator cross ground, realize the physical isolation of loop and chip;Signal generating unit generates the pulse signal required for testing, and the gate drive circuit controls the switching state of the device under test during the testing process according to the pulse signal;Waveform acquisition unit acquires the voltage signal and current signal of dynamic on resistance test unit during the testing process;Interactive control system calculates the dynamic on resistance of the device under test according to the voltage signal and current signal.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electrical parameter testing of wide bandgap semiconductor devices, and particularly relates to a dynamic on-resistance testing device and method for wide bandgap semiconductor devices. BACKGROUND

[0002] The third generation of wide bandgap semiconductor materials represented by silicon carbide and gallium nitride have greater bandgap, higher breakdown field, faster switching speed, smaller on-resistance and higher thermal conductivity, and can better meet the needs of power devices for performance indicators such as operating temperature, breakdown voltage and operating frequency, and have broad market prospects. However, compared with traditional silicon-based devices, the dynamic stability of gallium nitride and silicon carbide-based devices is poor, and the dynamic on-resistance degradation is particularly prominent: the lateral gallium nitride power high electron mobility transistor transmits current through the two-dimensional electron gas channel in the on state, and in the power electronic switching process, the device will be subjected to various stresses, resulting in the capture of part of the charge by the traps in the specific region of the transistor. When the device enters the switching state, the captured electrons will cause the on-resistance to increase; in order to distinguish the direct current on-resistance, the on-resistance in this switching state is called dynamic on-resistance. Greater dynamic on-resistance means higher power loss, reducing system efficiency; if its characteristics are not verified, the gallium nitride power device will face reliability risks, so it is necessary to conduct in-depth research on the changes of the dynamic on-resistance of the power device in the switching process.

[0003] The prior art generally uses a double pulse test circuit as a platform to carry out the test of the dynamic on-resistance of the power device. In theory, only the drain-source voltage VDS and the drain-source current IDS need to be measured when the device is turned on, and the curve of the dynamic on-resistance changing with time can be calculated using Ohm's law. However, when the device is switched under high voltage conditions, the accuracy of the oscilloscope is often insufficient. Taking an 8-bit oscilloscope as an example, if the drain-source voltage of the device when it is turned off is 400V and the on voltage is about 0.5V, the actual resolution is 400 / 2 8 =1.5625V, which cannot achieve the measurement accuracy of 0.5V voltage. In order to take into account the cost, the prior art usually adds a voltage clamping circuit in the original double pulse circuit to clamp the voltage when the device is turned off to a lower value, thereby improving the measurement accuracy.

[0004] However, the existing test device usually shares the same reference ground for power supply of the gate drive chip and the test loop, and high-voltage transients are easily coupled to the drive chip along the common ground line, which easily causes logic mis-triggering, pulse timing drift, or directly breaks the low-voltage port of the drive chip. At the same time, the common ground structure will introduce significant ground bounce noise at the switching moment, so that the VDS and IDS waveforms measured by the oscilloscope are superimposed with high-frequency oscillation, which causes the extraction error of the dynamic on-resistance to be amplified, and even the real voltage details of 0.5V level are covered. In order to avoid the above coupling, the existing method usually additionally increases an isolation power supply or an optical coupling device, which not only increases the system complexity and cost, but also limits the bandwidth and pulse count accuracy during continuous pulse testing. SUMMARY

[0005] The application provides a dynamic on-resistance test device and test method for a wide-bandgap semiconductor device, which realizes physical isolation and independent biasing of the power loop and the gate drive by cross-connection of the double adjustable voltage stabilizers, thereby improving the measurement accuracy and device reliability.

[0006] To achieve the above effects, the application provides a dynamic on-resistance test device for a wide-bandgap semiconductor device, which comprises an interactive control system, a signal generating unit, a waveform collecting unit, a power supply unit, and a dynamic on-resistance test unit.

[0007] The interactive control system is electrically connected with the signal generating unit, the waveform collecting unit, and the power supply unit, and the power supply unit is electrically connected with the dynamic on-resistance test unit.

[0008] The dynamic on-resistance test unit comprises a test loop and a gate drive circuit, the gate drive circuit comprises a gate drive chip, a first adjustable voltage stabilizer, and a second adjustable voltage stabilizer, the output end of the first adjustable voltage stabilizer is connected with the power supply end of the gate drive chip, the ground end of the first adjustable voltage stabilizer is connected with the ground end of the test loop, the output end of the second adjustable voltage stabilizer is connected with the ground end of the test loop, and the ground end of the second adjustable voltage stabilizer is connected with the ground end of the gate drive chip.

[0009] The signal generating unit generates a pulse signal required for testing, and the gate drive circuit controls the switching state of the device under test during the testing process according to the pulse signal.

[0010] The waveform collecting unit collects the voltage signal and the current signal of the dynamic on-resistance test unit during the testing process through a voltage probe and a current probe.

[0011] The interactive control system calculates the dynamic on-resistance of the device under test according to the voltage signal and the current signal.

[0012] Preferably, the waveform acquisition unit comprises a data acquisition card, a voltage probe and a current probe, the voltage probe comprises an optical isolation probe, a passive voltage probe and a high-voltage differential probe, and the data acquisition card is connected with the dynamic on-resistance test unit through the optical isolation probe, the passive voltage probe, the high-voltage differential probe and the current probe.

[0013] Preferably, the test loop comprises an inductive load, a resistive load, a switching switch, a device under test, a device under test, a first silicon carbide diode, a first test seat and a second test seat.

[0014] The inductive load and the resistive load are connected to the test loop through the terminal, the device under test is connected to the test loop through the first test seat, and the device under test or the first silicon carbide diode is connected to the test loop through the second test seat.

[0015] The first test seat and the second test seat have three terminals of gate G, drain D and source S, respectively, the G terminals of the first test seat and the second test seat are connected with the gate drive circuit, and the D terminals and the S terminals are connected with the test loop.

[0016] The switching switch is used for switching the soft switching mode and the hard switching mode of the test loop, in the soft switching mode, the G, D and S terminals of the device under test correspond to the G, D and S terminals of the second test seat inserted, and in the hard switching mode, the anode of the first silicon carbide diode is inserted into the S terminal of the second test seat, and the cathode is inserted into the D terminal of the second test seat.

[0017] Preferably, two gate drive circuits are arranged in the dynamic on-resistance test unit, and the output terminals of the two gate drive circuits are connected with the G terminals of the first test seat and the second test seat, respectively.

[0018] Preferably, the dynamic on-resistance test unit further comprises a clamping circuit, the power supply unit comprises a high-voltage power supply and an auxiliary power supply, the high-voltage power supply is electrically connected with the test loop, and the auxiliary power supply is electrically connected with the gate drive circuit and the clamping circuit.

[0019] The clamping circuit comprises a linear voltage stabilizer, a voltage stabilizing diode, a second silicon carbide diode and a current limiting resistor.

[0020] The first linear voltage stabilizer is connected with the auxiliary power supply, the anode of the voltage stabilizing diode is connected with the ground, the anode of the second silicon carbide diode is connected with the current limiting resistor and the cathode of the voltage stabilizing diode, respectively, the current limiting resistor is connected in series with the output terminal of the linear voltage stabilizer, and the cathode of the second silicon carbide diode is connected with the D terminal of the first test seat.

[0021] Preferably, the signal generation unit comprises a waveform generator and a radio frequency signal line, and the waveform generator is connected with the dynamic on-resistance test unit through the radio frequency signal line.

[0022] Preferably, the test circuit comprises a capacitor-resistor array, the input end of the capacitor-resistor array is connected with a high-voltage power supply, and the output end is connected with the main circuit of the test circuit.

[0023] The application also provides a dynamic on-resistance testing method for a wide-bandgap semiconductor device, which is implemented based on the above-mentioned dynamic on-resistance testing device for a wide-bandgap semiconductor device and comprises the following steps:

[0024] Step S1: According to the test requirements, the key switch is turned on, the test circuit of the dynamic on-resistance testing unit is adjusted, the selected inductive load or resistive load is connected through the terminal, and the required voltage and current probes are connected to the test position.

[0025] Step S2: The test conditions and signal acquisition conditions are set in the interactive control system, the auxiliary power supply is turned on without connecting the device to be tested and the device to be tested, the trigger button and the waveform generation button are clicked in sequence, the gate-source voltage of the first test seat and the second test seat under no-load is observed, the resistance value of the slide resistor at the output end of the first adjustable voltage stabilizer and the second adjustable voltage stabilizer is adjusted, and after the positive voltage and the negative voltage of the gate-source voltage are adjusted to the rated value of the device to be tested, the auxiliary power supply is turned off.

[0026] Step S3: When the test circuit is a soft switch, the G, D and S ends of the device to be tested are inserted into the G, D and S ends of the second test seat; when the test circuit is a hard switch, the positive and negative poles of the first silicon carbide diode are inserted into the S and D ends of the second test seat.

[0027] Step S4: The auxiliary power supply and the high-voltage power supply are turned on in sequence through the interactive control system, the high-voltage power supply indicator light is turned on, the trigger button and the waveform generation button are clicked in sequence, and the clamping voltage, the drain-source voltage, the drain-source current, the gate-source voltage waveform and the dynamic on-resistance waveform of the device to be tested are obtained.

[0028] Step S5: After the test is completed, the high-voltage power supply is turned off through the interactive control system, and after the high-voltage power supply indicator light is turned off, the auxiliary power supply is turned off.

[0029] Step S6: After the test process is completed through the interactive control system, all experimental data are viewed and analyzed, and the dynamic on-resistance change of the device to be tested under the preset test conditions is judged.

[0030] Preferably, the test conditions and signal acquisition conditions to be set in step S2 include: the forward conduction voltage drop of the second silicon carbide diode, the on-state pulse width, the off-state pulse width, the double-pulse cumulative test number, the test time interval, the high-voltage power supply output voltage, the auxiliary power supply output voltage, the amplification multiple and bandwidth of various probes, the signal sampling rate, and the sampling trigger condition.

[0031] Preferably, the expression for calculating the dynamic on-resistance curve of the device to be tested at the time of opening over time in step S6 is:

[0032] ;

[0033] In the formula, Vclamp is the clamping voltage between the drain and source of the device to be tested in the clamping circuit; Vf is the forward on-voltage drop of the second silicon carbide diode in the clamping circuit; Ids is the drain-source current flowing through the device to be tested at the time of opening.

[0034] The beneficial effects of the present application at least include:

[0035] 1. The first adjustable voltage regulator and the second adjustable voltage regulator are used to realize physical isolation of the test loop and the gate drive chip, the first adjustable voltage regulator takes the ground of the test loop as a reference to provide independent upper tube power supply for the gate drive chip, and the second adjustable voltage regulator takes the ground of the gate drive chip as a reference to provide controllable lower tube bias for the test loop. The structure of the double voltage regulators with cross grounding completely isolates the originally common ground high-power test loop and the low-noise gate drive chip, avoids the mis-triggering or damage caused by the coupling of high-voltage transients to the drive chip through the common ground line, and significantly suppresses the ground bounce noise in the switching process, thereby ensuring the accuracy and stability of the pulse signal and the collected waveform.

[0036] 2. The present application realizes dynamic on-resistance testing of wide bandgap semiconductor devices under various test conditions, such as switching conditions, inductive load and resistive load, on-state pulse width, off-state pulse width, double pulse cumulative test times, test time interval, and drain-source bias voltage of wide bandgap semiconductor devices.

[0037] 3. The present application uses a high-bandwidth, high-sampling-rate waveform acquisition unit to simultaneously obtain the clamping voltage, drain-source voltage, drain-source current, and gate-source voltage waveforms of the device to be tested, thereby monitoring the changes in the device state over time during the test process in real time. All channels can be adjusted for impedance matching, the waveform distortion is small, and the dynamic on-resistance calculated has high accuracy. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1 FIG. 1 is a schematic diagram of the overall structure of the device according to an embodiment of the present application;

[0039] Figure 2 FIG. 2 is a schematic diagram of the specific structure of the device according to an embodiment of the present application;

[0040] Figure 3 FIG. 3 is a schematic diagram of the principle of the gate drive circuit in the embodiment of the present application;

[0041] Figure 4The equivalent circuit diagram of the soft switch and the hard switch of the test circuit in the embodiment of the present application;

[0042] Figure 5 The control signal and the related waveform timing diagram for the single soft switch test and the hard switch test in the embodiment of the present application;

[0043] Figure 6 The actual waveform of the continuous 20 times of hard switch test obtained by the host integration in the embodiment of the present application;

[0044] Figure 7 The comparison schematic diagram of the gate drive signal and the gate signal of the conventional drive circuit in the embodiment of the present application. DETAILED DESCRIPTION

[0045] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0046] As shown in the figure, Figure 1 The embodiment of the present application provides a dynamic on-resistance test device of a wide bandgap semiconductor device, which comprises an interactive control system, a signal generating unit, a waveform collecting unit, a power supply unit and a dynamic on-resistance test unit.

[0047] The interactive control system is electrically connected with the signal generating unit, the waveform collecting unit and the power supply unit, and is used for sending a series of instructions in a test process, receiving test data, integrating test images and completing dynamic on-resistance calculation.

[0048] The signal generating unit is used for controlling the on-pulse width, the off-pulse width, the double-pulse cumulative test times and the test time interval of a pulse signal, and outputting the pulse signal to the dynamic on-resistance test unit.

[0049] The waveform collecting unit is connected with the dynamic on-resistance test unit through voltage and current probes, and is used for collecting gate-source voltage, drain-source voltage, clamping voltage and drain-source current in a test process.

[0050] The power supply unit is connected with different wiring posts of the dynamic on-resistance test unit through an adaptive wire, and is used for providing a power supply voltage required in a test, a working voltage 1 of a gate drive circuit isolation power supply of the dynamic on-resistance test unit and a working voltage 2 required by a clamping circuit of the dynamic on-resistance test unit; and the dynamic on-resistance test unit is used for performing dynamic on-resistance test under a specified test condition.

[0051] As shown in the figure, Figure 2As shown, the interactive control system of the embodiment of the application comprises a case, a host computer, and a display. The case provides installation positions for a signal generating unit, a waveform collecting unit, and a path for peripheral device interconnection PCL bus. The host computer is loaded with LabVIEW software and NI-DAQmx driver program. The host computer is connected with the signal generating unit and the waveform collecting unit through the PCL bus. The generation and editing of pulse signals are realized through the NI-FGEN module in the NI-DAQmx driver program. The waveform collecting is realized through the NI-Scope module in the NI-DAQmx driver program. The host computer is connected with a power supply unit through a network port, and the switching of a high-voltage power supply and an auxiliary power supply is realized through the modbus RTU communication mode. The display is connected with the host computer through an HDMI data line, and is used to provide an interactive operation interface for a tester.

[0052] The signal generating unit comprises a waveform generator and an SMA-to-BNC radio frequency signal line. The waveform generator is an NI PXI-5421 board card, and is connected with the dynamic on-resistance test unit through the SMA-to-BNC radio frequency signal line.

[0053] The waveform collecting unit comprises a data acquisition card, a voltage probe, and a current probe. The voltage probe comprises an optical isolation probe, a passive voltage probe, and a high-voltage differential probe. The data acquisition card is an NI PXIe-5162 board card, and is connected with the voltage probe and the current probe through BNC ports. The voltage probe and the current probe are respectively connected with test points and flying leads reserved on the dynamic on-resistance test unit.

[0054] The power supply unit comprises a high-voltage power supply and an auxiliary power supply, and is respectively connected with different binding posts of the dynamic on-resistance test unit through adaptive wires. The high-voltage power supply is used to provide a power supply voltage required for testing. The auxiliary power supply is used to provide a working voltage 1 of a gate drive circuit isolation power supply of the dynamic on-resistance test unit and a working voltage 2 required for a clamping circuit of the dynamic on-resistance test unit.

[0055] The dynamic on-resistance test unit comprises a test loop, a gate drive circuit, and a clamping circuit.

[0056] Specifically, the test circuit comprises a capacitor-resistor array, an inductive load, a resistive load, a key switch, a device under test, a device under test, a first silicon carbide diode, a first test seat and a second test seat. The capacitor-resistor array is used to filter out the noise of the power supply voltage and store energy to ensure voltage stability. The inductive load and the resistive load are connected to the test circuit through the terminal, and the user can select and external the load according to the test requirement. The key switch is used to switch the test circuit of the hard switch and the soft switch. The device under test is connected to the test circuit through the first test seat, which is used to test the dynamic on-resistance of the corresponding wide bandgap semiconductor device. The first and second test seats are directly welded on the dynamic on-resistance test unit, and the first and second test seats have three terminals of gate G, drain D and source S, respectively, for providing electrical connection mode for the device under test, the device under test or the first silicon carbide diode with the test circuit; the device under test and the silicon carbide diode are connected to the test circuit through the second test seat according to the switch condition, which is used to build the test circuit of the soft switch and the hard switch.

[0057] The gate drive circuit comprises an isolation power supply, a pulse width modulation (PWM) control unit and a gate drive module. The isolation power supply is used to provide a more stable power supply voltage for the gate drive module and protect the auxiliary power supply. The PWM control unit is used to receive the pulse signal output by the signal generating unit, which is connected to the gate drive module through a diode for transmitting the pulse signal to the gate drive module while protecting the signal generating unit. The output terminals of two identical gate drive modules are respectively connected to the G terminals of the first test seat and the second test seat, which are used to control the turn-on and turn-off of the device under test and the device under test in the test process. The clamping circuit comprises a linear voltage regulator, a voltage stabilizing diode, a second silicon carbide diode and a current limiting resistor. The linear voltage regulator is connected to the working voltage 2 of the auxiliary power supply, which is used to provide a stable input voltage for the clamping circuit and protect the auxiliary power supply. The positive electrode of the voltage stabilizing diode is connected to the ground, which is used to limit the clamping voltage in the clamping circuit when the device under test is not turned on to achieve the effect of voltage clamping. The positive electrode of the second silicon carbide diode is connected to the current limiting resistor and the negative electrode of the voltage stabilizing diode, and the negative electrode is connected to the D terminal of the first test seat, which is used to distinguish different current loops in the clamping circuit when the device is turned on and turned off. The current limiting resistor is connected in series with the output terminal of the linear voltage regulator, which is used to limit the current value in the clamping circuit and protect other elements.

[0058] As Figure 3As shown, the gate drive module of the gate drive circuit of the embodiment of the present application comprises a first adjustable voltage stabilizer, a second adjustable voltage stabilizer and a gate drive chip; the output end of the first adjustable voltage stabilizer is connected with the power supply end of the gate drive chip, and the grounding end is connected with the grounding end of the test loop; the output end of the second adjustable voltage stabilizer is connected with the grounding end of the test loop, and the grounding end is connected with the grounding end of the gate drive chip. The first adjustable voltage stabilizer and the second adjustable voltage stabilizer are used to output the gate voltage with adjustable and stable positive voltage and negative voltage amplitude, and simultaneously realize the physical separation of the ground of the test loop and the ground of the gate drive chip. The adjustable voltage stabilizer selected in the embodiment of the present application is LM317T, and the process that the output voltage of the adjustable voltage stabilizer changes with the change of the resistance value of the slide rheostat can be expressed as:

[0059] ;

[0060] In the formula, is the output voltage of the adjustable voltage stabilizer; is the output programming voltage of the adjustable voltage stabilizer, which can be queried through a data manual, and is usually about 1.25V; is the resistance value of the slide rheostat connected with the adjustment port ADJ of the adjustable voltage stabilizer; is the resistance value of the resistance connected with the output end of the adjustable voltage stabilizer.

[0061] The first adjustable voltage stabilizer outputs the positive voltage 4-20V to the power supply end of the drive chip, the second voltage stabilizer outputs the negative voltage -1 to -10V to the ground end of the drive chip, the slide rheostat resistance value of the output end of the drive ground and the power ground is physically isolated, and the gate voltage is continuously adjustable in a large range, which can be compatible with wide bandgap semiconductor devices with different gate voltages.

[0062] As shown in Figure 4 the equivalent circuit diagram of the soft switch and the hard switch of the dynamic on-resistance test unit of the embodiment of the present application, the control signal and the timing diagram of the related waveforms of the single soft switch test and the hard switch test are as shown in Figure 5The PWM1 controls the switch of the device under test, and the PWM2 controls the switch of the companion device. The two groups of control signals are provided by the waveform generator. When the key switch is adjusted to soft switch, the G, D and S terminals of the companion device are inserted into the G, D and S terminals of the second test seat. In the period of t1-t2, the companion device is turned on by the PWM2, the inductance current increases with the increase of the drain-source voltage of the device under test; in the period of t2-t3, the companion device is turned off, the inductance current discharges the parasitic capacitance of the device under test, and the drain-source voltage of the device under test decreases to zero; in the period of t3-t4, the device under test is provided with a gate pulse by the PWM1, and the drain-source voltage of the device under test is zero, so that the soft switch is realized. After the device under test is turned on, the drain-source current of the device under test increases; in the period of t4-t5, the device under test and the companion device are turned off; in the period of t5-t6, the companion device is turned on again; in the period of t5-t7, the process in the period of t1-t3 is repeated, so that the drain-source voltage of the device under test decreases to zero again when the device under test is turned on at the moment of t7, and the soft switch is realized; after the moment of t8, the dynamic on-resistance test of the soft switch is completed.

[0063] When the key switch is adjusted to hard switch, the anode and cathode of the first silicon carbide diode are inserted into the S and D terminals of the second test seat, respectively. At this time, the first silicon carbide diode and the inductor form a freewheeling circuit. In the period of t1-t2, the device under test is turned on, and the drain-source current increases; in the period of t2-t3, the device under test is turned off, and the drain-source current is zero, while the inductance current remains unchanged due to the existence of the first silicon carbide diode; in the period of t3-t4, the device under test is turned on again, and the drain-source current is the same as that at the moment of t2, and starts to increase from this value; after the moment of t4, the dynamic on-resistance test of the hard switch is completed.

[0064] When the device under test is turned off, the drain electrode is at a high level, and the first silicon carbide diode of the clamping circuit is turned off. At this time, the power supply, the current-limiting resistor and the stabilizing diode form a current loop, and the clamping voltage is clamped to a stable value by the stabilizing diode, which is much smaller than the actual drain-source voltage, thereby realizing the effect of voltage clamping. When the device under test is turned on, the first silicon carbide diode is turned on, and the current flows through the current-limiting resistor, the first silicon carbide diode and the device under test. After the test is completed, the host can calculate the curve of the dynamic on-resistance of the device under test with time according to Ohm's law:

[0065] ;

[0066] In the formula, Vclamp is the clamping voltage between the drain and source of the device under test in the clamping circuit; Vf is the forward voltage drop of the second silicon carbide diode in the clamping circuit; Ids is the drain-source current flowing through the device under test when the device under test is turned on.

[0067] Based on the above test device, the embodiment of the application proposes a dynamic on-resistance test method of a wide bandgap semiconductor device, comprising the following steps:

[0068] Step S1: The tester adjusts the test circuit of the dynamic on-resistance test unit according to the test requirements, and connects the selected inductive load or resistive load through the terminal, and connects the required voltage and current probes to the test position.

[0069] Step S2: The tester presets the test conditions and signal acquisition conditions in the interactive control system, including: the forward on-voltage drop of the second silicon carbide diode, the on-state pulse width, the off-state pulse width, the double-pulse cumulative test number, the test time interval, the high-voltage power supply output voltage, the auxiliary power supply output voltage, the amplification multiple and bandwidth of various probes, the signal sampling rate, and the sampling trigger condition.

[0070] Step S3: The tester turns on the auxiliary power supply without connecting the device to be tested and the auxiliary device, and clicks the trigger button and the waveform generation button in turn, observes the gate-source voltage at the first and second test seats under no load, adjusts the resistance value of the slide resistor at the output end of the first and second adjustable voltage stabilizers of the two gate drive modules, and adjusts the positive and negative voltage of the gate-source voltage to the appropriate value, and then turns off the auxiliary power supply.

[0071] Step S4: The tester selects the auxiliary device or inserts the first silicon carbide diode into the second test seat according to the test circuit, when the test circuit is soft switching, the G, D and S ends of the auxiliary device are inserted into the G, D and S three ends of the second test seat; when the test circuit is hard switching, the anode and cathode of the first silicon carbide diode are inserted into the S and D ends of the second test seat.

[0072] Step S5: The tester turns on the auxiliary power supply and the high-voltage power supply in turn through the interactive control system, and then clicks the trigger button and the waveform generation button in turn after the high-voltage power supply indicator light is on, to obtain the clamping voltage, drain-source voltage, drain-source current and gate-source voltage waveform of the device to be tested, and the dynamic on-resistance waveform processed by the host.

[0073] Step S6: After the test is completed, the tester turns off the high-voltage power supply through the interactive control system, and then turns off the auxiliary power supply after the high-voltage power supply indicator light is off.

[0074] Step S7: After the tester completes all the above test processes through the interactive control system, the tester views and analyzes all the experimental data to determine the dynamic on-resistance change of the device to be tested under the preset test conditions.

[0075] Figure 6After a wide band gap semiconductor device obtained after operation according to the above test procedure is continuously tested for 20 times of hard switching dynamic on-resistance, the host automatically clips the time interval of each test and integrates it into a complete waveform after saving the test waveform obtained by continuously triggering the waveform acquisition unit for 20 times, so as to facilitate the test personnel to analyze the change of the dynamic on-resistance during continuous testing.

[0076] The test device of the embodiment of the application realizes dynamic on-resistance testing of the wide band gap semiconductor device under various test conditions, such as switching conditions, inductive load and resistive load, on-state pulse width, off-state pulse width of the pulse signal, double-pulse cumulative test times, test time interval, and drain-source bias voltage of the wide band gap semiconductor device.

[0077] The clamping voltage, drain-source voltage, drain-source current, and gate-source voltage waveform of the device under test are obtained simultaneously through the waveform acquisition unit with high bandwidth and high sampling rate, so as to understand the change of the device state with time during the test process. All channels can be adjusted for impedance matching, the waveform distortion is small, the dynamic on-resistance calculated is high in precision, and the minimum can reach 7 mΩ, and the dynamic on-resistance waveform fluctuation is about 2 mΩ.

[0078] The gate voltage range provided by the test loop is large and can be freely adjusted, and is compatible with wide band gap semiconductor devices with different gate voltages. The positive voltage of 4V to 20V and the negative voltage of -1V to -10V can be provided through the slide rheostat of the output end of the first and second adjustable voltage stabilizers. At the same time, the ground of the gate drive chip is separated from the ground of the test loop through the design of the driving circuit in which the high level of the output end of the second adjustable voltage stabilizer is connected with the ground of the driving circuit, and the low level is connected with the ground end of the gate drive chip, thereby reducing the interference of the drain-source voltage change on the gate drive signal. The existing driving circuit usually adopts fixed gate voltage or single-channel voltage stabilization, and cannot eliminate the interference of the high voltage of the drain-source on the gate signal. The embodiment of the application completely suppresses the gate voltage fluctuation through ground isolation and double-channel adjustable. As shown in Figure 7 Fig. 2 is a comparison diagram of the gate drive signal of the embodiment of the application and the gate signal waveform of the conventional driving circuit, wherein the horizontal axis represents the test time, and the vertical axis represents the gate voltage. Figure 7 As can be seen from

[0079] The existing test device relies on manual operation of independent equipment, and it is difficult for an oscilloscope to continuously capture millisecond-level waveforms. The device of the embodiment of the application realizes seamless splicing of continuous multiple tests by high sampling rate of a data acquisition card and automatic integration of waveforms by LabVIEW. Meanwhile, the system operation of the test device of the embodiment of the application is simple and convenient, and the man-machine interaction is friendly. After the required devices for testing are installed, the test can be directly completed and the result can be saved through the interactive control system. The interactive control system can integrate the waveforms of continuous tests together and automatically calculate the dynamic on-resistance change curve of the device to be tested.

[0080] In summary, the dynamic on-resistance test device and test method of the wide-bandgap semiconductor device provided by the embodiment of the application can switch the two test circuits of hard switch and soft switch through a key switch, connect different inductive loads and resistive loads through a wiring terminal, complete the operations of power switch, pulse width and test number setting, waveform acquisition and integration, dynamic on-resistance calculation and the like through a program in the host computer, and can realize rapid capture and integration display of test signals, so as to meet different test requirements of dynamic on-resistance evaluation.

[0081] The technical features of the above embodiments can be combined arbitrarily. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, only the preferred embodiments of the application are expressed, and the description is more specific and detailed, but it should not be understood as limiting the scope of the application. As long as the combination of these technical features does not exist, it should be considered as the scope of the present application.

[0082] It should be noted that, for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A device for testing the dynamic on-resistance of a wide bandgap semiconductor device, comprising: a power supply; a current source; a voltage source; a load resistor; a wide bandgap semiconductor device; and a controller. The application relates to an interactive control system, a signal generating unit, a waveform collecting unit, a power supply unit and a dynamic on-resistance testing unit. The interactive control system is electrically connected with the signal generating unit, the waveform collecting unit and the power supply unit, and the power supply unit is electrically connected with the dynamic on-resistance testing unit. The dynamic on-resistance testing unit comprises a test loop and a gate driving circuit, the test loop comprises an inductive load, a resistive load, a switching switch, a device to be tested, an auxiliary device, a first silicon carbide diode, a first test seat and a second test seat. The inductive load and the resistive load are connected to the test loop through a terminal, the device to be tested is connected to the test loop through the first test seat, and the auxiliary device or the first silicon carbide diode is connected to the test loop through the second test seat. The first test seat and the second test seat respectively have three terminals of a gate G, a drain D and a source S, the G terminals of the first test seat and the second test seat are connected with the gate driving circuit, and the D terminals and the S terminals are connected with the test loop. The switching switch is used for switching a soft switching mode and a hard switching mode of the test loop, in the soft switching mode, the G, D and S terminals of the auxiliary device correspond to the G, D and S terminals of the second test seat, and in the hard switching mode, the anode of the first silicon carbide diode is inserted into the S terminal of the second test seat, and the cathode is inserted into the D terminal of the second test seat. The gate driving circuit comprises a gate driving chip, a first adjustable voltage stabilizer and a second adjustable voltage stabilizer, the output terminal of the first adjustable voltage stabilizer is connected with the power supply terminal of the gate driving chip, the grounding terminal of the first adjustable voltage stabilizer is connected with the grounding terminal of the test loop, the output terminal of the second adjustable voltage stabilizer is connected with the grounding terminal of the test loop, and the grounding terminal of the second adjustable voltage stabilizer is connected with the grounding terminal of the gate driving chip, two gate driving circuits are arranged in the dynamic on-resistance testing unit, and the output terminals of the two gate driving circuits are respectively connected with the G terminals of the first test seat and the second test seat. The signal generating unit generates a pulse signal required for testing, and the gate driving circuit controls the switching state of the device to be tested in the testing process according to the pulse signal. The waveform collecting unit collects voltage signals and current signals of the dynamic on-resistance testing unit in the testing process through voltage probes and current probes. The interactive control system calculates the dynamic on-resistance of the device to be tested according to the voltage signals and the current signals. The waveform collecting unit comprises a data acquisition card, voltage probes and current probes, the voltage probes comprise optical isolation probes, passive voltage probes and high-voltage differential probes, and the data acquisition card is connected with the dynamic on-resistance testing unit through the optical isolation probes, the passive voltage probes, the high-voltage differential probes and the current probes.

2. The dynamic on-resistance testing apparatus for a wide bandgap semiconductor device of claim 1, wherein: The dynamic on-resistance testing unit further comprises a clamping circuit, the power supply unit comprises a high-voltage power supply and an auxiliary power supply, the high-voltage power supply is electrically connected with the test loop, and the auxiliary power supply is electrically connected with the gate driving circuit and the clamping circuit.

3. The apparatus of claim 1, wherein: the wide bandgap semiconductor device is a gallium nitride based device. The clamping circuit comprises a linear voltage stabilizer, a voltage stabilizing diode, a second silicon carbide diode and a current limiting resistor. ​ The linear voltage stabilizer is connected with an auxiliary power supply, the positive electrode of the stabilizing diode is connected with the ground, the positive electrode of the second silicon carbide diode is connected with a current-limiting resistor and the negative electrode of the stabilizing diode respectively, the current-limiting resistor is connected with the output end of the linear voltage stabilizer in series, and the negative electrode of the second silicon carbide diode is connected with the D end of the first test seat.

4. The apparatus of claim 1, wherein: the wide bandgap semiconductor device is a gallium nitride based device. The signal generating unit comprises a waveform generator and a radio frequency signal line, and the waveform generator is connected with the dynamic on-resistance test unit through the radio frequency signal line.

5. The apparatus of claim 3, wherein: the first and second electrodes are configured to be connected to a power supply; and the third electrode is configured to be connected to a load. The test loop comprises a capacitor-resistor array, the input end of the capacitor-resistor array is connected with a high-voltage power supply, and the output end is connected with the main circuit of the test loop.

6. A method for testing the dynamic on-resistance of a wide bandgap semiconductor device, implemented on the basis of a device for testing the dynamic on-resistance of a wide bandgap semiconductor device according to any one of claims 1 to 5, characterized in that, The method comprises the following steps: Step S1: according to the test requirements, the key switch is adjusted, the test circuit of the dynamic on-resistance test unit is adjusted, the selected inductive load or resistive load is connected through the wiring terminal, and the required voltage and current probes are connected to the test position; Step S2: the test conditions and signal acquisition conditions are set in the interactive control system, the auxiliary power supply is turned on without connecting the device under test and the companion device, the trigger button and the waveform generation button are clicked in sequence, the gate-source voltage of the first test seat and the second test seat under no-load is observed, the resistance value of the slide rheostat at the output end of the first adjustable voltage stabilizer and the second adjustable voltage stabilizer is adjusted, and after the positive voltage and the negative voltage of the gate-source voltage are adjusted to the rated value of the device under test, the auxiliary power supply is turned off; Step S3: when the test circuit is a soft switch, the G, D and S ends of the companion device are inserted into the G, D and S three ends of the second test seat; when the test circuit is a hard switch, the positive electrode and the negative electrode of the first silicon carbide diode are inserted into the S and D ends of the second test seat respectively; Step S4: the auxiliary power supply and the high-voltage power supply are turned on in sequence through the interactive control system, the high-voltage power supply indicator light is turned on, the trigger button and the waveform generation button are clicked in sequence, and the clamping voltage, the drain-source voltage, the drain-source current, the gate-source voltage waveform and the dynamic on-resistance waveform of the device under test are obtained; Step S5: after the test is completed, the high-voltage power supply is turned off through the interactive control system, and after the high-voltage power supply indicator light is extinguished, the auxiliary power supply is turned off; Step S6: after the test process is completed through the interactive control system, all experimental data are viewed and analyzed, and the dynamic on-resistance change of the device under test under the preset test conditions is judged.

7. The method of claim 6, wherein: the wide bandgap semiconductor device is a power MOSFET. The test conditions and signal acquisition conditions required in step S2 include: the forward conduction voltage drop of the second silicon carbide diode, the on-pulse width, the off-pulse width, the double-pulse cumulative test number, the test time interval, the high-voltage power supply output voltage, the auxiliary power supply output voltage, the amplification multiple and bandwidth of various probes, the signal sampling rate, and the sampling trigger condition.

8. The method of claim 6, wherein the method further comprises: The expression for calculating the dynamic on-resistance change curve of the device under test with time in step S6 is: ； wherein, Vclamp is the clamping voltage across the drain and source of the device under test in the clamp circuit; Vf2 is the forward voltage drop of the second silicon carbide diode in the clamp circuit; Ids is the drain-to-source current flowing through the device under test when the device under test is turned on.

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