Anti-crosstalk ignition fault arc detection device and method

Abstract

The invention discloses an anti-crosstalk ignition fault arc detection device and method, relates to an intelligent power grid, and solves the problem that the existing fault arc detection cannot correctly distinguish the source of electromagnetic noise to cause the malfunction of fault arc protection equipment. According to the technical scheme, the method comprises the following steps: acquiring signals based on a pair of current sensors arranged on an internal electrical circuit to obtain a first analog signal and a second analog signal; performing digital shaping on the first analog signal and the second analog signal based on a pair of signal waveform digital shaping devices to obtain a first high-low level signal and a second high-low level signal; synchronously capturing the first digital signal and the second digital signal based on a timing clock and a pair of waveform capturing circuits to obtain a first high-low level waveform sequence and a second high-low level waveform sequence; the first high-low level waveform sequence and the second high-low level waveform sequence are matched and compared based on a waveform judgment circuit, and a signal source is determined; the problems are solved.

Description

Technical Field

[0001] The present invention relates to a smart grid, and more particularly, to a crosstalk-resistant fire-causing fault arc detection device and method. Background Art

[0002] Arc fault detection technology is a key technology for resolving electrical fires caused by aging electrical circuits and poor contact. This technology has been proposed for nearly four decades, and the world's first product standard UL1699 (AFCI) was formulated over 25 years ago. Its promotion and application has also been over 20 years. However, its global application has not yet become widespread. A key reason is that arc fault protection devices are prone to misoperation, and abnormal tripping and power outages affect consumers' living experience.

[0003] When detecting arc faults, one of the difficulties is the impact of grid crosstalk signals on detection reliability. Since the phase and neutral lines of all load electrical circuits in the same substation of the AC power grid are connected, the load changes and switching actions generated by a large number of loads, the coupling signals of the electromagnetic field in space, and especially the high-frequency electromagnetic noise signals generated by an increasing number of power electronic circuits will be transmitted along the electrical lines to various electrical locations, including arc fault protection equipment. This high-frequency electromagnetic noise is very easy to be confused with the signal when the arc fault occurs. Secondly, the working goal of the arc fault protection equipment is to protect the lines on the load side from fire. When the arc fault of the electrical line occurs on the power supply bypass side, it is not allowed to operate. Therefore, whether it is possible to correctly and reliably identify whether this high-frequency electromagnetic noise comes from the load side or the external crosstalk signal on the power supply side is a key problem to ensure the reliability of the arc fault protection equipment. For example Figure 1 As shown, Figure 1 This is a schematic diagram of an existing arc fault protection device. Both the load side and the power supply side may generate high-frequency electromagnetic signals and transmit them to the arc fault protection device, but only the high-frequency electromagnetic signals on the load side need to be processed.

[0004] The impact of external crosstalk signals on the power supply side on arc fault detection is primarily concentrated in the following two aspects: 1. The external crosstalk signal on the power supply side is very similar in form to the arc fault signal, which can easily cause the arc fault detection to malfunction. 2. Even if an arc fault actually occurs on the external bypass electrical line, it should not cause the arc fault protection device to operate. In short, existing arc fault detection cannot accurately distinguish the source of electromagnetic noise, that is, whether the external crosstalk comes from the load side or the power supply side, which can easily cause the arc fault protection device to malfunction.

[0005] Therefore, the present application provides a crosstalk-resistant fire-causing fault arc detection device and method to solve the above-mentioned problems. Summary of the Invention

[0006] The purpose of this application is to provide a crosstalk-resistant fire-causing fault arc detection device and method to solve the problem that the existing fault arc detection cannot correctly distinguish the source of electromagnetic noise, that is, external crosstalk from the load side or the power supply side, causing the fault arc protection device to malfunction; this application uses dual current sensors at different positions to detect high-frequency signals on the line respectively, and then uses a signal processing circuit to determine whether there is an external crosstalk signal to solve the above problem.

[0007] The present application first provides an anti-crosstalk fire-causing fault arc detection device, including: a pair of current sensors: a first sensor and a second sensor, the first sensor and the second sensor are located on the internal electrical circuit of the fault arc protection device and are a certain distance apart, the first sensor first collects the signal from the external power supply side, and the second sensor first collects the signal from the internal load side; a pair of signal waveform digital shapers: a first signal waveform digital shaper and a second signal waveform digital shaper, the first signal waveform digital shaper is connected to the first sensor, and the second signal waveform digital shaper is connected to the second sensor; a pair of waveform capture circuits: a first waveform capture circuit and a second waveform capture circuit, the first waveform capture circuit is connected to the first signal waveform digital shaper, and the second waveform capture circuit is connected to the second signal waveform digital shaper; a waveform judgment circuit, connected to the first waveform capture circuit and the second waveform capture circuit, for determining the signal source through waveform matching timing comparison, and deciding whether to perform subsequent fault arc identification according to the signal source; a timing clock, connected to the first waveform capture circuit, the second waveform capture circuit and the waveform judgment circuit.

[0008] In a possible implementation, there is only a wire between the first sensor and the second sensor, and the wires have the same specifications.

[0009] In a possible implementation, the signal waveform digital shaper uses a digital comparator to convert the analog signals output by the first and second sensors into high and low level signals.

[0010] In one possible embodiment, the waveform capture circuit uses a TDC circuit, which includes: multiple corresponding D flip-flops and delay units, multiple delay units are cascaded to form a delay line to access the high and low level signals output by the signal waveform digital shaper, the D input end of the D flip-flop is connected to the output of the corresponding delay unit, the clock end of the D flip-flop is connected to the timing clock through the clock signal line, the output end of the D flip-flop outputs the latched high and low levels, and multiple D flip-flops constitute a D flip-flop chain, which outputs a latched high and low level waveform sequence.

[0011] In one possible implementation, assume that the arrival time difference of the signals of a pair of current sensors is , time difference In the high and low level waveform sequence, it is reflected as The delay time of each delay unit in the delay line of the TDC circuit is at most , set the capture interval given by the clock to , then the number of D flip-flops in the delay chain of the TDC circuit is .

[0012] In one possible embodiment, a waveform judgment circuit is used to match two high and low level waveform sequences: if for each continuous 1 sequence segment in one high and low level waveform sequence, a matching or approximately matching continuous 1 sequence segment can be found in the other high and low level waveform sequence, and the time difference of the continuous 1 sequence segments remains consistent or approximately consistent, then it indicates that the two high and low level waveform sequences match, and an approximate match means that the sequence length deviation of the continuous 1 sequence segments is less than a threshold, and an approximate consistency means that the deviation of the time difference is less than a threshold; for the two matched high and low level waveform sequences, the current sensor whose signal arrives first is determined based on the time difference between the two high and low level waveform sequences, and whether the signal originates from the external power supply side or the internal load side is determined based on the position of the current sensor that arrives first; and whether to perform subsequent fault arc identification is determined based on the source of the signal.

[0013] In one possible implementation, two high- and low-level waveform sequences are matched; the method includes: assuming that the two high- and low-level waveform sequences include: a first high- and low-level waveform sequence from a first sensor and a second high- and low-level waveform sequence from a second sensor; first assuming that the signal of the first high- and low-level waveform sequence comes first, performing continuous segment matching and position difference comparison on the first high- and low-level waveform sequence and the second high- and low-level waveform sequence; if the continuous segment matches and the position difference is consistent, it indicates that the assumption is established, and the signal comes from the external power supply side; if the assumption that the signal of the first high- and low-level waveform sequence comes first is not established, then assuming that the signal of the second high- and low-level waveform sequence comes first, performing continuous segment matching and position difference comparison on the second high- and low-level waveform sequence and the first high- and low-level waveform sequence; if the continuous segment matches and the position difference is consistent, it indicates that the assumption is established, and the signal comes from the internal load side; if both assumptions are not established, it indicates that the signals are mixed and the direction cannot be determined.

[0014] In one possible implementation, whether to perform arc fault identification is determined based on the signal source; the process includes: a timing clock generates periodic clock pulses, triggering a waveform judgment circuit to perform a signal source identification, and generating a Mask code for controlling the arc fault protection device MCU to filter and process the signal; for signals from the external power supply side, the arc fault identification is not performed, and the Mask code is 0; for signals from the internal load side, the arc fault identification is performed, and the Mask code is 1; for aliased signals with no signal or unidentifiable source, the arc fault identification is not performed, and the Mask code is 0.

[0015] In a possible implementation, the Mask code is used to control the MCU of the arc fault protection device to filter the signal collected by the current sensor, extract only the time slice signal with the Mask code being 1, and shield the time slice signal with the Mask code being 0.

[0016] The present application also provides a crosstalk-resistant fire-causing fault arc detection method, which is executed based on the above-mentioned crosstalk-resistant fire-causing fault arc detection device, and the method includes: S1, based on a pair of current sensors set on the internal electrical circuit, collecting signals to obtain a first analog signal and a second analog signal; S2, based on a pair of signal waveform digital shapers, digitally shaping the first analog signal and the second analog signal respectively, to obtain a first high-low level signal and a second high-low level signal; S3, based on a timing clock and a pair of waveform capture circuits, synchronously capturing the first digital signal and the second digital signal respectively, to obtain a first high-low level waveform sequence and a second high-low level waveform sequence; S4, based on a waveform judgment circuit, matching and comparing the first high-low level waveform sequence and the second high-low level waveform sequence to determine the source of the signal.

[0017] Compared with the prior art, the present application has the following beneficial effects: the anti-crosstalk fire fault arc detection device and method of the present application adopts dual current sensors at different positions to detect high-frequency signals on the line respectively, and then uses the signal processing circuit to determine whether there is an external crosstalk signal; the signal processing circuit is mainly divided into three parts, namely the waveform digital shaper, the waveform capture circuit and the waveform judgment circuit; the waveform digital shaper is used to convert the analog signal collected by the current sensor into high and low level signals according to the set comparison reference voltage and send it to the waveform capture circuit to output a high and low level waveform sequence; the waveform capture circuit is used to accurately record The system records the transmission process of the digital signal on the delay line, accurately captures the timing difference of the signals induced on the two current sensors, and sends the two high- and low-level waveform sequences to the waveform judgment circuit; the waveform judgment circuit is used to judge the source of the high-frequency signal based on the two sets of time-synchronized high- and low-level waveform sequences captured by the waveform capture circuit, thereby judging whether there is an external crosstalk signal; based on the Mask sequence obtained by the above circuit, the MCU of the fault arc protection device shields and filters the sensor analog signal collected by the AD according to the Mask sequence, thereby avoiding malfunction caused by crosstalk and improving the accuracy of fault arc processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, constitute a part of this application, and do not constitute a limitation of the embodiments of the present invention. In the drawings: Figure 1 This is a schematic diagram of the current arc fault protection equipment; Figure 2A schematic diagram of a crosstalk-resistant arc detection device for fire-causing faults provided in an embodiment of the present application; Figure 3 A schematic diagram of a signal waveform digital shaper provided in an embodiment of the present application; Figure 4 A schematic diagram of a simulation signal provided in an embodiment of the present application; Figure 5 A schematic diagram of a waveform capture circuit provided in an embodiment of the present application; Figure 6 A schematic diagram of a single pulse waveform provided in an embodiment of the present application after shaping and capturing; Figure 7 A schematic diagram of a pulse group signal provided in an embodiment of the present application; Figure 8 A schematic diagram of shaping and capturing a multi-pulse signal provided in an embodiment of the present application; Figure 9 A flow chart of a signal source identification algorithm provided in an embodiment of the present application; Figure 10 A schematic diagram of the MCU provided in an embodiment of the present application performing shielding processing on the high-frequency AD data to be processed; Figure 11 A schematic diagram of air conditioner fault arc detection provided by an embodiment of the present application; Figure 12 This is a flow chart of a crosstalk-resistant fire-causing fault arc detection method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0019] Hereinafter, the terms "include" or "may include" as used in various embodiments of the present application indicate the presence of the claimed function, operation, or element, and do not limit the addition of one or more functions, operations, or elements. In addition, as used in various embodiments of the present application, the terms "include", "have" and their cognates are intended only to indicate specific features, numbers, steps, operations, elements, components, or combinations of the foregoing, and should not be understood as first excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing or the possibility of adding one or more features, numbers, steps, operations, elements, components, or combinations of the foregoing.

[0020] In various embodiments of the present application, the expression "or" or "at least one of B or / and C" includes any or all combinations of the words listed simultaneously. For example, the expression "B or C" or "at least one of B or / and C" may include B, may include C, or may include both B and C.

[0021] The expressions used in the various embodiments of the present application (such as "first," "second," etc.) may modify the various components in the various embodiments, but may not limit the corresponding components. For example, the above expressions do not limit the order and / or importance of the elements. The above expressions are merely used to distinguish one element from other elements. For example, a first user device and a second user device refer to different user devices, even though both are user devices. For example, without departing from the scope of the various embodiments of the present application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0022] It should be noted that when a component is described as being “connected” to or “connected to” another component, the first component may be directly connected to the second component, and a third component may be “connected” between the first and second components. Conversely, when a component is described as being “directly connected” to or “directly connected to” another component, it can be understood that there is no third component between the first and second components.

[0023] The terms used in the various embodiments of the present application are only used for the purpose of describing specific embodiments and are not intended to limit the various embodiments of the present application. As used herein, the singular form is intended to also include the plural form, unless the context clearly indicates otherwise. Unless otherwise specified, all terms used herein (including technical terms and scientific terms) have the same meaning as those generally understood by those skilled in the art to which the various embodiments of the present application belong. Terms (such as those defined in generally used dictionaries) will be interpreted as having the same meaning as the contextual meaning in the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning, unless clearly defined in the various embodiments of the present application.

[0024] In order to make the objectives, technical solutions and advantages of this application more clear, the present application is further described in detail below in conjunction with examples and drawings. The schematic implementation methods of this application and their descriptions are only used to explain this application and are not intended to limit this application.

[0025] First, the current arc fault detection technology is described to facilitate those skilled in the art in identifying the improvements of this application. Currently, the most common arc fault detection technology uses current waveforms collected from the circuit and analyzed for waveform distortion to identify the source. This distortion is present not only in low-frequency current signals but also in high-frequency current signals. Because low-frequency current signals are linearly additive, meaning that the current signals of multiple loads are linearly added at the arc fault protection device, if a small current branch experiences an arc fault, it can easily be lost in the overall current. Therefore, the most common technology uses current signal acquisition over a wide frequency band, particularly at high frequencies, to enable sensitive identification of arc faults in small current branches. Regarding the bypass crosstalk issue, although relevant product standards (UL1699, IEC62606, and GB / T31143) include relevant test items, these are essentially specialized treatments tailored to standard test scenarios. There is no fundamental solution for the diverse crosstalk signals encountered in actual applications, presenting a significant obstacle to achieving the reliability and widespread adoption of such products.

[0026] In short, the existing arc fault protection equipment is very easy to confuse the high-frequency crosstalk noise on the external power supply side with the arc fault signal on the internal load side that needs to be identified. Figure 1 The purpose of the present invention is to identify the source of the above signal through circuits and logic to avoid malfunction of the arc fault protection device.

[0027] See Figure 2 As shown, Figure 2 A schematic diagram of a crosstalk-resistant arc fault detection device provided in an embodiment of the present application. The device includes: a pair of current sensors: a first sensor and a second sensor, located a certain distance apart on the internal electrical circuit of the arc fault protection device, with the first sensor first collecting signals from the external power supply side, and the second sensor first collecting signals from the internal load side; a pair of signal waveform digital shapers: a first signal waveform digital shaper and a second signal waveform digital shaper, with the first signal waveform digital shaper connected to the first sensor and the second signal waveform digital shaper connected to the second sensor; a pair of waveform capture circuits: a first waveform capture circuit and a second waveform capture circuit, with the first waveform capture circuit connected to the first signal waveform digital shaper and the second waveform capture circuit connected to the second signal waveform digital shaper; a waveform judgment circuit, connected to the first and second waveform capture circuits, configured to determine the signal source through waveform matching timing comparison and determine whether to perform subsequent arc fault identification based on the signal source; and a timing clock, connected to the first and second waveform capture circuits, and the waveform judgment circuit.

[0028] The detection principle of the arc fault detection device provided by the present invention is to set a pair of current sensors at a certain distance from each other on the internal electrical circuit of the arc fault protection device, and realize signal recognition through the signal processing circuit. Although the transmission speed of high-frequency electromagnetic signals on the line is close to the speed of light, due to the certain amount of distributed capacitance and distributed inductance on the wire, it takes a certain delay for the signal at a certain distance to reach the two sensors. If the signal comes from the load side, the sensor close to the load side will arrive first, and then reach the power supply side sensor after a certain delay; the electromagnetic signal from the power supply side will first reach the sensor close to the power supply side, and then reach the load side after a certain delay. Therefore, it is possible to realize the recognition of high-frequency crosstalk noise on the power supply side and fault arc signals on the load side.

[0029] Specifically, the device includes a pair of current sensors, two digital waveform shapers, and a waveform capture circuit. The current sensor senses the high-frequency current signal on the line, converts it into a voltage signal, and then inputs it into the digital waveform shaper. After shaping, the waveform capture circuit receives the sensor's signal waveform, which is equivalent to taking a snapshot of the waveform. The two sets of time-captured 0 and 1 sequence signals are then input into a logic judgment circuit to determine whether the signal is a crosstalk signal from the external power supply side or a high-frequency arc signal from the load side. If it is an external crosstalk signal, the subsequent arc fault identification process is not performed. Otherwise, arc fault identification is required on the sensor signal. Arc fault identification is performed by the MCU of the arc fault protection device performing A / D conversion on the analog signal collected by the sensor, using the judgment result of the logic judgment circuit.

[0030] A pair of current sensors see Figure 2 As shown, in a possible implementation, there is only a wire between the first sensor and the second sensor, and the wires have the same specifications.

[0031] Specifically, a pair of current sensors of the same specifications, spaced a certain distance apart, are used. One sensor is located closer to the external power supply, while the other is located closer to the load. These sensors simultaneously detect signals on the line. When external crosstalk signals originate from the power supply, the first sensor detects them first; when high-frequency signals originate from the load, the second sensor detects them first. The current sensors can be connected to filters, amplifiers, and other devices as needed to process the signals and output analog signals.

[0032] Signal waveform digital shaper see Figure 3 As shown, Figure 3 Schematic diagram of a digital signal waveform shaper provided in an embodiment of the present application. In one possible implementation, the digital signal waveform shaper uses a digital comparator to convert the analog signals output by the first and second sensors into high and low level signals.

[0033] Specifically, see Figure 4 As shown, Figure 4 A schematic diagram of a simulation signal provided in an embodiment of the present application. Figure 4 It shows an analog signal with a high-frequency pulse impact. After passing through a digital comparator, the analog signal can be shaped into a signal with high and low level changes.

[0034] It should be noted that traditional analog-to-digital conversion of high-frequency signal waveforms mostly uses ADC conversion circuits. However, based on the special application scenarios of the present invention, in order to meet the extremely high waveform matching timing comparison of high-frequency signals, the cost of using high-speed ADC is very high. Therefore, the present invention uses a digital comparator to convert analog waveforms into high and low level waveforms, which has a high conversion rate and low cost. At the same time, it can also reduce the complexity of waveform matching timing comparison implementation, and can directly use logic circuits to perform waveform matching timing comparison at high speed. Figure 2 When the first and second signal waveform digital shapers shown are in operation, signals are obtained from the first and second sensors. The signals pass through the digital comparator. If the signal level is higher than the comparison reference voltage, the digital comparator outputs a high level, otherwise it outputs a low level, forming high and low level waveforms.

[0035] Waveform capture circuit see Figure 5 As shown, in one possible embodiment, the waveform capture circuit adopts a TDC circuit, which includes: multiple corresponding D flip-flops and delay units, multiple delay units are cascaded to form a delay line to access the high and low level signals output by the signal waveform digital shaper, the D input end of the D flip-flop is connected to the output of the corresponding delay unit, the clock end of the D flip-flop is connected to the timing clock through the clock signal line, the output end of the D flip-flop outputs the latched high and low levels, and multiple D flip-flops constitute a D flip-flop chain, which outputs a latched high and low level waveform sequence.

[0036] Furthermore, let the arrival time difference of the signals of a pair of current sensors be , time difference In the high and low level waveform sequence, it is reflected as The delay time of each delay unit in the delay line of the TDC circuit is at most , set the capture interval given by the clock to , then the number of D flip-flops in the delay chain of the TDC circuit is .

[0037] Specifically, due to the volume limitation of the fault arc equipment, the distance between a pair of current sensors cannot be too far apart, generally a few centimeters. According to calculations combined with experiments, the properties of copper wires and insulating PVC layers in low-voltage power distribution scenarios have a current signal transmission rate of approximately 60% of the speed of light, and this delay is approximately at the level of hundreds of picoseconds. Therefore, the present invention needs to meet the requirements of making accurate timing resolution of the signal at the order of hundreds of picoseconds, requiring a high-speed waveform capture circuit that can capture the rapid waveform changes of high-frequency current signals, so as to facilitate the subsequent accurate waveform timing comparison of the signal waveforms input by the two sensors, determine whether the signals obtained by the two sensors are from the same source, and be able to distinguish which sensor waveform arrives first and which sensor waveform lags behind.

[0038] The waveform capture circuit of the present invention applies the TDC principle. The timing clock generates a synchronous clock signal at a certain time interval (such as 1us). Under the action of the synchronous clock edge, the two waveform capture circuits latch the high and low level signals generated by the signal waveform digital shaper into the D flip-flop chain.

[0039] like Figure 5 As shown, to build a high-precision TDC circuit, the present invention utilizes a delay line method, employing buffer gates as delay units. The basic operating principle of a TDC circuit is that high and low-level signals sequentially pass through several delay units. When a clock signal arrives, due to the synchronization of the clock network wiring, the clock input pulse edge reaches all D flip-flops simultaneously, inputting the signal at each instantaneous D input into the D flip-flop. This means that the D flip-flop chain latches the current delay line state. In this invention, the signal output by the digital waveform shaper has a known and uniform time delay after passing through each delay unit. The D flip-flops serve as latching units. When the clock signal arrives, the level state between the buffer gates on the delay line is latched into the Q terminal (output) of the corresponding D flip-flop.

[0040] The high and low levels of the delay line are input into the serial D flip-flop chain, thus generating a set of 01 serial codes on the serial D flip-flop chain of the TDC circuit, which is equivalent to taking a snapshot of the signal waveform on the delay chain.

[0041] For example, for Figure 4 For the single pulse waveform shown, assuming that the pulse exceeds the high-level threshold for 1ns, and if the delay of each delay unit in the delay chain is 33ps, the captured high and low level waveform sequence is roughly as follows: 00…01111111111111111111…11111111111111111111100…0; The first and last bits are both 0, and the number of segments with a pulse high level (i.e., 1) is 1ns / 33ps=30 consecutive segments.

[0042] If the signal is a multi-pulse waveform, there will be multiple sequences of 0s and 1s in the above sequence, similar to the following figure: 00…01111111111111000000011111111111111111111111100000001111111111111111100…0 This sequence represents a waveform with three consecutive 1s, representing a multi-pulse signal with three pulse impacts.

[0043] The present invention utilizes two waveform capture circuits based on the TDC principle. Driven by a timing clock, the circuit captures the high and low level waveform sequences passing through the serial D flip-flop chain at intervals of, for example, 1µs. Considering the size of the arc fault circuit breaker, the installation distance between the pair of current sensors cannot be too far, for example, 0.03 meters. Because the current transmission speed is approximately 60% of the speed of light, that is, about 1.8*10 8 m / s, the arrival time difference between the two sensor signals is approximately 167 picoseconds. If this time difference is Td, for reliability, the TDC circuit must be able to reliably represent this time difference. Specifically, the delay time between each flip-flop in the TDC circuit's delay line must be reliably less than Td to reliably reflect the signal time difference in the output serial code. For example, this time difference must be sufficient to represent a three-bit difference in the serial code. Therefore, the delay of each delay unit in the TDC circuit's delay line must be at most Td / 3. For a 167-picosecond time difference, the delay time of each delay line is at least 167 picoseconds / 3, which is approximately 55 picoseconds. For a 1µs timing capture, the number of D flip-flops in the TDC circuit's delay chain is approximately 18,181, which is 1µs / 55 picoseconds.

[0044] The waveform judgment circuit performs signal source identification. In one possible embodiment, the waveform judgment circuit is used to match two high and low level waveform sequences: if for each continuous 1 sequence segment in one high and low level waveform sequence, a matching or approximately matching continuous 1 sequence segment can be found in the other high and low level waveform sequence, and the time difference of the continuous 1 sequence segments remains consistent or approximately consistent, then it means that the two high and low level waveform sequences are matched. Approximate matching means that the sequence length deviation of the continuous 1 sequence segment is less than a threshold, and approximately consistent means that the deviation of the time difference is less than a threshold; for the two matched high and low level waveform sequences, the current sensor whose signal arrives first is determined based on the time difference between the two high and low level waveform sequences, and whether the signal originates from the external power supply side or the internal load side is determined based on the position of the current sensor that arrives first; and whether subsequent fault arc identification is performed is determined based on the signal source.

[0045] Specifically, the waveform judgment circuit captures two sets of high and low level waveform sequences based on the synchronized clock, corresponding to signals from two sensors. Because the two sensors are separated by only a copper wire with no circuit components, for a pair of sensors with identical parameters, their output analog signal waveforms are identical, as are the shaped high and low level signals. The only difference is the position of the high and low level waveform sequences due to signal delay.

[0046] like Figure 6 As shown in the figure, a single pulse waveform is acquired by a pair of sensors, shaped by a digital signal waveform shaper, and captured by a waveform capture circuit to create a sequence of high and low level waveforms. It can be seen that the two sets of signal waveforms are identical, differing only in timing. Triggered by a timing clock, the waveform capture circuit converts the high and low level signals into a sequence of high and low level waveforms represented by a sequence of 0s and 1s. The binary code sequences are identical, indicating that they originate from the same signal source. The timing relationship of the consecutive 1s in high and low level waveform sequence 1 and high and low level waveform sequence 2 indicates which signal arrived first. By comparing the sensor positions, it is possible to determine whether the signal originates from the power supply side or the load side, thereby making a decision on arc detection.

[0047] like Figure 7 As shown in Figure 1, arc or interference signals in reality usually appear as pulse group signals. Figure 8 The figure shows the high and low level signals of a multi-pulse signal and the corresponding high and low level waveform sequences (high and low level waveform sequence 1 and high and low level waveform sequence 2). A careful analysis shows that if high and low level waveform sequence 2 is scanned first, three consecutive 1 segments are encountered. Then, high and low level waveform sequence 1 is scanned and a consecutive 1 segment of equal length is also found, with a time interval of 13. High and low level waveform sequence 2 is scanned again and a consecutive 1 segment of 6 is encountered. High and low level waveform sequence 1 is scanned again and a consecutive 1 segment of 6 is also encountered. If a sequence segment of consecutive 1s with the same or similar width can be found in the other sequence, they may be matching high pulse segments. If a matching sequence segment can be found for each such consecutive 1 sequence segment, and their time difference remains consistent, it means that the two waveforms are matched, and the source of the signal can be deduced from the relationship between the time differences. For example, if the high-low level waveform sequence 1 is the load side signal waveform and lags behind the high-low level waveform sequence 2 in timing, it means that the signal source is the power supply side crosstalk signal and does not enter the subsequent fault arc identification to avoid misjudgment; if on the contrary, the high-low level waveform sequence 1 is the power supply side signal waveform and also lags behind the high-low level waveform sequence 2, it means that the signal source is the load side and needs to enter the subsequent fault arc identification.

[0048] Furthermore, the two high and low level waveform sequences are matched; including: assuming that the two high and low level waveform sequences include: a first high and low level waveform sequence from a first sensor and a second high and low level waveform sequence from a second sensor; first assuming that the signal of the first high and low level waveform sequence comes first, performing continuous one-segment matching and position difference comparison on the first high and low level waveform sequence and the second high and low level waveform sequence; if continuous one-segment matching and the position difference are consistent, it indicates that the assumption is established, and the signal comes from the external power supply side; if the assumption that the signal of the first high and low level waveform sequence comes first is not established, then assuming that the signal of the second high and low level waveform sequence comes first, performing continuous one-segment matching and position difference comparison on the second high and low level waveform sequence and the first high and low level waveform sequence; if continuous one-segment matching and the position difference are consistent, it indicates that the assumption is established, and the signal comes from the internal load side; if both assumptions are not established, it indicates that the signal is mixed and the direction cannot be determined.

[0049] Specifically, if Figure 9 As shown in the figure (the two high- and low-level waveform sequences are referred to as Serial Code 1 and Serial Code 2), the waveform judgment circuit implements the following signal source identification algorithm: First, assume that the Serial Code 1 signal comes first and begin scanning Serial Code 1. If a segment of continuous 1s is found, the length of this segment is recorded. Then, scan the segments of continuous 1s in Serial Code 2 and compare their lengths to see if they are equal (accounting for digitization errors, a length deviation of ±1 is allowed). This indicates a segment match, and the position difference of the matching segments is recorded. Scanning the next segment of continuous 1s continues. If no matching segment is found for any of the segments of Serial Code 1, an error is assumed and scanning proceeds, with Serial Code 2 in the first position. If all the segments of continuous 1s in Serial Code 1 find a matching segment in Serial Code 2, and the position differences of all matching segments are consistent (approximately ±1 is allowed), the delays are equal, the assumption holds, and the signal source is the external power supply. If the assumption that the Serial Code 1 signal comes first does not hold, scan Serial Code 2 again and perform the same matching of the segments of continuous 1s. If all segments are matched successfully and the position differences are equal, the signal source is the load. If neither assumption is true, it means that the signal is aliased and the direction cannot be determined.

[0050] Furthermore, whether to perform arc fault identification is determined based on the signal source; this includes: a timing clock generates periodic clock pulses, triggering a waveform judgment circuit to perform a signal source identification, and generating a Mask code for controlling the arc fault protection device MCU to filter and process the signal; for signals from the external power supply side, the arc fault identification is not entered, and the Mask code is 0; for signals from the internal load side, the arc fault identification is entered, and the Mask code is 1; for aliased signals with no signal or unidentifiable source, the arc fault identification is not entered, and the Mask code is 0.

[0051] Specifically, the synchronous clock generates a clock pulse every 1µs, triggering a signal source check and generating a corresponding 1-bit mask code. There are three signal source scenarios: a signal from the external power supply side is ignored, with a mask code of 0; a signal from the internal load side requires processing, with a mask code of 1; and no signal requires no processing, also with a mask code of 0.

[0052] Because the synchronization clock interval is very short (1us), the probability of signal aliasing is very low, and the source direction can mostly be effectively determined. Therefore, it can effectively prevent misjudgment caused by crosstalk noise on the power supply side, and can effectively extract the fault arc signal, thereby improving the reliability of fault arc identification.

[0053] Furthermore, the Mask code is used to control the MCU of the arc fault protection device to filter the signal collected by the current sensor, extracting only the time slice signal with the Mask code being 1 and shielding the time slice signal with the Mask code being 0.

[0054] Specifically, the MCU of the arc fault protection device extracts the arc fault signal according to the mask sequence (composed of the mask code) to perform arc fault identification. Figure 2 The device shown uses a clock pulse generated by a timing clock to trigger a waveform judgment circuit to perform signal source identification. For example, signal source identification is performed once every 1us, a mask code is generated based on the identification result, and the above identification result is transmitted to the MCU of the arc fault protection device. The MCU of the arc fault protection device generally makes identification judgments based on the half-cycle period of the power frequency AC. For a 50Hz power frequency line, the time interval is 10ms. With the help of the mask sequence of valid or ignored signal periods generated every 1us, the MCU performs shielding processing on the high-frequency AD data to be processed, such as Figure 10 As shown in the figure, the MCU of the arc fault protection device filters the raw signal collected by the current sensor using the mask sequence output by the waveform judgment circuit. It extracts only the time-slice signals where the mask sequence is 1, and blocks the time-slice signals where the mask sequence is 0. The final software algorithm identifies the fault by blocking crosstalk or unidentifiable aliased signals on the power supply side, retaining only the high-frequency signals on the load side. This not only improves identification reliability but also helps enhance arc detection accuracy.

[0055] It is understood that the crosstalk-resistant arc fault detection device of the present application utilizes dual current sensors at different locations in its hardware circuitry to detect high-frequency signals on the line. The signal processing circuit then determines whether external crosstalk signals are present. The signal processing circuit primarily consists of three components: a waveform digital shaper, a waveform capture circuit, and a waveform determination circuit. The waveform digital shaper converts the analog signal collected by the current sensor into high- and low-level signals based on a set reference voltage, feeding these signals into the waveform capture circuit, which then outputs a sequence of high- and low-level waveforms. The waveform capture circuit accurately records the transmission of digital signals along the delay line and precisely captures the timing differences between the signals sensed by the two current sensors. The waveform determination circuit then determines the source of the high-frequency signal based on the two time-synchronized high- and low-level waveform sequences captured by the waveform capture circuit, thereby determining whether external crosstalk signals are present. Finally, based on the Mask sequence obtained by the above circuit, the MCU of the arc fault protection device shields and filters the sensor analog signal collected by the AD according to the Mask sequence, thereby avoiding false operation caused by crosstalk and improving the accuracy of arc fault processing.

[0056] See Figure 11 As shown, Figure 11 This is a schematic diagram of air conditioner fault arc detection provided by the embodiment of the present application. Figure 11 As shown, after completing the hardware connection, the following internal steps are performed: 1. The waveform judgment circuit identifies the order of the two sensor signals. If it is determined that there is an external crosstalk signal on the line, then no fault arc judgment is performed at this time. Otherwise, it is considered that the noise on the line at this time comes from the air conditioner load, and a fault arc judgment is required. 2. If it is confirmed that a fault arc judgment is required, the sensor signal after filtering and amplification by the signal processing circuit is sent to the MCU. 3. The MCU uses the mask sequence generated by the waveform judgment circuit at a time interval of 10ms to filter the signal collected by the AD. 4. The MCU runs the existing software algorithm to extract feature quantities. 5. The extracted feature quantities are sent to the existing arc recognition model, and the presence of a fault arc is determined based on the feature quantities and the model.

[0057] Similarly, it can also be expanded to other types of household appliance load scenarios and applied to general-purpose arc fault circuit interrupters (AFCI / AFDD).

[0058] See Figure 12 , Figure 12 The flowchart of the anti-crosstalk fire fault arc detection method provided in the embodiment of the present application is based on the following Figure 2The anti-crosstalk fire fault arc detection device shown is executed, and the method includes: S1, based on a pair of current sensors set on the internal electrical circuit to collect signals, obtain a first analog signal and a second analog signal; S2, based on a pair of signal waveform digital shapers, digitally shape the first analog signal and the second analog signal respectively, to obtain a first high-low level signal and a second high-low level signal; S3, based on a timing clock and a pair of waveform capture circuits, synchronously capture the first digital signal and the second digital signal respectively, to obtain a first high-low level waveform sequence and a second high-low level waveform sequence; S4, based on a waveform judgment circuit, match and compare the first high-low level waveform sequence and the second high-low level waveform sequence to determine the signal source.

[0059] Specifically, the crosstalk-resistant fire-causing fault arc detection method provided by the present invention utilizes a pair of waveform capture circuits, driven by a timing clock, to synchronously capture high and low level waveform sequences, such as every 1us. The signal source judgment circuit matches and compares the two groups of 0 and 1 sequences. If the waveforms are identical or highly similar, the timing sequence relationship of the two groups of waveforms is determined. If the waveform proves that the signal comes from the load side, the subsequent fault arc identification is carried out; if the signal waveform comes from the external power supply side, the identification of this time slice is abandoned, thereby eliminating the interference of external crosstalk signals and improving the reliability of fault arc detection. If the signal comes from two directions, the waveforms will be mixed together and matching cannot be achieved, indicating that the time slice is mixed with noise, and identification is also abandoned.

[0060] It can be seen that the crosstalk-resistant fire-causing fault arc detection device and method provided in the present application can improve the detection accuracy and reliability of fault arcs occurring on the line while eliminating external noise interference.

[0061] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A crosstalk-resistant arc detection device for fire-causing faults, characterized in that: include: A pair of current sensors: a first sensor and a second sensor, wherein the first sensor and the second sensor are located on an internal electrical circuit of the arc fault protection device and are a certain distance apart, wherein the first sensor first collects a signal from the external power supply side, and the second sensor first collects a signal from the internal load side; a pair of signal waveform digital shapers: a first signal waveform digital shaper and a second signal waveform digital shaper, wherein the first signal waveform digital shaper is connected to the first sensor, and the second signal waveform digital shaper is connected to the second sensor; a pair of waveform capture circuits: a first waveform capture circuit and a second waveform capture circuit, wherein the first waveform capture circuit is connected to the first signal waveform digital shaper, and the second waveform capture circuit is connected to the second signal waveform digital shaper; a waveform judgment circuit, connected to the first waveform capture circuit and the second waveform capture circuit, for determining the signal source by waveform matching timing comparison, and deciding whether to perform subsequent fault arc identification according to the signal source; A timing clock is connected to the first waveform capture circuit, the second waveform capture circuit and the waveform judgment circuit.

2. The crosstalk-resistant arc detection device for fire-causing faults according to claim 1, characterized in that: There is only a wire between the first sensor and the second sensor, and the wires are of the same gauge.

3. The crosstalk-resistant arc detection device for fire-causing faults according to claim 1, characterized in that: The signal waveform digital shaper adopts a digital comparator to convert the analog signals output by the first and second sensors into high and low level signals.

4. The crosstalk-resistant arc detection device for fire-causing faults according to claim 1, characterized in that: The waveform capture circuit adopts a TDC circuit, which includes: multiple corresponding D flip-flops and delay units. The multiple delay units are cascaded to form a delay line to access the high and low level signals output by the signal waveform digital shaper. The D input end of the D flip-flop is connected to the output of the corresponding delay unit, the clock end of the D flip-flop is connected to the timing clock through a clock signal line, and the output end of the D flip-flop outputs the latched high and low levels. The multiple D flip-flops form a D flip-flop chain, which outputs a latched high and low level waveform sequence.

5. The anti-crosstalk fire fault arc detection device according to claim 4 is characterized in that The arrival time difference of the signals from a pair of current sensors is , time difference In the high and low level waveform sequence, it is reflected as The delay time of each delay unit in the delay line of the TDC circuit is at most , set the capture interval given by the clock to , then the number of D flip-flops in the delay chain of the TDC circuit is .

6. The crosstalk-resistant arc detection device for fire-causing faults according to claim 1, characterized in that: The waveform judgment circuit is used to match two high- and low-level waveform sequences: if for each continuous 1-sequence segment in one high- and low-level waveform sequence, a matching or approximately matching continuous 1-sequence segment can be found in the other high- and low-level waveform sequence, and the time difference of the continuous 1-sequence segments remains consistent or approximately consistent, then it is indicated that the two high- and low-level waveform sequences match. The "approximate match" means that the sequence length deviation of the continuous 1-sequence segments is less than a threshold value, and the "approximate consistency" means that the deviation of the time difference is less than a threshold value. For two matching high and low level waveform sequences, the current sensor whose signal arrives first is determined based on the time difference between the two high and low level waveform sequences, and whether the signal originates from the external power supply side or the internal load side is determined based on the position of the current sensor that arrives first. Whether to perform subsequent arc fault identification is determined based on the signal source.

7. The crosstalk-resistant arc detection device for fire-causing faults according to claim 6, characterized in that: Match two high and low level waveform sequences; including: Assume that the two high and low level waveform sequences include: a first high and low level waveform sequence from a first sensor and a second high and low level waveform sequence from a second sensor; First, assume that the signal of the first high-low level waveform sequence comes first, and perform continuous segment matching and position difference comparison on the first high-low level waveform sequence and the second high-low level waveform sequence. If the continuous segments match and the position differences are consistent, it means that the assumption is valid and the signal comes from the external power supply side; If the assumption that the signal of the first high-low level waveform sequence comes first is not true, then assume that the signal of the second high-low level waveform sequence comes first. Perform continuous segment matching and position difference comparison on the second high-low level waveform sequence and the first high-low level waveform sequence. If the continuous segment matches and the position difference is consistent, it means that the assumption is true and the signal comes from the internal load side. If neither assumption is established, it means that the signal is aliased and the direction cannot be determined.

8. The crosstalk-resistant arc fault detection device according to claim 6, characterized in that: Decide whether to perform arc fault identification based on the signal source; include: The timing clock generates periodic clock pulses, triggering the waveform judgment circuit to identify the signal source and generate a mask code to control the MCU of the arc fault protection device to filter and process the signal; For signals from the external power supply side, arc fault identification is not performed and the Mask code is 0; For the signal from the internal load side, it enters the fault arc identification, and the Mask code is 1; For aliased signals with no signal or unidentifiable source, arc fault identification is not performed and the Mask code is 0.

9. The crosstalk-resistant arc detection device for fire-causing faults according to claim 8, characterized in that: The Mask code is used to control the MCU of the arc fault protection device to filter the signal collected by the current sensor, extract only the time slice signal with the Mask code being 1, and shield the time slice signal with the Mask code being 0.

10. A crosstalk-resistant arc fault detection method, characterized in that: Based on the anti-crosstalk fire fault arc detection device according to any one of claims 1 to 9, the method includes: S1. Collecting signals based on a pair of current sensors provided on an internal electrical circuit to obtain a first analog signal and a second analog signal; S2. Digitally shaping the first analog signal and the second analog signal using a pair of signal waveform digital shapers to obtain first high-low level signals and second high-low level signals; S3, synchronously capturing the first digital signal and the second digital signal based on a timing clock and a pair of waveform capture circuits, respectively, to obtain a first high-low level waveform sequence and a second high-low level waveform sequence; S4. Based on the waveform judgment circuit, the first high-low level waveform sequence and the second high-low level waveform sequence are matched and compared to determine the signal source.

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