A single-phase energy storage inverter parallel grid wiring detection method

Abstract

The application discloses a kind of single-phase energy storage inverter parallel connection time grid wiring detection method, method is applied to inverter grid, inverter grid includes multiple parallel connection and be connected to inverter module of grid, method includes: each inverter module is based on the voltage waveform of grid bus and generates level signal by built-in digital signal processor;Grid bus generates total level signal according to the level signal output by each inverter module;At least one inverter module is captured in real time to total level signal by enhanced capture module in digital signal processor, and the time difference value of high level duration and low level duration in preset time window is calculated to total level signal;At least one inverter module obtains grid wiring detection result according to time difference value, and grid wiring detection result is used to determine whether wiring error exists in each inverter module in inverter grid, realizes fast identification wiring error and improves system security.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power electronics, in particular to a grid connection detection method for single-phase energy storage inverters in parallel. BACKGROUND

[0002] Currently, with the rapid development of renewable energy such as solar energy and wind energy, the proportion of distributed power generation systems in the energy structure has significantly increased. As the core equipment of distributed energy systems, single-phase energy storage inverters are responsible for converting the direct current of energy storage batteries into alternating current and operating in parallel with the grid. The reliability and safety of their operation directly affect the stability of the entire energy system. In actual applications, to improve system capacity and redundancy, multiple inverter modules are often used in parallel. However, when the grid connection (L line and N line) of a certain inverter module is accidentally reversed, although the system may temporarily operate normally in grid-connected state, when switching to off-grid mode, the voltage waveform output by the reversed module will form a 180° phase difference with other modules, causing a short circuit fault and safety hazards. SUMMARY

[0003] The purpose of the present application is to provide a grid connection detection method for single-phase energy storage inverters in parallel, which can accurately detect the parallel connection state of multiple inverter modules in real time, quickly identify connection errors, and improve system safety.

[0004] The present application provides a grid connection detection method for single-phase energy storage inverters in parallel. The method is applied to an inverter grid, which includes multiple inverter modules connected in parallel to the grid. The L interface and N interface of each inverter module are connected to the L line and N line of the grid bus, respectively. The method includes: each inverter module samples the voltage waveform of the grid bus in real time through a built-in digital signal processor, and generates a level signal based on the phase angle of the voltage waveform; the grid bus performs logical AND operation on the level signals output by each inverter module through a hardware AND gate circuit, generating a total level signal; at least one inverter module captures the total level signal in real time through an enhanced capture module in the digital signal processor, and calculates the time difference between the high-level duration and the low-level duration of the total level signal within a preset time window; at least one inverter module obtains a grid connection detection result according to the time difference, which is used to determine whether there is a connection error in each inverter module in the inverter grid.

[0005] In some embodiments, generating a level signal based on the phase angle of the voltage waveform includes: outputting a high-level signal to the grid bus through the L interface when the phase angle of the voltage waveform is between 0° and 180°; outputting a low-level signal to the grid bus through the N interface when the phase angle of the voltage waveform is between 180° and 360°.

[0006] In some embodiments, the at least one inverter module obtains the grid connection detection result according to the time difference value, including: the at least one inverter module compares the time difference value with a preset threshold; if the time difference value is less than the preset threshold, a grid connection detection result is obtained, which indicates that there is no wiring error in each inverter module in the inverter grid; if the time difference value is greater than or equal to the preset threshold, a grid connection detection result is obtained, which indicates that there is a wiring error in each inverter module in the inverter grid.

[0007] In some embodiments, the time difference value between the high-level duration and the low-level duration of the total level signal in the preset time window is calculated, including: the rising edge and the falling edge of the total level signal in the preset time window are recorded by the enhanced capture module; based on the time stamp, the high-level duration and the low-level duration are accumulated respectively, and the time difference value between the two is calculated.

[0008] In some embodiments, after obtaining the grid connection detection result indicating that there is a wiring error in each inverter module in the inverter grid, the method further includes: controlling the DC side relay of the inverter grid to disconnect the energy storage battery from the inverter circuit; controlling the AC side relay of the inverter grid to cut off the physical connection between the inverter and the grid; activating the LED indicator light on the inverter panel of the inverter grid, and generating an alarm signal containing the fault module number.

[0009] In some embodiments, the preset time window includes a plurality of consecutive power frequency periods, and based on the time stamp, the high-level duration and the low-level duration are accumulated respectively, and the time difference value between the two is calculated, including: based on the time stamp, the positive half cycle duration and the negative half cycle duration of each power frequency period are accumulated and counted, and the average positive half cycle duration and the average negative half cycle duration are calculated; the time difference value is calculated according to the average positive half cycle duration and the average negative half cycle duration.

[0010] In some embodiments, the method further includes: calculating the first standard deviation of the positive half cycle duration and the second standard deviation of the negative half cycle duration in a plurality of periods; and dynamically setting the preset threshold for comparing the time difference value according to the first standard deviation and the second standard deviation.

[0011] In some embodiments, the at least one inverter module obtains the grid connection detection result according to the time difference value, further including: each inverter module sends its own wiring detection result through the communication bus, receives the detection results of other inverter modules and compares them, and if more than half of the modules correspond to the grid connection detection result indicating that there is a wiring error, it is confirmed that there is a global wiring error in the inverter grid.

[0012] In some embodiments, the preset time window is set to a range of 1 second to 5 seconds, and at least contains 10 sampling data of power frequency periods.

[0013] In some embodiments, the method further comprises: after the first obtained power grid connection detection result represents that there is a connection error, re-executing the power grid connection detection method after a delay preset time; if the power grid connection detection results obtained continuously for multiple times all represent that there is a connection error, locking a fault state of the inverter grid, and prohibiting grid-connected processing until manual reset.

[0014] In summary, the power grid connection detection method and system for single-phase energy storage inverters in parallel provided by the present application generates a level signal by each inverter module and aggregates the level signals into a total level signal, calculates and judges the time difference value, and detects the connection state of multiple modules in parallel in real time, avoids the short circuit risk caused by connection errors, and can accurately detect the connection state of multiple inverter modules in parallel in real time, quickly identify connection errors, and improve system safety. BRIEF DESCRIPTION OF DRAWINGS

[0015] The accompanying drawings are used to provide a further understanding of the technical solutions of the present application, and constitute a part of the specification, and are used to explain the technical solutions of the present application together with embodiments of the present application, and do not constitute a limitation on the technical solutions of the present application.

[0016] The present application is further described below in combination with the drawings and embodiments;

[0017] Figure 1 The step schematic diagram of the power grid connection detection method for single-phase energy storage inverters in parallel provided by the embodiment of the present application is shown in the figure.

[0018] Figure 2 The step schematic diagram of the power grid connection detection method for single-phase energy storage inverters in parallel provided by the embodiment of the present application is shown in the figure.

[0019] Figure 3 The step schematic diagram of the power grid connection detection method for single-phase energy storage inverters in parallel provided by the embodiment of the present application is shown in the figure.

[0020] Figure 4 The step schematic diagram of the power grid connection detection method for single-phase energy storage inverters in parallel provided by the embodiment of the present application is shown in the figure.

[0021] Figure 5 The step schematic diagram of the power grid connection detection method for single-phase energy storage inverters in parallel provided by the embodiment of the present application is shown in the figure.

[0022] Figure 6 The step schematic diagram of the power grid connection detection method for single-phase energy storage inverters in parallel provided by the embodiment of the present application is shown in the figure.

[0023] Figure 7The single-phase energy storage inverter parallel connection grid wiring detection method provided by the embodiment of the present application includes a schematic diagram of correct connection of the inverter module;

[0024] Figure 8 The single-phase energy storage inverter parallel connection grid wiring detection method provided by the embodiment of the present application includes a waveform diagram of correct connection of the inverter module;

[0025] Figure 9 The single-phase energy storage inverter parallel connection grid wiring detection method provided by the embodiment of the present application includes a schematic diagram of incorrect connection of the inverter module;

[0026] Figure 10 The single-phase energy storage inverter parallel connection grid wiring detection method provided by the embodiment of the present application includes a waveform diagram of incorrect connection of the inverter module. DETAILED DESCRIPTION

[0027] The technical solutions in the present application will be described in detail below with reference to the drawings in the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. The components of the present application described and shown in the drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. It should be noted that: similar reference numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. Meanwhile, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0028] In the prior art, at present, with the rapid development of renewable energy such as solar energy and wind energy, the proportion of distributed power generation system in energy structure has been significantly improved. As the core equipment of distributed energy system, single-phase energy storage inverter undertakes the key task of converting the direct current of energy storage battery into alternating current and parallel operation with the grid, and its reliability and safety directly affect the stability of the entire energy system. In practical application, in order to improve the system capacity and redundancy, multiple inverter modules are often used in parallel operation. However, when the grid wiring (L line and N line) of a certain inverter module is connected reversely, although the system may temporarily operate normally in grid-connected state, when switching to off-grid mode, the voltage waveform output by the reversely connected module will form a 180° phase difference with other modules, resulting in short circuit fault and safety hazard.

[0029] The application will be described in detail below with reference to the drawings.

[0030] Reference Figure 1 , Figure 1 A step schematic diagram of a grid connection detection method for single-phase energy storage inverters in parallel is provided for an embodiment of the application. The application provides a grid connection detection method for single-phase energy storage inverters in parallel. The method is applied to an inverter grid, which includes a plurality of inverter modules connected in parallel to the grid. The L interface and the N interface of each inverter module are connected to the L line and the N line of the grid bus, respectively. The method includes the following steps:

[0031] In step S110, each inverter module samples the voltage waveform of the grid bus in real time through a built-in digital signal processor, and generates a level signal based on the phase angle of the voltage waveform.

[0032] In step S120, the grid bus performs logical AND operation on the level signals output by each inverter module through a hardware AND gate circuit, to generate a total level signal.

[0033] In step S130, at least one inverter module captures the total level signal in real time through an enhanced capture module in the digital signal processor, and calculates the time difference between the high-level duration and the low-level duration of the total level signal within a preset time window.

[0034] In step S140, at least one inverter module obtains a grid connection detection result according to the time difference, which is used to determine whether there is a wiring error in each inverter module in the inverter grid.

[0035] The real-time sampling of the voltage waveform of the grid bus by the digital signal processor refers to obtaining the instantaneous value of the grid voltage through an analog-to-digital conversion module at a fixed sampling rate. Specifically, a successive approximation type ADC module can be used to achieve this, and the sampling frequency can be tens of times the power frequency. The generation of the level signal based on the phase angle refers to determining the positive and negative half-cycle states according to the zero-crossing point of the voltage waveform. For example, when the voltage is in the positive half-cycle, a high level is output, and when the voltage is in the negative half-cycle, a low level is output. The hardware AND gate circuit refers to a circuit composed of transistors or logic gate chips, which can perform parallel processing on the level signals output by each module. Specifically, a collector open gate circuit can be used to ensure that the total level signal remains low when any module outputs a low level. The enhanced capture module refers to a hardware unit with edge detection and timestamp recording functions. Specifically, a timer input capture channel can be used in combination with an interrupt mechanism to accurately record the time of the rising edge and the falling edge of the signal.

[0036] In some embodiments, each inverter module collects grid bus voltage through a voltage transformer, and inputs a digital signal to a digital signal processor through a conditioning circuit. The processor converts the sinusoidal voltage into a square wave signal, outputs a high level through the L line when the voltage phase is in the positive half cycle, and outputs a low level through the N line when the voltage phase is in the negative half cycle. The level signals of all modules are connected to a hardware AND gate circuit, and when any module outputs a low level during the positive half cycle, the total level signal is forced to be low. The capture module continuously monitors the total level signal and records the duration of the high level and the low level in each power frequency cycle. The time difference is counted in multiple cycles, and if the difference exceeds a threshold value, it is determined that there is a wiring error. For example, when all modules are normally connected, the positive half cycle levels of all modules are synchronized, and the high level time of the total level signal accounts for 50% of the power frequency cycle; when a module is incorrectly connected, the positive half cycle level of the module is opposite to that of other modules, resulting in a significant decrease in the high level time of the total level signal.

[0037] It can be understood that the traditional method relies on voltage phase analysis of a single module, requires complex software algorithms for cross verification, and has the risk of calculation delay and misjudgment. The present scheme realizes instant logic operation of multi-module signals through a hardware AND gate circuit, avoids complex software communication protocols, and reduces the load of the processor. At the same time, the enhanced capture module directly measures the level duration, converts the phase deviation into a quantifiable time difference parameter, and improves the detection accuracy. Compared with the Fourier analysis or correlation calculation realized by software, the method has faster response speed and can complete the preliminary judgment within a single power frequency cycle.

[0038] Through the above technical solutions, the application can monitor the wiring state of the multi-inverter parallel system in real time, identify the L / N line reverse connection fault within milliseconds, effectively eliminate the possibility of misjudgment through the cooperative work of the hardware circuit and the digital processing, and avoid the short circuit risk caused by the wiring error. At the same time, the method does not need to increase additional detection equipment, fully utilizes the existing hardware resources of the inverter, and reduces the system modification cost.

[0039] Reference Figure 2 , Figure 2 In the grid wiring detection method for single-phase energy storage inverters in parallel provided by the embodiments of the application, a step diagram for generating a level signal is provided. In some embodiments, the level signal is generated based on the phase angle of the voltage waveform, and the method comprises the following steps:

[0040] Step S210: When the phase angle of the voltage waveform is between 0° and 180°, output a high level signal to the grid bus through the L interface.

[0041] Step S220: When the phase angle of the voltage waveform is between 180° and 360°, output a low level signal to the grid bus through the N interface.

[0042] The phase angle refers to an angle offset of a grid voltage waveform relative to a reference time point, and can be calculated by a timer module in a digital signal processor after capturing a zero-crossing point of the grid voltage, and is used to divide a positive half cycle and a negative half cycle of the sinusoidal waveform. The level signal refers to a logic signal output by the inverter module, and can be generated by a transistor switching circuit or an optocoupler isolation circuit to generate high and low levels, and is used to represent a polarity state of a current phase interval. The L interface and the N interface refer to AC output ends of the inverter module, and are connected to a live wire and a neutral wire of the grid bus by using a copper bar or a terminal, and are used to transmit the level signal to a common logic operation node.

[0043] In some embodiments, during a positive half cycle of the grid voltage, that is, when the phase angle is in a range of 0° to 180°, the inverter module outputs a high-level signal to the grid bus through the L interface, and the N interface remains in a low-level state. When the voltage enters a negative half cycle, the phase angle is in a range of 180° to 360°, at this time, the N interface is switched to output a low-level signal, and the high-level signal of the L interface is canceled. The level generation mechanism is strictly synchronized with the phase of the grid voltage, for example, a phase-locked loop module in the digital signal processor can be used to track the grid frequency, and then the switching time of the level signal is controlled. As a preferred implementation, when a plurality of inverter modules are connected in parallel, the level signals output by the modules are logically superimposed by a hardware AND gate circuit, and a total level signal formed thereby can directly reflect the consistency of the phase states of all the modules.

[0044] It can be understood that the traditional method usually detects polarity by using a voltage comparator or determines a phase interval by relying on a software algorithm, and is susceptible to signal interference and has a large response delay. The present scheme converts phase information into a digital level signal and directly outputs the same by using a hardware interface, thereby improving the reliability of signal transmission and avoiding calculation errors caused by software processing. At the same time, the switching logic of the high and low levels is completely matched with the natural phase change of the grid voltage, and there is no need to additionally configure a sensor or a sampling circuit, thereby significantly simplifying the system architecture.

[0045] Reference Figure 3 , Figure 3 In the grid wiring detection method for single-phase energy storage inverters connected in parallel provided by the embodiments of the present application, a step diagram for obtaining a grid wiring detection result is provided. In some embodiments, at least one inverter module obtains a grid wiring detection result according to a time difference value, including:

[0046] In step S310, at least one inverter module compares and judges the time difference value based on a preset threshold value.

[0047] In step S320, if the time difference value is less than the preset threshold value, a grid wiring detection result is obtained, which indicates that there is no wiring error of each inverter module in the grid.

[0048] Step S330, if the time difference value is greater than or equal to the preset threshold value, a power grid wiring detection result indicating that wiring errors exist in each inverter module in the inverter grid is obtained.

[0049] The preset threshold value is a critical reference value for determining the wiring error state, which can be realized by an empirical value or a dynamically adjusted value according to the power grid fluctuation characteristics, for example, the threshold value range is determined by historical data statistics or system stability test. The time difference value is the difference between the cumulative duration of the high level and the low level of the total level signal in the preset time window, which can be realized by recording the time stamp of the level signal edge by the timing module of the digital signal processor and calculating the difference, for example, the counter function of the enhanced capture module is used to synchronously accumulate the duration of the high level and the low level.

[0050] In some embodiments, after the inverter module completes the time difference value calculation, the time difference value is compared with the preset threshold value. When the time difference value does not exceed the threshold value, it indicates that the phase deviation of the level signal output by each module is within the allowable range, and at this time it is judged that the wiring state is normal. If the time difference value exceeds the threshold value, it indicates that there is at least one inverter module with L / N wiring polarity error, which causes the high level duration and the low level duration of the total level signal to be significantly unbalanced. For example, when the L line and the N line of a module are connected in reverse, the phase of the level signal output by the module is 180 degrees different from that of other modules, which will cause the high level duration of the total level signal to be much longer than the low level duration under the hardware AND gate logic, thereby generating a time difference value that exceeds the threshold value. It can be understood that the prior art usually relies on manual inspection or independent judgment of a single module, and cannot effectively identify the polarity reverse problem in the multi-module and system. For example, the traditional method may only make a judgment through voltage amplitude detection or phase sampling of a single module, which is easy to cause misjudgment due to power grid harmonic interference or load fluctuation. The present scheme integrates the output signals of all modules through hardware AND gate logic, and compares the threshold value based on the time difference value, which can more accurately distinguish between global wiring errors and transient power grid disturbances, and improve the detection reliability.

[0051] Reference Figure 4 , Figure 4 In the single-phase energy storage inverter parallel power grid wiring detection method provided by the embodiments of the present application, the step of calculating the time difference value is shown in the schematic diagram; in some embodiments, the time difference value of the high level duration and the low level duration of the total level signal in the preset time window is calculated, including:

[0052] Step S410, recording the time stamps of the rising edge and the falling edge of the total level signal in the preset time window by the enhanced capture module;

[0053] Step S420, based on the time stamps, respectively accumulating the high level duration and the low level duration, and calculating the time difference value of the two.

[0054] Among them, the enhanced capture module refers to a hardware functional unit with high-speed signal edge detection capability, which can be implemented by using a microprocessor peripheral module with timer input capture function. Its role is to accurately capture the jump moment of the total level signal. The timestamp refers to the absolute time mark recorded when the signal edge occurs, which can be represented by the timer counter value or the number of system clock cycles, and is used for subsequent calculation of the level duration. The preset time window refers to a fixed time interval for statistical level duration, which can be configured as a sampling range containing multiple power frequency cycles to ensure the representativeness of the statistical results.

[0055] In some embodiments, when the total level signal appears a rising edge or a falling edge, the enhanced capture module triggers an interrupt immediately and records the current timestamp. By continuously recording the timestamps of multiple edges, the time intervals between adjacent rising edges and falling edges can be calculated respectively, and the intervals belonging to the high level state are accumulated to obtain the total duration of the high level, and the intervals belonging to the low level state are accumulated to obtain the total duration of the low level. The difference between the two is used to judge whether the level signals output by each inverter module are synchronized. For example, if the high level duration of the total level signal within the preset time window is significantly longer than the low level duration, it indicates that the phase output of part of the inverter modules is abnormal, which may be caused by wiring error. It can be understood that the traditional method usually relies on the comparison of the level width in a single period, which is easily affected by transient noise interference or signal distortion, resulting in misjudgment. However, through the cumulative statistics of the timestamps of multiple edges within the preset time window, random interference can be effectively filtered, and the stability and accuracy of the detection results can be improved. In addition, compared with pure software polling detection, the timestamp recording method based on the enhanced hardware capture module significantly improves the time resolution and real-time performance.

[0056] Reference Figure 5 , Figure 5 In the single-phase energy storage inverter parallel grid wiring detection method provided by the embodiments of the present application, a schematic diagram of the step of generating an alarm signal is provided. In some embodiments, after obtaining the grid wiring detection result indicating that there is a wiring error in each inverter module of the inverter grid, the method further includes:

[0057] Step S510: controlling the DC side relay of the inverter grid to disconnect the connection between the energy storage battery and the inverter circuit;

[0058] Step S520: controlling the AC side relay of the inverter grid to cut off the physical connection between the inverter and the grid;

[0059] Step S530: activating the LED indicator light on the inverter panel of the inverter grid, and generating an alarm signal containing the fault module number.

[0060] The DC side relay refers to an electromagnetic switch device for controlling the on-off between the energy storage battery and the inverter circuit, and a normally closed relay can be specifically used to achieve this purpose, so as to immediately cut off the DC side power input when a wiring error is detected, thereby preventing abnormal current from damaging the energy storage battery. The AC side relay refers to a contactor for isolating the AC output end of the inverter from the power grid, and a circuit breaker with arc extinguishing function can be specifically used to achieve this purpose, so as to avoid equipment burning caused by short-circuit current by quickly cutting off the AC circuit. The LED indicator light refers to a multi-color light-emitting diode embedded on the inverter panel, which can specifically use a red flashing mode to indicate the fault state, so as to facilitate the operation and maintenance personnel to quickly identify the position of the abnormal module. The alarm signal refers to an electronic signal containing the unique identification of the fault module, which can be specifically sent to the monitoring system through the RS-485 communication bus or the wireless transmission module to provide direct data support for fault location.

[0061] In some embodiments, when a wiring error is detected, the DC side relay preferentially performs the disconnection action to block the power supply of the energy storage battery to the inverter circuit, thereby avoiding the continuous input of DC side power to cause the overload of power devices. At the same time, the AC side relay cuts off the physical connection between the inverter and the power grid under the driving of the hardware circuit, forming a double protection mechanism. At this time, the LED indicator light on the inverter panel enters a high-brightness flashing state, and alarm information containing the module number is generated, for example, the serial number of the fault module is encoded into a binary pulse signal output, so that the operation and maintenance personnel can directly obtain the fault source information through the panel display or the background system. It can be understood that the traditional wiring error protection scheme usually only performs a single loop disconnection operation, and lacks a clear fault module positioning function. The present scheme cooperatively controls the DC side and AC side relays to achieve double electrical isolation protection, and combines visual indicator lights and digital alarm signals to significantly improve the fault handling efficiency. For example, when multiple parallel modules simultaneously have wiring abnormalities, the system can quickly lock the specific fault point through the module number without the need to cut off the loop one by one.

[0062] Reference Figure 6 , Figure 6 In the power grid wiring detection method for parallel single-phase energy storage inverters provided by the embodiments of the present application, another step of calculating the time difference value is shown in the schematic diagram; in some embodiments, the preset time window includes a plurality of continuous power frequency periods, based on the time stamp, the high level duration and the low level duration are accumulated respectively, and the time difference value of the two is calculated, including:

[0063] In step S610, the positive half cycle and negative half cycle duration of each power frequency period are accumulated and counted based on the time stamp, and the average duration of the positive half cycle and the average duration of the negative half cycle are calculated;

[0064] Step S620, calculating the time difference value according to the positive half-cycle average duration and the negative half-cycle average duration.

[0065] Wherein, the power frequency cycle refers to the time length of one complete oscillation of the grid voltage waveform, for example, 20ms cycle corresponding to 50Hz, which can be accurately measured by the clock module of the digital signal processor. The positive half-cycle corresponds to the 0° to 180° phase interval of the voltage waveform, and its duration can be calculated by recording the time stamp difference of the rising edge and the falling edge by the capture module. The negative half-cycle corresponds to the 180° to 360° phase interval, and the calculation method of the duration is similar to that of the positive half-cycle. The preset time window is set to a time period containing multiple consecutive power frequency cycles, for example, it can be set to the range of 1 second to 5 seconds, ensuring to cover at least 10 cycles, so as to eliminate the influence of transient disturbance on the detection result.

[0066] In some embodiments, the enhanced capture module records the rising edge and falling edge time stamps of the total level signal in each power frequency cycle, then accumulates the positive half-cycle duration of multiple cycles and calculates the average value, and at the same time, accumulates the negative half-cycle duration to calculate the average value. By comparing the difference between the positive half-cycle average duration and the negative half-cycle average duration, it is determined whether there is a wiring abnormality. For example, when multiple inverter modules are correctly wired, the positive half-cycle and negative half-cycle average durations should be close to equal, and the time difference value tends to zero; if there is a wiring error, it will cause the positive half-cycle and negative half-cycle durations to deviate significantly, and the difference value exceeds the preset threshold.

[0067] It can be understood that the traditional detection method usually relies on the comparison of high and low level durations in a single power frequency cycle, which is easily affected by grid harmonics or transient disturbances, resulting in misjudgment. While the present scheme introduces multi-cycle accumulation statistics and average value calculation, effectively suppressing the interference of single-cycle abnormal fluctuations on the detection result, improving the stability and anti-interference ability of the detection. In addition, by dynamically setting the time window length, the detection sensitivity can be flexibly adjusted according to the actual grid working condition.

[0068] In some embodiments, the method further comprises: calculating a first standard deviation of the positive half-cycle duration and a second standard deviation of the negative half-cycle duration within a plurality of cycles; and dynamically setting a preset threshold for the comparison of the time difference according to the first standard deviation and the second standard deviation. The first standard deviation refers to a dispersion degree index of the positive half-cycle duration within a plurality of power frequency cycles, and can be obtained by calculating the variance of the sample sequence of the positive half-cycle duration and then taking the square root. The first standard deviation quantifies the phase stability of the positive half-cycle waveform of the grid voltage. The second standard deviation refers to a dispersion degree index of the negative half-cycle duration within a plurality of power frequency cycles, and can be obtained by the same calculation method as the first standard deviation. The second standard deviation evaluates the phase offset fluctuation characteristics of the negative half-cycle waveform of the grid voltage. The dynamic setting of the preset threshold refers to the adaptive adjustment of the wiring error determination threshold according to the fluctuation range of the positive and negative half-cycle durations, and can be obtained by weighting and summing the first standard deviation and the second standard deviation and then multiplying by a proportionality coefficient. The dynamic threshold eliminates the false judgment interference caused by the fluctuation of the grid voltage.

[0069] In some embodiments, during the voltage waveform sampling of the grid bus, the enhanced capture module continuously records the duration of the positive half-cycle and the negative half-cycle within each power frequency cycle. When the preset time window reaches the set range, the digital signal processor calculates the first standard deviation of all positive half-cycle duration sequences in the window, and calculates the second standard deviation of the negative half-cycle duration sequences. Then, the two standard deviation data are input into a dynamic threshold generation algorithm, for example, the weighted average of the two is multiplied by a safety factor as a new preset threshold. Through the dynamic threshold updating mechanism, the sensitivity of the wiring error criterion can be automatically corrected when the grid voltage has inherent fluctuations or transient disturbances, avoiding false alarms or missed detection problems caused by improper fixed threshold setting.

[0070] In some embodiments, the at least one inverter module obtains the grid connection detection result according to the time difference value, and further comprises: each inverter module sends its own connection detection result through a communication bus, receives the detection results of other inverter modules and compares them, and if more than half of the modules correspond to the grid connection detection result indicating that there is a connection error, it is confirmed that there is a global connection error in the inverter grid. The communication bus refers to a communication link for transmitting detection results between inverter modules, which can be implemented by CAN bus or RS-485 bus, and can realize efficient transmission and synchronous processing of data between multiple nodes. More than half of the modules refers to more than half of the total number of inverter modules participating in comparison, which can be realized by calculating the half threshold after counting the number of valid feedback modules, avoiding global false triggering caused by false judgment of a single module. The global connection error refers to the connection of the L line and the N line of at least one module in the entire inverter grid, which can reduce the influence of local interference or single point failure on the overall judgment through the consistency of the detection results of multiple modules.

[0071] In some embodiments, the preset time window is set to 1-5 seconds and contains at least 10 sampling data of power frequency cycles. The preset time window refers to a continuous time period for collecting grid bus voltage waveform, which can be set by a timer module or a counter module, for example, by configuring the clock source of a digital signal processor to realize time reference, which serves to ensure that the sampling data covers a sufficient number of power frequency cycles to reduce the influence of transient interference on the detection result. The power frequency cycle refers to the periodic change of the grid voltage waveform, which can be calculated based on 50Hz or 60Hz AC frequency, for example, by detecting the zero crossing point of the voltage waveform to determine the cycle length, which serves to provide a stable frequency reference for the calculation of the time difference value, avoiding insufficient sampling data caused by grid frequency fluctuations.

[0072] In some embodiments, when detecting the grid connection state, the preset time window is limited to 1-5 seconds and ensures that the window contains at least 10 data of power frequency cycles. For example, in a 50Hz grid, a power frequency cycle is 20 milliseconds, and 250 cycles can be collected in a 5-second time window, exceeding the minimum requirement of 10 cycles. By this setting, the complete trend of the grid voltage waveform can be covered, avoiding false judgment of high-frequency noise or transient interference as a connection error due to too short sampling time. At the same time, the upper limit of the time window is controlled within 5 seconds, which can balance the detection efficiency and data sufficiency, preventing the system response speed from being affected by too long detection time.

[0073] In some embodiments, the starting point of the time window can be synchronized by the trigger signal of the enhanced capture module, for example, the first rising edge of the total level signal is taken as the starting point of the time window, ensuring that the sampling data of each inverter module is aligned in time. In addition, when there is a slight fluctuation in the power grid frequency, the number of power frequency cycles can be dynamically adjusted to meet the requirement of at least 10 cycles, for example, in a 60Hz power grid, a 1 second time window can contain 60 cycles, which is still much higher than the threshold.

[0074] It can be understood that the existing scheme usually adopts a fixed time window or single cycle sampling, which is easy to cause misjudgment due to insufficient sampling data. For example, some methods only make judgments based on the time difference between the high and low levels of a single power frequency cycle, which cannot effectively filter out transient interference. However, the present scheme sets a reasonable time window range and a minimum number of cycles to ensure that the detection algorithm can identify real wiring errors based on statistical rules, avoiding the influence of accidental interference.

[0075] In some embodiments, the method further comprises: after the first obtained power grid wiring detection result represents that there is a wiring error, re-executing the power grid wiring detection method after a delay of a preset time; if the power grid wiring detection results obtained continuously for multiple times all represent that there is a wiring error, locking the fault state of the inverter grid and prohibiting the grid-connected process until manual reset. It can be understood that when the inverter grid detects a wiring error for the first time, the control module starts a delay timer, for example, set to 5 seconds, during which the system maintains the current running state but does not perform grid switching operation. After the delay ends, the system automatically triggers the complete process of the power grid wiring detection method, including voltage waveform sampling, level signal generation and logic operation, time difference calculation and result judgment. If the number of continuously triggered detections reaches a preset threshold, for example, 3 times, and each result shows that there is a wiring error, it is determined as a confirmed fault. At this time, the system cuts off the connection between the energy storage battery and the inverter circuit through the hardware relay, and disconnects the physical interface between the alternating current side and the grid, and at the same time displays the locking state warning information on the operation interface. All fault states can only be reset by manual intervention, for example, by physical button or special reset instruction to clear the fault record.

[0076] Reference Figures 7 to 10 , Figure 7 In the power grid wiring detection method for parallel connection of single-phase energy storage inverters provided by the embodiments of the present application, a schematic diagram of correct connection of inverter modules is shown; Figure 8 In the power grid wiring detection method for parallel connection of single-phase energy storage inverters provided by the embodiments of the present application, a waveform diagram of correct connection of inverter modules is shown; Figure 9 In the power grid wiring detection method for parallel connection of single-phase energy storage inverters provided by the embodiments of the present application, a schematic diagram of incorrect connection of inverter modules is shown; Figure 10The waveform diagram of incorrect inverter module connection in the grid connection detection method for single-phase energy storage inverters in parallel provided in the embodiments of the present invention.

[0077] In some embodiments, such as Figure 7 and Figure 8 As shown, this corresponds to the grid wiring detection results indicating that there are no wiring errors in each inverter module in the inverter grid. n inverter modules are connected in parallel. Figure 7 There are power grid L line and power grid N line in the system, and each module is also correctly connected to the power grid N line and L line; Figure 8 Signal #1 represents the grid voltage detected by inverter module #1, and signal #2 represents the grid voltage detected by inverter module #2. The two voltages are in phase and frequency. The inverter sends high and low levels to the bus via the I / O bus. When the inverter detects the grid angle (…),… When ), send a high level signal, the grid angle ( When ), send a low level, such as Figure 8 Signal #3 represents the level signal sent by module #1 to the bus based on signal #1, and signal #4 represents the level signal sent by module #1 to the bus based on signal #2. Since the bus uses AND logic, the bus level is obtained by ANDing #3 and #4, resulting in signal #5. Signal #5 indicates that when the module detects a consistent mains voltage, the signal received on the bus is a power frequency square wave signal with consistent high and low levels. This bus signal is then sent to the DSP of each module via hardware. The DSP calculates a time interval using ECAP capture time. Within a single second (e.g., 1 second), the time difference between the high and low levels is small. If the answer is yes, then the power grid wiring is considered correct.

[0078] In some embodiments, such as Figure 9 and Figure 10 As shown, this corresponds to the grid wiring detection results indicating wiring errors in each inverter module within the inverter grid. n inverter modules are connected in parallel. Figure 9 There are power grid L line and power grid N line in the system. Module #1 is incorrectly connected to the power grid N line and L line; the other modules are connected normally. Figure 10 Signal #1 represents the grid voltage detected by inverter module #1, and signal #2 represents the grid voltage detected by inverter module #2. The two voltages are in phase but out of phase. The inverter sends high and low levels to the bus via the I / O bus. When the inverter detects the grid angle (…),… When the grid angle is ( ), a high level is sent; when the grid angle is ( ) When ), send a low level. For example... Figure 10Signal #3 represents the level signal sent to the bus by module #1 according to signal #1, signal #4 represents the level signal sent to the bus by module #1 according to signal #2, since the bus adopts the relation of AND logic, the bus level is obtained by the AND of signal #3 and signal #4, that is, signal #5. According to signal 5, when the module detects that the grid voltage is opposite, the signal received by the bus is a low level signal. The bus signal is sent to the DSP of each module through hardware, and the DSP calculates a period of time through ECAP capture time The high and low level time in a period (for example, 1s). If the high and low level time is not much different, for example, then it is considered that the grid connection is correct, otherwise, it is considered to be reversed. Figure 10 indicates that the grid is reversed.

[0079] The above is only an embodiment of the present application and is not used to limit the protection scope of the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for detecting grid connection when single-phase energy storage inverters are connected in parallel, characterized in that, The method is applied to an inverter grid including a plurality of inverter modules connected in parallel to the grid, an L interface and an N interface of each inverter module being connected to an L line and an N line of a grid bus respectively, and the method comprises: Each inverter module samples a voltage waveform of the grid bus in real time through a built-in digital signal processor, and generates a level signal based on a phase angle of the voltage waveform; The grid bus performs logical AND operation on the level signals output by each inverter module through a hardware AND gate circuit to generate a total level signal; At least one inverter module calculates a time difference value of a high-level duration and a low-level duration of the total level signal within a preset time window through an enhanced capture module in the digital signal processor; At least one inverter module obtains a grid wiring detection result according to the time difference value, and the grid wiring detection result is used to determine whether wiring errors exist in each inverter module in the inverter grid.

2. The single-phase energy storage inverter parallel connection power grid connection detection method according to claim 1, characterized in that, The method for generating a level signal based on a phase angle of the voltage waveform comprises: When the phase angle of the voltage waveform is between 0° and 180°, output a high-level signal to the grid bus through the L interface; When the phase angle of the voltage waveform is between 180° and 360°, output a low-level signal to the grid bus through the N interface.

3. The single-phase energy storage inverter parallel connection power grid connection detection method according to claim 1, characterized in that, The method for obtaining a grid wiring detection result according to the time difference value comprises: The at least one inverter module compares the time difference value with a preset threshold value; If the time difference value is less than the preset threshold value, obtain a grid wiring detection result representing that no wiring errors exist in each inverter module in the inverter grid; If the time difference value is greater than or equal to the preset threshold value, obtain a grid wiring detection result representing that wiring errors exist in each inverter module in the inverter grid.

4. The single-phase energy storage inverter parallel connection power grid connection detection method according to claim 1, characterized in that, The method for calculating a time difference value of a high-level duration and a low-level duration of the total level signal within a preset time window comprises: Record time stamps of rising edges and falling edges of the total level signal within a preset time window through the enhanced capture module; Based on the time stamps, respectively accumulate the high-level duration and the low-level duration, and calculate the time difference value of the two.

5. The single-phase energy storage inverter parallel connection power grid connection detection method according to claim 3, characterized in that, After obtaining the grid wiring detection result representing that wiring errors exist in each inverter module in the inverter grid, the method further comprises: Control a DC side relay of the inverter grid to disconnect a connection between an energy storage battery and an inverter circuit; Control an AC side relay of the inverter grid to cut off a physical connection between an inverter and the grid; Activate an LED indicator light on an inverter panel of the inverter grid, and generate an alarm signal containing a fault module number.

6. The single-phase energy storage inverter parallel connection power grid connection detection method according to claim 4, characterized in that, The preset time window includes a plurality of consecutive power frequency periods, and the method for calculating a time difference value of a high-level duration and a low-level duration of the total level signal within a preset time window comprises: Accumulate statistics based on the time stamp of each of the positive half cycle and negative half cycle duration of the power frequency cycle, and calculate the average duration of the positive half cycle and the average duration of the negative half cycle; Calculate the time difference value according to the average duration of the positive half cycle and the average duration of the negative half cycle.

7. The single-phase energy storage inverter parallel connection power grid connection detection method according to claim 6, characterized in that, The method further comprises: Calculate the first standard deviation of the positive half cycle duration and the second standard deviation of the negative half cycle duration within a plurality of cycles; Dynamically set a preset threshold for comparing the time difference value according to the first standard deviation and the second standard deviation.

8. The single-phase energy storage inverter parallel connection power grid connection detection method according to claim 1, characterized in that, The at least one of the inverter modules obtains the grid connection detection result according to the time difference value, and further comprises: Each of the inverter modules sends its own connection detection result through a communication bus, receives the detection results of other inverter modules and compares them, and if the grid connection detection results of more than half of the modules represent that there is a connection error, it is confirmed that there is a global connection error in the inverter grid.

9. The single-phase energy storage inverter parallel connection power grid connection detection method according to claim 6, characterized in that, The preset time window is set in the range of 1 second to 5 seconds, and at least contains 10 sampling data of power frequency cycles.

10. The single-phase energy storage inverter parallel connection power grid connection detection method according to claim 1, characterized in that, The method further comprises: After the first obtained grid connection detection result represents that there is a connection error, the grid connection detection method is re-executed after a delay of a preset time; If the grid connection detection results obtained continuously for multiple times all represent that there is a connection error, the inverter grid is locked in a fault state, and the grid connection is prohibited until manual reset.

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