LDO circuit structure for FVF structure

Abstract

The invention discloses an LDO circuit structure for an FVF structure, and belongs to the field of integrated circuit design. A two-stage output buffer framework is adopted, the power tube is divided into two stages, and the Miller effect is considered when a secondary pole is located at medium-high frequency, so that the grid equivalent capacitance of the power tube can be deduced to be approximately reduced to one half of that of a single power tube, namely, the original grid end pole can be increased by about two times, and the overall stability of a circuit is facilitated. Compared with the existing multi-stage output buffer architecture, the multi-stage output buffer architecture has the advantages that the influence of a complex plane zero point can be eliminated, the problem of the complex plane zero point caused by excessive feed-forward paths is avoided, the circuit analysis complexity is simplified, the abnormal frequency response of a circuit at a high-frequency position is avoided, and the stability of the circuit is improved. And the quiescent current required by the buffer stage is reduced. And meanwhile, the bandwidth is improved by utilizing a symmetrical structure, the power supply ripple feedforward efficiency can be improved, and the self power supply rejection ratio is improved through transconductance ratio constraint.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit design, and in particular relates to an LDO circuit structure that can be used in a FVF structure. Background Art

[0002] The circuit structure of a traditional FVF-structured LDO mainly includes an error amplifier, a power transistor, and a buffer stage. The power transistor's output is susceptible to power supply ripple interference and has limited bandwidth. Therefore, it is difficult to use feedforward ripple cancellation technology to feed the power supply ripple forward to the power transistor gate. Currently, to improve the phase margin of the LDO system, a large number of buffer stages are used, such as a four-stage buffer structure. However, this has the disadvantages of excessive power consumption and reduced zero-pole cancellation efficiency caused by complex plane zeros, which affects the overall stability of the system. Summary of the Invention

[0003] The present invention aims to provide an LDO circuit structure with an FVF structure, which can improve the power supply rejection ratio of the system.

[0004] In order to achieve the above object, the technical solution of the present invention is as follows:

[0005] A low-voltage-dropout (LDO) circuit structure for an FVF structure includes an error amplifier, a power tube, and a buffer stage structure. The buffer stage structure includes a first buffer stage B1, a second buffer stage B2, a first power tube MP,1, and a second power tube MP,2. The output end of the first buffer stage B1 is connected to the gate of the first power tube MP,1 and the positive input end of the second buffer stage B2, and the output end of the second buffer stage B2 is connected to the gate of the second power tube MP,2. At the same time, the output end of the first buffer stage B1 is connected back to its negative input end, and the output end of the second buffer stage B2 is connected back to its negative input end, forming a unity gain negative feedback structure. The output ends of the buffer stage structure are respectively connected to the gates of the power tubes.

[0006] Furthermore, the first buffer stage B1 and the second buffer stage B2 respectively adopt symmetrical operational transconductance amplifiers.

[0007] Furthermore, the symmetrical operational transconductance amplifier includes an input pair of transistors M6 and M7, and a load transistor M8 and M9, wherein the drain of the load transistor M8 is connected to the drain of the input pair of transistors M7, the gate of the load transistor M8 is connected to the drain of the load transistor M8, the drain of the load transistor M9 is connected to the drain of the input pair of transistors M6, the gate of the load transistor M9 is connected to the drain of the load transistor M9, the gate of the input pair of transistors M6 is connected to the input of the buffer stage, and the drain of the input pair of transistors M7 serves as the output of the buffer stage.

[0008] Furthermore, symmetrical mirror tubes M10 and M11, symmetrical mirror tubes M12 and M13, and current mirrors M14, M15, M16, M17, M18, and M19 are used to provide a dynamic bias current for the symmetrical operational transconductance amplifier, and a current source IB3 provides a fixed bias current, wherein the gate of the symmetrical mirror tube M10 is connected to the gate of M8, the drain of the symmetrical mirror tube M10 is connected to the drain of the symmetrical mirror tube M12, the source of the symmetrical mirror tube M10 is connected to the power supply VIN, the gate of the symmetrical mirror tube M11 is connected to the gate of M9, the drain of the symmetrical mirror tube M11 is connected to the drain of the symmetrical mirror tube M13, the source of the symmetrical mirror tube M11 is connected to the power supply VIN, the gate and drain of the symmetrical mirror tube M12 are connected together, and connected to the symmetrical mirror tube M13. The gates of current mirror M14, current mirror M15, and current mirror M16 are connected together, and their sources are all connected to ground. The drain of current mirror M15 is connected to the drain of current mirror M17, the gate of current mirror M17 is connected together to the drain of current mirror M17, the gate of current mirror M17 is connected together to the gates of current mirrors M18 and M19, and the sources of current mirrors M17, M18, and M19 are all connected to the power supply VIN. The drain of current mirror M18 is connected to the gate of M8, the drain of current mirror M19 is connected to the gate of load transistor M9, and the drain of current mirror M16 is connected to the sources of input pair transistors M6 and M7.

[0009] The beneficial effects of the present invention are as follows:

[0010] The present invention adopts a two-stage output buffer architecture. By dividing the power tube into two stages and considering the Miller effect when the secondary pole is located at medium and high frequencies, it can be deduced that the equivalent capacitance of the power tube gate can be regarded as approximately reduced to half of that of a single power tube, which can increase the original gate terminal pole by about two times, which is more conducive to the overall stability of the circuit. In addition, by cascading the two-stage buffer stage, the circuit stability is optimized. Compared with the existing multi-stage output buffer architecture, the present invention can eliminate the influence of the complex plane zero point, avoid the problem of complex plane zero points caused by too many feedforward paths, simplify the complexity of circuit analysis, avoid abnormal circuit frequency response at high frequencies, and reduce the static current required by the buffer stage. At the same time, the present invention uses a symmetrical structure to increase bandwidth, which can improve the efficiency of power supply ripple feedforward and improve its own power supply rejection ratio through transconductance ratio constraints. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 1 is a schematic diagram of the LDO circuit structure of a specific embodiment of the present invention.

[0012] Figure 2 It is a structural diagram of two-level output buffer.

[0013] Figure 3 It is a schematic diagram of the structure of a symmetrical operational transconductance amplifier as a buffer stage. DETAILED DESCRIPTION

[0014] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the embodiments of the present invention and are not intended to limit the embodiments of the present invention.

[0015] Figure 1 This is a schematic diagram of an LDO structure according to a specific embodiment of the present invention. It primarily includes an error amplifier, a two-stage buffer architecture, power transistors, and auxiliary circuitry for improving the power supply rejection ratio. The error amplifier EA has its positive input connected to a reference voltage, its negative input connected to the output of the LDO, and its output VSA connected to the gate of power transistor M1 and capacitor CEA. One end of CEA is grounded. The source of power transistor M1 is connected to the output of the LDO, while its drain is connected to current source IB1 and the gate of power transistor M2, VFA. The source of power transistor M2 is connected to the output of the auxiliary circuit and to the gate of MAB, which is connected to the input of the first stage of the two-stage buffer architecture. The drain of power transistor M2 is grounded. The drain of MAB is connected to the source of power transistor M3. The current generated by the drain of power transistor M3 is used to bias buffer stages B1 and B2, respectively. The gate of power transistor M3 is also connected to the error amplifier output VSA. The power supplies for the error amplifier and buffer stages B1 and B2 are also connected to VIN. The output of the LDO is connected to load capacitor CL and load resistor RL. One end of CL and RL is grounded.

[0016] Figure 2 This is a schematic diagram of a two-stage output buffer structure, comprising a first buffer stage B1, a second buffer stage B2, a first power transistor MP,1, and a second power transistor MP,2. The output of the first buffer stage B1 is connected to the gate of the power transistor MP,1 and the positive input of the second buffer stage B2, while the output of the second buffer stage B2 is connected to the gate of the power transistor MP,2. Simultaneously, the output of the first buffer stage B1 is connected back to its negative input, and the output of the second buffer stage B2 is connected back to its negative input, forming a unity-gain negative feedback structure. The two buffer stages are cascaded in a unity-gain negative feedback configuration, with their outputs connected to the gates of the power transistors. This two-stage output buffer structure pushes the secondary pole further away, improving system stability.

[0017] Figure 3This is a structural diagram of using a symmetrical operational transconductance amplifier as the first-stage buffer stage B1 and the second-stage buffer stage B2, including input pair transistors M6 and M7, M8 and M9 as load transistors, M10 and M11, M12 and M13 as symmetrical mirror transistors, M14, M15, M16, M17, M18, and M19 as current mirrors to provide dynamic bias current for the symmetrical operational transconductance amplifier, and current source IB3 to provide a fixed bias current. The gates of M14, M15, and M16 are connected together, and their sources are connected to ground. The drain of M14 is connected to the drain of a transistor used to generate bias current. The drain of M15 is connected to the drain of M17, the gate of M17 is connected to the drain of M17, and the gate of M17 is connected to the gates of M18 and M19. The sources of M17, M18, and M19 are all connected to the power supply VIN. The drain of M18 is connected to the gate of M8, the drain of M19 is connected to the gate of M9, and the sources of M8 and M9 are connected to the power supply VIN. The drain of M8 is connected to the drain of M7, the gate of M8 is connected to the drain of M8, the drain of M9 is connected to the drain of M6, and the gate of M9 is connected to the drain of M9. The gate of M6 is connected to the input of the buffer stage, and the drain of M7 serves as the output of the buffer stage. The gate of M10 is connected to the gate of M8, the drain of M10 is connected to the drain of M12, and the source of M10 is connected to the power supply VIN. The gate of M11 is connected to the gate of M9, the drain of M11 is connected to the drain of M13, and the source of M11 is connected to the power supply VIN. The gate and drain of M12 are connected together and to the gate of M13. The sources of M12 and M13 are grounded. The drain of M13 is connected to the drain of M11 and to the output of the buffer stage. The drain of M16 is connected to the sources of M6 and M7. One end of current source IB3 is connected to the sources of M6 and M7, and one end is grounded.

[0018] The present invention utilizes the mirroring effect of M10, M11, M12, and M13 to increase the bandwidth. When the buffer stage input receives an AC power ripple signal, a higher feedforward efficiency can be achieved to the gate end of the power tube, thereby achieving that the AC signal voltage of the power tube gate follows the change of the power ripple, thereby improving the power supply rejection ratio of the system. At the same time, the power supply ripple interference of the buffer stage is transmitted to its output end through two paths. The first path is through the drain-source equivalent small signal resistance of M10, and is transmitted to the output end via the mirroring effect of M12 and M13. The second path is through the drain-source equivalent small signal resistance of M11 and is transmitted to the output end. Since the current directions of the two branches are opposite, the power supply ripple at the output end of the buffer stage can be offset by making the drain-source equivalent small signal resistance of M10 and M11 equal, and the transconductance of M12 and M13 equal, so that the circuit as a whole is not interfered with by the power supply rejection capability of the buffer stage itself, thereby improving the overall power supply rejection ratio of the system.

[0019] Finally, it should be noted that the purpose of disclosing the embodiments is to facilitate a further understanding of the present invention. However, those skilled in the art will appreciate that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments, and the scope of protection claimed by the present invention shall be determined by the scope defined in the claims.

Claims

1. An LDO circuit structure for a FVF structure, comprising an error amplifier, a power tube, and a buffer stage structure, characterized in that: The buffer stage structure includes a first-stage buffer stage B1, a second-stage buffer stage B2, a first-stage power tube MP,1, and a second-stage power tube MP,2, wherein the output end of the first-stage buffer stage B1 is connected to the gate of the first-stage power tube MP,1 and the positive input end of the second-stage buffer stage B2, and the output end of the second-stage buffer stage B2 is connected to the gate of the second-stage power tube MP,2. At the same time, the output end of the first-stage buffer stage B1 is connected back to its negative input end, and the output end of the second-stage buffer stage B2 is connected back to its negative input end, forming a unit gain negative feedback structure, and the output ends of the buffer stage structure are respectively connected to the gates of the power tubes.

2. The LDO circuit structure for the FVF structure according to claim 1, wherein: The first buffer stage B1 and the second buffer stage B2 respectively adopt symmetrical operational transconductance amplifiers.

3. The LDO circuit structure for the FVF structure according to claim 2, wherein: The symmetrical operational transconductance amplifier includes an input pair of transistors M6 and M7, and load transistors M8 and M9, wherein the drain of load transistor M8 is connected to the drain of input pair of transistors M7, the gate of load transistor M8 is connected to the drain of load transistor M8, the drain of load transistor M9 is connected to the drain of input pair of transistors M6, the gate of load transistor M9 is connected to the drain of load transistor M9, the gate of input pair of transistors M6 is connected to the input of the buffer stage, and the drain of input pair of transistors M7 serves as the output of the buffer stage.

4. The LDO circuit structure for the FVF structure according to claim 3, wherein: Symmetrical mirror tubes M10, M11, M12, M13, and current mirrors M14, M15, M16, M17, M18, and M19 are used to provide dynamic bias current for the symmetrical operational transconductance amplifier, and current source IB3 provides a fixed bias current. The gate of the symmetrical mirror tube M10 is connected to the gate of M8, the drain of the symmetrical mirror tube M10 is connected to the drain of the symmetrical mirror tube M12, the source of the symmetrical mirror tube M10 is connected to the power supply VIN, the gate of the symmetrical mirror tube M11 is connected to the gate of M9, the drain of the symmetrical mirror tube M11 is connected to the drain of the symmetrical mirror tube M13, the source of the symmetrical mirror tube M11 is connected to the power supply VIN, the gate and drain of the symmetrical mirror tube M12 are connected together and connected to the gate of the symmetrical mirror tube M13. The gates of current mirror M14, current mirror M15, and current mirror M16 are connected together, and their sources are all connected to ground. The drain of current mirror M15 is connected to the drain of current mirror M17, the gate of current mirror M17 is connected to the drain of current mirror M17 together, the gate of current mirror M17 is connected to the gates of current mirrors M18 and M19 together, and the sources of current mirrors M17, M18, and M19 are all connected to the power supply VIN. The drain of current mirror M18 is connected to the gate of M8, the drain of current mirror M19 is connected to the gate of load transistor M9, and the drain of current mirror M16 is connected to the sources of input pair transistors M6 and M7.

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