Voltage stabilizer chip management system, method, electronic device, and storage medium

Abstract

The application discloses a voltage stabilizer chip management system and method, electronic equipment and storage medium, and relates to the technical field of digital data processing, which can realize the monitoring of the voltage stabilizer chip through a management controller, the management controller can set two monitoring tasks, one is used for acquiring an alarm signal and positioning an abnormal chip, and the other can call information according to the abnormal chip positioning, so as to manage the voltage stabilizer chip, through more efficient alarm signal acquisition and hierarchical task design, the technical problems of rough abnormal chip positioning, delayed alarm signal acquisition, and the need for full data acquisition during diagnosis, which causes resource waste and other technical problems in the related art are solved, and the technical effects of efficiently and accurately positioning the abnormal chip and reasonably allocating resources to optimize the voltage stabilizer chip management are achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of digital data management, and particularly relates to a voltage stabilizer chip management system and method, an electronic device and a storage medium. BACKGROUND

[0002] Reliable operation of the voltage stabilizer chip is crucial to the timing stability of the mainboard. In the related art, the management controller can interact with the complex programmable logic device (CPLD / FPGA) of the mainboard, read the preset register to diagnose the timing fault. However, this method has significant limitations: only the timing state register is concerned, and no active monitoring and alarm response mechanism for the voltage stabilizer chip is involved. When the voltage stabilizer chip is abnormal, the fault source cannot be accurately located, resulting in low diagnosis efficiency; there is a lack of cross-process coordination mechanism, which cannot dynamically trigger targeted log collection, and a large amount of original register data needs to be retrieved; the alarm signal needs to be transferred through multiple layers, making it difficult to realize sub-second fault capture and directional response, and increasing the risk of system downtime.

[0003] In summary, in the related art, the abnormal chip positioning is rough, the alarm signal acquisition is delayed, and full data collection is required during diagnosis, which easily causes resource waste and needs to be improved. SUMMARY

[0004] The present application provides a voltage stabilizer chip management system and method, an electronic device and a storage medium to at least solve the technical problems of rough abnormal chip positioning, delayed alarm signal acquisition, and full data collection during diagnosis in the related art, which causes resource waste.

[0005] The present application provides a voltage stabilizer chip management system applied to a server, the system comprising: a plurality of voltage stabilizer chips; a management controller configured to create a first preset monitoring task and a second preset monitoring task, and in response to receiving an information collection instruction, call chip information of at least one target voltage stabilizer chip from the second preset monitoring task, and generate corresponding log information based on the chip information; and a mainboard controller configured to respond to the first preset monitoring task, generate an information collection instruction based on an alarm signal generated by the plurality of voltage stabilizer chips, and in response to the log information, control the server to perform a control action corresponding to the log information.

[0006] The application further provides a voltage stabilizer chip management method, comprising the following steps: generating a first preset monitoring task of a motherboard controller to monitor a voltage stabilizer chip, so as to detect whether an alarm signal is generated by the voltage stabilizer chip; if the alarm signal is generated, generating an information collection instruction based on the alarm signal; based on the information collection instruction, obtaining a response result of a second preset monitoring task of the monitored voltage stabilizer chip, and obtaining log information of at least one target voltage stabilizer chip according to the response result, so as to control a server to perform a control action corresponding to the log information.

[0007] The application further provides an electronic device, comprising: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the voltage stabilizer chip management methods.

[0008] The application further provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of any of the voltage stabilizer chip management methods.

[0009] The application further provides a computer program product, comprising a computer program, and the computer program is executed by a processor to implement the steps of any of the voltage stabilizer chip management methods.

[0010] Through the application, the monitoring of the voltage stabilizer chip can be realized by a management controller, the management controller can set two monitoring tasks, one is used to obtain an alarm signal and locate an abnormal chip, and the other can call information according to the abnormal chip location, so as to manage the voltage stabilizer chip, through more efficient alarm signal acquisition and hierarchical task design, the technical problems of rough abnormal chip location, delayed alarm signal acquisition, and the need for full data acquisition during diagnosis in the related art are solved, resource waste is caused, and the technical effects of efficiently and accurately locating an abnormal chip and reasonably allocating resources to optimize voltage stabilizer chip management are achieved. BRIEF DESCRIPTION OF DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the application, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0012] Figure 1 A structural schematic diagram of a voltage stabilizer chip management system according to an embodiment of the application is provided.

[0013] Figure 2 A principle schematic diagram of a voltage stabilizer chip management system according to an embodiment of the application is provided.

[0014] Figure 3 A hardware design architecture diagram according to one embodiment of the present application is provided;

[0015] Figure 4 A hardware design architecture diagram according to another embodiment of the present application is provided;

[0016] Figure 5 A flow chart of a voltage stabilizer chip management method according to an embodiment of the present application is provided. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0018] It should be noted that, in the description of the present application, the terms "comprise", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. The terms "first", "second" and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0019] In order for those skilled in the art to better understand the technical solutions of the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0020] It can be understood that the VR (Voltage Regulator) is an electronic device or circuit for maintaining the stability of the output voltage even if the input voltage, load condition or environmental temperature changes. The voltage regulator is widely used in various electronic devices to ensure a stable working voltage supply for electronic components that is not sensitive to power fluctuations. Many VR chips also have voltage, current and power consumption monitoring functions. Generally, VR chips can be used in CPU (Central Processing Unit) power supply modules on the motherboard, memory power supply modules, fan boards, hard disk backplanes and other card power supply modules. On the one hand, it provides stable power supply, and on the other hand, it can monitor the voltage, current and power consumption of the power supply module. The BMC (Baseboard Management Controller) generally communicates with the VR chip through the i2c (Inter-Integrated Circuit) protocol, and the BMC can read the input, output voltage, current, power consumption from the VR chip, and read the working state and fault code of the VR from the state register of the VR, to find out the cause when the circuit power supply fails.

[0021] As shown in Figure 1 The voltage stabilizer chip management system 10 is applied to a server, and the voltage stabilizer chip management system 10 comprises a plurality of voltage stabilizer chips 100, a management controller 200 and a mainboard controller 300.

[0022] Specifically, the management controller 200 is configured to create a first preset monitoring task and a second preset monitoring task, and in a case where an information collection instruction is received, call chip information of at least one target voltage stabilizer chip 100 from the second preset monitoring task, and generate corresponding log information based on the chip information.

[0023] In actual execution process, the management controller 200 of the embodiment of the present application, that is, the BMC, can create a monitoring task, wherein the BMC is an independent service processor based on the intelligent platform management interface specification. The device monitors the hardware state data of the server power supply, CPU, memory, hard disk and environmental parameters in real time through the built-in sensor network, and supports out-of-band communication with the mainboard through the baseband management interface. It has the functions of remote power-on / off control, firmware update, event log recording and fault diagnosis, and is widely used in data center server cluster monitoring, distributed device remote maintenance and other scenes.

[0024] In actual execution, the management controller 200 can create a mainboard controller monitoring process, i.e., a first preset monitoring task of the mainboard controller voltage stabilizer chip, to monitor whether the plurality of voltage stabilizer chips generate an alarm signal, i.e., to read the state data of at least one voltage stabilizer chip to determine whether the first preset alarm signal is included in the state data.

[0025] The management controller 200 can determine whether the information collection instruction sent by the mainboard controller 300 is received. If the information collection instruction from the first preset monitoring task is received, the chip identifier in the information collection instruction can be used to read the corresponding chip information from the register of the corresponding VR chip, and then the log information can be formed according to the chip information, and the log information is returned to the first preset monitoring task to analyze the log information, confirm the abnormal reason, take corresponding control action, suppress abnormal expansion, facilitate timely correction of faults, and reduce the impact of faults on the actual process.

[0026] Optionally, in an embodiment of the present application, the management controller 200 comprises a first connection module.

[0027] The first connection module is used to communicate with the mainboard controller 300 to read the alarm signal in the mainboard controller 300, and the first connection module is a preset serial bus.

[0028] The management controller 200 can communicate with the mainboard controller 300 through the i2c bus to read the data of at least one voltage stabilizer chip 100 in the mainboard controller 300.

[0029] Optionally, in an embodiment of the present application, the management controller 200 comprises a first positioning module, a third determination module, a second positioning module and a generation module.

[0030] The first positioning module is used to position the chip identifier of at least one target voltage stabilizer chip 100 based on the information collection instruction.

[0031] The third determination module is used to determine the chip model, chip label, chip parameter, bus type, bus serial number, device address, Switch chip address and Switch chip channel of at least one target voltage stabilizer chip 100 based on the chip identifier.

[0032] The second positioning module is used to position at least one target voltage stabilizer chip 100 based on the chip model, chip label, chip parameter, bus type, bus serial number, device address, Switch chip address and Switch chip channel to read the corresponding chip information from the chip register of at least one target voltage stabilizer chip 100.

[0033] generating module, configured to generate the log information based on the chip information.

[0034] Since the management controller 200 communicates with the voltage stabilizer chip 100 through the i2c bus, and there are multiple voltage stabilizer chips 100, the management controller 200 needs to know the hardware topology of the target voltage stabilizer chip 100, such as the i2c bus number where it is located, the device address of the i2c switch chip, the channel number of the i2c switch chip where it is located, and its own device address, mainly including the device ID, the target voltage stabilizer chip 100 model, the label (which is the label of the target voltage stabilizer chip 100 in the circuit diagram, and has no actual use in the management controller 200), the parameter (including the Type / Label of the target voltage stabilizer chip 100 represented in the management controller 200, and the CPU serial number CPUIdx corresponding to the target voltage stabilizer chip 100), the bus type (the management controller 200 generally uses the i2c bus to communicate with the target voltage stabilizer chip 100), the bus number (the serial number of the i2c bus where the target voltage stabilizer chip 100 is located), the device address (the i2c device address of the target voltage stabilizer chip 100), the switch chip address (the address of the i2c switch chip where the target voltage stabilizer chip 100 is located), and the switch chip channel (the channel of the i2c switch chip where the target voltage stabilizer chip 100 is located), before reading the registers of the target voltage stabilizer chip 100 where the alarm occurs, so as to form a configuration file.

[0035] The mainboard manager 300 monitors the process, that is, the first preset monitoring task sends the device ID of the target voltage stabilizer chip 100 where the alarm occurs, and then the voltage stabilizer chip 100 monitoring process matches the target VR chip in the above-mentioned file according to the device ID, and then reads the target voltage stabilizer chip 100 according to the i2c topology.

[0036] The management controller 200 mainly reads a series of state registers of the target voltage stabilizer chip 100, and the register addresses are from 0x70-0x80. Some register reading values are 1 byte, and some register addresses are 2 bytes. Therefore, the management controller 200 first reads whether the value of the register is 1 byte or 2 bytes, and then reads the value of the register, so as to form a complete register log of the voltage stabilizer chip 100.

[0037] Optionally, in an embodiment of the present application, the management controller 200 comprises a second connection module.

[0038] The second connection module is configured to communicate with the plurality of voltage stabilizer chips 100 to detect the alarm signals of the plurality of voltage stabilizer chips 100.

[0039] The management controller 200 can also directly connect the voltage stabilizer chip 100 alarm pin to the GPIO (General-purpose input / output) pin of the chip of the management controller 200 to directly read the alarm signal of the voltage stabilizer chip 100.

[0040] Optionally, in an embodiment of the present application, the management controller 200 comprises a setting module and an interrupt module.

[0041] The setting module is configured to set the second connection module to the interrupt mode.

[0042] The interrupt module is configured to interrupt the connection between at least one voltage stabilizer chip 100 and the management controller 200 when the at least one voltage stabilizer chip 100 meets the preset abnormal condition to determine the at least one target voltage stabilizer chip 100 and the alarm signal of the at least one target voltage stabilizer chip 100.

[0043] In other embodiments, the management controller 200 can also capture the alarm state of the voltage stabilizer chip 100 through interrupt triggering. When the voltage stabilizer chip 100 generates an alarm, the alarm pin thereof is pulled low, and the GPIO pin of the BMC connected thereto is also pulled low. The management controller 200 sets the GPIO pin connected to the voltage stabilizer chip 100 alarm pin to the interrupt mode, and generates an interrupt as soon as the pulled low state is detected.

[0044] Optionally, in an embodiment of the present application, the interrupt module comprises an acquisition unit and a tracing unit.

[0045] The acquisition unit is configured to acquire the identifier of the interrupt pin.

[0046] The tracing unit is configured to trace the corresponding at least one target voltage stabilizer chip 100 based on the identifier of the interrupt pin.

[0047] The management controller 200 of the embodiment of the present application can know which voltage stabilizer chip 100 generates an alarm according to the correspondence between the serial number of the GPIO and the device ID of the voltage stabilizer chip 100. This has the advantages that the voltage stabilizer chip 100 alarm state does not need to be read from the mainboard controller 300, the interrupt response is faster, the voltage stabilizer chip 100 alarm can be captured faster, and the system complexity can be reduced.

[0048] The mainboard controller 300 is configured to, in response to the first preset monitoring task, detect whether an alarm signal is generated from the plurality of voltage stabilizer chips 100, and in the case that the alarm signal is generated, generate information collection instructions based on the alarm signal, and in response to the log information, control the server to perform a control action corresponding to the log information.

[0049] The mainboard controller 300 can be a mainboard (MB) complex programmable logic device (CPLD). The CPLD is a high-density programmable logic device, and has an integrated density greater than 1000 gates, more input / output signals, product terms and macro cells.

[0050] Since the mainboard controller 300 can only record which voltage stabilizer chip 100 (VR0~X) generates an alarm, and cannot tell the management controller 200 the topology of the voltage stabilizer chip 100, the management controller 200 can only obtain the serial number VRX (X: 0, 1, 2,...) of the VR chip, and cannot directly match the topology of the target voltage stabilizer chip 100 in the configuration file. Therefore, the management controller 200 needs to set a device ID (chip identification) for each voltage stabilizer chip 100, and bind the device ID with the serial number VRX of the voltage stabilizer chip 100 recorded in the mainboard controller 300. In the embodiment of the present application, the management controller 200 can also create a voltage stabilizer chip 100 monitoring process, i.e., a second preset monitoring task for monitoring the voltage stabilizer chip. The voltage stabilizer chip 100 monitoring process can determine whether the information collection instructions from the first preset monitoring task are received.

[0051] Optionally, in an embodiment of the present application, the mainboard controller 300 comprises a third connection module.

[0052] The third connection module is configured to communicate with the plurality of voltage stabilizer chips 100 to detect the alarm signals of the plurality of voltage stabilizer chips 100. The mainboard controller 300 is connected to the pins of the plurality of voltage stabilizer chips 100 to form the third connection module.

[0053] The mainboard controller 300 can be connected with the voltage stabilizer chip 100 through pins to obtain the state or alarm information of the voltage stabilizer chip 100 more quickly; the state or alarm information of the voltage stabilizer chip 100 can also be confirmed by acquiring error codes and a mapping relationship of the error codes; through the dual-mode monitoring of time-sharing polling (presetting a power-on timing table (containing error code mapping) of the voltage stabilizer chip 100, and the mainboard controller 300 sending a power-off instruction to the EN pin of the target voltage stabilizer chip 100 in sequence) and event triggering (the mainboard controller 300 is provided with a plurality of signal comparators, which monitor the PG signals of all voltage stabilizer chips 100 in real time, and any PG jump triggers an immediate interruption, and the position of the fault voltage stabilizer chip 100 is locked in combination with the polling timing), the embodiment of the application can confirm whether the voltage stabilizer chip 100 generates an alarm according to any result or the mutual verification of two or more results.

[0054] Optionally, in an embodiment of the application, the mainboard controller 300 comprises a reading module and a first judging module.

[0055] The reading module is configured to read the state values of the abnormal registers of the plurality of voltage stabilizer chips 100 based on the third connecting module.

[0056] The first judging module is configured to judge whether there is at least one byte with a value of 0 in the state values, to obtain a judgment result, and to determine whether an alarm signal is generated based on the judgment result.

[0057] In some embodiments, taking the pin connection between the mainboard controller 300 and the voltage stabilizer chip 100 as an example, the abnormal registers of the voltage stabilizer chip can be arranged in the mainboard controller 300, so as to determine whether there is an alarm signal by directly reading the state values of the abnormal registers.

[0058] For example, for a normal voltage stabilizer chip 100, the reading value of the abnormal register is 1 byte, the total number of bytes represents the total number of voltage stabilizer chips 100, and each bit represents the state of a voltage stabilizer chip 100. If there is 0, it means that there is an abnormal state voltage stabilizer chip 100, i.e., the voltage stabilizer chip 100 has an alarm or an error.

[0059] In the embodiment of the application, the mainboard controller only needs to read the value (one or more bytes) of the abnormal register once, and then check whether there is a byte equal to 0, so as to improve the detection efficiency and save the complex analysis process of checking whether each bit represents a specific alarm type is set. This simple judgment method can confirm whether a certain voltage stabilizer chip 100 is in an abnormal state at the fastest speed, which is very important for the power failure scene that needs to respond quickly.

[0060] On the basis of locating the voltage stabilizer chip corresponding to the character with the value of 0 through the state value, the embodiment of the application can obtain the chip serial number of the target voltage stabilizer chip that occurs the alarm, and convert the chip serial number into the device ID of the chip, that is, the chip identification, and then generate the corresponding information collection instruction through the chip identification, so as to perform the corresponding chip information collection based on the information collection instruction.

[0061] Optionally, in an embodiment of the application, the mainboard controller 300 further comprises a conversion module.

[0062] The conversion module is configured to convert the state value into binary to obtain a new state value, so as to determine whether there is at least one byte with the value of 0 in the new state value.

[0063] For example, if the VR_STATUS1 read value is hexadecimal 0xFE, which is converted into binary 1111 1110, it is indicated that the VR0 chip, that is, the 0th voltage stabilizer chip 100, has an error, and if the VR_STATUS2 read value is hexadecimal 0xFE, which is converted into binary 1111 1110, it is indicated that the VR8 chip, that is, the 8th voltage stabilizer chip 100, has an error.

[0064] Optionally, in an embodiment of the application, the mainboard controller 300 comprises an acquisition module and a first determination module.

[0065] The acquisition module is configured to acquire the position of the byte in the state value.

[0066] The first determination module is configured to determine at least one target voltage stabilizer chip 100 based on the position, and acquire the chip identification of the at least one target voltage stabilizer chip, so as to generate an information collection instruction based on the chip identification.

[0067] When the chip is located, the embodiment of the application can be confirmed through the position of the 0 character in the abnormal register.

[0068] For example, in the embodiment of the application, the read value of the VR fault register (abnormal register) of one mainboard controller 300 is 1 byte (8 bits), each bit represents the state of one voltage stabilizer chip 100, and if it is 0, it represents that the voltage stabilizer chip 100 has an alarm or error. If a machine has 12 voltage stabilizer chips 100, the mainboard controller 300 needs to take out two registers as the VR state register, the VR_STATUS1 register represents VR0-7, and the VR_STATUS2 register represents VR8-15.

[0069] According to the positioning of the chip, the embodiment of the present application can obtain the corresponding identification of the target voltage stabilizer chip 100, such as serial number, ID, etc., so as to write the chip identification into the information collection instruction, so that the management controller 200 can call the corresponding information according to the chip identification.

[0070] Optionally, in an embodiment of the present application, the mainboard controller 300 comprises a detection module, a second judgment module and a second determination module.

[0071] The detection module is configured to detect the pin connection state in the third connection module.

[0072] The second judgment module is configured to judge whether the pins corresponding to the at least one voltage stabilizer chip 100 satisfy the preset level change condition according to the pin connection state.

[0073] The second determination module is configured to determine that the at least one target voltage stabilizer chip 100 has an alarm in the case of satisfying the preset level change condition.

[0074] Further, the embodiment of the present application can connect the fault / alt alarm information of the voltage stabilizer chip 100 to a pin of the mainboard controller 300. Once an alarm or an abnormality occurs in the voltage stabilizer chip 100, it will change the level of the pin. The mainboard controller 300 detects that the pin connected to the voltage stabilizer chip 100 has a level change (for example, the default is generally high level. If the level is pulled low, it means that the voltage stabilizer chip 100 generates an alarm signal). It means that the voltage stabilizer chip 100 generates an alarm. Then the mainboard controller 300 stores the alarm state in the state register of the voltage stabilizer chip 100, i.e. the abnormal register.

[0075] On this basis, the embodiment of the present application can determine whether there is an alarm signal according to the state value in the abnormal register.

[0076] Optionally, in an embodiment of the present application, the mainboard controller 300 comprises an analysis module and a control module.

[0077] The analysis module is configured to analyze the log information to obtain the alarm reason of the at least one target voltage stabilizer chip 100.

[0078] The control module is configured to match a control action based on the alarm reason and cut off the power supply of the at least one target voltage stabilizer chip 100.

[0079] Further, the first preset monitoring task, that is, the motherboard controller 300 monitors the process which can call the method of VR.MonitorDbus to obtain the read value information str_vr_reg of the register of the voltage stabilizer chip 100, that is, the response result of the second preset monitoring task, and then a timestamp string is added in front of the string to form a voltage stabilizer chip 100 register read value log to be stored in the vr.log file, and a sel log and a diagnosis log with the same timestamp are generated. After knowing that there is a VR alarm log in the sel log, the user can check the vr.log log to obtain the register information of the VR chip to further analyze and diagnose the alarm cause, and match the corresponding control action according to the alarm cause.

[0080] Optionally, in an embodiment of the present application, the voltage stabilizer chip management system 10 further comprises an executor and a recovery controller.

[0081] The executor is configured to execute the first preset monitoring task to determine whether the at least one target voltage stabilizer chip 100 generates a new alarm signal.

[0082] The recovery controller is configured to restore the power supply in the case where no new alarm signal is generated.

[0083] The management controller 200 can intelligently diagnose the alarm cause according to the register information of the voltage stabilizer chip 100 and give a solution suggestion to be stored in the diagnosis log. The management controller 200 can also select to cut off the power supply of this path according to the problem cause (such as current overload, power consumption overload, etc.) to protect the safety of the circuit, wait until the equipment is repaired and no current overload and other abnormalities are detected, and then restore the power supply.

[0084] In combination with Figures 2 to 4 As shown in FIG. 1, the working principle of the voltage stabilizer chip management method of the embodiment of the present application is described in detail.

[0085] As shown in FIG. 1, the working principle of the voltage stabilizer chip management method of the embodiment of the present application is described in detail. Figure 2 As shown in FIG. 1, the working principle of the voltage stabilizer chip management method of the embodiment of the present application is described in detail.

[0086] Step S201: creating an MB CPLD monitoring process.

[0087] Step S202: reading an abnormal register. The embodiment of the present application can communicate with the MB CPLD through an i2c bus to read the read value of the abnormal register in the MB CPLD.

[0088] Step S203, determine whether there is a VR chip alarm. The alarm information of the VR chip is connected to a pin of the MB CPLD. Once there is an alarm or an exception in the VR chip, it will change the level of the pin. The MB CPLD detects that the pin connected to the VR has a level change (for example, the default is generally high level, if the level is pulled low, it means that the VR generates an alarm signal), which means that the VR generates an alarm, and then the MB CPLD stores the alarm state in the VR state register.

[0089] The hardware design architecture diagram of the embodiment of the present application can be as shown in the following figure. Figure 3

[0090] Generally, the MB CPLD uses a bit of binary to represent the alarm state of a VR chip, 1 represents normal, and 0 represents alarm. A register of the MB CPLD is 1 Byte, which is equal to 8 bits, that is, a state register of the MB CPLD can store the states of 8 VR chips. If the number of VR chips is more than 8, multiple VR state registers can be used for storage. The BMC communicates with the MB CPLD through the i2c bus and reads the VR fault register of the MB CPLD in a round-robin manner.

[0091] The read value of an exception register of one MB CPLD is 1 byte (8 bits), and each bit represents the state of a VR. If it is 0, it means that the VR has an alarm or an error. If a machine has 12 VR chips in total, the MB CPLD needs to take out two registers as VR state registers, and the VR_STATUS1 register represents VR0-7 and the VR_STATUS2 register represents VR8-15.

[0092] If the read value of the VR_STATUS1 is hexadecimal 0xFE, which is converted into binary as 1111 1110, it means that the VR0 chip has an error, and the read value of the VR_STATUS2 is hexadecimal 0xFE, which is converted into binary as 1111 1110, which means that the VR8 chip has an error.

[0093] In addition, the BMC can also directly connect the VR chip alarm pin to the GPIO pin of the BMC chip to capture the VR chip alarm state through an interrupt trigger. As shown in the following figure. Figure 4 ​As shown, when the VR chip generates an alarm, it will pull down its alarm pin, and the GPIO pin of the BMC connected thereto will also be pulled down. The BMC sets the GPIO pin connected to the VR chip alarm pin to an interrupt mode, and immediately generates an interrupt upon detecting that it is pulled down. Then, according to the correspondence between the GPIO number and the VR chip device ID, the BMC knows which VR chip generates the alarm.

[0094] In step S204, the chip identification of the target VP chip is obtained. Since the MB CPLD can only record which VR chip (VR0-X) generates an alarm, and cannot tell the BMC the topology of the VR chip, the BMC only obtains the serial number VRX (X: 0, 1, 2,...) of a VR chip, and cannot directly match the topology of the VR chip in the yaml file. Therefore, the BMC needs to set a device ID for each VR chip, and bind the device ID with the serial number VRX of the VR chip recorded in the MB CPLD.

[0095] For example, the device ID COMMER_COMP_DEVID_VR_CPU0VR0 is bound with VR0, COMMER_COMP_DEVID_VR_CPU0VR1 is bound with VR1,..., and COMMER_COMP_DEVID_VR_CPU0VRx is bound with VRx.

[0096] In this way, the MB CPLD monitoring process in the BMC can convert the serial number of the target VR chip into a device ID according to which VR generates an alarm or has an error read from the VR fault register of the MB CPLD, and then pass the device ID as a parameter to the method of the DBUS.

[0097] In step S205, an information acquisition instruction is generated. The MB CPLD monitoring process in the BMC calls the method of the VR.Monitor Dbus service created in the VR monitoring process in step 1 according to which VR generates an alarm or has an error read from the VR fault register of the MB CPLD, and this method reads a series of state registers of the VR chip according to the device ID (that is, the device ID in the yaml file) of the target VR chip passed by the MB CPLD.

[0098] In step S206, a VR monitoring process is created. The BMC creates a VR chip monitoring process, which is used to obtain VR chip information and respond to external sending of acquisition of VR chip information or VR chip control commands.

[0099] Step S207, create VR.Monitor DBUS service. The VR chip monitoring process creates a VR.MonitorDbus, service=xyz.openbmc_project.VR.Monitor, path= / xyz / openbmc_project / collection,

[0100] interface= xyz.openbmc_project.Collection, method=RegCollect,

[0101] The method is a function for processing reading VR register information and then passing the information out.

[0102] Step S207, judge whether the information acquisition instruction is received.

[0103] Step S208, read the VR chip register based on the chip identification. Since the BMC communicates with the VR chip through the i2c bus, because there are multiple VR chips, the BMC needs to know the hardware topology of the target VR chip, such as the i2c bus number it is in, the device address of the i2c switch chip, the channel number of the i2c switch chip it is in, and its own device address, before reading the register of the target VR chip that generates the alarm.

[0104] For example, this information is configured in a.yaml type configuration file, mainly including device ID, target VR chip model, label (this is the label of the target VR chip in the circuit diagram, which has no actual use in the BMC), parameter (including the Type / Label represented by the target VR chip in the BMC, and the CPU serial number CPUIdx corresponding to the target VR chip), bus type (the BMC generally uses the i2c bus to communicate with the target VR chip), bus number (the serial number of the i2c bus where the target VR chip is located), device address (the i2c device address of the target VR chip), switch chip address (the address of the i2c switch chip where the target VR chip is located), and switch chip channel (the channel of the i2c switch chip where the VR chip is located).

[0105] The MB CPLD monitoring process sends the device ID of the VR chip that generates the alarm, and then the VR monitoring process matches the VR chip in the.yaml file according to the device ID, and then reads the VR chip according to the i2c topology.

[0106] Step S209, return the log information. BMC mainly reads a series of state registers of the VR chip, the register address is from 0x70-0x80, some register reading values are 1 byte, and some register addresses are 2 bytes, so BMC first reads the value of the register, which is 1 byte or 2 bytes, and then reads the value of the register.

[0107] For example, the 0x80 register is 2 bytes, so BMC needs to read 2 bytes from the 0x80 register as the reading value, the first byte is the low 8 bits: 0xff, and the second byte is the high 8 bits: 0xee, combined into a hexadecimal value 0xeeff, combined with the register address to become 0x80-0xeeff.

[0108] For another example, the 0x7f register is 1 byte, and the reading value is 0xdd, which is finally combined with the register address to become 0x7f-0xdd. Finally, the reading values of all registers are read out and combined to form the register reading value information str_vr_reg as follows: 0x70-0x00, 0x71-0x01,..., 0x7f-0xdd, 0x80-0xeeff, then add the time stamp and time zone, and the name of the VR chip in BMC to form a complete VR register log: [2025-03-17T18:12:39+08:00] PVCCIN_CPU0[0x70-0x00, 0x71-0x01,..., 0x7f-0xdd, 0x80-0xeeff].

[0109] Step S210, receive the log information. The MB CPLD monitoring process calls the method of VR.Monitor Dbus to obtain the reading value information str_vr_reg of the VR register, and then adds a timestamp string in front of the string to form a VR register reading value log which is stored in the vr.log file, and a sel log and a diagnostic log with the same timestamp are generated.

[0110] Step S211, analyze the log information and match the control action. After the user learns that there is a VR alarm log in the sel log, the user can view the vr.log log to obtain the register information of the VR chip for further analysis and diagnosis of the alarm cause.

[0111] Further, BMC can intelligently diagnose the alarm cause according to the VR chip register information and give a solution suggestion which is stored in the diagnostic log. BMC can also select to cut off the power supply of this path according to the problem cause (current, power overload, etc.) to protect the safety of the circuit, wait for the equipment to be repaired, and then restore the power supply when no current overload or other abnormalities are detected.

[0112] In summary, the embodiment of the present application can connect the alarm state pin of the VR chip to the MB CPLD, the BMC can obtain the VR chip that generates an alarm from the MB CPLD monitoring process reading the VR state register of the MB CPLD, and obtain the hardware topology of the VR chip through the conversion of the VR chip serial number and the device ID and then according to the VR chip hardware topology yaml file. And a set of Dbus services are designed to realize the inter-process call, realize the VR chip register collection method of calling the VR chip monitoring process from the MB CPLD monitoring process (log collection process) to obtain the VR chip register log. And after the VR chip generates an alarm state, the BMC can timely capture the alarm and trigger the method in the Dbus to collect the read values of the related VR chip registers and generate logs, and the BMC can further analyze the read values of the registers to give diagnosis, maintenance suggestions or even cut off the power supply to prevent the circuit from being damaged.

[0113] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and the necessary general hardware platform, of course, it can also be realized by hardware, but in many cases the former is a better embodiment.

[0114] As shown in Figure 5 The embodiment of the present application further provides a voltage stabilizer chip management method, comprising the following steps:

[0115] Step S501, a first preset monitoring task of a motherboard controller is generated to detect whether an alarm signal is generated from a plurality of voltage stabilizer chips.

[0116] Step S502, if the alarm signal is generated, an information collection instruction is generated based on the alarm signal.

[0117] Step S503, a response result of a second preset monitoring task of the monitored voltage stabilizer chip is obtained based on the information collection instruction, and log information of at least one target voltage stabilizer chip is obtained according to the response result, so as to control the server to perform a control action corresponding to the log information.

[0118] The features of the embodiment corresponding to the voltage stabilizer chip management method can be referred to the related description of the embodiment corresponding to the voltage stabilizer chip management system, which will not be repeated here.

[0119] The embodiment of the present application further provides an electronic device, comprising a memory and a processor, the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above voltage stabilizer chip management method embodiments.

[0120] The embodiment of the present application further provides a computer readable storage medium, which stores a computer program, wherein the computer program is arranged to execute the steps in any of the above-mentioned voltage stabilizer chip management method embodiments when running.

[0121] In an example embodiment, the above-mentioned computer readable storage medium can include, but is not limited to, a U disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media capable of storing computer programs.

[0122] The embodiment of the present application further provides a computer program product, which comprises a computer program, and the computer program is executed by a processor to implement the steps in any of the above-mentioned voltage stabilizer chip management method embodiments.

[0123] The embodiment of the present application further provides another computer program product, which comprises a non-volatile computer readable storage medium, and the non-volatile computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps in any of the above-mentioned voltage stabilizer chip management method embodiments.

[0124] The skilled person can further realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in general terms in the above description. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0125] The above provides a detailed description of the voltage stabilizer chip management system, method, electronic device and storage medium provided by the present application. The principles and implementation modes of the present application are described by applying specific examples in this paper, and the above description of the examples is only used to help understand the method of the present application and its core idea. It should be pointed out that, for ordinary skilled person in the art, without departing from the principles of the present application, the present application can be improved and modified in several ways, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A voltage regulator chip management system, characterized by, Applied to a server, comprising: a plurality of voltage stabilizer chips; a management controller configured to create a first preset monitoring task and a second preset monitoring task, and in response to receiving an information collection instruction, call chip information of at least one target voltage stabilizer chip from the second preset monitoring task, and generate corresponding log information based on the chip information; a mainboard controller configured to, in response to the first preset monitoring task, determine whether an alarm signal is generated from the plurality of voltage stabilizer chips, and in response to the alarm signal being generated, generate the information collection instruction based on the alarm signal, and in response to the log information, control the server to perform a control action corresponding to the log information; wherein the management controller is further configured to determine a hardware topology of at least one of the target voltage stabilizer chips based on the chip information, read a value of a register recording at least one of the target voltage stabilizer chips from a configuration file based on the hardware topology, and generate the log information based on the value of the register; wherein the mainboard controller comprises a third connection module configured to communicate with the plurality of voltage stabilizer chips to detect the alarm signal of the plurality of voltage stabilizer chips; wherein the mainboard controller comprises a reading module configured to read a state value of an abnormal register of the plurality of voltage stabilizer chips based on the third connection module, a first judgment module configured to determine whether at least one byte with a value of 0 exists in the state value to obtain a judgment result, and determine whether the alarm signal is generated based on the judgment result; wherein the mainboard controller further comprises a conversion module configured to convert the state value into a binary value to obtain a new state value, and determine whether at least one byte with a value of 0 exists in the new state value.

2. The voltage regulator chip management system of claim 1, wherein, The management controller comprises: a first connection module configured to communicate with the mainboard controller to read an alarm signal in the mainboard controller.

3. The voltage regulator chip management system of claim 2, wherein, The first connection module is a preset serial bus.

4. The voltage regulator chip management system of claim 1, wherein, The management controller comprises: a second connection module configured to communicate with the plurality of voltage stabilizer chips to detect the alarm signal of the plurality of voltage stabilizer chips.

5. The voltage regulator chip management system of claim 4, wherein, The management controller is connected to pins of the plurality of voltage stabilizer chips to constitute the second connection module.

6. The voltage regulator chip management system of claim 5, wherein, The management controller comprises: a setting module configured to set the second connection module to an interrupt mode; an interrupt module configured to, in response to at least one of the voltage stabilizer chips satisfying a preset abnormal condition, interrupt a connection between at least one of the voltage stabilizer chips and the management controller, and determine at least one of the target voltage stabilizer chips and the alarm signal of at least one of the target voltage stabilizer chips.

7. The voltage regulator chip management system of claim 6, wherein, The interrupt module comprises: an acquisition unit configured to acquire an identifier of an interrupt pin; a tracing unit configured to trace at least one of the target voltage stabilizer chips corresponding to the interrupt pin based on the identifier of the interrupt pin.

8. The voltage regulator chip management system of claim 1, wherein, The mainboard controller is connected to pins of the plurality of voltage stabilizer chips to constitute the third connection module.

9. The voltage regulator chip management system of claim 1, wherein, The mainboard controller comprises: An acquisition module is configured to acquire a position of the byte in the state value; A first determination module is configured to determine the at least one target voltage stabilizer chip based on the position, and acquire a chip identification of the at least one target voltage stabilizer chip, so as to generate the information acquisition instruction based on the chip identification.

10. The voltage regulator chip management system of claim 8, wherein, The mainboard controller comprises: A detection module is configured to detect a pin connection state in the third connection module; A second judgment module is configured to judge whether a pin corresponding to at least one voltage stabilizer chip satisfies a preset level change condition according to the pin connection state; A second determination module is configured to determine that at least one target voltage stabilizer chip is in alarm in a case where the preset level change condition is satisfied.

11. The voltage regulator chip management system of claim 1, wherein, The mainboard controller comprises: An analysis module is configured to analyze the log information to obtain an alarm cause of at least one target voltage stabilizer chip; A control module is configured to match the control action based on the alarm cause, and cut off power supply of at least one target voltage stabilizer chip.

12. The voltage regulator chip management system of claim 11, wherein, Further comprising: An executor is configured to execute the first preset monitoring task to judge whether at least one target voltage stabilizer chip generates a new alarm signal; A recovery controller is configured to recover the power supply in a case where the new alarm signal is not generated.

13. The voltage regulator chip management system of claim 1, wherein, The management controller comprises: A first positioning module is configured to position a chip identification of at least one target voltage stabilizer chip based on the information acquisition instruction; A third determination module is configured to determine a chip model, a chip label, a chip parameter, a bus type, a bus serial number, a device address, a Switch chip address and a Switch chip channel of at least one target voltage stabilizer chip based on the chip identification; A second positioning module is configured to position at least one target voltage stabilizer chip based on the chip model, the chip label, the chip parameter, the bus type, the bus serial number, the device address, the Switch chip address and the Switch chip channel, so as to read corresponding chip information from a chip register of at least one target voltage stabilizer chip; A generation module is configured to generate the log information based on the chip information.

14. A method of voltage regulator chip management, the method comprising: The voltage stabilizer chip management system according to any one of claims 1-13, wherein the method comprises the following steps: A first preset monitoring task of a mainboard controller is generated to monitor voltage stabilizer chips, so as to detect whether the voltage stabilizer chips generate alarm signals; If the alarm signals are generated, an information acquisition instruction is generated based on the alarm signals; Based on the information acquisition instruction, a response result of a second preset monitoring task of the monitored voltage stabilizer chips is acquired, and log information of at least one target voltage stabilizer chip is obtained according to the response result, so as to control a server to execute a control action corresponding to the log information.

15. An electronic device, comprising: Comprise: A memory is configured to store a computer program; A processor is configured to execute the computer program to realize the steps of the voltage stabilizer chip management method according to claim 14.

16. A computer-readable storage medium, characterized in that, The computer program is stored in the computer readable storage medium and is executed by the processor to implement the steps of the voltage stabilizer chip management method in claim 14.

17. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the voltage stabilizer chip management method in claim 14.

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