Gated clock automatic verification method, electronic equipment and medium

Abstract

The invention relates to the technical field of chip verification, in particular to an automatic verification method for a gated clock, electronic equipment and a medium, and the method comprises the steps: S1, obtaining gated clock path information Gn corresponding to a to-be-tested chip design, Gn being path information corresponding to the nth gated clock in the to-be-tested chip design, and Gn being generated by splicing G1n, G2n and G3n; s2, generating a corresponding gated clock signal value reading function An based on each Gn; s3, in the design simulation process of the to-be-tested chip, An is called to obtain a gated clock measured value Bn corresponding to Gn; and S4, acquiring a predicted value corresponding to each gated clock, comparing Bn with the predicted value corresponding to the nth gated clock, if all Bn are consistent with the predicted value corresponding to the nth gated clock, determining that verification is passed, otherwise, generating prompt information based on the gated clocks of which the measured values are not consistent with the predicted values. According to the invention, the verification efficiency of the gated clock is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip verification, and in particular to a gated clock automatic verification method, electronic equipment and medium. Background Art

[0002] Clock gating is a traditional dynamic low-power technology widely used in digital integrated circuit design, significantly reducing chip power consumption. Verifying clock gating typically requires adding a clock gating checker to verify that the clock gating configuration meets expectations. The typical configuration step for a clock gating checker is to iterate through all clock gating units and manually write the clock gating checker for each one. However, for complex chip systems with diverse chip IP (Intellectual Property), manually writing clock gating units individually is time-consuming and labor-intensive, and is not easily reusable across multiple chip projects, resulting in low clock gating verification efficiency. Therefore, improving clock gating verification efficiency has become a pressing technical challenge. Summary of the Invention

[0003] The present invention aims to provide a gated clock automatic verification method, electronic equipment and medium, thereby improving the verification efficiency of the gated clock.

[0004] According to a first aspect of the present invention, a method for automatically verifying a gated clock is provided, comprising: Step S1: Obtain the gated clock path information {G1, G2, ..., G n ,...,G N}, G n G is the path information corresponding to the nth gated clock in the chip under test design. n By G1 n , G2 n 、G3 n Splicing generation, G1 n Design name for the chip to be tested, G2 n G3 is the chip IP name corresponding to the nth gated clock in the chip under test design. n is the name of the public library unit corresponding to the nth gated clock, the chip design to be tested includes multiple chip IPs, the chip IPs include multiple public library units, and each public library unit corresponds to a gated clock; Step S2: Based on each G n Generate the corresponding gated clock signal value reading function A n ; Step S3: During the chip design simulation process, call A n Get G n The corresponding gated clock measured value Bn ; Step S4: Get the predicted value corresponding to each gated clock, and n Compare with the predicted value corresponding to the nth gated clock. If all B n If both the measured value and the predicted value are consistent with the predicted value corresponding to the nth gated clock, the verification is passed; otherwise, a prompt message is generated based on the gated clock whose measured value and the predicted value are inconsistent.

[0005] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executed by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0006] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions, wherein the computer instructions are used to execute the method according to the first aspect of the present invention.

[0007] The present invention has significant advantages and beneficial effects compared to the prior art. By utilizing the above technical solution, the gated clock automatic verification method, electronic device, and medium provided by the present invention can achieve considerable technological advancement and practicality, and have wide industrial application value, with at least the following beneficial effects: The present invention can automatically obtain the path information of each gated clock in the chip design under test, generate a corresponding gated clock signal value reading function based on the path information of each gated clock, obtain the actual value corresponding to each gated clock through the gated clock signal value reading function during the simulation process of the chip design under test, and compare the measured value of each gated clock with the corresponding predicted value to achieve automatic verification of the gated clock. The present invention improves the verification efficiency of the gated clock. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0009] Figure 1 This is a flow chart of the gated clock automatic verification method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0010] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0011] The embodiment of the present invention provides a gated clock automatic verification method, such as Figure 1 As shown, including: Step S1: Obtain the gated clock path information {G1, G2, ..., G n ,...,G N}, G n G is the path information corresponding to the nth gated clock in the chip under test design. n By G1 n , G2 n 、G3 n Splicing generation, G1 n Design name for the chip to be tested, G2 n G3 is the chip IP name corresponding to the nth gated clock in the chip under test design. n is the name of the public library unit corresponding to the nth gated clock. The chip design to be tested includes multiple chip IPs, the chip IPs include multiple public library units, and each public library unit corresponds to a gated clock.

[0012] It should be noted that the gated clock path information in this embodiment of the present invention is generated by concatenating three pieces of information: the chip design name under test, the chip IP name, and the public library unit. Different chip designs under test can contain the same chip IP, and different chip IPs can also contain the same public library unit. Therefore, the chip IP name and public library unit name can be reused by different chip designs under test.

[0013] Step S2: Based on each G n Generate the corresponding gated clock signal value reading function A n .

[0014] It should be noted that the gated clock signal value reading function template is set to input G n , the output is G n The corresponding measured value of the gated clock.

[0015] Step S3: During the chip design simulation process, call A n Get G n The corresponding gated clock measured value B n .

[0016] Among them, in the process of designing and simulating the chip to be tested, the backdoor access method can be used to call A n Get G n The corresponding gated clock measured value B n .

[0017] Step S4: Get the predicted value corresponding to each gated clock, and n Compare with the predicted value corresponding to the nth gated clock. If all B n If both the measured value and the predicted value are consistent with the predicted value corresponding to the nth gated clock, the verification is passed; otherwise, a prompt message is generated based on the gated clock whose measured value and the predicted value are inconsistent.

[0018] It should be noted that the embodiments of the present invention can automatically obtain the gated clock path information corresponding to the chip design under test, which is described below through two specific embodiments.

[0019] Example 1 The step S1 comprises: Step S11 : Obtain hierarchical information corresponding to the chip design under test, wherein the hierarchical information corresponding to the chip design under test includes a chip design identifier under test, a chip IP identifier corresponding to the chip design under test, and a common library unit identifier corresponding to each chip IP of the chip design under test.

[0020] Step S12: Based on the hierarchical information corresponding to the chip design to be tested and the pre-set first mapping table, second mapping table and third mapping table, obtain the chip design name to be tested, chip IP name and public library unit name corresponding to each gated clock; the first mapping table includes the chip design identifier to be tested and the chip design name to be tested, the second mapping table includes the chip IP identifier and the chip IP name, and the third mapping table includes the public library unit identifier and the public library unit name.

[0021] It should be understood that the information in the second mapping table and the third mapping table can be reused by different chip designs under test in the first mapping table.

[0022] Step S13: Concatenate the design name of the chip to be tested, the chip IP name, and the public library unit name corresponding to each gated clock to generate gated clock path information corresponding to each gated clock.

[0023] It should be noted that the name mapping information of different levels of the chip design under test is maintained based on the first mapping table, the second mapping table, and the third mapping table. When a new chip design under test appears, only the first mapping table, the second mapping table, and the third mapping table need to be partially modified. As an embodiment, the method further includes: Step S10: If the chip design to be tested is a newly added chip design to be tested, execute step S20; otherwise, execute step S1.

[0024] Step S20: Obtain the name of the newly added chip design to be tested, the chip IP identifiers and corresponding chip IP names of all chip IPs of the newly added chip design to be tested, and the public library unit identifiers and corresponding public library unit names of all the newly added chip design to be tested.

[0025] Step S30: Add the name of the newly added chip design to be tested and the corresponding identifier of the newly added chip design to be tested to the first mapping table.

[0026] Step S40: Store the chip IP identifier of the newly added chip design to be tested and the name of the corresponding chip IP in the second mapping table, which does not currently exist in the second mapping table.

[0027] It is understandable that some chip IP identifiers and corresponding chip IP names of the newly added chip design to be tested may already exist in the second mapping table, and the existing information in the second mapping table can be directly used without repeated addition.

[0028] Step S50: store the public library unit identifier and the corresponding public library unit name of the newly added chip design to be tested that does not currently exist in the third mapping table in the third mapping table, and then execute step S1.

[0029] It is understandable that some public library unit identifiers and corresponding public library unit names of the newly added chip design to be tested may already exist in the third mapping table, and the existing information in the third mapping table can be directly used without repeated addition.

[0030] It should be noted that when a new chip design to be tested appears, only the first mapping table, the second mapping table and the third mapping table need to be partially updated to realize automatic verification of the gated clock of the chip design to be tested based on steps S1 to S4, thereby improving the verification efficiency of the gated clock.

[0031] When there is a chip design to be tested that needs to be deleted, the method further includes: Step S100: Obtain the design identifier of the chip to be tested to be deleted.

[0032] Step S200: Determine the chip IP identifier of the chip IP that exists in the chip design to be deleted and does not exist in other chip designs to be tested other than the chip design to be deleted as the chip IP identifier to be deleted.

[0033] Step S300: Determine the public library cell identifiers that exist in the chip design to be deleted and do not exist in other designs to be tested other than the chip design to be deleted as public library cell identifiers to be deleted.

[0034] Step S400: Delete the mapping relationship information corresponding to the design identifier of the chip to be tested in the first mapping table, delete the mapping relationship information corresponding to the IP identifier of the chip to be deleted in the second mapping table, and delete the mapping relationship corresponding to the public library unit identifier in the design to be tested in the third mapping table.

[0035] Embodiment 1 can realize rapid generation of gated clock path information through the first mapping table, the second mapping table and the third mapping table, and only the first mapping table, the second mapping table and the third mapping table need to be partially modified during the process of adding or deleting chip designs to be tested.

[0036] Example 2 Each chip IP design under test has at least one register pre-configured in the chip IP, which can be either a single register or multiple registers. The registers of the chip IP are pre-configured with the gated clock path information and gated clock enable flag corresponding to the chip IP. This means the gated clock path information and gated clock enable flag corresponding to the chip IP can be stored in a single register or distributed across multiple registers.

[0037] The step S1 comprises: Step C11: traverse each register of each chip IP in the chip design to be tested, and obtain the gated clock path information {G1, G2, ..., G n ,...,G N}.

[0038] In this embodiment, the gated clock path information corresponding to the chip under test design is obtained by reading each register of each chip IP.

[0039] The default predicted value of each gated clock is set to the first value. In step S4, obtaining the predicted value corresponding to each gated clock includes: Step S41: Read the gated clock enable flag in each register in the chip IP of the chip to be tested.

[0040] The gated clock on flag specifically includes an on flag and a off flag.

[0041] Step S42: If the gated clock on flag is an on flag, the preset value corresponding to the gated clock is set to a second value; if the gated clock on flag is an off flag, the preset value corresponding to the gated clock is maintained at the default first value.

[0042] As an example, the first value is set to 1 and the second value is set to 2.

[0043] As another example, the chip under test is designed to include a target register for storing overall preset value configuration information. In step S4, obtaining a predicted value corresponding to each gated clock includes: Step S40, read the target register. If the configuration value is empty, execute step S41. If the target register is the first configuration value, set the preset values ​​corresponding to all gated clocks of the chip under test to the first value. If the target register is the second configuration value, set the preset values ​​corresponding to all gated clocks of the chip under test to the second value.

[0044] Step S40 can further satisfy application scenarios requiring unified configuration of overall prediction values.

[0045] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of the steps can be performed in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. A process can be terminated when its operation is completed, but can also have additional steps not included in the accompanying drawings. A process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0046] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executed by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0047] An embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0048] The embodiments of the present invention can automatically obtain the path information of each gated clock in the chip design under test, generate a corresponding gated clock signal value reading function based on the path information of each gated clock, obtain the actual value corresponding to each gated clock through the gated clock signal value reading function during the simulation process of the chip design under test, and compare the measured value of each gated clock with the corresponding predicted value to achieve automatic verification of the gated clock. The present invention improves the verification efficiency of the gated clock.

[0049] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make slight changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A gated clock automatic verification method, characterized in that: include: Step S1: Obtain the gated clock path information {G1, G2, ..., G n ,...,G N }, G n G is the path information corresponding to the nth gated clock in the chip under test design. n By G1 n , G2 n 、G3 n Splicing generation, G1 n Design name for the chip to be tested, G2 n G3 is the chip IP name corresponding to the nth gated clock in the chip under test design. n is the name of the public library unit corresponding to the nth gated clock, the chip design to be tested includes multiple chip IPs, the chip IPs include multiple public library units, and each public library unit corresponds to a gated clock; Step S2: Based on each G n Generate the corresponding gated clock signal value reading function A n ; Step S3: During the chip design simulation process, call A n Get G n The corresponding gated clock measured value B n ; Step S4: Get the predicted value corresponding to each gated clock, and n Compare with the predicted value corresponding to the nth gated clock. If all B n If both the measured value and the predicted value are consistent with the predicted value corresponding to the nth gated clock, the verification is passed; otherwise, a prompt message is generated based on the gated clock whose measured value and the predicted value are inconsistent.

2. The method according to claim 1, characterized in that The step S1 comprises: Step S11: Obtain hierarchical information corresponding to the chip design under test, wherein the hierarchical information corresponding to the chip design under test includes a chip design identifier under test, a chip IP identifier corresponding to the chip design under test, and a common library unit identifier corresponding to each chip IP of the chip design under test; Step S12: obtaining the chip design name, chip IP name, and public library unit name corresponding to each gated clock based on the hierarchical information corresponding to the chip design under test and the preset first mapping table, second mapping table, and third mapping table; The first mapping table includes the design identifier of the chip to be tested and the design name of the chip to be tested, the second mapping table includes the chip IP identifier and the chip IP name, and the third mapping table includes the public library unit identifier and the public library unit name; Step S13: Concatenate the design name of the chip to be tested, the chip IP name, and the public library unit name corresponding to each gated clock to generate gated clock path information corresponding to each gated clock.

3. The method according to claim 2, characterized in that The method further comprises: Step S10: If the chip design to be tested is a newly added chip design to be tested, execute step S20; otherwise, execute step S1; Step S20: Obtain the name of the newly added chip design to be tested, the chip IP identifiers and corresponding chip IP names of all chip IPs of the newly added chip design to be tested, and the identifiers and corresponding public library unit names of all public library units of the newly added chip design to be tested; Step S30: adding the name of the newly added chip design to be tested and the corresponding identifier of the newly added chip design to be tested to the first mapping table; Step S40: storing the chip IP identifier of the newly added chip design to be tested and the name of the corresponding chip IP in the second mapping table, which does not currently exist in the second mapping table; Step S50: store the public library unit identifier and the corresponding public library unit name of the newly added chip design to be tested that does not currently exist in the third mapping table in the third mapping table, and then execute step S1.

4. The method according to claim 2, characterized in that The method further comprises: Step S100: obtaining the design identifier of the chip to be tested to be deleted; Step S200: Determine the chip IP identifier of the chip IP that exists in the chip design to be deleted and does not exist in other chip designs to be tested other than the chip design to be deleted as the chip IP identifier to be deleted; Step S300: Determine a public library cell identifier that exists in the chip design to be deleted and does not exist in other designs to be tested other than the chip design to be deleted as a public library cell identifier to be deleted; Step S400: Delete the mapping relationship information corresponding to the design identifier of the chip to be tested in the first mapping table, delete the mapping relationship information corresponding to the IP identifier of the chip to be deleted in the second mapping table, and delete the mapping relationship corresponding to the public library unit identifier in the design to be tested in the third mapping table.

5. The method according to claim 1, characterized in that At least one register is pre-set in the chip IP of each chip to be tested, and the register of the chip IP is pre-configured with gated clock path information and a gated clock start flag corresponding to the chip IP.

6. The method according to claim 5, characterized in that The step S1 comprises: Step C11: traverse each register of each chip IP in the chip design to be tested, and obtain the gated clock path information {G1, G2, ..., G n ,...,G N }.

7. The method according to claim 5, characterized in that The default predicted value of each gated clock is set to the first value. In step S4, obtaining the predicted value corresponding to each gated clock includes: Step S41, reading the gated clock enable flag in each register in the chip IP of the chip under test design; Step S42: If the gated clock on flag is an on flag, the preset value corresponding to the gated clock is set to a second value; if the gated clock on flag is an off flag, the preset value corresponding to the gated clock is maintained at the default first value.

8. The method according to claim 7, characterized in that The chip under test is designed to be provided with a target register for storing overall preset value configuration information. In step S4, obtaining the predicted value corresponding to each gated clock includes: Step S40, read the target register. If the configuration value is empty, execute step S41. If the target register is the first configuration value, set the preset values ​​corresponding to all gated clocks of the chip under test to the first value. If the target register is the second configuration value, set the preset values ​​corresponding to all gated clocks of the chip under test to the second value.

9. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions to be executed by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that The computer-executable instructions are stored, and the computer-executable instructions are used to execute the method according to any one of the preceding claims 1 to 8.

Images