Gate driving device and display panel

Abstract

The application provides a gate driving device and a display panel, and relates to the technical field of display driving. The gate driving device comprises a stage transmission circuit, a first frequency division circuit and a first output circuit. The stage transmission circuit is connected with a first node and is used for controlling the potential of the first node according to a stage transmission signal. The first frequency division circuit is used for controlling the potential of a second node according to the potential of the first node and a first frequency division signal transmitted by a first frequency division line. The first output circuit comprises a sixth transistor. When the first node is in a low level state, the potential of the second node is maintained above a preset threshold voltage, so that the sixth transistor is cut off or turned on in a linear region. When frequency division switching is needed, even if the second node is in a passive high level state, when the first node is in a low level state, the potential of the second node is maintained above the preset threshold voltage, so that the sixth transistor is cut off or turned on in a linear region, and display abnormalities caused by abnormal output of a first gate driving signal during frequency division switching are avoided.

Description

Technical Field

[0001] This application relates to the field of display driving technology, and in particular to a gate driving device and a display panel. Background Technology

[0002] Zoned-frequency display technology is a technique that divides a display screen into multiple independent zones, allowing each zone to flexibly set different display frequencies. For example, in scenarios where complex dynamic videos and static images alternate, zoned-frequency display technology allows different zones to adjust the display frequency of the display panel according to the characteristics of the image, thus enabling the display panel to balance display quality and power consumption.

[0003] However, at the moment when the display panel switches from a low-frequency state to a high-frequency state, the state of each signal in the gate driving device of the display panel needs to change and interact. This can easily cause abnormal fluctuations in the potential of some key nodes in the gate driving device, resulting in uneven display brightness or color at the moment of frequency division switching (Mura phenomenon). Summary of the Invention

[0004] This application provides a gate driving device that avoids display abnormalities in the display panel during frequency division switching, thereby at least partially solving the above-mentioned technical problems.

[0005] To achieve the above objectives, according to a first aspect of this application, a gate driving device is provided, comprising a plurality of cascaded gate driving units, wherein the gate driving unit includes: A cascade circuit, connected to the first node, is used to control the potential of the first node according to the cascade signal; A first frequency divider circuit is connected to the first node, the second node, and the first frequency divider line, and is used to control the potential of the second node according to the potential of the first node and the first frequency divider signal transmitted by the first frequency divider line. A first output circuit, connected to the second node, is used to output a first gate drive signal according to the potential of the second node; The first output circuit includes a sixth transistor; the sixth transistor includes a control electrode connected to the second node, a first electrode connected to the third power line, and a second electrode for outputting the first gate drive signal. When the first node is in a low-level state, the potential of the second node is maintained above a preset threshold voltage, so that the sixth transistor is turned off or turned on in the linear region.

[0006] Optionally, the first frequency divider circuit includes a first transistor, a second transistor, and a first capacitor; The first transistor includes a first electrode connected to the first frequency divider line, a second electrode connected to the second transistor and the first capacitor, and a control electrode connected to the first control signal; the first capacitor also includes a second terminal connected to the second node; The second transistor includes a control electrode connected to the first transistor, a first electrode connected to the first node, and a second electrode connected to the second node; Optionally, the second transistor is a dual-gate transistor, so that when the first node is in a low-level state, the potential of the second node is maintained above the turn-on threshold voltage of the sixth transistor, so that the sixth transistor is turned off. Wherein, the conduction threshold voltage is greater than the preset threshold voltage.

[0007] Optionally, the aspect ratio of the second transistor is greater than 1.5, so that when the first node is in a low-level state, the potential of the second node is maintained above a preset threshold voltage, so that the sixth transistor is turned on in the linear region.

[0008] Optionally, the cascade circuit includes a third transistor, a fourth transistor, and a fifth transistor; The third transistor includes a control electrode for transmitting signals at the access stage, a first electrode connected to the first power line, and a second electrode connected to the third node. The fourth transistor includes a control electrode for transmitting signals at the access stage, a first electrode connected to the second power line, and a second electrode connected to the third node. The fifth transistor includes a control electrode for receiving a first clock signal, a second electrode connected to the third node, and a second electrode connected to the first node.

[0009] Optionally, the first output circuit may further include a seventh transistor; The seventh transistor includes a control electrode connected to the first node, a first electrode connected to the first power line, and a second electrode connected to the sixth transistor. The seventh transistor is used to pull down the first gate drive signal.

[0010] Optionally, it also includes a pull-down control circuit for outputting the first control signal according to the reset control signal and controlling the potential of the first node; The pull-down control circuit includes an eighth transistor, a ninth transistor, and an inverter. The eighth transistor includes a control electrode for receiving the reset control signal, a first electrode connected to the second power line, and a second electrode connected to the inverter and the first node. The inverter includes an input terminal connected to the eighth transistor and an output terminal connected to the ninth transistor; The ninth transistor includes a control electrode connected to the inverter, a first electrode connected to the first power line, and a second electrode connected to the first node.

[0011] Optionally, when the first frequency division signal is at its falling edge, the potential of the first node is an active low potential, the potential of the second node is a passive high potential, and the potential difference between the first node and the second node is greater than 10V.

[0012] Optionally, the second transistor is turned off when the first frequency division signal is at its falling edge; When the second transistor is off, leakage current in the second node is suppressed to slow down the rate of potential drop in the second node.

[0013] According to a second aspect of this application, a display panel is provided, including the aforementioned gate driving device. In summary, in the gate driving device of this application embodiment, when frequency division switching is required, even if the first frequency division signal on the first frequency division line changes from a high level to a low level, causing the second node W to be in a passive high level state, the potential of the second node W is maintained above a preset threshold voltage when the first node K is in a low level state, so that the sixth transistor T6 is turned off or turned on in the linear region, reducing the degree of abnormal conduction of the first output circuit 3, and avoiding display abnormalities caused by abnormal output of the first gate driving signal during frequency division switching to a certain extent.

[0014] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0016] Figure 1 This is a schematic diagram illustrating an application scenario of the gate driving device provided in an exemplary embodiment of this disclosure; Figure 2 This is a schematic diagram of a gate driving device in related technologies; Figure 3It is a waveform diagram of the driving signal in the related technology; Figure 4 This is a schematic diagram of a gate driving device provided in an exemplary embodiment of this disclosure; Figure 5 These are waveform diagrams of each node provided in the exemplary embodiments of this disclosure; Figure 6 These are waveforms of the first gate drive signal under different aspect ratios provided in the exemplary embodiments of this disclosure; Figure 7 This is a waveform diagram of the first gate drive signal when the second transistor provided in the exemplary embodiment of this disclosure is a dual-gate transistor; Figure 8 This is a circuit diagram of a gate driving device provided in an exemplary embodiment of this disclosure.

[0017] Explanation of reference numerals in the attached diagram: 1. Transmission circuit; 2. First frequency divider circuit; 3. First output circuit; 4. Pull-down control circuit; 41. Inverter; 5. Second frequency divider circuit; 6. Second output circuit. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0019] Reference Figure 1 As shown, Figure 1 This is a schematic diagram of a display panel in an embodiment of this application. The display panel includes a display area AA and a non-display area NA adjacent to the display area AA, with the non-display area NA surrounding the display area AA. The display area AA is the region within the display panel used for display functions, and it contains multiple display units that implement these functions. The non-display area NA may be a border area of ​​the display panel, and it may contain functional components that assist the display units within the display area AA in their display functions. For example, multiple light-emitting devices D1 and pixel circuits 30 for driving the light-emitting devices D1 may be arrayed within the display area AA.

[0020] Combination Figure 1A gate driving device is provided in the non-display area AA. The gate driving device may include a threshold compensation circuit 11, a first reset circuit 12, a second reset circuit 13, a light emission control circuit 14, and a scanning circuit 20 arranged in a cascaded manner. As an example, the threshold compensation circuit 11 is used to output a threshold compensation signal Nscan1. The threshold compensation circuit 11 can be located on one side of the display area AA. Each threshold compensation circuit 11 drives two rows of pixel circuits 30 in the display area AA. For example, the threshold compensation circuit 11 can be configured as one-to-two on one side, and the two rows of pixel circuits 30 share one threshold compensation signal Nscan1. The first reset circuit 12 is used to output a first reset signal Nscan2. The first reset circuit 12 can be located on the other side of the display area AA, opposite to the threshold compensation circuit 11. Each first reset circuit 12 drives two rows of pixel circuits 30 in the display area AA. The second reset circuit 13 is used to output a second reset signal Pscan2. The second reset circuit 13 can be located on one side of the display area AA. Each second reset circuit 13 drives two rows of pixel circuits 30 in the display area AA. The light emission control circuit 14 is used to output the light emission control signal EM. The light emission control circuit 14 can be set on the other side of the display area AA, opposite to the second reset circuit 13. The scanning circuit 20 is used to output the scanning signal Pscan1. The scanning circuits 20 are respectively set on both sides of the display area AA. The two scanning circuits 20 located on both sides of the same row of pixel circuits 30 share the same area of ​​the row of pixel circuits 30.

[0021] Thus, the pixel circuit 30 can realize data writing and light emission control of the light-emitting device D1 based on the scan signal Pscan1, the threshold compensation signal Nscan1, the first reset signal Nscan2, the second reset signal Pscan2, and the light emission control signal EM.

[0022] Secondly, refer to Figure 2 In conjunction with the aforementioned background technology, the background of this application will be further elaborated. Figure 2 This is a circuit connection diagram of a gate driving device in related technologies. The gate driving device includes a shift register 100, a frequency divider module 200, and an output module 300. The shift register 100 and the frequency divider module 200 are connected to a first connection point A, used to control the potential of the first connection point A according to a transmission signal. The frequency divider module 200 and the output module 300 are connected to a second connection point B. The frequency divider module 200 controls the potential of the second connection point B according to the potential of the first connection point A and the frequency division control signal LF. The output module 300 outputs a driving signal for driving the pixel circuit according to the potential of the second connection point B.

[0023] The frequency divider module 200 includes a first driving transistor Q1, a second crystal driving transistor, and a first capacitor. The first driving transistor Q1 includes a first electrode connected to the frequency divider control signal LF, a second electrode connected to the second driving transistor Q2 and the first terminal of the capacitor, and a control electrode connected to the control signal. The capacitor also includes a second terminal connected to the second connection point B. The second driving transistor Q2 includes a control electrode connected to the first driving transistor Q1, a first electrode connected to the first connection point A, and a second electrode connected to the second connection node. The output module 300 includes a third driving transistor Q3, which includes a first electrode connected to a voltage source, a second electrode for outputting the driving signal OUT, and a control electrode connected to the second connection point B.

[0024] Reference Figure 3 When frequency division switching is required, the frequency division control signal LF needs to switch from a high level to a low level. This control signal turns off the first driving transistor Q1, and the second electrode Q2-2 of the second driving transistor Q2 is at a passive high potential, causing the second driving transistor Q2 to turn off. This, in turn, keeps the second connection point B at a passive high potential, keeping the third driving transistor Q3 off and preventing the output of the drive signal OUT. However, during frequency division switching, the shift register 100 controls the first connection point A to be at a low level. At this time, there is a voltage difference between the first connection point A and the second connection point B, meaning there is a voltage difference between the first electrode and the second electrode of the second driving transistor Q2. If there is a voltage difference between the first and second electrodes of the second driving transistor Q2 when it is off, leakage current will form, causing the second connection point B to continuously discharge to the first connection point A. This results in a continuous decrease in the potential of the second connection point B, causing the third driving transistor Q3 to be abnormally turned on, outputting a high-level drive signal OUT, thus causing display abnormalities during frequency division switching.

[0025] It should be noted that, Figure 1 The application scenario of the gate driving device shown is merely an example. The application scenario of the gate driving device described in the embodiments of this application is to more clearly illustrate the technical solution of the embodiments of this application, and does not constitute a limitation on the technical solution provided in the embodiments of this application.

[0026] According to the first aspect of this application, referring to Figure 4This disclosure provides a gate driving device, including a plurality of cascaded gate driving units. Each gate driving unit includes a cascade circuit 1, a first frequency divider circuit 2, and a first output circuit 3. The cascade circuit 1 is connected to a first node K and is used to control the potential of the first node K according to a cascade signal. The first frequency divider circuit 2 is connected to the first node K, a second node W, and a first frequency divider line, and is used to control the potential of the second node W according to the potential of the first node K and the first frequency divider signal transmitted by the first frequency divider line. The first output circuit 3 is connected to the second node W and is used to output a first gate driving signal according to the potential of the second node W.

[0027] The first output circuit 3 includes a sixth transistor T6; the sixth transistor T6 includes a control electrode connected to the second node W, a first electrode connected to the third power supply line, and a second electrode for outputting a first gate drive signal Nout. When the first node K is in a low-level state, the potential of the second node W is maintained above the preset threshold voltage, so that the sixth transistor T6 is turned off or turned on in the linear region.

[0028] In the above embodiments, when frequency division switching is required, even if the first frequency division signal on the first frequency division line changes from a high level to a low level, causing the second node W to be in a passive high level state, the potential of the second node W is maintained above the preset threshold voltage when the first node K is in a low level state, so that the sixth transistor T6 is turned off or turned on in the linear region, reducing the degree of abnormal conduction of the first output circuit 3, and avoiding display abnormalities caused by abnormal output of the first gate drive signal during frequency division switching to a certain extent.

[0029] In some embodiments, the first frequency divider circuit 2 includes a first transistor T1, a second transistor T2, and a first capacitor C1. The first transistor T1 includes a first electrode connected to a first frequency divider line, a second electrode connected to a first terminal of the second transistor T2 and the first capacitor C1, and a control electrode connected to a first control signal. The first capacitor C1 also includes a second terminal connected to a second node W. The second transistor T2 includes a control electrode connected to the first transistor T1, a first electrode connected to a first node K, and a second electrode connected to the second node W.

[0030] In the first embodiment, the second transistor T2 is a dual-gate transistor, such that when the first node K is in a low-level state, the potential of the second node W is maintained above the turn-on threshold voltage of the sixth transistor T6, thereby turning off the sixth transistor T6. The turn-on threshold voltage is greater than the preset threshold voltage.

[0031] In the second embodiment, the second transistor T2 is a single-gate transistor and the aspect ratio of the second transistor T2 is greater than 1.5, so that when the first node K is in a low-level state, the potential of the second node W is maintained above a preset threshold voltage, so that the sixth transistor T6 is turned on in the linear region.

[0032] In this case, using a dual-gate transistor or increasing the width-to-length ratio of the second transistor T2 can reduce the leakage current of the second transistor T2.

[0033] As an example, the first frequency division signal transmitted on the first frequency division line is used to control the start and stop of the frequency division switching of the display panel. When the first frequency division signal is in a high-level state, it indicates that the frequency division function is turned on, and when the first frequency division signal is in a low-level state, it indicates that the frequency division function is turned off.

[0034] Reference Figure 5 As an example, Nout is the first gate drive signal. The second electrode of the first transistor T1 and the control electrode of the second transistor T2 are connected to the fourth node H. The potential of the fourth node H is controlled by the first transistor T1. During the time period t1, when the first frequency divider signal is low and the first control signal is low, causing the first transistor T1 to turn on, the fourth node H is low, causing the second transistor T2 to turn on. At this time, the first node K is high, thus causing the second node W to be high.

[0035] During time period t2, the frequency division function of the display panel is activated. The first frequency division signal is at a high level and the first control signal is at a low level, causing the first transistor T1 to conduct, making the fourth node H at a high level, thereby controlling the second transistor T2 to turn off. Subsequently, the first control signal is at a high level, causing the first transistor T1 to turn off. At this time, both the fourth node H and the second node W are at a passive high level, and the second transistor T2 remains off. However, at this time, the first node K is at a low level. Therefore, at the switching moment of the frequency division function of the display panel, the second node W is at a passive high level, and the voltage difference between the first electrode and the second electrode of the second transistor T2 is the voltage difference between the second node W and the first node K.

[0036] In the above embodiments, by using a dual-gate transistor or a width-to-length ratio greater than 1.5 for the second transistor T2, the leakage current between its first and second electrodes is reduced when the second transistor T2 is off, thereby reducing the leakage current from the second node W to the first node K. When frequency division switching is required, even if the first frequency division signal on the first frequency division line changes from a high level to a low level, causing the second node W to be in a passive high level state, the reduced leakage current between the first node K and the second node W results in a slower potential drop at the second node W. This ensures that when the first node K is in a low level state, the potential of the second node W remains above a preset threshold voltage, so that the sixth transistor T6 is turned off or turned on in the linear region.

[0037] Reference Figure 8 As one embodiment of the cascade circuit 1, the cascade circuit 1 includes a third transistor T3, a fourth transistor T4, and a fifth transistor T5. The third transistor T3 includes a control electrode for receiving a cascade signal, a first electrode connected to a first power supply line, and a second electrode connected to a third node O. The fourth transistor T4 includes a control electrode for receiving a cascade signal, a first electrode connected to a second power supply line, and a second electrode connected to the third node O. The fifth transistor T5 includes a control electrode for receiving a first clock signal, a first electrode connected to the third node O, and a second electrode connected to the first node K.

[0038] Among them, the stage transmission signal can be the first control signal output by the gate drive unit of the stage preceding the gate drive unit of this stage.

[0039] In the above embodiment, the third transistor T3 and the fourth transistor T4 form an inverting structure, so that the potential of the third node O is always opposite to the potential of the transmission signal, and the potential of the first node K is controlled according to the potential of the third node O and the first clock signal.

[0040] Reference Figure 8 As one embodiment of the first output circuit 3, the first output circuit 3 further includes a seventh transistor T7. The seventh transistor T7 includes a control electrode connected to the first node K, a first electrode connected to the first power supply line, and a second electrode connected to the sixth transistor T6. The seventh transistor T7 is used to pull down the first gate drive signal Nout.

[0041] As an example, the sixth transistor T6 is a P-type transistor, and the turn-on threshold voltage of the sixth transistor T6 is less than or equal to 5V.

[0042] Reference Figure 5For example, when the first frequency division signal is at the falling edge, the potential of the first node K is an active low potential, the potential of the second node W is a passive high potential, and the potential difference between the first node K and the second node W is greater than 10V.

[0043] The falling edge of the first frequency divider signal refers to the instant when the first frequency divider signal changes from a high level to a low level, indicating the moment when the display panel switches frequency division. For example, the moment when the first frequency divider signal is at its falling edge indicates when the display panel's frequency division function is turned off, and the moment when the first frequency divider signal is at its rising edge indicates when the display panel's frequency division function is turned on.

[0044] As an example, when the first frequency division signal is at its falling edge, the second transistor T2 is turned off. With the second transistor T2 off, leakage current in the second node W is suppressed, thus slowing down the rate of potential drop in the second node W.

[0045] Reference Figure 6 , Figure 6 This is the output waveform of the first gate drive signal at the frequency division switching moment, given different width-to-length ratios of the second transistor T2. W / L represents the width-to-length ratio of the second transistor T2.

[0046] Specifically, the larger the width-to-length ratio of the second transistor T2, the smaller the leakage current when the second transistor T2 is off, and the slower the potential of the second node W decreases when the second node W is at a passive high potential. Combined with... Figure 6 When the aspect ratio of the second transistor T2 is 0.5, its leakage current is large in the off state, which causes the potential of the second node W to drop faster. When the potential of the second node W drops to the conduction threshold voltage of the sixth transistor T6, the sixth transistor T6 starts to conduct in the linear region, thereby outputting the first gate drive signal with a gradually rising potential. Finally, the potential of the second gate drive signal will rise to -2V.

[0047] As an example, the aspect ratio of the second transistor T2 is greater than or equal to 2. In particular, when the aspect ratio of the second transistor T2 is 2.5 or 3, the potential of the second node W drops more slowly. Therefore, the time required for the potential of the second node W to drop to the conduction threshold voltage of the sixth transistor T6 is longer, and the conduction degree of the sixth transistor T6 is smaller. Finally, the highest potential of the first gate drive signal output by the sixth transistor T6 is stabilized at around -6V, which reduces the amplitude of the first gate drive signal being abnormally pulled up.

[0048] It should be noted that when the aspect ratio of the second transistor T2 is greater than 1.5, the potential of the second node W will still drop to the conduction threshold voltage of the sixth transistor T6. However, the potential drop of the second node W is smaller at this time, so that the sixth transistor T6 will only conduct in the linear region and will not saturate conduct. Compared with the sixth transistor T6 being saturated conduct, the amplitude of the first gate drive signal being abnormally pulled up can be reduced.

[0049] Reference Figure 5 and Figure 7 , Figure 7 This is the output waveform of the first gate drive signal at the frequency division switching moment when the second transistor T2 is a dual-gate transistor. When the second transistor T2 is a dual-gate transistor, its leakage current in the off state is small, causing the potential of the second node W to drop more slowly. Furthermore, during the period when the first node K is in a low-level state, the potential of the second node W is always higher than the conduction threshold voltage of the sixth transistor T6. For example, combined with... Figure 5 When the threshold voltage of the sixth transistor T6 is 5V, the potential of the second node W remains higher than 5V while the first node K is in a low-level state, thus preventing the sixth transistor T6 from conducting abnormally. However, when the potential of the first node K is in a high-level state, it will be higher than the potential of the second node W. At this time, the potential of the second node W will no longer decrease due to leakage current, thus preventing the first gate drive signal from abnormally increasing during frequency division switching.

[0050] Reference Figure 8 In a further embodiment of the first output circuit 3, the first output circuit 3 further includes a fourteenth transistor T14 and a fifteenth transistor T15. The fourteenth transistor T14 includes a control electrode connected to a first clock signal, a first electrode connected to the second node W, and a second electrode connected to the fifteenth transistor T15. The fifteenth transistor T15 includes a first electrode connected to the fourteenth transistor T14, a second electrode connected to the second power supply line, and a control electrode connected to a first control signal.

[0051] Reference Figure 8 As a further embodiment of the gate driving device, the gate driving device further includes a pull-down control circuit 4, which outputs a first control signal according to a reset control signal and controls the potential of the first node K. The pull-down control circuit 4 includes an eighth transistor T8, a ninth transistor T9, and an inverter 41.

[0052] The eighth transistor T8 includes a control electrode for receiving a reset control signal, a first electrode connected to the second power supply line, and a second electrode connected to the inverter 41 and the first node K. The inverter 41 includes an input terminal connected to the eighth transistor T8 and an output terminal connected to the ninth transistor T9. The ninth transistor T9 includes a control electrode connected to the inverter 41, a first electrode connected to the first power supply line, and a second electrode connected to the first node K.

[0053] The inverter 41 includes a tenth transistor T10 and an eleventh transistor T11. The tenth transistor T10 includes a first electrode connected to the second power supply line, a second electrode for outputting a first control signal, and a control electrode connected to the eighth transistor T8. The eleventh transistor T11 includes a first electrode for outputting the first control signal connected to a third power supply line, a second electrode connected to the eighth transistor T8, and a control electrode connected to the eighth transistor T8. The tenth transistor T10 and the eleventh transistor T11 are different types of transistors. For example, if the tenth transistor T10 is a P-type transistor, then the eleventh transistor T11 is an N-type transistor. Alternatively, if the tenth transistor T10 is an N-type transistor, then the eleventh transistor T11 is a P-type transistor.

[0054] As an example, assuming the tenth transistor T10 is a P-type transistor and the eleventh transistor T11 is an N-type transistor, when the second electrode of the eighth transistor T8 is at a high level, the eleventh transistor T11 is turned on, using the low-level signal transmitted on the third power line as the first control signal. Conversely, when the second electrode of the eighth transistor T8 is at a low level, the tenth transistor T10 is turned on, using the high-level signal transmitted on the second power line as the first control signal, thus ensuring that the potential of the first control signal is always opposite to that of the second electrode of the eighth transistor T8.

[0055] Reference Figure 8 As a further embodiment of the pull-down control circuit 4, the pull-down control circuit 4 also includes a twelfth transistor T12 and a thirteenth transistor T13. The twelfth transistor T12 includes a first electrode connected to the first node K, a second electrode connected to the thirteenth transistor T13, and a control electrode connected to the first clock signal. The thirteenth transistor T13 includes a first electrode connected to the twelfth transistor T12, a second electrode connected to the second power line, and a control electrode connected to the output terminal of the inverter 41.

[0056] Reference Figure 8As a further embodiment of the gate driving device, the gate driving device further includes a second frequency divider circuit 5 and a second output circuit 6. The second frequency divider circuit 5 includes a sixteenth transistor T16, a seventeenth transistor T17, and an eighteenth transistor T18. The sixteenth transistor T16 includes a first electrode connected to the second frequency divider line, a second electrode connected to the seventeenth transistor T17, and a control electrode connected to a first control signal. The seventeenth transistor T17 includes a first electrode connected to the first node K, a second electrode connected to the eighteenth transistor T18, and a control electrode connected to the sixteenth transistor T16. The eighteenth transistor T18 includes a first electrode connected to the seventeenth transistor T17, a second electrode connected to the second output circuit 6, and a control electrode connected to a second control signal.

[0057] Reference Figure 8 The second output circuit 6 includes a nineteenth transistor T19, a twentieth transistor T20, a twenty-first transistor T21, and a twenty-second transistor T22. The nineteenth transistor T19 includes a first electrode for receiving a second clock signal, a second electrode for outputting a second gate drive signal, and a control electrode connected to the eighteenth transistor T18. The twentieth transistor T20 includes a control electrode for receiving a first control signal, a first electrode connected to the nineteenth transistor T19, and a second electrode connected to the second power supply line.

[0058] As an example, the first frequency divider circuit 2 outputs a first gate drive signal based on the first frequency divider signal, and the second frequency divider circuit 5 outputs a second gate drive signal based on the second frequency divider signal. Thus, by controlling the multi-level gate drive units to output the first gate drive signal and the second gate drive signal respectively within multiple frames. As an example, if both the first and second frequency divider signals are at a low potential, the frequencies of all areas on the display panel are equal. If either the first or second frequency divider signal is at a high potential, one of the first transistor T1 and the sixteenth transistor T16 is turned on. Then, one of the corresponding second node W and the first electrode of the eighteenth transistor T18 is electrically disconnected from the first node K, causing one of the first frequency divider circuits 2 and 5 to be unable to be controlled by the first node K in real time, thereby preventing the output of either the first or second gate drive signal, thus achieving the segmented frequency setting of the display panel. Therefore, by preventing the first gate drive signal from abnormally going high during frequency division switching, display abnormalities during frequency division switching can be avoided to a certain extent.

[0059] According to a second aspect of this disclosure, a display panel is provided that includes the gate driving device described above. This display panel possesses all the beneficial effects of the gate driving device described above, which will not be elaborated further herein.

[0060] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0061] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0062] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0063] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A gate driving device, characterized in that, It includes several cascaded gate driving units, each gate driving unit comprising: A cascade circuit, connected to the first node, is used to control the potential of the first node according to the cascade signal; A first frequency divider circuit, connected to the first node, the second node, and the first frequency divider line, is used to control the potential of the second node according to the potential of the first node and the first frequency divider signal transmitted through the first frequency divider line. The first frequency divider circuit includes a first transistor and a second transistor. The first transistor includes a first electrode connected to the first frequency divider line, a second electrode connected to the second transistor, and a control electrode connected to a first control signal. The second transistor includes a control electrode connected to the first transistor, a first electrode connected to the first node, and a second electrode connected to the second node. A first output circuit, connected to the second node, is used to output a first gate drive signal according to the potential of the second node; The first output circuit includes a sixth transistor; the sixth transistor includes a control electrode connected to the second node, a first electrode connected to the third power line, and a second electrode for outputting the first gate drive signal. The second transistor is a dual-gate transistor, so that when the first node is in a low-level state, the potential of the second node is maintained above a preset threshold voltage, thereby turning off the sixth transistor.

2. The gate driving device according to claim 1, characterized in that, The first frequency divider circuit also includes a first capacitor; The first capacitor is connected to the second node and the second electrode of the first transistor.

3. The gate driving device according to claim 2, characterized in that, The cascade circuit includes a third transistor, a fourth transistor, and a fifth transistor; The third transistor includes a control electrode for transmitting signals at the access stage, a first electrode connected to the first power line, and a second electrode connected to the third node. The fourth transistor includes a control electrode for transmitting signals at the access stage, a first electrode connected to the second power line, and a second electrode connected to the third node. The fifth transistor includes a control electrode for receiving a first clock signal, a second electrode connected to the third node, and a second electrode connected to the first node.

4. The gate driving device according to claim 2, characterized in that, The first output circuit also includes a seventh transistor; The seventh transistor includes a control electrode connected to the first node, a first electrode connected to the first power line, and a second electrode connected to the sixth transistor. The seventh transistor is used to pull down the first gate drive signal.

5. The gate driving device according to claim 3, characterized in that, It also includes a pull-down control circuit, used to output the first control signal according to the reset control signal and control the potential of the first node; The pull-down control circuit includes an eighth transistor, a ninth transistor, and an inverter. The eighth transistor includes a control electrode for receiving the reset control signal, a first electrode connected to the second power line, and a second electrode connected to the inverter and the first node. The inverter includes an input terminal connected to the eighth transistor and an output terminal connected to the ninth transistor; The ninth transistor includes a control electrode connected to the inverter, a first electrode connected to the first power line, and a second electrode connected to the first node.

6. The gate driving device according to claim 2, characterized in that, When the first frequency division signal is at its falling edge, the potential of the first node is an active low potential, the potential of the second node is a passive high potential, and the potential difference between the first node and the second node is greater than 10V.

7. The gate driving device according to claim 6, characterized in that, When the first frequency division signal is at its falling edge, the second transistor is turned off; When the second transistor is off, leakage current in the second node is suppressed to slow down the rate of potential drop in the second node.

8. A gate driving device, characterized in that, It includes several cascaded gate driving units, each gate driving unit comprising: A cascade circuit, connected to the first node, is used to control the potential of the first node according to the cascade signal; A first frequency divider circuit, connected to the first node, the second node, and the first frequency divider line, is used to control the potential of the second node according to the potential of the first node and the first frequency divider signal transmitted through the first frequency divider line. The first frequency divider circuit includes a first transistor and a second transistor. The first transistor includes a first electrode connected to the first frequency divider line, a second electrode connected to the second transistor, and a control electrode connected to a first control signal. The second transistor includes a control electrode connected to the first transistor, a first electrode connected to the first node, and a second electrode connected to the second node. A first output circuit, connected to the second node, is used to output a first gate drive signal according to the potential of the second node; The first output circuit includes a sixth transistor; the sixth transistor includes a control electrode connected to the second node, a first electrode connected to the third power line, and a second electrode for outputting the first gate drive signal. The second transistor has a width-to-length ratio greater than 1.5, so that when the first node is in a low-level state, the potential of the second node is maintained above a preset threshold voltage, causing the sixth transistor to conduct in the linear region.

9. A display panel, characterized in that, Includes the gate driving device according to any one of claims 1 to 8.

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