Display device

Abstract

The display device includes: a display panel including pixels, data lines, and gate lines; a data driver connected to the data line; a gate driver connected to the gate line; and a timing controller configured to control the data driver and the gate driver, in which when a frame of the display panel has been switched from a black frame to a gray frame, the timing controller is configured to output a scan signal having an adjusted pulse width for the gray frame immediately after the black frame.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] Recently, the most widely developed display devices include liquid crystal display (LCD) devices, organic light emitting diode (OLED) display devices, and quantum dot light emitting diode (QLED) display devices.

[0003] Among these display devices, a display panel of a liquid crystal display device does not have a self-luminous device.

[0004] Therefore, the liquid crystal display device requires a separate backlight that supplies light to the display panel. In this regard, a light emitting diode LED is used as a light source of the backlight.

[0005] OLED and QLED display devices have OLED and QLED that emit light by themselves and thus do not require a separate backlight, and thus have a fast response speed, high luminous efficiency, high brightness, and a wide viewing angle. Summary of the Invention

[0006] A problem with the display device is that the response characteristics and the flicker characteristics are traded off with each other depending on the voltage intensity.

[0007] Therefore, the inventors of the present disclosure invented a display device that can satisfy both the response characteristics and the flicker characteristics of a driving transistor.

[0008] A technical object according to one embodiment of the present disclosure is to provide a display device including a display panel that can satisfy both response characteristics and flicker characteristics of a driving transistor.

[0009] The objects according to the present disclosure are not limited to the objects mentioned above. Other objects and advantages not mentioned according to the present disclosure can be understood based on the following description and can be more clearly understood based on the embodiments according to the present disclosure. In addition, it will be easily understood that the objects and advantages according to the present disclosure can be achieved using the means shown in the claims or their combination.

[0010] A display device according to one embodiment of the present disclosure may include: a display panel including pixels, data lines, and gate lines; a data driver connected to the data lines; a gate driver connected to the gate lines; and a timing controller configured to control the data driver and the gate driver, wherein, when a frame of the display panel has switched from a black frame to a gray frame, the timing controller is configured to output a scan signal with an adjusted pulse width for a gray frame immediately following the black frame.

[0011] According to one embodiment of the present disclosure, when the display panel operates at a low frequency, the timing controller is configured to output a scan signal having an adjusted pulse width for the gray frame immediately following the black frame when the frame of the display panel has switched from a black frame to a gray frame. Thus, the trade-off between the response characteristics and flicker characteristics of the drive transistor can be resolved, thereby improving both the response characteristics and the flicker characteristics of the drive transistor.

[0012] Furthermore, according to one embodiment of the present disclosure, hysteresis of a driving transistor that may occur when a frame of a display panel has been switched from a black frame to a gray frame may be removed.

[0013] In addition, according to one embodiment of the present disclosure, when the frame of the display panel has switched from a black frame to a gray frame, the timing controller can be configured to output a scan signal with an adjusted pulse width for the gray frame immediately following the black frame, so that the touch efficiency of the display device can be increased and the display device can operate at a low power level, thereby reducing power consumption.

[0014] The effects of the present disclosure are not limited to the above-mentioned effects, and other effects that are not mentioned will be clearly understood by those skilled in the art from the description as set forth below.

[0015] In addition to the above effects, specific effects of the present disclosure will be described together with specific details for carrying out the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a block diagram schematically illustrating a display device according to one embodiment of the present disclosure.

[0017] Figure 2 is an exemplary diagram illustrating a pixel circuit in a display panel according to one embodiment of the present disclosure.

[0018] Figure 3 is a cross-sectional view illustrating a display device according to one embodiment of the present disclosure.

[0019] Figure 4 is an example diagram illustrating a frame based on an operating frequency according to one embodiment of the present disclosure.

[0020] Figure 5 is an exemplary diagram illustrating an operation timing including a data scanning period and a bias scanning period of a pixel circuit according to an embodiment of the present disclosure.

[0021] Figure 6is an exemplary diagram illustrating an example in which a turn-on bias adding frame is inserted when a display panel operates in an AoD mode in which the display panel operates at a low frequency according to an embodiment of the present disclosure.

[0022] Figure 7 1 is an exemplary diagram illustrating an operation timing of modifying a first period with respect to a non-light emitting period of a data scanning period according to an embodiment of the present disclosure.

[0023] Figure 8 1 is an exemplary diagram illustrating an operation timing of modifying a first period with respect to a non-light emitting period of a data scanning period according to another embodiment of the present disclosure.

[0024] Figure 9 1 is an exemplary diagram illustrating an operation timing of modifying a second period for a non-light-emitting period of a data scanning period according to an embodiment of the present disclosure.

[0025] Figure 10 (a) to (c) are experimental results showing response characteristics and flicker characteristics of a display panel operated at an operation sequence according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] The advantages and features of the present disclosure and the methods for achieving the advantages and features will be described with reference to the following and accompanying drawings. Figure 1 The embodiments described in detail below will become apparent. However, the present disclosure is not limited to the embodiments disclosed below, but can be implemented in a variety of different forms. Therefore, these embodiments are set forth only to make the present disclosure complete and to fully inform those of ordinary skill in the art to which the present disclosure belongs of the scope of the present disclosure, and the present disclosure is limited only by the scope of the claims.

[0027] For simplicity and clarity of illustration, the elements in the accompanying drawings are not necessarily drawn to scale. The same reference numerals in different figures represent the same or similar elements and therefore perform similar functions. In addition, for simplicity of description, descriptions and details of well-known steps and elements are omitted. In addition, in the following detailed description of the present disclosure, many specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it should be understood that the present disclosure can be implemented without these specific details. In other cases, well-known methods, processes, components and circuits are not described in detail so as not to unnecessarily obscure the aspects of the present disclosure. Examples of various embodiments are further illustrated and described below. It should be understood that the description herein is not intended to limit the claims to the specific embodiments described. On the contrary, it is intended to cover alternatives, modifications and equivalents that may be included in the spirit and scope of the present disclosure as defined by the appended claims.

[0028] The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for explaining the embodiments of the present disclosure are illustrative, and the present disclosure is not limited thereto.

[0029] The terms used herein are only used to describe the purpose of specific embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular formations "one" and "an" are also intended to include plural formations. It should also be understood that the terms "comprise," "comprises," "includes," and "comprising" specify the presence of stated features, integers, operations, elements, and / or parts when used in this specification, but do not exclude the presence or addition of one or more other features, integers, operations, elements, parts, and / or parts thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated enumerated items.

[0030] Expressions such as "at least one of" when preceding a list of elements may modify the entire list of elements and may not modify the individual elements of the list. In interpreting numerical values, errors or tolerances may occur even if not explicitly stated.

[0031] Additionally, it should be understood that when a first element or layer is referred to as being “on” a second element or layer, the first element may be directly disposed on the second element, or may be indirectly disposed on the second element with a third element or layer disposed between the first element or layer and the second element or layer. It should be understood that when a first element or layer is referred to as being “connected to” or “coupled to” a second element or layer, the first element may be directly connected to or directly coupled to the second element or layer, or one or more intermediate elements or layers may exist therebetween. It should be understood that when an element or layer is referred to as being “between” two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may exist therebetween.

[0032] In a description of a temporal precedence relationship between two events, such as a temporal relationship such as "after," "followed," "before," etc., another event may occur in between unless it is indicated "directly after," "directly followed," or "directly before."

[0033] When a certain embodiment can be implemented differently, the functions or operations specified in a particular block may occur in an order different from the order specified in the flow chart. For example, two consecutive blocks can actually be executed substantially simultaneously, or the two blocks can be executed in reverse order according to the functions or operations involved.

[0034] It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or time periods, these elements, components, regions, layers, and / or time periods should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a first element, component, region, layer, or portion described below may be referred to as a second element, component, region, layer, or portion without departing from the spirit and scope of the present disclosure.

[0035] When the embodiment can be realized differently, the function or operation specified in a particular block can be performed in an order different from the order specified in the flow chart. For example, two consecutive blocks can actually be performed substantially simultaneously, or the blocks can be performed in reverse order according to the related functions or operations.

[0036] The features of various embodiments of the present disclosure may be combined with each other in part or in whole, and may be technically related to each other or operate with each other. The embodiments may be implemented independently of each other, and may be implemented together in a related relationship.

[0037] When interpreting numerical values, unless otherwise expressly stated, the values ​​are interpreted as including the error range.

[0038] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention pertains. It should also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0039] As used herein, "embodiment," "example," "aspect," etc. should not be construed to render any aspect or design described preferred or advantageous over other aspects or designs.

[0040] Furthermore, the term "or" means an inclusive or, not an exclusive or. That is, unless stated otherwise or clear from the context, the expression "x employs a or b" means any of the natural inclusive permutations.

[0041] The terms used in the description as set forth below are selected to be general and commonly used in the relevant technical field. However, other terms may exist in addition to the terms described, depending on the development and / or changes in technology, conventions, preferences of technicians, etc. Therefore, the terms used in the description as set forth below should not be understood as limiting the technical concept, but should be understood as examples of terms used to illustrate the embodiments.

[0042] In addition, in certain cases, the applicant may arbitrarily select terms, and in such cases, their detailed meanings will be described in the corresponding description period. Therefore, the terms used in the description as set forth below should not be understood simply based on the names of the terms but based on the meanings of the terms and the content throughout the detailed description.

[0043] In the description of signal flow, for example, when a signal is delivered from node A to node B, this may include a case where the signal is transferred from node A to node B via another node unless the phrase "immediately transferred" or "directly transferred" is used.

[0044] Throughout this disclosure, unless otherwise stated, "A and / or B" means A, B, or A and B, and unless otherwise stated, "C to D" means C (inclusive) to D (inclusive).

[0045] Hereinafter, a display device according to each embodiment of the present disclosure is described with reference to the accompanying drawings. When describing an embodiment, description of components in a corresponding embodiment that are the same as or similar to those of the previous embodiment will be omitted.

[0046] Figure 1 is a block diagram schematically illustrating a display device according to one embodiment of the present disclosure.

[0047] Reference Figure 1 , a display device 100 according to one embodiment of the present disclosure may include a display panel 110 , a timing controller 120 , a gate driver 130 , a data driver 140 , and a power supply 150 .

[0048] Figure 1 The configuration of the display device 100 shown is an example according to one embodiment, and the components of the display device 100 are not limited to Figure 1 The embodiments shown are described below, and some components may be added, modified, or deleted as needed.

[0049] According to one embodiment, the display panel 110 may include at least one pixel P. The display panel 110 may include a display area ( Figure 3 AA) and non-display area ( Figure 3 NA). Non-display area ( Figure 3 The NA) can surround the display area. It can be in the non-display area ( Figure 3 A gate driver 130 and a data driver 140 are provided in the NA).

[0050] According to one embodiment, a plurality of gate lines GL and a plurality of data lines DL may be provided in the display panel 110. Each of the plurality of pixels P in the display panel 110 may be connected to the gate line GL and the data line DL. The plurality of gate lines GL and the plurality of data lines DL may extend to intersect each other.

[0051] The gate driver 130 may be configured to supply a gate signal to each of the plurality of pixels P. The data driver 140 may supply a data signal to each of the plurality of pixels P. The power supply 150 may be configured to supply power required to drive each of the plurality of pixels P to each of the plurality of pixels P.

[0052] For example, each pixel P may receive a gate signal from the gate driver 130 via a gate line GL and a data signal from the data driver 140 via a data line DL. In addition, each pixel P may receive a high potential driving voltage EVDD and a low potential driving voltage EVSS from the power supply 150. However, embodiments of the present disclosure are not limited thereto. The gate driver 130 includes at least one light emitting control signal driver 131 and at least one scan driver 132. The light emitting control signal driver 131 outputs a light emitting control signal pulse in response to a start pulse and a shift clock from the timing controller 120, and sequentially shifts the light emitting control signal pulse according to the shift clock. The scan driver 132 outputs a scan pulse in response to a start pulse and a shift clock from the timing controller 120, and shifts the scan pulse according to the shift clock timing.

[0053] The gate lines GL may supply scan signals SC and emission control signals EM. The data lines DL may supply data voltages Vdata. Furthermore, according to various embodiments, the gate lines GL may include a plurality of scan lines SCL supplying scan signals SC and emission control signal lines EML supplying emission control signals EM. Furthermore, the display panel 110 may additionally include power lines VL. Thus, each pixel P may receive a bias voltage Vobs and initialization voltages Var and Vini via the power lines VL.

[0054] In addition, if Figure 2 As shown, each pixel P may include a light emitting element EL and a pixel circuit for controlling the operation of the light emitting element EL. In this regard, the light emitting element EL may include an anode electrode 171, a cathode electrode 173, and a light emitting layer 172 between the anode electrode 171 and the cathode electrode 173. Figure 3 However, the embodiments of the present disclosure are not limited thereto.

[0055] According to one embodiment, the pixel circuit may include a plurality of switching elements, a driving element, and a capacitor. However, the embodiments of the present disclosure are not limited thereto. Each of the switching element and the driving element may be implemented as a thin film transistor. In the pixel circuit, the driving element may control the amount of current supplied to the light-emitting element EL based on the data voltage to adjust the amount of light emitted by the light-emitting element EL.

[0056] In addition, each of the plurality of switching elements may receive a scan signal SC supplied via each of the plurality of scan lines SCL and a light emission control signal EM supplied via the light emission control signal line EML, and switch the pixel circuit based on the scan signal and the light emission control signal. The light emission control signal EM may be referred to as a "light emission signal EM." However, embodiments of the present disclosure are not limited thereto.

[0057] According to one embodiment, the display panel 110 can be implemented as a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be applied to a transparent display device in which an image is displayed on a screen and real objects in the background are visible to a viewer in front of the display device. The display panel 110 can be manufactured as a flexible display panel. However, the embodiments of the present disclosure are not limited thereto. The flexible display panel can be implemented as an OLED panel using a plastic substrate. However, the embodiments of the present disclosure are not limited thereto.

[0058] According to one embodiment, the pixel P may include a red pixel, a green pixel, and a blue pixel to emit light of corresponding colors. However, the embodiments of the present disclosure are not limited thereto. The pixel P may also include a white pixel. Each pixel P may include a pixel circuit.

[0059] According to one embodiment, a touch unit or touch sensor may be provided on the display panel 110. Touch input may be sensed using a separate touch sensor, or may be sensed by the pixel P. The touch sensor may be provided on the screen of the display panel in an on-cell type or an add-on type, or may be implemented as an in-cell type touch sensor built into the display panel 110. However, embodiments of the present disclosure are not limited thereto.

[0060] According to one embodiment, the timing controller 120 may be configured to process image data RGB input from an external source, such as a host system, to adapt the size and resolution of the display panel 110, and supply the processed image data to the data driver 140. The timing controller 120 may be configured to generate a gate control signal GCS and a data control signal DCS based on synchronization signals, such as a dot clock signal CLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync input from an external source.

[0061] The timing controller 120 may be configured to supply the generated gate control signal GCS and the data control signal DCS to the gate driver 130 and the data driver 140 , respectively, thereby controlling the gate driver 130 and the data driver 140 .

[0062] According to one embodiment, the timing controller 120 may be configured to be coupled to various processors according to the type of device in which the controller is installed, such as a microprocessor, a mobile processor, an application processor, etc. However, embodiments of the present disclosure are not limited thereto.

[0063] According to one embodiment, the host system may be any one of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, and a vehicle system. However, the embodiments of the present disclosure are not limited thereto.

[0064] According to one embodiment, the timing controller 120 multiplies the input frame frequency by i and uses the frame frequency = input frame frequency × i (i is a positive integer greater than 0) Hz to control the operation timing of each of the gate driver 130 and the data driver 140. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) scheme and 50 Hz in the Phase-Alternating Line (PAL) scheme. However, embodiments of the present disclosure are not limited thereto.

[0065] According to one embodiment, the timing controller 120 may be configured to generate and output signals so that the pixels can operate at various refresh rates. That is, the timing controller 120 may be configured to generate and output operation-related signals so that the pixels can operate in a variable refresh rate (VRR) mode, or their refresh rate can be switched between a first refresh rate and a second refresh rate.

[0066] For example, the timing controller 120 may be configured to simply change the rate of the clock signal to generate a synchronization signal to generate horizontal blanking or vertical blanking, or operate the gate driver 130 in a masking manner so that the pixels P can operate at various refresh rates.

[0067] According to one embodiment, the timing controller 120 may be configured to control the data driver 140 and the gate driver 130. The display device 100 may be adopted in a small device such as a smart phone and may be operated in an AoD (Always on Display) mode. In the AoD mode, the display device may operate at a low frequency to reduce power consumption. The timing controller 120 may be configured to generate (or output) at least one scan signal with an adjusted pulse width for a gray frame to which a frame of the display panel 110 has been switched from a black frame when the display panel 110 operates in the AoD (Always on Display) mode at a low frequency (e.g., 1 Hz). The timing controller 120 may then be configured to send the generated (or output) at least one scan signal to the gate driver 130.

[0068] The timing controller 120 may be configured to generate at least one scan signal having an adjusted pulse width for a gray frame to which a frame of the display panel 110 has switched from a black frame when the display panel 110 operates at a frequency different from 1 Hz (e.g., 10 Hz, 30 Hz, 60 Hz, or 120 Hz). The timing controller 120 may then be configured to transmit the generated at least one scan signal to the gate driver 130.

[0069] For example, when the display panel 110 operates at 1 Hz, one data scan and 239 bias scans may be performed on one frame. However, embodiments of the present disclosure are not limited thereto. In addition, when the display panel 110 operates at 10 Hz, one data scan and 23 bias scans may be performed on one frame. However, embodiments of the present disclosure are not limited thereto. In another example, when the display panel 110 operates at 30 Hz, one data scan and 7 bias scans may be performed on one frame. However, embodiments of the present disclosure are not limited thereto. In another example, when the display panel 110 operates at 60 Hz, one data scan and 3 bias scans may be performed on one frame. However, embodiments of the present disclosure are not limited thereto. In another example, when the display panel 110 operates at 120 Hz, one data scan and one bias scan may be performed on one frame. However, embodiments of the present disclosure are not limited thereto.

[0070] According to one embodiment, the timing controller 120 may be configured to insert a timing of turning on the bias into each of a plurality of subframes in a gray frame to which the frame of the display panel 110 has switched from a black frame. For example, the plurality of subframes may be at least two subframes. However, embodiments of the present disclosure are not limited thereto.

[0071] In addition, the timing controller 120 can be configured to adjust the pulse width (e.g., adjust the on-time or off-time) within the data scanning period in each of the multiple subframes in the gray frame. When the display panel 110 operates at a low frequency, the adjustment of the pulse width can satisfy both the flicker characteristics and the response characteristics of the drive transistor. The change in brightness over time can be converted into the change in brightness over frequency to identify the flicker characteristics. The frequency with the maximum gain in the frequency domain is called the flicker frequency. Therefore, it is possible to identify whether the flicker characteristics are superior or inferior based on the flicker frequency.

[0072] For example, when the frame of the display panel has switched from the black frame to the gray frame, hysteresis may occur in the driving transistor. Therefore, the pulse width of the scanning signal in the gray frame to which the black frame has switched can be adjusted to solve the hysteresis.

[0073] For example, the data scanning period may include: an off bias period to minimize the difference between the characteristics of the gate node of the driving transistor of different frames; an initialization period to resolve the lag of the driving transistor and initialize the gate node of the driving transistor; a sampling period to write the data voltage to the gate node of the driving transistor; and an on bias period to balance the voltage of the data scanning period and the voltage of the bias scanning period with each other.

[0074] According to one embodiment, the timing controller 120 may be configured to adjust a pulse width of at least one scan signal in each of the off bias period and the initialization period.

[0075] In addition, the timing controller 120 may be configured to generate (or output) a scan signal having an adjusted pulse width for the gray frame to which the frame of the display panel has switched from the black frame. For example, the timing controller 120 may be configured to generate (or output) a third scan signal and a fourth scan signal each having an adjusted pulse width.

[0076] According to one embodiment, when the timing controller 120 has sent a control signal to the gate driver 130, the gate driver 130 may generate (or output) a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal. The first scan signal may be a signal for turning on the first transistor T1, and the second scan signal may be a signal for turning on the second transistor T2. The third scan signal may be a signal for turning on the sixth transistor T6 before (or after) the light emitting element EL emits light, and the fourth scan signal may be a signal for turning on the seventh transistor T7.

[0077] According to one embodiment, the timing controller 120 can be configured to add a pulse indicating the start of the timing of the conduction bias to the fourth scan signal to generate (or output) the fourth scan signal. In addition, the timing controller 120 can be configured to generate (or output) a fourth scan signal having an added pulse of the fourth scan signal before the third scan signal is turned on. In this regard, the conduction bias timing can be set to a period from the start time of the pulse added to the fourth scan signal to the time when the third scan signal is turned off. The third scan signal can include a pulse that is turned on at the start time of the pulse added to the fourth scan signal.

[0078] According to one embodiment, the timing controller 120 may be configured to generate a gate control signal GCS for controlling the operation timing of the gate driver 130 and a data control signal DCS for controlling the operation timing of the data driver 140 based on timing signals received from the host system, such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. The timing controller 120 may be configured to control the operation timing of each of the gate driver 130 and the data driver 140 so that the gate driver 130 and the data driver 140 are synchronized with each other.

[0079] According to one embodiment, the voltage level of the gate control signal GCS output from the timing controller 120 can be converted into gate-on voltages VGL and VEL and gate-off voltages VGH and VEH via a level shifter. The gate-on voltages VGL and VEL and the gate-off voltages VGH and VEH can be supplied to the gate driver 130. The level shifter can convert the low-level voltage of the gate control signal GCS into the gate-on voltage VGL having a gate-low voltage, and can convert the high-level voltage of the gate control signal GCS into the gate-off voltage VGH having a gate-high voltage. The gate control signal GCS can include a start pulse and a shift clock.

[0080] According to one embodiment, the gate driver 130 may be configured to supply the scan signal SC to the gate line GL based on the gate control signal GCS supplied from the timing controller 120. The gate driver 130 may be provided at one side or each of two opposite sides of the display panel 110 in a GIP (gate in panel) manner. However, embodiments of the present disclosure are not limited thereto.

[0081] According to one embodiment, the gate driver 130 may be configured to sequentially output gate signals to a plurality of gate lines GL under the control of the timing controller 120. The gate driver 130 may be configured to shift the gate signals using a shift register and sequentially supply the shifted gate signals to the gate lines GL.

[0082] For example, the gate signal may include a scan signal SC and an emission control signal EM in a display device. The scan signal SC may include a scan pulse that swings between a gate-on voltage VGL and a gate-off voltage VGH. The emission control signal EM may include an emission control signal pulse that swings between a gate-on voltage VEL and a gate-off voltage VEH.

[0083] The scan pulse may be synchronized with the data voltage Vdata to select the pixel P of the line to which data is to be written. The light emission control signal EM may define the light emission time of each pixel P.

[0084] According to one embodiment, the gate driver 130 may be configured to include a light emitting control signal driver outputting the light emitting control signal EM and a scan driver outputting at least one scan signal SC.

[0085] For example, the light emitting control signal driver may output a light emitting control signal pulse in response to a start pulse and a shift clock from the timing controller 120 , and may sequentially shift the light emitting control signal pulse according to the shift clock.

[0086] For example, at least one scan driver may output a scan pulse in response to a start pulse and a shift clock from the timing controller 120 , and may shift the scan pulse according to the shift clock timing.

[0087] According to one embodiment, the data driver 140 may convert the image data RGB into the data voltage Vdata based on the data control signal DCS supplied from the timing controller 120 and supply the converted data voltage Vdata to the pixels P through the data lines DL.

[0088] According to one embodiment, the power supply 150 can be configured to use a DC-DC converter to generate the DC power required to drive the pixel array of the display panel 110 and the display panel driver including the gate driver and the data driver. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. However, the embodiments of the present disclosure are not limited to this. The power supply 150 can be configured to receive a DC input voltage applied from the host system and generate DC voltages, such as gate-on voltages VGL and VEL, gate-off voltages VGH and VEH, a high potential drive voltage EVDD, and a low potential drive voltage EVSS. The gate-on voltages VGL and VEL and the gate-off voltages VGH and VEH can be supplied to the level shifter and the gate driver 130. Each of the high potential drive voltage EVDD and the low potential drive voltage EVSS can be supplied to the pixel P in common.

[0089] Figure 2is an exemplary diagram of a pixel circuit in a display panel according to an embodiment of the present disclosure.

[0090] Figure 2 Only an example of a pixel circuit is shown for illustration. The structure of the pixel circuit is not particularly limited as long as its structure can apply the light emitting control signal EM(n) to the pixel to control the light emitting element EL. For example, the pixel circuit may include a switching thin film transistor connected to an additional scanning signal and a switching thin film transistor to which an additional initialization voltage is applied. The connection relationship of the switching element or the connection position of the capacitor may vary. In the following, for the convenience of description, the description is made of a pixel circuit having Figure 2 However, the embodiments of the present disclosure are not limited thereto.

[0091] Reference Figure 2 Each of the plurality of pixels P according to an embodiment of the present disclosure may include a pixel circuit including a driving transistor DT and a light emitting element EL connected to the pixel circuit. However, the embodiment of the present disclosure is not limited thereto.

[0092] According to one embodiment, the pixel circuit can control the driving current flowing through the light-emitting element EL to drive the light-emitting element EL. The pixel circuit may include a driving transistor DT, first to seventh transistors T1 to T7, and a capacitor Cst. Each of the transistors DT and T1 to T7 may include a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode may be a source electrode, and the other of the first electrode and the second electrode may be a drain electrode.

[0093] According to one embodiment, each of the transistors DT and T1 to T7 may be a P-type thin film transistor or an N-type thin film transistor. Figure 2 In an embodiment of the present disclosure, the first transistor T1 and the seventh transistor T7 are implemented as N-type thin film transistors, and the remaining transistors DT and T2 to T6 are implemented as P-type thin film transistors. However, the embodiments of the present disclosure are not limited thereto. According to an embodiment, each of all or some of the transistors DT and T1 to T7 may be a P-type thin film transistor or an N-type thin film transistor. In addition, the N-type thin film transistor may be implemented as an oxide thin film transistor, and the P-type thin film transistor may be implemented as a low-temperature polycrystalline silicon (LTPS) thin film transistor. For example, one of the transistors DT, T1 to T7 may be implemented as one or a combination of an oxide thin film transistor and a low-temperature polycrystalline silicon (LTPS) thin film transistor.

[0094] Hereinafter, an example is described in which the first transistor T1 and the seventh transistor T7 are implemented as N-type thin film transistors and the remaining transistors DT and T2 to T6 are implemented as P-type thin film transistors. However, the embodiments of the present disclosure are not limited thereto. Therefore, when a high voltage is applied to each of the first transistor T1 and the seventh transistor T7, each of the first transistor T1 and the seventh transistor T7 can be turned on. When a low voltage is applied to each of the remaining transistors DT and T2 to T6, each of the remaining transistors DT and T2 to T6 can be turned on.

[0095] According to one embodiment, the first transistor T1 constituting the pixel circuit may be used as a compensation transistor, the second transistor T2 may be used as a data supply transistor, each of the third transistor T3 and the fourth transistor T4 may be used as a light emitting control transistor, the fifth transistor T5 may be used as a bias transistor, and each of the sixth transistor T6 and the seventh transistor T7 may be used as an initialization transistor. However, the embodiments of the present disclosure are not limited thereto. In addition, the sixth transistor T6 may be used as a reset transistor among the initialization transistors to reset the anode electrode of the light emitting element (EL). However, the embodiments of the present disclosure are not limited thereto.

[0096] According to one embodiment, the light emitting element EL may include a first electrode and a second electrode. The first electrode of the light emitting element EL may be an anode electrode, and the second electrode of the light emitting element EL may be a cathode electrode. The anode electrode of the light emitting element EL may be connected to the fifth node N5, and the cathode electrode thereof may be connected to the low potential driving voltage EVSS.

[0097] According to one embodiment, the driving transistor DT may include a first electrode connected to the second node N2, a second electrode connected to the third node N3, and a gate electrode connected to the first node N1. The driving transistor DT may provide a driving current Id to the light emitting element EL based on the voltage of the first node N1 or the data voltage stored in the capacitor Cst, which will be described later. For example, the driving transistor DT may be connected to the third node N3 and the second node N2 and disposed between the third node N3 and the second node N2.

[0098] According to one embodiment, the first transistor T1 may include a first electrode connected to the first node N1, a second electrode connected to the third node N3, and a first gate electrode that receives the first scan signal SC1(n). The first transistor T1 may be turned on in response to the first scan signal SC1(n), thereby establishing a diode connection between the first node N1 and the third node N3 to sample the threshold voltage Vth of the drive transistor DT. The first transistor T1 may function as a compensation transistor. However, embodiments of the present disclosure are not limited thereto. For example, the first transistor T1 may be connected to the third node N3 and the first node N1 and disposed between the third node N3 and the first node N1.

[0099] According to one embodiment, the capacitor Cst may be connected to the first node N1 and the fourth node N4 and disposed between the first node N1 and the fourth node N4. The capacitor Cst may store or hold therein the high potential driving voltage EVDD supplied thereto.

[0100] According to one embodiment, the second transistor T2 may include a first electrode connected to the data line DL or receiving the data voltage Vdata, a second electrode connected to the second node N2, and a second gate electrode receiving the second scan signal SC2(n). The second transistor T2 may be turned on in response to the second scan signal SC2(n) and may thus transmit the data voltage Vdata to the second node N2. The second transistor T2 may function as a data supply transistor. However, embodiments of the present disclosure are not limited thereto. The second transistor T2 may be connected to the data line and the second node N2 and disposed between the data line and the second node N2.

[0101] According to one embodiment, the third transistor T3 and the fourth transistor T4 (or the first light emission control transistor and the second light emission control transistor) can be connected to the high potential driving voltage EVDD and the light emitting element EL and arranged between the high potential driving voltage EVDD and the light emitting element EL, and can establish a current flow path through which the driving current Id generated by the driving transistor DT flows.

[0102] According to one embodiment, the third transistor T3 may include a first electrode connected to the fourth node N4 to receive the high-potential driving voltage EVDD, a second electrode connected to the second node N2, and a third gate electrode receiving the light emitting control signal EM(n). The third transistor T3 may be connected to the fourth node N4 and the second node N2 and disposed between the fourth node N4 and the second node N2.

[0103] According to one embodiment, the fourth transistor T4 may include a first electrode connected to the third node N3, a second electrode connected to the fifth node N5 (or the anode electrode of the light emitting element EL), and a fourth gate electrode receiving the light emitting control signal EM(n). The fourth transistor T4 may be connected to the third node N3 and the fifth node N5 and disposed between the third node N3 and the fifth node N5.

[0104] According to one embodiment, each of the third transistor T3 and the fourth transistor T4 may be turned on in response to the light emitting control signal EM(n). In this case, the driving current Id may be supplied to the light emitting element EL so that the light emitting element EL may emit light at a brightness level corresponding to the driving current Id.

[0105] According to one embodiment, the fifth transistor T5 may include a first electrode receiving a bias voltage Vobs, a second electrode connected to the second node N2, and a fifth gate electrode receiving the third scan signal SC3(n). The fifth transistor T5 may be a bias transistor. However, embodiments of the present disclosure are not limited thereto. The fifth transistor T5 may be connected to a bias voltage line and a second node N2 and disposed between the bias voltage line and the second node N2.

[0106] According to one embodiment, the sixth transistor T6 may include a first electrode receiving the first initialization voltage Var, a second electrode connected to the fifth node N5, and a sixth gate electrode receiving the third scan signal SC3(n). The first electrode of the sixth transistor T6 may be connected to the reset voltage line. The sixth transistor T6 may be connected to the first initialization voltage line and the fifth node N5 and disposed between the first initialization voltage line and the fifth node N5.

[0107] According to one embodiment, the sixth transistor T6 can be turned on in response to the third scan signal SC3(n) before (or after) the light emitting element EL emits light, so that the anode electrode (or pixel electrode) of the light emitting element EL can be initialized based on the first initialization voltage Var.

[0108] The light-emitting element EL may have a parasitic capacitor generated between the anode electrode and the cathode electrode. Therefore, when the light-emitting element EL emits light, the parasitic capacitor may be charged, so that the anode electrode of the light-emitting element EL may have a specific voltage. Therefore, the amount of charge accumulated in the light-emitting element EL can be initialized by applying a first initialization voltage Var to the anode electrode of the light-emitting element EL via the sixth transistor T6.

[0109] In the present disclosure, the fifth transistor T5 and the sixth transistor T6 are configured such that the gate electrodes of the fifth transistor T5 and the sixth transistor T6 receive the third scan signal SC3(n) in common. However, embodiments of the present disclosure are not necessarily limited thereto, and the fifth transistor T5 and the sixth transistor T6 are configured such that the gate electrodes of the fifth transistor T5 and the sixth transistor T6 receive separate scan signals, and thus the fifth transistor T5 and the sixth transistor T6 operate independently.

[0110] According to one embodiment, the seventh transistor T7 may include a first electrode receiving the second initialization voltage Vini, a second electrode connected to the first node N1, and a seventh gate electrode receiving the fourth scan signal SC4(n). The seventh transistor T7 may be connected to the second initialization voltage line and the first node N1 and disposed between the second initialization voltage line and the first node N1.

[0111] According to one embodiment, the seventh transistor T7 may be turned on in response to the fourth scan signal SC4(n), so that the gate electrode of the driving transistor DT may be initialized using the second initialization voltage Vini. Due to the high potential driving voltage EVDD stored in the capacitor Cst, unnecessary charge may remain in the gate electrode of the driving transistor DT. Therefore, the residual charge amount may be initialized by applying the second initialization voltage Vini to the gate electrode of the driving transistor DT via the seventh transistor T7.

[0112] Figure 3 is a cross-sectional view illustrating a display device according to an embodiment of the present disclosure.

[0113] Reference Figure 3 The display device 100 according to an embodiment of the present disclosure may include a fourth transistor T4 disposed on a substrate 101. The fourth transistor T4 may include a fourth semiconductor layer 115, a fourth gate electrode 125, and a source electrode 14a and a drain electrode 14b, referred to as first and second electrodes thereof, respectively. The substrate 101 may include a display area AA and a non-display area NA. The display area AA may display an image. The non-display area NA may be disposed around or surround the display area AA. The fourth transistor T4 may function as a light emission control transistor for driving the light emitting element EL in the display area AA. However, embodiments of the present disclosure are not limited thereto.

[0114] According to one embodiment of the present disclosure, the display device 100 may have a sixth transistor T6 disposed on the substrate 101 .

[0115] The sixth transistor T6 may include a sixth semiconductor layer 215, a sixth gate electrode 225, and a source electrode 24a and a drain electrode 24b, respectively referred to as a first electrode and a second electrode thereof. The sixth transistor T6 may function as a reset transistor for resetting the anode electrode of the light-emitting element EL in the display area AA. However, embodiments of the present disclosure are not limited thereto.

[0116] For ease of illustration, only the fourth transistor T4 and the sixth transistor T6 are shown among the various thin film transistors that may be included in the display device 100. However, another thin film transistor that functions as a switching transistor may be included in the display device 100. Furthermore, an example in which the thin film transistors have a coplanar structure is described. However, the thin film transistors may be implemented with other structures such as a staggered structure. However, embodiments of the present disclosure are not limited thereto.

[0117] According to one embodiment, the fourth transistor T4 can receive a high-potential driving voltage EVDD in response to a light-emission control signal EM supplied to its fourth gate electrode 125, and control the current to be supplied to the light-emitting element EL based on the received high-potential driving voltage EVDD, thereby controlling the amount of light emitted by the light-emitting element EL. The fourth transistor T4 can allow a constant current to be supplied to the light-emitting element EL using the voltage charged in the storage capacitor Cst until the data signal of the next frame is supplied to the light-emitting element EL, so that the light-emitting element EL can maintain a light-emitting state. The high-voltage supply line can extend in parallel with the data line. However, embodiments of the present disclosure are not limited thereto.

[0118] According to one embodiment, the sixth transistor T6 can receive a first initialization voltage (reset voltage signal) Var in response to a scan signal SC supplied to its sixth gate electrode 225, and send the reset voltage signal to the anode electrode (which is connected to the fifth node N5) serving as the first electrode of the light emitting element EL, thereby resetting the anode electrode of the light emitting element EL.

[0119] According to one embodiment, the fourth transistor T4 may include a fourth semiconductor layer 115, a fourth gate electrode 125, and source and drain electrodes 14a and 14b. Figure 3As shown. Although the first electrode of the fourth transistor T4 is schematically shown as a source electrode and the second electrode is a drain electrode, the embodiments of the present disclosure are not limited thereto. Alternatively, when its first electrode is a drain electrode, its second electrode may be a source electrode. A fourth semiconductor layer 115 may be provided on the first insulating layer 11. A second insulating layer 12 may be provided on the fourth semiconductor layer 115. A fourth gate electrode 125 may be provided on the second insulating layer 12. The fourth gate electrode 125 may overlap with the fourth semiconductor layer 115. For example, the fourth gate electrode 125 may overlap with the fourth semiconductor layer 115 with the second insulating layer 12 interposed therebetween. A source electrode 14a and a drain electrode 14b may be provided on the third insulating layer 135. The source electrode 14a and the drain electrode 14b may be in contact with the fourth semiconductor layer 115. The fourth transistor T4 may include a P-type MOS thin film transistor (P-MOSFET) or a low-temperature polycrystalline silicon (LTPS) thin film transistor. However, the embodiments of the present disclosure are not limited thereto.

[0120] According to one embodiment, the sixth transistor T6 may include a sixth semiconductor layer 215, a sixth gate electrode 225, and source and drain electrodes 24a and 24b. Figure 3 As shown. Although it is schematically shown that in the sixth transistor T6, the first electrode is a source electrode and the second electrode is a drain electrode, the embodiments of the present disclosure are not limited thereto. Alternatively, when the first electrode is a drain electrode, the second electrode may be a source electrode. A sixth semiconductor layer 215 may be provided on the first insulating layer 11. A sixth gate electrode 225 may be provided on the second insulating layer 12. The sixth gate electrode 225 may overlap with the sixth semiconductor layer 215. For example, the sixth gate electrode 225 may overlap with the sixth semiconductor layer 215 with the second insulating layer 12 interposed therebetween. A source electrode 24a and a drain electrode 24b may be provided on the third insulating layer 135. The source electrode 24a and the drain electrode 24b may be in contact with the sixth semiconductor layer 215. The sixth transistor T6 may include an N-type MOS thin film transistor (N-MOSFET) or an oxide thin film transistor. However, the embodiments of the present disclosure are not limited thereto.

[0121] According to one embodiment, each of the fourth semiconductor layer 115 and the sixth semiconductor layer 215 can be a region where a channel is formed when a thin film transistor (TFT) operates. Each of the fourth semiconductor layer 115 and the sixth semiconductor layer 215 can be made of an oxide semiconductor, or can be made of each of various organic semiconductors such as amorphous silicon (a-Si), polycrystalline silicon (poly-Si), low temperature polycrystalline silicon (LTPS) or pentacene. However, the embodiments of the present disclosure are not limited thereto. The fourth semiconductor layer 115 and the sixth semiconductor layer 215 can be disposed on the first insulating layer 11. Each of the fourth semiconductor layer 115 and the sixth semiconductor layer 215 can include a channel region, a source region and a drain region. The channel region of the fourth semiconductor layer 115 can overlap with the fourth gate electrode 125, with the second insulating layer 12 interposed therebetween, and the channel region of the fourth semiconductor layer 115 can be disposed between the source electrode 14a and the drain electrode 14b. The channel region of the sixth semiconductor layer 215 may overlap with the sixth gate electrode 225 with the second insulating layer 12 interposed therebetween, and the channel region of the sixth semiconductor layer 215 may be disposed between the source electrode 24a and the drain electrode 24b. The source region of the fourth semiconductor layer 115 may be electrically connected to the source electrode 14a via a contact hole extending through the second insulating layer 12 and the third insulating layer 135. The source region of the sixth semiconductor layer 215 may be electrically connected to the source electrode 24a via a contact hole extending through the second insulating layer 12 and the third insulating layer 135. The drain region of the fourth semiconductor layer 115 may be electrically connected to the drain electrode 14b via a contact hole extending through the second insulating layer 12 and the third insulating layer 135. The drain region of the sixth semiconductor layer 215 may be electrically connected to the drain electrode 24b via a contact hole extending through the second insulating layer 12 and the third insulating layer 135. A buffer layer 105 and a first insulating layer 11 may be disposed between each of the fourth semiconductor layer 115 and the sixth semiconductor layer 215 and the substrate 101. The buffer layer 105 may delay diffusion of moisture and / or oxygen that has penetrated into the substrate 101. The first insulating layer 11 protects the fourth semiconductor layer 115 and the sixth semiconductor layer 215, and may block various types of defects introduced from the substrate 101.

[0122] According to one embodiment, the uppermost layer of the buffer layer 105 in contact with the first insulating layer 11 may be made of a material having an etching characteristic different from that of each of the remaining layers of the buffer layer 105, the first insulating layer 11, the second insulating layer 12, and the third insulating layer 135. However, the embodiments of the present disclosure are not limited thereto. The uppermost layer of the buffer layer 105 in contact with the first insulating layer 11 may be made of silicon nitride (SiN x ) and silicon oxide (SiO x) are made of one of the following. However, the embodiments of the present disclosure are not limited thereto. Each of the remaining layer of the buffer layer 105, the first insulating layer 11, the second insulating layer 12, and the third insulating layer 135 may be made of silicon nitride (SiN x ) and silicon oxide (SiO x ) is made of the other one of the above. However, the embodiments of the present disclosure are not limited thereto. For example, the uppermost layer of the buffer layer 105 in contact with the first insulating layer 11 may be made of silicon nitride (SiN x ), and each of the remaining layers of the buffer layer 105, the first insulating layer 11, the second insulating layer 12, and the third insulating layer 135 may be made of silicon oxide (SiO x However, the embodiments of the present disclosure are not limited thereto.

[0123] According to one embodiment, the fourth gate electrode 125 and the sixth gate electrode 225 may be formed on the second insulating layer 12. The fourth gate electrode 125 and the sixth gate electrode 225 may overlap with the channel regions of the fourth semiconductor layer 115 and the sixth semiconductor layer 215, respectively, with the second insulating layer 12 interposed therebetween. Each of the fourth gate electrode 125 and the sixth gate electrode 225 may be made of a first conductive material and may be implemented as a single layer or multiple layers made of magnesium (Mg), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof. However, embodiments of the present disclosure are not limited thereto.

[0124] According to one embodiment, the source electrode 14a may be connected to the exposed source region of the fourth semiconductor layer 115 via a contact hole extending through the second insulating layer 12 and the third insulating layer 135. The source electrode 24a may be connected to the exposed source region of the sixth semiconductor layer 215 via a contact hole extending through the second insulating layer 12 and the third insulating layer 135. The drain electrode 14b may be opposite to the source electrode 14a and may be connected to the drain region of the fourth semiconductor layer 115 via a contact hole extending through the second insulating layer 12 and the third insulating layer 135. The drain electrode 24b may be opposite to the source electrode 24a and may be connected to the drain region of the sixth semiconductor layer 215 via a contact hole extending through the second insulating layer 12 and the third insulating layer 135. Each of the source electrodes 14a and 24a and the drain electrodes 14b and 24b may be made of a second conductive material and may be implemented as a single layer or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof. However, embodiments of the present disclosure are not limited thereto.

[0125] According to one embodiment, a connection electrode 155 may be provided between the first intermediate layer 15 and the second intermediate layer 16. The connection electrode 155 may be connected to each of the drain electrodes 14 b and 24 b via a connection electrode contact hole 156 extending through the protective film 145 and the first intermediate layer 15. The connection electrode 155 may be made of a material having a low resistivity and being the same as or similar to the material of each of the drain electrodes 14 b and 24 b. However, embodiments of the present disclosure are not limited thereto.

[0126] Reference Figure 3 , a light-emitting element EL including a light-emitting layer 172 may be provided on the second intermediate layer 16 and the bank layer 165. The light-emitting element EL may include an organic electroluminescent diode. However, the embodiments of the present disclosure are not limited thereto. For example, the light-emitting element EL may include an inorganic light-emitting element, a quantum dot element, a micro-LED element, or a mini-LED element. However, the embodiments of the present disclosure are not limited thereto. In the light-emitting element EL, the first electrode may be an anode electrode, and the second electrode may be a cathode electrode.

[0127] According to one embodiment, the light emitting element EL may include an anode electrode 171 , at least one light emitting layer 172 formed on the anode electrode 171 , and a cathode electrode 173 formed on the light emitting layer 172 .

[0128] According to one embodiment, the anode electrode 171 may be electrically connected to an exposed portion of the connection electrode 155 disposed on the first intermediate layer 15 and facing the second intermediate layer 16 via a contact hole extending through the second intermediate layer 16 .

[0129] According to one embodiment, the anode electrode 171 of each pixel may be exposed without being covered by the bank layer 165. The bank layer 165 may be made of an opaque material (e.g., black) to prevent light interference between adjacent pixels. In this case, the bank layer 165 may include a light-shielding material comprising at least one of a color pigment, organic black, and carbon black. However, the embodiments of the present disclosure are not limited thereto. The bank layer 165 may be made of a material comprising a black pigment or an organic material such as a benzocyclobutene resin, a polyimide resin, an acrylic resin, or a photosensitive polymer. However, the embodiments of the present disclosure are not limited thereto. When the bank layer 165 is made of a material comprising a black pigment or a black dye, the bank layer may be a black bank layer. When the bank layer 165 is made of a material comprising a black pigment or a black dye, the bank layer may block light from the outside or light reflected from the outside, thereby further improving the brightness of the display device. Spacers may also be provided on the bank layer 165. The spacers may be made of the same material as the bank layer 165. However, the embodiments of the present disclosure are not limited thereto.

[0130] Reference Figure 3, at least one light-emitting layer 172 may be formed on a portion of the anode electrode 171 corresponding to the light-emitting area defined by the bank layer 165. At least one light-emitting layer 172 may include a hole transport layer, a hole injection layer, a hole blocking layer, a light-emitting layer 172, an electron injection layer, an electron blocking layer, and an electron transport layer on the anode electrode 171. The stacking order of the hole transport layer, the hole injection layer, the hole blocking layer, the light-emitting layer 172, the electron injection layer, the electron blocking layer, and the electron transport layer may be based on the light-emitting direction. However, the embodiments of the present disclosure are not limited thereto. In addition, the light-emitting layer 172 may include a first light-emitting stack and a second light-emitting stack facing each other, with a charge generation layer inserted therebetween. In this case, the light-emitting layer 172 of one of the first light-emitting stack and the second light-emitting stack may generate blue light, while the light-emitting layer 172 of the other of the first light-emitting stack and the second light-emitting stack may generate yellow-green light, so that white light can be generated from the combination of the first light-emitting stack and the second light-emitting stack. However, the embodiments of the present disclosure are not limited thereto. The white light generated by the combination of the first and second light-emitting stacks can be incident on a color filter located above or below the light-emitting layer 172, so that a color image can be realized. In another example, each light-emitting layer 172 can generate light of each color corresponding to each pixel without the need for a separate color filter, so that a color image can be presented. For example, the light-emitting layer 172 of a red (R) pixel emits red light, the light-emitting layer 172 of a green (G) pixel emits green light, and the light-emitting layer 172 of a blue (B) pixel emits blue light.

[0131] Reference Figure 3 The cathode electrode 173 may be formed to face the anode electrode 171 with the light emitting layer 172 disposed therebetween, and may receive a high potential driving voltage EVDD.

[0132] According to one embodiment, the encapsulation stack or encapsulation layer 18 can prevent external moisture or oxygen from penetrating into the light-emitting element EL that is susceptible to external moisture or oxygen. To this end, the encapsulation layer 18 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. However, the embodiments of the present disclosure are not limited thereto. In the present disclosure, the structure of the encapsulation layer 18 is described by way of example, in which the first encapsulation layer 181, the second encapsulation layer 182, and the third encapsulation layer 183 are stacked sequentially. However, the embodiments of the present disclosure are not limited thereto.

[0133] According to one embodiment, the first encapsulation layer 181 may be formed on the substrate 101 on which the cathode electrode 173 has been formed. The third encapsulation layer 183 may be formed on the substrate 101 on which the second encapsulation layer 182 has been formed. The third encapsulation layer 183 and the first encapsulation layer 181 may surround the top surface, bottom surface, and side surfaces of the second encapsulation layer 182. The first encapsulation layer 181 and the third encapsulation layer 183 may minimize or prevent external moisture or oxygen from penetrating into the light emitting element EL. Each of the first encapsulation layer 181 and the third encapsulation layer 183 may be made of an inorganic insulating material that can be deposited at a low temperature, such as silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiON), or aluminum oxide (Al2O3). However, the embodiments of the present disclosure are not limited thereto. Each of the first encapsulation layer 181 and the third encapsulation layer 183 is deposited in a low-temperature atmosphere. Therefore, during the deposition process of the first encapsulation layer 181 and the third encapsulation layer 183, damage to the light-emitting element EL, which is susceptible to the high-temperature atmosphere, can be prevented.

[0134] According to one embodiment, the second encapsulation layer 182 is used as a shock absorbing layer to reduce the interlayer stress caused by the bending of the display device 100, and can flatten the steps between the layers. The second encapsulation layer 182 can be made of a non-photosensitive organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, polyethylene or silicon oxycarbon (SiOC), or made of a photosensitive organic insulating material such as photo acrylic. However, the embodiments of the present disclosure are not limited to this. When the second encapsulation layer 182 is formed using an inkjet method, a dam DAM can be provided to prevent the liquid second encapsulation layer 182 from diffusing to the edge of the substrate 101. The dam DAM can be closer to the edge of the substrate 101 than the second encapsulation layer 182. The dam DAM can prevent the liquid second encapsulation layer 182 from diffusing to the pad area, in which a conductive pad arranged on the outermost side of the substrate 101 is provided.

[0135] According to one embodiment, the dam DAM is designed to prevent the diffusion of the second encapsulation layer 182. However, if the second encapsulation layer 182 overflows the dam DAM during processing, the second encapsulation layer 182, as an organic layer, may be exposed to the outside, allowing moisture and the like to invade the light-emitting element. Therefore, to prevent this invasion, at least two dams DAM may be stacked. However, embodiments of the present disclosure are not limited thereto.

[0136] Reference Figure 3 , the dam DAM may be provided on the protection film 145 and in the non-display area NA.

[0137] Furthermore, the dam DAM, the first intermediate layer 15, and the second intermediate layer 16 can be formed simultaneously. However, embodiments of the present disclosure are not limited thereto. The first intermediate layer 15 and the lower layer of the dam DAM can be formed simultaneously. The second intermediate layer 16 and the upper layer of the dam DAM can be formed simultaneously. Thus, the dam DAM can have a two-layer structure. However, embodiments of the present disclosure are not limited thereto.

[0138] Therefore, the dam DAM may be made of the same material as that of each of the first and second intermediate layers 15 and 16. However, embodiments of the present disclosure are not limited thereto.

[0139] Reference Figure 3 The dam DAM may overlap the low potential driving power line VSS. For example, the low potential driving power line VSS may be formed in a layer below the dam DAM and in the non-display area NA.

[0140] According to one embodiment, the low potential drive power line VSS and the gate driver 30 in the form of a gate in panel (GIP) may surround the periphery of the display panel. The low potential drive power line VSS may be located outside the gate driver 30. In addition, the low potential drive power line VSS may be connected to the anode electrode 171 to apply a common voltage thereto. The gate driver 30 is simply shown in plan view and cross-sectional view. However, the gate driver 30 may be configured using a thin film transistor (TFT) having the same structure as that of the thin film transistor (TFT) of the display area AA. However, the embodiments of the present disclosure are not limited thereto.

[0141] Reference Figure 3 , the low potential drive power line VSS can be set outside the gate driver 30. The low potential drive power line VSS can be set outside the gate driver 30 and can surround the display area AA. The low potential drive power line VSS can be made of the same material as the source electrodes 14a and 24a and the drain electrodes 14b and 24b of the fourth thin film transistor T4 and the sixth thin film transistor T6. However, the embodiments of the present disclosure are not limited to this. For example, the low potential drive power line VSS can be made of the same material as the material of each of the fourth gate electrode 125 and the sixth gate electrode 225. However, the embodiments of the present disclosure are not limited to this.

[0142] Furthermore, the low potential driving power line VSS may be electrically connected to the anode electrode 171. Alternatively, the low potential driving power line VSS may be electrically connected to the cathode electrode 173. The low potential driving power line VSS may supply a low potential driving voltage EVSS to a plurality of pixels in the display area AA.

[0143] According to one embodiment, a touch layer 19 may be provided on the encapsulation layer 18. In the touch layer 19, a buffer film 191 may be positioned between a touch sensor metal including touch connection electrodes 192 and 194 and touch electrodes 195 and 196 and the cathode electrode 173 of the light emitting element EL.

[0144] According to one embodiment, the buffer film 191 can prevent chemical substances (developer, etchant, etc.) used in the manufacturing process of the touch sensor metal provided on the buffer film 191 or moisture from the outside from intruding into the light emitting layer 172 including the organic material. Therefore, the buffer film 191 can prevent damage to the light emitting layer 172 that is susceptible to chemical substances or moisture.

[0145] According to one embodiment, the buffer film 191 may be made of an organic insulating material that may be formed at a low temperature lower than or equal to a specific temperature (100 degrees Celsius) to prevent damage to the light-emitting layer 172 including an organic material that is susceptible to high temperatures, and the organic insulating material has a low dielectric constant of 1 to 3. However, the embodiments of the present disclosure are not limited thereto. For example, the buffer film 191 may be made of an acrylic, epoxy, or siloxane-based material. However, the embodiments of the present disclosure are not limited thereto. The buffer film 191 made of an organic insulating material and having a planarizing property may prevent damage to the encapsulation layer 18 due to bending of the display device and fracture of the touch sensor metal formed on the buffer film 191.

[0146] According to one embodiment, according to a touch sensor structure based on mutual capacitance, the touch electrodes 195 and 196 may be provided on the buffer film 191 and the touch electrodes 195 and 196 may be provided to intersect each other. However, embodiments of the present disclosure are not limited thereto.

[0147] According to one embodiment, the touch connection electrodes 192 and 194 may electrically connect the touch electrodes 195 and 196 to each other. The touch connection electrodes 192 and 194 and the touch electrodes 195 and 196 may be positioned on different layers with the touch insulation film 193 interposed therebetween. However, embodiments of the present disclosure are not limited thereto.

[0148] According to one embodiment, the touch connection electrodes 192 and 194 may overlap the bank layer 165 , thereby preventing the aperture ratio of the display device from being reduced.

[0149] According to one embodiment, a portion of the touch connection electrode 192 may extend along the upper and side surfaces of the encapsulation layer 18 and the upper and side surfaces of the dam DAM, and then may be electrically connected to a touch driver circuit (not shown) via the touch pad 198. Thus, the touch electrodes 195 and 196 may be electrically connected to the touch driver circuit.

[0150] According to one embodiment, a portion of the touch connection electrode 192 can receive a touch drive signal from a touch driver circuit and send the touch drive signal to the touch electrodes 195 and 196, and can receive a touch sensing signal from the touch electrodes 195 and 196 and send the touch sensing signal to the touch driver circuit.

[0151] According to one embodiment, a protective film 197 may be provided on the touch electrodes 195 and 196. In the accompanying drawings, protective film 197 is shown provided only on the touch electrodes 195 and 196. However, embodiments of the present disclosure are not limited thereto. Protective film 197 may extend to the inner or outer ends of the dam DAM and, therefore, may also be provided on the touch connection electrode 192.

[0152] In addition, a color filter (not shown) may be further provided on the encapsulation layer 18, and the color filter may be positioned on the touch layer 19 or between the encapsulation layer 18 and the touch layer 19. However, embodiments of the present disclosure are not limited thereto.

[0153] exist Figure 3 In the embodiment of the present invention, the display area AA of the display device 100 can be configured as follows. The buffer layer 105 can be provided on the substrate 101 including the display area AA and the non-display area NA. The first insulating layer 11 can be provided on the buffer layer 105. The fourth semiconductor layer 115 of the fourth transistor T4 and the sixth semiconductor layer 215 of the sixth transistor T6 can be provided on the first insulating layer 11. The second insulating layer 12 can be provided on the first insulating layer 11, the fourth semiconductor layer 115, and the sixth semiconductor layer 215.

[0154] According to one embodiment, the low potential driving power line VSS, the fourth gate electrode 125 of the fourth transistor T4, and the sixth gate electrode 225 of the sixth transistor T6 may be disposed on the second insulating layer 12. The third insulating layer 135 may be disposed on the second insulating layer 12, the low potential driving power line VSS, the fourth gate electrode 125, and the sixth gate electrode 225. Both the fourth gate electrode 125 and the sixth gate electrode 225 may be in contact with the light emitting signal line.

[0155] According to one embodiment, the first electrode 14a and the second electrode 14b of the fourth transistor T4 and the first electrode 24a and the second electrode 24b of the sixth transistor T6 may be disposed on the third insulating layer 135. Each of the first electrode 14a and the second electrode 14b of the fourth transistor T4 may be in contact with the fourth semiconductor layer 115 via a first contact hole, and each of the first electrode 24a and the second electrode 24b of the sixth transistor T6 may be in contact with the sixth semiconductor layer 215 via a second contact hole. A protective film 145 may be disposed on the third insulating layer 135, the first electrode 14a and the second electrode 14b of the fourth transistor T4, and the first electrode 24a and the second electrode 24b of the sixth transistor T6.

[0156] According to one embodiment, the first intermediate layer 15 may be provided on the protective film 145 and in the display area AA. The connecting electrode 155 may be provided on the first intermediate layer 15 and in the display area AA. The connecting electrode 155 may contact the first electrode 14a or the second electrode 14b of the fourth transistor T4 via the connecting electrode contact hole (third contact hole) 156, and may contact the first electrode 24a or the second electrode 24b of the sixth transistor T6 via another connecting electrode contact hole (third contact hole) 156. The first electrode 14a or the second electrode 14b of the fourth transistor T4 not connected to the connecting electrode 155 may contact the driving transistor. The first electrode 24a or the second electrode 24b of the sixth transistor T6 not connected to the connecting electrode 155 may contact the reset voltage line. The second intermediate layer 16 may be provided on the first intermediate layer 15 and the connecting electrode 155 and in the display area AA.

[0157] According to one embodiment, the first electrode 171 of the light-emitting element EL may be provided on the second intermediate layer 16 and in the display area AA. The first electrode 171 of the light-emitting element EL may contact the connection electrode 155 via a fourth contact hole. The bank layer 165 may be provided on the second intermediate layer 16 except for the first electrode 171 of the light-emitting element EL and in the display area AA. The light-emitting layer 172 may be provided on the bank layer 165 and the first electrode 171 of the light-emitting element EL and in the display area AA. The second electrode 173 of the light-emitting element EL may be provided on the light-emitting layer 172 and in the display area AA. The encapsulation stack or encapsulation layer 18 may be provided on the second electrode 173 of the light-emitting element EL and in the display area AA and on the protective film 145 in the non-display area NA.

[0158] Figure 4 is an example diagram illustrating a frame based on an operating frequency according to an embodiment of the present disclosure. Figure 5 is an exemplary diagram illustrating an operation timing including a data scanning period and a bias scanning period of a pixel circuit according to an embodiment of the present disclosure.

[0159] Reference Figure 4 , Figure 4 (a) is an exemplary diagram illustrating a case where the display panel 110 according to an embodiment of the present disclosure operates at 120 Hz. Figure 4 (b) is an exemplary diagram illustrating a case where the display panel 110 according to an embodiment of the present disclosure operates at 60 Hz. Figure 4 (c) is an exemplary diagram illustrating a case where the display panel 110 according to an embodiment of the present disclosure operates at 30 Hz.

[0160] Reference Figure 4 , when the display panel 110 operates at 120 Hz ( Figure 4 (a)), each of the data scanning period 311 and the bias scanning period 312 may appear once within one frame. However, the embodiments of the present disclosure are not limited thereto. In another example, when the display panel 110 operates at 60 Hz ( Figure 4 (b)), the data scan period 321 may appear once in one frame, and the bias scan period 322 may appear three times in one frame. However, the embodiments of the present disclosure are not limited thereto. In another example, when the display panel 110 operates at 30 Hz ( Figure 4 (c)), the data scanning period 331 may appear once within one frame, and the bias scanning period 332 may appear 7 times within one frame. However, embodiments of the present disclosure are not limited thereto.

[0161] For example, when the display panel 110 operates at 10 Hz, the data scan period may occur once within one frame, and the bias scan period may occur 23 times within one frame. However, embodiments of the present disclosure are not limited thereto. In another example, when the display panel 110 operates at 1 Hz, the data scan period may occur once within one frame, and the bias scan period may occur 239 times within one frame. However, embodiments of the present disclosure are not limited thereto.

[0162] As described above, when the display panel 110 operates at an increasingly lower frequency, the data scan period may occur once within one frame, and the number of bias scan periods occurring within one frame may increase. However, embodiments of the present disclosure are not limited thereto.

[0163] Reference Figure 5, each of the data scanning period 430 and the bias scanning period 460 of the pixel circuit may include non-luminous periods 410 and 440 and luminous periods 420 and 450. However, the embodiments of the present disclosure are not limited thereto. The non-luminous period 410 of the data scanning period 430 may include four periods 401, 402, 403, and 404 (which may also be referred to herein as four periods P1, P2, P3, and P4, respectively). However, the embodiments of the present disclosure are not limited thereto.

[0164] The first period 401 of the time periods may be an off-bias period for minimizing the difference between the characteristics of the gate node of the drive transistor in different frames. The second period 402 may be an initialization period for resolving the hysteresis of the drive transistor and initializing the gate node of the drive transistor. The third period 403 may be a sampling period for writing the data voltage to the gate node of the drive transistor. The fourth period 404 may be an on-bias period for balancing the voltage of the data scanning period and the voltage of the bias scanning period.

[0165] The display device according to an embodiment of the present disclosure can operate in VRR (variable refresh rate) mode. However, the embodiment of the present disclosure is not limited thereto. In VRR mode, the display device operates at a constant frequency. However, when high-speed operation is required, the refresh rate at which the data voltage Vdata is updated increases. Therefore, the pixels operate at an increased refresh rate. When low power consumption or low-speed operation is required, the refresh rate is reduced so that the pixels operate at a reduced refresh rate. However, the embodiment of the present disclosure is not limited thereto.

[0166] According to one embodiment, each of the plurality of pixels P may operate based on a combination of a refresh frame and a hold frame within 1 second. However, embodiments of the present disclosure are not limited thereto. In the present disclosure, a setup is defined as a combination of a refresh frame in which the data voltage Vdata is updated and a hold frame in which the data voltage Vdata is not updated within 1 second. The combination of the refresh frame and the hold frame is repeated based on one setup period.

[0167] When the device operates at a refresh rate of 120 Hz, only the refresh frame can be repeated. That is, the refresh frame can be repeated 120 times in 1 second. One refresh frame period is 1 / 120=8.33 ms, and one setup period is also 8.33 ms.

[0168] When the refresh rate is 60 Hz, the refresh frame and the hold frame can be repeated alternately. That is, the refresh frame and the hold frame can be repeated alternately so that each of the refresh frame and the hold frame can be repeated 60 times within 1 second. Therefore, each of one refresh frame period and one hold frame period is 0.5 / 60=8.33 ms, and one setup period is 16.66 ms.

[0169] When the refresh rate is 1 Hz, one frame can include one refresh frame and 119 hold frames following the refresh frame. In addition, when the refresh rate is 1 Hz, one frame can include multiple refresh frames and multiple hold frames. In this regard, the period of each of one refresh frame and one hold frame is 1 / 120 = 8.33 ms, and one setup period is 1 s.

[0170] In the refresh frame, a new data voltage Vdata is charged to apply the new data voltage Vdata to the driving transistor DT. In the hold frame, the data voltage Vdata of the previous frame is held. In this regard, the hold frame can be referred to as a skip period in the sense that the process of applying the new data voltage Vdata to the driving transistor DT is omitted in the hold frame.

[0171] Each of the plurality of pixels P can initialize a charged voltage or residual voltage within the pixel circuit during a refresh frame. Specifically, each of the plurality of pixels P can remove the effects of the data voltage Vdata and the high-potential driving voltage EVDD stored in the previous frame during the refresh frame. Therefore, each of the plurality of pixels P can display an image corresponding to the new data voltage Vdata during a hold frame.

[0172] Each of the plurality of pixels P may display an image by supplying a driving current corresponding to the data voltage Vdata to the light emitting element EL during a holding frame, and may maintain a turned-on state of the light emitting element EL.

[0173] The pixel circuit may operate such that a refresh frame includes at least one bias period 401 and 404, an initialization period 402, a sampling period 403, and a light emitting period 405. However, this is merely an example and embodiments of the present disclosure are not necessarily limited thereto.

[0174] The pixel circuit may be operated such that a refresh frame includes at least one bias period 401 and 404 .

[0175] According to one embodiment, at least one of the bias periods 401 and 404 is a period during which an on-bias stress operation OBS is performed by applying a bias voltage Vobs. During the bias period, the emission control signal EM(n) may be at a high voltage, and the third transistor T3 and the fourth transistor T4 may be turned off. The first scan signal SC1(n) and the fourth scan signal SC4(n) may be at a low voltage, and the first transistor T1 and the seventh transistor T7 may be turned off. The second scan signal SC2(n) may be at a high voltage, and the second transistor T2 may be turned off.

[0176] According to one embodiment, a low voltage third scan signal SC3 (n) may be input and the fifth and sixth transistors T5 and T6 may be turned on. When the fifth transistor T5 is turned on, the bias voltage Vobs may be applied to the first electrode of the driving transistor DT connected to the second node N2.

[0177] In this regard, the bias voltage Vobs can be supplied to the third node N3 as the drain electrode of the driving transistor DT, thereby reducing the charging time or charging delay of the voltage of the fifth node N5 as the anode electrode of the light emitting element EL during the light emission period. The driving transistor DT can be maintained in a strong saturation state.

[0178] For example, as the bias voltage Vobs increases, the voltage of the third node N3 as the drain electrode of the driving transistor DT may increase, and the gate-source voltage or drain-source voltage of the driving transistor DT may decrease. Therefore, the bias voltage Vobs may be at least greater than the data voltage Vdata.

[0179] In this regard, the magnitude of the drain-source current Id flowing through the drive transistor DT can be reduced, and the stress of the drive transistor DT can be reduced in the case of positive bias stress, thereby resolving the charging delay of the voltage of the third node N3. In addition, the hysteresis of the drive transistor DT can be alleviated by performing a turn-on bias stress operation on the drive transistor DT before sampling the threshold voltage Vth of the drive transistor DT.

[0180] Therefore, in at least one bias period 401 and 402 , the on-bias stress operation OBS may be defined as an operation of directly applying an appropriate bias voltage to the driving transistor DT during a non-light emitting period.

[0181] In addition, when the sixth transistor T6 may be turned on in at least one bias period 401 and 402 , the anode electrode (or pixel electrode) of the light emitting element EL connected to the fifth node N5 may be initialized with the first initialization voltage Var.

[0182] The fifth transistor T5 and the sixth transistor T6 may be configured such that their gate electrodes receive separate scan signals and are thus independently controlled. That is, it is not necessary to apply bias voltage to the first electrode of the driving transistor DT and the anode electrode of the light emitting element EL at the same time during the bias period.

[0183] Reference Figure 5 , the pixel circuit may operate such that an initialization period 402 is included in a refresh frame. The initialization period 402 refers to a period for initializing the voltage of the gate electrode of the driving transistor DT.

[0184] During the initialization period 402, each of the first scan signal SC1(n), the fourth scan signal SC4(n), and the light emitting control signal EM(n) may be at a high voltage, and the first transistor T1 and the seventh transistor T7 may be turned on. The second to sixth transistors T2, T3, T4, T5, and T6 may be turned off. When the first transistor T1 and the seventh transistor T7 are turned on, the gate electrode of the driving transistor DT connected to the first node N1 and the drain electrode of the driving transistor DT connected to the third node N3 may be initialized with the initialization voltage Vini.

[0185] Reference Figure 5 , the pixel circuit may operate such that the sampling period 403 is included in the refresh frame. The sampling period refers to a period for sampling the threshold voltage Vth of the driving transistor DT.

[0186] During the sampling period 403, each of the first scan signal SC1(n), the third scan signal SC3(n), and the light emitting control signal EM(n) may be at a high voltage, and each of the second scan signal SC2(n) and the fourth scan signal SC4(n) may be at a low voltage. Therefore, the third to seventh transistors T3, T4, T5, T6, and T7 may be turned off, the first transistor T1 may remain in an on state, and the second transistor T2 may be turned on. That is, the second transistor T2 may be turned on so that the data voltage Vdata may be applied to the driving transistor DT, and thus, a diode connection may be established between the first node N1 and the third node N3 of the first transistor T1, so that the threshold voltage Vth of the driving transistor DT may be sampled.

[0187] Reference Figure 5 , the pixel circuit can operate so that the light emitting period 405 is included in the refresh frame. The light emitting period 405 refers to a period during which the light emitting element EL emits light under a driving current corresponding to the sampled data voltage Vdata.

[0188] In the light emitting period 405 , the light emitting control signal EM(n) may be at a low voltage, and the third transistor T3 and the fourth transistor T4 may be turned on.

[0189] When the third transistor T3 is turned on, the high potential driving voltage EVDD connected to the fourth node N4 can be applied to the first electrode of the driving transistor DT connected to the second node N2 via the third transistor T3. The driving current Id supplied from the driving transistor DT to the light-emitting element EL via the fourth transistor T4 can be independent of the value of the threshold voltage Vth of the driving transistor DT. Therefore, the threshold voltage Vth of the driving transistor DT can be compensated.

[0190] Reference Figure 5The hysteresis characteristics of the driving transistor vary according to the timing of each of the first period 401 and the second period 402, so that the change in the threshold voltage Vth due to the hysteresis may cause a deviation in the response characteristics. In order to improve the response characteristics, the hysteresis of the driving transistor should be eliminated (or controlled) by applying a significant level of on-bias in the first period 401 and the second period 402 before the third period 403.

[0191] However, when the conduction bias of the first period 401 and the second period 402 increases, the balance between the threshold voltage of the data scanning period and the threshold voltage of the bias period may be damaged. Therefore, when the display panel 110 operates at a low frequency, flicker may occur due to fluctuations in brightness within the frame. Therefore, the current operation timing may not meet both the response characteristics and the flicker characteristics.

[0192] Hereinafter, a driving method for satisfying both the response characteristic and the flicker characteristic of the driving transistor when the display panel 110 operates at a low frequency, for example, in an AoD (Always-On Display) mode is described.

[0193] Figure 6 is an exemplary diagram illustrating an example in which a turn-on bias adding frame is inserted when a display panel operates in an AoD mode in which the display panel operates at a low frequency according to an embodiment of the present disclosure. Figure 7 1 is an exemplary diagram illustrating an operation timing of modifying a first period with respect to a non-light emitting period of a data scanning period according to an embodiment of the present disclosure. Figure 8 1 is an exemplary diagram illustrating an operation timing of modifying a first period with respect to a non-light emitting period of a data scanning period according to another embodiment of the present disclosure. Figure 9 1 is an exemplary diagram illustrating an operation timing of modifying a second period for a non-light-emitting period of a data scanning period according to an embodiment of the present disclosure.

[0194] Reference Figure 6 In order to satisfy (or control) both the response characteristics and the flicker characteristics of the driving transistor, which have a trade-off relationship with each other, the display device 100 according to one embodiment of the present disclosure may be configured to insert the timing of the on-bias into each of the plurality of gray frames within a reference time, such as a POR (power-on reset) timing optimized for the initial flicker characteristics of the gray frame, after the frame PTN of the display panel 110 switches from the black frame to the gray frame. For example, the POR frame may have a refresh rate of 1 Hz, and the frame into which the on-bias is inserted (or the on-bias addition frame) may have a refresh rate of 10 Hz. The POR frame following the on-bias addition frame may have a refresh rate of 1 Hz.

[0195] According to one embodiment, when the display panel 110 switches from a black frame (e.g., 5 frames) to a gray frame (e.g., 10 frames), a hysteresis of the driving transistor may occur. To this end, the display device 100 (e.g., the timing controller 120) of the present disclosure can be configured to generate and output a scanning signal with an adjusted pulse width for each of a plurality of gray frames 510 (e.g., 3 gray frames) following the black frame (e.g., 5 black frames) to meet both the response characteristics and the flicker characteristics of the driving transistor.

[0196] Alternatively, the timing controller 120 can be configured to send a control signal to the gate driver 130 to generate a scan signal with an adjusted pulse width for each of a plurality of gray frames 510 (e.g., three gray frames), so that the gate driver 130 can output a scan signal with an adjusted pulse width for each of a plurality of gray frames 510 (e.g., three gray frames) after the black frame (e.g., five black frames).

[0197] Reference Figure 7 According to one embodiment, the gate driver 130 may output a first scan signal 610 , a second scan signal 620 , a third scan signal 630 , a fourth scan signal 640 and a light emitting control signal 650 to the display panel 110 under the control of the timing controller 120 .

[0198] According to one embodiment, the timing controller 120 may be configured to send a control signal to the gate driver 130, the control signal being used to control output of the fourth scan signal 640 having an adjusted pulse width during the first period 601. The gate driver 130 may output the fourth scan signal 640 having an adjusted pulse width 642 during the first period 601 based on the control signal.

[0199] According to one embodiment, the timing controller 120 can control the output of the fourth scan signal 640 having an adjusted pulse width 642 (in this regard, the adjustment refers to changing the off bias to the on bias) within the first period 601 to the output of the gate driver 130, and the gate driver 130 can in turn apply the fourth scan signal 640 having a pulse (on bias) 641 added to the fourth scan signal 640 to the gate electrode of the driving transistor DT.

[0200] According to one embodiment, the timing controller 120 may control the gate driver 130 so as to output the fourth scan signal 640 including the pulse 641 of the first period 601 before the third scan signal 630 is turned on by the pulse 631. For example, the third scan signal 630 may be turned on by the pulse 631 at a time when the fourth scan signal 640 has been turned off in the first period 601. For example, in the first period 601, the width of the pulse 631 of the third scan signal may be equal to the width 642 of the pulse 641 of the fourth scan signal.

[0201] As described above, the timing controller 120 according to the present disclosure can be configured to control the gate driver 130 so that within the first period 601, before the third scan signal 630 is turned on by the pulse 631, the fourth scan signal 640 having an adjusted width 642 of the pulse 641 of the first period 601 is output, thereby initializing the gate electrode of the driving transistor DT using the second initialization voltage Vini.

[0202] Reference Figure 8 According to one embodiment, the gate driver 130 may output a first scan signal 710 , a second scan signal 720 , a third scan signal 730 , a fourth scan signal 740 and a light emitting control signal 750 to the display panel 110 under the control of the timing controller 120 .

[0203] According to one embodiment, the timing controller 120 may be configured to send a control signal to the gate driver 130, the control signal being used to control output of each of the third scan signal 730 having an adjusted pulse width and the fourth scan signal 740 having an adjusted pulse width during the first period 701. The gate driver 130 may output the third scan signal 730 having an adjusted pulse width 732 and the fourth scan signal 740 having an adjusted pulse width 742 during the first period 701 based on the control signal.

[0204] According to one embodiment, the timing controller 120 may be configured to control the gate driver 130 to output a third scan signal 730 having an adjusted pulse width 732 of a pulse 731 (in this respect, the adjustment refers to changing the off bias to the on bias) during the first period 701, thereby turning on the sixth transistor T6. Furthermore, the timing controller 120 may be configured to control the gate driver 130 to output a fourth scan signal 740 having an adjusted pulse width 742 of a pulse 741 (in this respect, the adjustment refers to changing the off bias to the on bias) during the first period 701, and apply the fourth scan signal 740 including a bias voltage to the gate electrode of the drive transistor DT. Due to the bias voltage, the drive transistor DT may be initialized.

[0205] According to one embodiment, the timing controller 120 may control the gate driver 130 so that, during the first period 701, after the third scan signal 730 is turned on by the pulse 731, the fourth scan signal 740 having the adjusted width 742 of the pulse 741 is output. Alternatively, during the first period 701, at the time point when the third scan signal 730 is turned on (the left falling edge of the pulse 731), the fourth scan signal 740 having the adjusted width 742 of the pulse 741 may be turned on. For example, during the first period 701, the width 732 of the pulse 731 of the third scan signal may be greater than the width 742 of the pulse 741 of the fourth scan signal.

[0206] The timing controller 120 according to the present disclosure may be configured to control the gate driver 130 so that, during the first period 701, after the third scan signal 730 is turned on by the pulse 731, the fourth scan signal 740 having the adjusted pulse width 742 of the pulse 741 is output, thereby turning on the fifth transistor T5 and the sixth transistor T6. When the fifth transistor T5 is turned on, the bias voltage Vobs may be applied to the first electrode of the driving transistor DT connected to the second node N2.

[0207] Reference Figure 9 According to one embodiment, the gate driver 130 may be configured to output a first scan signal 810 , a second scan signal 820 , a third scan signal 830 , a fourth scan signal 840 and a light emitting control signal 850 to the display panel 110 under the control of the timing controller 120 .

[0208] According to one embodiment, the timing controller 120 may be configured to send a control signal to the gate driver 130, the control signal being used to control output of the fourth scan signal 840 having an adjusted pulse width 842 during the second period 802. The gate driver 130 may be configured to output the fourth scan signal 840 having an adjusted pulse width 842 of 841 during the second period 802 based on the control signal.

[0209] According to one embodiment, the timing controller 120 may be configured to control the output of the fourth scan signal 840 having the adjusted width 842 of the pulse 841 (in this respect, the adjustment refers to increasing the application time of the on-bias in the second period 802) through the gate driver 130 to apply the bias voltage to the gate electrode of the driving transistor DT. In other words, the timing controller 120 may be configured to increase the application time of the on-bias for initializing the gate node of the driving transistor.

[0210] According to one embodiment, the timing controller 120 may be configured to control the gate driver 130 so that the third scan signal 830 is turned on by the pulse 831 during the first period 801, and then, the fourth scan signal 840 having the adjusted width 842 of the pulse 841 is output during the second period 802. For example, after the third scan signal 830 has been turned on by the pulse 831 during the first period 801, the fourth scan signal 840 may be turned on by the pulse 841 during the second period 802.

[0211] Figure 10 (a) to (c) are experimental results showing response characteristics and flicker characteristics of a display panel operated at an operation sequence according to another embodiment of the present disclosure.

[0212] Figure 10 (a) in FIG. 1 is an example diagram in which two frames with an on-bias added thereto are inserted into the POR timing. Figure 10 (b) in FIG. 1 is an experimental result showing the response characteristics of a display panel operated at the operation timing according to another embodiment of the present disclosure. Figure 10 (c) in FIG. 1 is an experimental result showing the flicker characteristics of a display panel operated at an operation timing according to another embodiment of the present disclosure. Figure 10 In (b), the horizontal axis may refer to time (seconds), and the vertical axis may refer to brightness ratio (%). Figure 10 In (c), the horizontal axis may refer to time (seconds), and the vertical axis may refer to brightness level (cd / m 2 ).

[0213] It can be determined that when the display panel is turned on based on the operation timing ( Figure 8 ) operates at a frequency of 10 Hz, both the response characteristic 1020 and the flicker characteristic 1030 of the driving transistor for the eighth frame are improved.

[0214] The timing controller 120 according to the present disclosure may be configured to control the gate driver 130 so that after the third scan signal 830 has been turned on by the pulse 831 in the first period 801, the fourth scan signal 840 having the adjusted pulse 841 width 842 is output in the second period 802, thereby increasing the on-bias application time for removing the hysteresis of the driving transistor DT using the second initialization voltage Vini. In addition, Figure 9 The implementation method can also be compared with the Figure 7 or Figure 8 The described embodiments are combined to improve both response characteristics and scintillation characteristics.

[0215] In addition, when the display panel 110 operates in an AoD (always on display) mode in which the display panel operates at a low frequency, the timing controller 120 of the display device 100 of the present disclosure can be configured to control the output of a scanning signal with an adjusted pulse width for a gray frame to which the frame of the display panel has been switched from a black frame, thereby improving both the response characteristics and the flicker characteristics of the driving transistor.

[0216] The display device according to various embodiments of the present disclosure can be applied to mobile devices, video phones, smart watches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, bending devices, sliding devices, variable devices, electronic notebooks, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbook computers, workstations, navigation devices, vehicle navigation devices, vehicle display devices, vehicle equipment, cinema equipment, cinema display devices, televisions, wallpaper devices, signage devices, gaming devices, notebooks, monitors, cameras, camcorders, and home appliances.

[0217] A display device according to one aspect and some embodiments of the present disclosure may be described as follows.

[0218] One aspect of the present disclosure provides a display device comprising: a display panel including pixels, data lines, and gate lines; a data driver connected to the data lines; a gate driver connected to the gate lines; and a timing controller configured to control the data driver and the gate driver, wherein, when a frame of the display panel has switched from a black frame to a gray frame, the timing controller is configured to output a scan signal with an adjusted pulse width for a gray frame immediately following the black frame.

[0219] According to some embodiments of the display device, the timing controller is configured to provide a control signal for controlling at least one driving transistor of a pixel of the display panel to a gate driver.

[0220] According to some embodiments of the display device, the gray frame immediately following the black frame includes a plurality of gray frames, wherein the timing controller is configured to insert the turn-on bias timing into each of the plurality of gray frames.

[0221] According to some embodiments of the display device, the timing controller is configured to adjust a pulse width of the scan pulse within the data scan period for each of the plurality of gray frames.

[0222] According to some embodiments of the display device, the number of the plurality of gray frames is at least two.

[0223] According to some embodiments of the display device, the data scanning period includes: an off-bias period for minimizing the difference between the characteristics of the gate node of the driving transistor of different frames; an initialization period for initializing the gate node of the driving transistor; a sampling period for writing the data voltage to the gate node of the driving transistor; and an on-bias period between the data scanning period and the bias scanning period.

[0224] According to some embodiments of the display device, the timing controller is configured to adjust a pulse width of the at least one scan signal in each of the off bias period and the initialization period.

[0225] According to some embodiments of the display device, the timing controller is configured to control output of each of the first scan signal, the second scan signal, the third scan signal, and the fourth scan signal.

[0226] According to some embodiments of the display device, the timing controller is configured to control the output of the fourth scan signal by inserting a pulse indicating a start of the on-bias timing into the fourth scan signal.

[0227] According to some embodiments of the display device, the timing controller is configured to control output of the fourth scan signal having the inserted pulse before the third scan signal is turned on.

[0228] According to some embodiments of the display device, the turn-on bias timing is set to a period from a start time of a pulse inserted into the fourth scan signal to a timing at which the third scan signal starts to be turned off.

[0229] According to some embodiments of the display device, the third scan signal includes a pulse that is turned on at a start time of the inserted pulse.

[0230] Although some embodiments of the present disclosure have been described above with reference to the accompanying drawings, the present disclosure may not be limited to some embodiments and may be implemented in various different forms. Those skilled in the art of the present disclosure will understand that the present disclosure may be implemented in other specific forms without changing the technical ideas or basic features of the present disclosure. Therefore, it should be understood that some of the embodiments described above are not restrictive in all aspects, but illustrative.

Claims

1. A display device, comprising: A display panel, comprising pixels, data lines, and gate lines; a data driver connected to the data line; a gate driver connected to the gate line; as well as a timing controller configured to control the data driver and the gate driver, Wherein, when the frame of the display panel has switched from a black frame to a gray frame, the timing controller is configured to output a scan signal with an adjusted pulse width for the gray frame immediately following the black frame.

2. The display device according to claim 1, wherein The timing controller is configured to provide a control signal for controlling at least one driving transistor of the pixel of the display panel to the gate driver.

3. The display device according to claim 1, wherein The gray frame immediately following the black frame includes a plurality of gray frames, The timing controller is configured to insert a turn-on bias timing into each of the plurality of gray frames.

4. The display device according to claim 3, wherein The timing controller is configured to adjust a pulse width of the scan signal within a data scan period for each of the plurality of gray frames.

5. The display device according to claim 3, wherein The number of the plurality of gray frames is at least 2. The display device according to claim 4 , wherein: The data scanning period includes: an off bias period for minimizing a difference between characteristics of gate nodes of driving transistors of the pixels of the display panel of different frames; an initialization period for initializing the gate node of the driving transistor; a sampling period for writing a data voltage to the gate node of the driving transistor; and A bias-on period is between the data scanning period and the bias scanning period.

7. The display device according to claim 6, wherein The timing controller is configured to adjust a pulse width of at least one scan signal in at least one of the off bias period and the initialization period.

8. The display device according to claim 6, wherein The timing controller is configured to control output of each of the first scan signal, the second scan signal, the third scan signal, and the fourth scan signal.

9. The display device according to claim 8, wherein The timing controller is configured to control output of the fourth scan signal by inserting a pulse indicating a start of the on-bias timing into the fourth scan signal.

10. The display device according to claim 9, wherein The timing controller is configured to control output of the fourth scan signal having the inserted pulse before the third scan signal is turned on.

11. The display device according to claim 8, wherein The on-bias timing is set to a period from a start time of a pulse inserted into the fourth scan signal to a timing at which the third scan signal starts to be turned off.

12. The display device according to claim 11, wherein The third scan signal includes a pulse turned on at the start time of the inserted pulse.

13. The display device according to claim 1, wherein The timing controller is configured to increase, for the gray frame, an application time of a turn-on bias for initializing a gate node of a driving transistor of the pixel of the display panel.

14. The display device according to claim 8, wherein The third scan signal is used to apply a bias voltage to a source or a drain of the driving transistor, and the fourth scan signal is used to initialize a gate of the driving transistor.

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