Gate driver and display device including same

Abstract

According to one aspect of the present disclosure, a gate driver includes a plurality of stages, each of which includes: a node controller configured to control voltages of a Q node, a Q2 node, a Qb node, and a QN node connected to a transistor based on a first clock signal and a second clock signal; a dummy signal output unit configured to output a dummy signal based on voltages of the Q node and the Qb node; and a scan signal output unit configured to output a scan signal to the scan line based on voltages of the Q node and the QN node, and in a structure of the scan signal output unit, a transistor configured to output a gate low voltage as the scan signal in accordance with the voltage of the Q node is a P-type transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0029727 filed on February 29, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a gate driver and a display device including the gate driver. Background Art

[0004] With the advent of the information age, the field of displays that visually represent electrical information signals has rapidly developed. In response, display devices with excellent performance, such as thinness, light weight, and low power consumption, have been developed. Examples of such display devices include liquid crystal displays (LCDs) and organic light-emitting displays (OLEDs). Summary of the Invention

[0005] The display device includes driving circuits such as a data driver supplying data signals to data lines, a gate driver supplying gate signals to gate lines disposed in a display area, and a timing controller configured to control the data driver and the gate driver.

[0006] One object to be achieved by the present disclosure is to provide a gate driver including a P-type transistor and a display device including the gate driver.

[0007] Another object to be achieved by the present disclosure is to provide a gate driver with improved response speed and a display device including the gate driver.

[0008] Another object to be achieved by the present disclosure is to provide a gate driver that minimizes a frame size and a display device including the gate driver.

[0009] Another object to be achieved by the present disclosure is to provide a gate driver with improved driving reliability and a display device including the gate driver.

[0010] The objects of the present disclosure are not limited to the above objects, and those skilled in the art can clearly understand other objects not mentioned above from the following description.

[0011] According to one aspect of the present disclosure, a gate driver includes multiple stages, each of the multiple stages including: a node controller, the node controller is configured to control the voltages of the Q node, the Q2 node, the Qb node and the QN node connected to the transistor based on a first clock signal and a second clock signal; a virtual signal output unit, the virtual signal output unit is configured to output a virtual signal based on the voltages of the Q node and the Qb node; and a scan signal output unit, the scan signal output unit is configured to output a scan signal to a scan line based on the voltages of the Q node and the QN node, and in the structure of the scan signal output unit, the transistor configured to output a gate low voltage as the scan signal according to the voltage of the Q node can be a P-type transistor.

[0012] According to one aspect of the present disclosure, a display device includes: a display panel including an active area provided with a plurality of pixels; and the gate driver.

[0013] Additional details of exemplary embodiments are included in the detailed description and accompanying drawings.

[0014] According to the present disclosure, the rising time and the falling time of the scan signal can be minimized, thereby improving the response speed of the display device.

[0015] In the present disclosure, the area occupied by the gate driver can be minimized, thereby reducing the frame size.

[0016] According to the present disclosure, a complete low level can be output, thereby suppressing positive bias temperature stress of a gate driver, so that driving reliability can be improved.

[0017] According to the present disclosure, node voltage fluctuation of a gate driver can be minimized, thereby improving driving stability of the gate driver.

[0018] Effects of the present disclosure are not limited to the aforementioned effects, and other effects not mentioned above will be apparently understood by those of ordinary skill in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0020] Figure 1 is a block diagram illustrating a display device according to an exemplary embodiment of the present disclosure;

[0021] Figure 2is a cross-sectional view illustrating a stacked structure of a display device according to an exemplary embodiment;

[0022] Figure 3 is a diagram illustrating a structure of a gate driver in a display device according to an exemplary embodiment of the present disclosure;

[0023] Figure 4 is a diagram of a pixel circuit in a display device according to an exemplary embodiment of the present disclosure;

[0024] Figure 5A and Figure 5B It means Figure 4 FIG. 1 is a diagram illustrating operations of a scan signal and a light emission control signal in a refresh period and a hold period in a pixel circuit shown in FIG.

[0025] Figure 6 is a circuit diagram of a stage of a gate driver of a display device according to an exemplary embodiment of the present disclosure;

[0026] Figure 7 is a waveform illustrating signals input to and output from a plurality of stages of a gate driver of a display device according to an exemplary embodiment of the present disclosure;

[0027] Figure 8A is a circuit diagram illustrating operations of multiple stages of a gate driver of a display device according to an exemplary embodiment of the present disclosure in a first period;

[0028] Figure 8B is a circuit diagram illustrating operations of a plurality of stages of a gate driver of a display device according to an exemplary embodiment of the present disclosure in a second period;

[0029] Figure 8C is a circuit diagram illustrating operations of a plurality of stages of a gate driver of a display device according to an exemplary embodiment of the present disclosure in a third period;

[0030] Figure 8D is a circuit diagram illustrating operations of a plurality of stages of a gate driver of a display device according to an exemplary embodiment of the present disclosure in a fourth period;

[0031] Figure 9 is a circuit diagram of a gate driver stage of a display device according to another exemplary embodiment of the present disclosure;

[0032] Figure 10 is a waveform illustrating signals input to and output from a plurality of stages of a gate driver of a display device according to another exemplary embodiment of the present disclosure;

[0033] Figure 11Ais a circuit diagram illustrating operations of a plurality of stages of a gate driver of a display device according to another exemplary embodiment of the present disclosure in a first period;

[0034] Figure 11B is a circuit diagram illustrating operations of a plurality of stages of a gate driver of a display device according to another exemplary embodiment of the present disclosure in a second period;

[0035] Figure 11C is a circuit diagram illustrating operations of a plurality of stages of a gate driver of a display device according to another exemplary embodiment of the present disclosure in a third period;

[0036] Figure 11D is a circuit diagram illustrating operations of a plurality of stages of a gate driver of a display device according to another exemplary embodiment of the present disclosure in a fourth period;

[0037] Figure 12 is a circuit diagram of a gate driver stage of a display device according to still another exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] The advantages and features of the present disclosure and the methods for achieving these advantages and features are described in detail below and in the accompanying drawings. Figure 1 The exemplary embodiments described in detail below will become clear. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example to enable those skilled in the art to fully understand the disclosure of the present invention and the scope of the present disclosure.

[0039] The shapes, sizes, proportions, angles, quantities, etc. shown in the accompanying drawings for the purpose of describing exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. The same reference numerals generally represent the same elements throughout the application. In addition, in the description below the present disclosure, detailed explanations of known related arts may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including," "having," and "consisting of" used herein are generally intended to allow the addition of other components, unless the term "only" is used in these terms. Any reference in the singular may include the plural, unless otherwise expressly stated.

[0040] Even if not explicitly stated, parts are interpreted as including the usual margin of error.

[0041] When terms such as “on,” “above,” “below,” and “after” are used to describe the positional relationship between two parts, one or more parts may be set between the two parts unless these terms use the terms “immediately” or “directly”.

[0042] When an element or layer is referred to as being “on” another element or layer, the element or layer can be directly on the other element or layer or other elements or layers may be interposed therebetween.

[0043] Although the terms "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from other components. Therefore, within the technical concept of the present disclosure, the first component mentioned below may be the second component.

[0044] Like reference numbers generally refer to like elements throughout the application.

[0045] The size and thickness of each component shown in the drawings are shown for convenience of description, and the present disclosure is not limited to the size and thickness of the components shown in the drawings.

[0046] The features of the various embodiments of the present disclosure may be combined or coupled with each other in part or in whole, and may be interconnected and operated in various technical ways, and the various embodiments may be implemented independently of each other, or in association with each other.

[0047] Hereinafter, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0048] Figure 1 is a block diagram schematically illustrating a display device according to an exemplary embodiment of the present disclosure.

[0049] Reference Figure 1 The display device 10 may include a display panel 100 including a plurality of pixels P, a controller 200, a gate driver 300 for providing a gate signal to each of the plurality of pixels P, a data driver 400 for providing a data signal to each of the plurality of pixels P, and a power supply unit 500. The power supply unit 500 provides power required for driving each of the plurality of pixels P.

[0050] The display panel 100 may include an active area AA (see FIG. Figure 2 ), and non-valid area NA (see Figure 2 In the effective area AA (see Figure 2 ) can be set in the pixel P. Non-effective area NA (see Figure 2 ) can be set around the active area AA to surround the active area AA. In the non-active area NA (see Figure 2 ) can be provided with a gate driver 300 and a data driver 400.

[0051] In the display panel 100, a plurality of gate lines GL and a plurality of data lines DL may be arranged side by side, and a plurality of pixels P may be connected to the gate lines GL and the data lines DL, respectively. The plurality of gate lines GL and the plurality of data lines DL may be arranged to intersect with each other, but exemplary embodiments of the present disclosure are not limited thereto. For example, a pixel P may be supplied with a gate signal from the gate driver 300 via the gate line GL, may be supplied with a data signal from the data driver 400 via the data line DL, and may be supplied with a high potential driving voltage EVDD and a low potential driving voltage EVSS from the power supply unit 500.

[0052] The gate lines GL may provide scan signals SC and emission control signals EM, and the data lines DL may provide data voltages Vdata. Furthermore, according to various exemplary embodiments, the gate lines GL may include a plurality of gate lines SCL providing scan signals SC and emission control signal lines EML providing emission control signals EM. Furthermore, the plurality of pixels P further include power lines VL to which bias voltages Vobs and initialization voltages Var and Vini are provided.

[0053] In addition, each pixel P may include a light emitting diode OLED and a pixel circuit configured to control the operation of the light emitting diode OLED, such as Figure 2 As shown in . The light emitting diode OLED may be composed of an anode electrode ANO, a cathode electrode CAT, and a light emitting layer EL between the anode electrode ANO and the cathode electrode CAT.

[0054] The pixel circuit may include multiple switching elements, driving elements, and capacitors. The switching elements and driving elements may be composed of thin-film transistors. In the pixel circuit, the driving element controls the amount of current supplied to the light-emitting diode (OLED) based on the data voltage to adjust the amount of light emitted by the light-emitting diode (OLED). In addition, the multiple switching elements receive scan signals SC provided via multiple gate lines SCL and emission control signals EM provided via emission control signal lines EML to operate the pixel circuit.

[0055] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be applied to a transparent display device in which an image is displayed on the screen and real objects in the background can be seen. The display panel 100 can be configured as a flexible display panel, but the exemplary embodiments of the present disclosure are not limited thereto. The flexible display panel can be implemented by an OLED panel using a plastic substrate, but the exemplary embodiments of the present disclosure are not limited thereto. For example, the display panel or flexible display panel can be composed of a quantum dot panel, a micro LED panel, or a mini LED panel, but the exemplary embodiments of the present disclosure are not limited thereto.

[0056] Each pixel P may include a red pixel, a green pixel, and a blue pixel to realize each color, but the exemplary embodiments of the present disclosure are not limited thereto. Each pixel P may include a white pixel. Each pixel P may include a pixel circuit.

[0057] A touch unit or touch sensor may be provided on the display panel 100. A touch input may be sensed using a separate touch sensor or may be sensed through the pixels P. The touch sensor may be provided on the screen of the display panel in an on-cell type or an add-on type, or may be implemented as an in-cell type touch sensor to be built into the display panel 100, but exemplary embodiments of the present disclosure are not limited thereto.

[0058] The controller 200 processes the image data RGB input from the outside to a size and resolution suitable for the display panel 100, and provides the processed image data to the data driver 400. The controller 200 can use the synchronization signals input from the outside, such as the dot clock signal CLK, the data enable signal DE, the horizontal synchronization signal Hsync, and the vertical synchronization signal Vsync, to generate the gate control signal GCS and the data control signal DCS. The generated gate control signal GCS and data control signal DCS are provided to the gate driver 300 and the data driver 400, respectively, to control the gate driver 300 and the data driver 400.

[0059] The controller 200 may be configured to be combined with various processors such as a microprocessor, a mobile processor, or an application processor according to a device to be installed, but exemplary embodiments of the present disclosure are not limited thereto.

[0060] The host system may be any one of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, and a vehicle system, but exemplary embodiments of the present disclosure are not limited thereto.

[0061] The controller 200 multiplies the input frame frequency by i and may control the operation timing of the display panel driver at a frame frequency of input frame frequency×i (i is a positive integer greater than 0) Hz. The input frame frequency may be 60 Hz in the National Television Standards Committee (NTSC) standard or 50 Hz in the Phase Alternation Line (PAL) standard, but exemplary embodiments of the present disclosure are not limited thereto.

[0062] The controller 200 can generate signals that drive the pixels P at various refresh rates. For example, the controller 200 can generate drive-related signals to drive the pixels P in a variable refresh rate (VRR) mode or to switch the pixels P between a first refresh rate and a second refresh rate. For example, the controller 200 can drive the pixels P at various refresh rates by simply changing the rate of a clock signal, generating a synchronization signal to generate horizontal blanks or vertical blanks, or driving the gate driver 300 in a masked manner.

[0063] The controller 200 may generate a gate control signal GCS for controlling the operation timing of the gate driver 300 and a data control signal DCS for controlling the operation timing of the data driver 400 based on the timing signals Vsync, Hsync, and DE received from the host system. The controller 200 controls the operation timing of the display panel driver to synchronize the gate driver 300 and the data driver 400.

[0064] The voltage level of the gate control signal GCS output from the controller 200 is converted into gate-on voltages VGL and VEL and gate-off voltages VGH and VEH by a level shifter. The level shifter converts the low-level voltage of the gate control signal GCS into the gate-low voltage VGL and converts the high-level voltage of the gate control signal GCS into the gate-high voltage VGH. The gate control signal GCS may include a start pulse and a shift clock.

[0065] The gate driver 300 may provide the scan signal SC to the gate line GL according to the gate control signal GCS provided from the controller 200. The gate driver 300 may be provided on one or both sides of the display panel 100 in a gate-in-panel (GIP) manner, but exemplary embodiments of the present disclosure are not limited thereto.

[0066] The gate driver 300 may sequentially output gate signals to the plurality of gate lines GL under the control of the controller 200. The gate driver 300 shifts the gate signals using a shift register to sequentially provide the gate signals to the gate lines GL.

[0067] In an organic light-emitting display device, gate signals may include a scan signal SC and an emission control signal EM. The scan signal SC may include a scan pulse that swings between a gate-on voltage VGL and a gate-off voltage VGH. The emission control signal EM may include an emission control signal pulse that swings between a gate-on voltage VEL and a gate-off voltage VEH.

[0068] The scan pulse is synchronized with the data voltage Vdata to select pixels P of a row to which data is written. The light emitting control signal EM may define the light emitting time of the pixels P.

[0069] The gate driver 300 may include a light emitting control signal driver 310 and at least one or more scan drivers 320 .

[0070] The light emitting control signal driver 310 may output a light emitting control signal pulse in response to a start pulse and a shift clock from the controller 200 and sequentially shift the light emitting control signal pulse according to the shift clock.

[0071] At least one or more scan drivers 320 may output a scan pulse in response to a start pulse and a shift clock from the controller 200 and shift the scan pulse according to the shift clock timing.

[0072] The data driver 400 may convert the image data RGB into data voltages Vdata according to the data control signal DCS provided from the controller 200 and provide the converted data voltages Vdata to the pixels P through the data lines DL.

[0073] Despite Figure 1 1 and 2 illustrate that one data driver 400 is disposed on one side of the display panel 100 , but the number of the data drivers 400 and their placement positions are not limited thereto.

[0074] For example, the data driver 400 is composed of a plurality of integrated circuits (ICs) to be divided into a plurality of parts on one side of the display panel 100 , but exemplary embodiments of the present disclosure are not limited thereto.

[0075] The power supply unit 500 can use a DC-DC converter to generate the DC power required to drive the pixel array and display panel driver of the display panel 100. The DC-DC converter may include a charge pump, a regulator, a buck converter, and a boost converter. The power supply unit 500 receives a DC input voltage applied from the host system to generate DC voltages such as gate-on voltages VGL and VEL; gate-off voltages VGH and VEH; a high-potential driving voltage EVDD; and a low-potential driving voltage EVSS. The gate-on voltages VGL and VEL and the gate-off voltages VGH and VEH are provided to the level shifter and the gate driver 300. The high-potential driving voltage EVDD and the low-potential driving voltage EVSS can be provided together to the pixels P.

[0076] Figure 2 is a cross-sectional view illustrating a display device according to an exemplary embodiment.

[0077] Reference Figure 2 , Figure 2The figure shows a cross-sectional view of a device including two switching thin-film transistors TFT1 and TFT2 and a storage capacitor Cst. The two thin-film transistors TFT1 and TFT2 may include: a switching thin-film transistor or a driving transistor made of a polycrystalline semiconductor material; and an oxide thin-film transistor TFT2 made of an oxide semiconductor material. In this case, the thin-film transistor made of a polycrystalline semiconductor material or a low-temperature polycrystalline semiconductor material is referred to as a polycrystalline thin-film transistor TFT1, and the thin-film transistor made of an oxide semiconductor material is referred to as an oxide thin-film transistor TFT2.

[0078] Figure 2 The polycrystalline thin film transistor TFT1 shown in FIG may be a light emitting switching thin film transistor connected to the light emitting diode OLED, and the oxide thin film transistor TFT2 may be any switching thin film transistor connected to the storage capacitor Cst, but exemplary embodiments of the present disclosure are not limited thereto.

[0079] A pixel P may include a light-emitting diode (OLED) and a pixel driving circuit for applying a driving current to the light-emitting diode (OLED). The pixel driving circuit may be provided on the substrate 111, and the light-emitting diode (OLED) may be provided on the pixel driving circuit. An encapsulation layer 120 may be provided on the light-emitting diode (OLED). The encapsulation layer 120 may protect the light-emitting diode (OLED). The light-emitting diode (OLED) is denoted by the reference symbol OLED, but the light-emitting diode (OLED) is not limited thereto. For example, the light-emitting diode (OLED) may include an inorganic light-emitting diode, an organic light-emitting diode, a quantum dot light-emitting diode, a micro LED element, or a mini LED element, but exemplary embodiments of the present disclosure are not limited thereto.

[0080] The pixel driving circuit can be referred to as a pixel (P) array unit including a driving thin film transistor, a switching thin film transistor, and a capacitor. The light emitting diode OLED can be referred to as an array unit including an anode electrode, a cathode electrode, and a light emitting layer disposed between the anode electrode and the cathode electrode to emit light.

[0081] In one exemplary embodiment, the driver thin film transistor and at least one switching thin film transistor may comprise an oxide semiconductor as their active layer. Thin film transistors with oxide semiconductor materials as their active layers have excellent leakage current blocking effects and are less expensive to manufacture than thin film transistors with low-temperature polycrystalline semiconductor materials or polycrystalline semiconductor materials as their active layers. Therefore, to reduce power consumption and manufacturing costs, the pixel driver circuit according to this exemplary embodiment may include a driver thin film transistor and at least one switching thin film transistor comprised of oxide semiconductor materials.

[0082] All thin film transistors constituting the pixel driving circuit may be implemented using oxide semiconductor materials, or only some thin film transistors may be implemented using oxide semiconductor materials. For example, any one of the driving thin film transistor and the switching thin film transistor may be composed of one of an oxide semiconductor material, a low-temperature polycrystalline semiconductor material, and a polycrystalline semiconductor material, or a combination thereof.

[0083] However, thin film transistors using oxide semiconductor materials have difficulty ensuring reliability, while thin film transistors using low-temperature polycrystalline semiconductor materials or polycrystalline semiconductor materials have fast operating speeds and excellent reliability. Therefore, exemplary embodiments may include both switching thin film transistors using oxide semiconductor materials and switching thin film transistors composed of polycrystalline semiconductor materials.

[0084] The substrate 111 may be configured as a multilayer structure in which organic films and inorganic films are alternately stacked, but exemplary embodiments of the present disclosure are not limited thereto. For example, the substrate 111 may be formed by alternately stacking an organic film such as polyimide and an inorganic film such as silicon oxide (SiO 2 ), but exemplary embodiments of the present disclosure are not limited thereto.

[0085] A lower buffer layer 112a may be formed on the substrate 111. The lower buffer layer 112a is provided to block moisture penetrating from the outside and may be formed by stacking a plurality of silicon oxide (SiO2) films. An auxiliary buffer layer 112b may be further provided on the lower buffer layer 112a to protect the device from moisture penetration, but exemplary embodiments of the present disclosure are not limited thereto.

[0086] A polycrystalline thin film transistor TFT1 may be formed on a substrate 111. The polycrystalline thin film transistor TFT1 may include a polycrystalline semiconductor as an active layer. The polycrystalline thin film transistor TFT1 may include a first active layer ACT1 including a channel for electrons or holes to move, a first gate electrode GE1, a first source electrode SD1, and a first drain electrode SD2.

[0087] The first active layer ACT1 may include a first channel region, a first source region disposed on one side of the first channel region, and a first drain region disposed on the other side. The first source region and the first drain region are disposed with the first channel region interposed therebetween.

[0088] The first source region and the first drain region may be regions in which an intrinsic polycrystalline semiconductor material is doped with Group 5 or Group 3 impurity ions, such as phosphorus (P) or boron (B), at a predetermined concentration to become conductive, but exemplary embodiments of the present disclosure are not limited thereto. In the first channel region, the polycrystalline semiconductor material remains in an intrinsic state and can provide a path for electrons or holes to move.

[0089] The polycrystalline thin film transistor TFT1 may include a first gate electrode GE1 overlapping with a first channel region of the first active layer ACT1. A first insulating layer 113 may be provided between the first gate electrode GE1 and the first active layer ACT1. A single layer or multiple layers such as a silicon oxide (SiO2) film or a silicon nitride (SiN) film may be stacked. x ) film to constitute the first insulating layer 113, but exemplary embodiments of the present disclosure are not limited thereto.

[0090] In an exemplary embodiment, the polycrystalline thin-film transistor TFT1 may have a top-gate structure in which the first gate electrode GE1 is located above the first active layer ACT1, but the exemplary embodiments of the present disclosure are not limited thereto. Accordingly, the first electrode CST1 included in the storage capacitor Cst and the light shielding layer LS included in the oxide thin-film transistor TFT2 may be formed of the same material as the first gate electrode GE1, but the exemplary embodiments of the present disclosure are not limited thereto. The first gate electrode GE1, the first electrode CST1, and the light shielding layer LS are formed using a single mask process, thereby reducing the number of mask processes.

[0091] The first gate electrode GE1 may be made of a metal material. For example, the first gate electrode GE1 may be a single layer or multiple layers formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof, but is not limited thereto.

[0092] A second insulating layer 114 may be provided on the first gate electrode GE1. The second insulating layer 114 may be made of silicon oxide (SiO2) or silicon nitride (SiN x ), but the exemplary embodiments of the present disclosure are not limited thereto.

[0093] The display panel 100 may further include an upper buffer layer 115, a third insulating layer 116, and a fourth insulating layer 117 on the second insulating layer 114. The polycrystalline thin film transistor TFT1 is formed on the fourth insulating layer 117 and may include a first source electrode SD1 and a first drain electrode SD2 connected to the first source region and the first drain region, respectively.

[0094] The first source electrode SD1 and the first drain electrode SD2 may be formed of a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof, but are not limited thereto.

[0095] The upper buffer layer 115 separates the second active layer ACT2 of the oxide thin film transistor TFT2 implemented by an oxide semiconductor material from the first active layer ACT1 implemented by a polycrystalline semiconductor material and may provide a base for forming the second active layer ACT2 .

[0096] The third insulating layer 116 may be provided on the second active layer ACT2 of the oxide thin film transistor TFT2. The third insulating layer 116 may cover the second active layer ACT2 of the oxide thin film transistor TFT2. The third insulating layer 116 is formed on the second active layer ACT2 implemented by the oxide semiconductor material, so that the third insulating layer may be implemented by an inorganic film. However, the third insulating layer 116 may cover the second active layer ACT2 of the oxide thin film transistor TFT2. For example, the third insulating layer 116 may be made of silicon oxide (SiO2) or silicon nitride (SiN x ), but the exemplary embodiments of the present disclosure are not limited thereto.

[0097] The second gate electrode GE2 may be made of a metal material. For example, the second gate electrode GE2 may be a single layer or multiple layers formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof, but is not limited thereto.

[0098] The oxide thin film transistor TFT2 may include a second active layer ACT2 formed on the upper buffer layer 115 and made of an oxide semiconductor material, a second gate electrode GE2 disposed on the third insulating layer 116, and second source and drain electrodes SD3 and SD4. The second source and drain electrodes SD3 and SD4 are disposed on the fourth insulating layer 117.

[0099] The second active layer ACT2 may include an intrinsic second channel region implemented by an oxide semiconductor material and not doped with impurities, and a second source region and a second drain region doped with impurities to become conductive.

[0100] The oxide thin film transistor TFT2 may further include a light shielding layer LS located below the upper buffer layer 115 and overlapping the second active layer ACT2. The light shielding layer LS blocks light incident on the second active layer ACT2 to ensure the reliability of the oxide thin film transistor TFT2. The light shielding layer LS may be formed of the same material as the first gate electrode GE1, but exemplary embodiments of the present disclosure are not limited thereto. The light shielding layer LS may be formed on the upper surface of the first insulating layer 113. The light shielding layer LS is electrically connected to the second gate electrode GE2 to form a dual gate, but exemplary embodiments of the present disclosure are not limited thereto.

[0101] The second source electrode SD3 and the second drain electrode SD4 are simultaneously formed of the same material as the first source electrode SD1 and the first drain electrode SD2 on the fourth insulating layer 117 to reduce the number of mask processes.

[0102] The second electrode CST2 is disposed on the second insulating layer 114 and overlaps the first electrode CST1 to implement the storage capacitor Cst. For example, the second electrode CST2 may be a single layer or multiple layers formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof, but exemplary embodiments of the present disclosure are not limited thereto.

[0103] The storage capacitor Cst can store a data voltage applied through the data line DL for a predetermined period of time and then provide the data voltage to the light emitting diode OLED. The storage capacitor Cst may include two corresponding electrodes and a dielectric material disposed between the two electrodes. The second insulating layer 114 may be located between the first electrode CST1 and the second electrode CST2.

[0104] The first electrode CST1 or the second electrode CST2 of the storage capacitor Cst may be electrically connected to the second source electrode SD3 or the second drain electrode SD4 of the oxide thin film transistor TFT2. However, the connection relationship of the storage capacitor Cst may vary depending on the pixel driving circuit.

[0105] A first planarization layer 118 and a second planarization layer 119 may be provided on the pixel driving circuit to planarize the upper end of the pixel driving circuit. The first planarization layer 118 and the second planarization layer 119 may be organic films such as polyimide or acrylic resin, but the exemplary embodiments of the present disclosure are not limited thereto.

[0106] A light emitting diode OLED may be formed on the second planarization layer 119 .

[0107] The light emitting diode OLED may include an anode electrode ANO, a cathode electrode CAT, and a light emitting layer EL disposed between the anode electrode ANO and the cathode electrode CAT. When a pixel driving circuit that commonly uses a low potential voltage connected to the cathode electrode CAT is implemented, the anode electrode ANO may be provided as a separate electrode in each sub-pixel. When a pixel driving circuit that commonly uses a high potential voltage is implemented, the cathode electrode CAT may be provided as a separate electrode in each sub-pixel.

[0108] The light emitting diode OLED can be electrically connected to the driving element through the intermediate electrode CNE provided on the first planarization layer 118. For example, the anode electrode ANO of the light emitting diode OLED and the first source electrode SD1 of the polycrystalline thin film transistor TFT1 constituting the pixel driving circuit can be connected to each other through the intermediate electrode CNE.

[0109] The anode electrode ANO may be connected to the intermediate electrode CNE exposed through a contact hole passing through the second planarization layer 119. Also, the intermediate electrode CNE may be connected to the first source electrode SD1 exposed through a contact hole passing through the first planarization layer 118.

[0110] The intermediate electrode CNE may serve as a medium connecting the first source electrode SD1 and the anode electrode ANO. The intermediate electrode CNE may be formed of a conductive material such as copper (Cu), silver (Ag), molybdenum (Mo), or titanium (Ti), but exemplary embodiments of the present disclosure are not limited thereto.

[0111] The anode electrode ANO may be formed into a multilayer structure comprising a transparent conductive film and an opaque conductive film having high reflective efficiency, but exemplary embodiments of the present disclosure are not limited thereto. The transparent conductive film may be formed of a material having a high work function, such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the opaque conductive film may be formed in a single layer or multilayer structure comprising aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), or alloys thereof. However, exemplary embodiments of the present disclosure are not limited thereto. For example, the anode electrode ANO may be formed in a structure in which a transparent conductive film, an opaque conductive film, and a transparent conductive film are sequentially stacked, or in a structure in which a transparent conductive film and an opaque conductive film are sequentially stacked. However, exemplary embodiments of the present disclosure are not limited thereto.

[0112] The light emitting layer EL may be formed by stacking a hole related layer, an organic light emitting layer, and an electron related layer in this order or in reverse order on the anode electrode ANO, but exemplary embodiments of the present disclosure are not limited thereto.

[0113] The bank layer BNK may be a pixel-defining film that exposes the anode electrode ANO of each pixel P. The bank layer BNK may be formed of an opaque material (e.g., black) to suppress optical interference between adjacent pixels P. In this case, the bank layer BNK may include a light-shielding material formed from at least one of a color pigment, an organic black dye, and carbon. For example, the bank layer BNK may be formed from a material including a black dye or an organic material such as a benzocyclobutene resin, a polyimide resin, an acrylic resin, or a photosensitive polymer, but exemplary embodiments of the present disclosure are not limited thereto. When the bank layer BNK is formed from a material including a black pigment or a black dye, the bank layer may be a black bank portion. When the bank layer BNK is formed from a material including a black pigment or a black dye, external light can be blocked, further improving the brightness of the display device. Spacers may be further disposed on the bank layer BNK. For example, the spacers may include an organic insulating material, but exemplary embodiments of the present disclosure are not limited thereto. The spacers may be formed from the same material as the bank layer BNK, but exemplary embodiments of the present disclosure are not limited thereto.

[0114] The cathode electrode CAT may be formed on the upper and side surfaces of the light-emitting layer EL, thereby opposing the anode electrode ANO across the light-emitting layer EL. The cathode electrode CAT may be integrally formed over the entire active area AA. When the cathode electrode CAT is applied to a top-emission organic light-emitting display device, the cathode electrode may be formed of a transparent conductive film such as indium tin oxide (ITO) or indium zinc oxide (IZO), but exemplary embodiments of the present disclosure are not limited thereto.

[0115] An encapsulation layer 120 may be further formed on the cathode electrode CAT to suppress moisture penetration.

[0116] Encapsulation layer 120 can prevent moisture or oxygen from penetrating into the light-emitting diode (OLED), which is susceptible to moisture or oxygen from the outside. To this end, encapsulation layer 120 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer, but is not limited thereto. In this disclosure, a structure of encapsulation layer 120 in which first, second, and third encapsulation layers 121, 122, and 123 are sequentially stacked will be described as an example, but exemplary embodiments of the present disclosure are not limited thereto.

[0117] The first encapsulation layer 121 may be formed on the substrate 111 on which the cathode electrode CAT is formed. The third encapsulation layer 123 is formed on the substrate 111 on which the second encapsulation layer 122 is formed, and surrounds the top surface, bottom surface, and side surface of the second encapsulation layer 122 together with the first encapsulation layer 121. The first encapsulation layer 121 and the third encapsulation layer 123 may minimize or inhibit the penetration of external moisture or oxygen into the light emitting diode OLED. The first encapsulation layer 121 and the third encapsulation layer 123 may be made of an inorganic insulating material that allows low temperature deposition, such as silicon nitride (SiNx ), silicon oxide (SiO x ), silicon oxynitride (SiON), or aluminum oxide (Al2O3), but exemplary embodiments of the present disclosure are not limited thereto. The first encapsulation layer 121 and the third encapsulation layer 123 are deposited in a low-temperature environment, so that damage to the light-emitting diode OLED, which is susceptible to high-temperature environments, can be suppressed during the deposition process of the first encapsulation layer 121 and the third encapsulation layer 123.

[0118] The second encapsulation layer 122 serves as a buffer to reduce stress between layers caused by the bending of the display device 10 and to flatten steps between the layers. The second encapsulation layer 122 can be formed on the substrate 111 on which the first encapsulation layer 121 is formed, using, but not limited to, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, and polyethylene; or a non-photosensitive organic insulating material such as silicon oxycarbide (SiOC); or a photosensitive organic insulating material such as optical acrylic. When the second encapsulation layer 122 is formed using an inkjet method, a dam (DAM) may be provided to prevent the liquefied second encapsulation layer 122 from spreading to the edge of the substrate 111. The DAM may be provided closer to the edge of the substrate 111 than the second encapsulation layer 122. The DAM prevents the second encapsulation layer 122 from spreading into the pad region, where the conductive pads disposed at the outermost periphery of the substrate 111 are located.

[0119] The dam portion DAM is designed to suppress diffusion of the second encapsulation layer 122. However, if the second encapsulation layer 122 is formed to exceed the height of the dam portion DAM during the process, the second encapsulation layer 122, as an organic layer, may be exposed to the outside, allowing moisture and the like to easily penetrate into the light-emitting diode. Therefore, to suppress this problem, at least one or more dam portions DAM may be formed to overlap, but exemplary embodiments of the present disclosure are not limited thereto.

[0120] The dam portion DAM may be disposed on the fourth insulating layer 117 of the non-active area NA.

[0121] In addition, the dam portion DAM may be formed simultaneously with the first planarization layer 118 and the second planarization layer 119. When the first planarization layer 118 is formed, the lower layer of the dam portion DAM is formed together, and when the second planarization layer 119 is formed, the upper layer of the dam portion DAM is formed together. Therefore, the dam portion DAM may be stacked to have a double-layer structure, but exemplary embodiments of the present disclosure are not limited thereto.

[0122] Therefore, the dam portion DAM may be made of the same material as the first planarization layer 118 and the second planarization layer 119 , but is not limited thereto.

[0123] The dam portion DAM may be formed to overlap with the low potential driving power line VSS. For example, the low potential driving power line VSS may be formed below the region where the dam portion DAM is located in the non-active region NA.

[0124] A low-potential drive power line VSS and a gate driver 300 configured in a gate-in-panel (GIP) configuration are formed around the periphery of the display panel, and the low-potential drive power line VSS may be positioned further outward than the gate driver 300. Furthermore, the low-potential drive power line VSS is connected to the cathode electrode CAT to apply a common voltage. Although the gate driver 300 is shown simplified in the plan view and cross-sectional view, the gate driver 300 may be formed using thin-film transistors having the same structure as the thin-film transistors in the active area AA.

[0125] The low-potential driving power line VSS is disposed outside the gate driver 300. The low-potential driving power line VSS is disposed outside the gate driver 300 and surrounds the active area AA. For example, the low-potential driving power line VSS may be formed of the same material as the first gate electrode GE1, but is not limited thereto, and may be formed of the same material as the second electrode CST2 or the first source electrode SD1 and the first drain electrode SD2, but is not limited thereto.

[0126] In addition, a low potential driving power line VSS may be electrically connected to the cathode electrode CAT. The low potential driving power line VSS may provide a low potential driving voltage EVSS to the plurality of pixels P in the active area AA.

[0127] A touch layer may be provided on the encapsulation layer 120. On the touch layer, a buffer film 151 may be provided between the touch sensor metal including the touch electrode connection lines 152 and 154 and the touch electrodes 155 and 156 and the cathode electrode CAT of the light emitting diode OLED.

[0128] The buffer film 151 can prevent chemical solutions (developers or etchants) used in the process of manufacturing the touch sensor metal disposed on the buffer film 151 or moisture from the outside from penetrating into the light-emitting layer EL including the organic material. In this way, the buffer film 151 can prevent damage to the light-emitting layer EL, which is susceptible to chemical solutions or moisture.

[0129] The buffer film 151 may be formed from an organic insulating material formed at a temperature lower than a predetermined temperature (e.g., 100°C) to prevent damage to the light-emitting layer EL, which includes organic materials susceptible to high temperatures. The buffer film 151 may be formed from an organic insulating material having a low dielectric constant of 1 to 3, but exemplary embodiments of the present disclosure are not limited thereto. For example, the buffer film 151 may be formed from an acrylic, epoxy, or siloxane-based material, but exemplary embodiments of the present disclosure are not limited thereto. Formed from an organic insulating material and having planarizing properties, the buffer film 151 can prevent damage to the encapsulation layer 120 caused by bending of the organic light-emitting display device and fracture of the touch sensor metal formed on the buffer film 151.

[0130] According to the touch sensor structure based on mutual capacitance, the touch electrodes 155 , 156 are disposed on the buffer film 151 , and the touch electrodes 155 , 156 may be alternately disposed, but exemplary embodiments of the present disclosure are not limited thereto.

[0131] The touch electrode connection lines 152 and 154 may electrically connect the touch electrodes 155 and 156. The touch electrode connection lines 152 and 154 and the touch electrodes 155 and 156 may be located on different layers with the insulating film 153 interposed therebetween, but exemplary embodiments of the present disclosure are not limited thereto.

[0132] The touch electrode connection lines 152 and 154 are disposed to overlap with the bank layer BNK to suppress degradation of the aperture ratio.

[0133] In the touch electrodes 155 and 156 , a portion of the touch electrode connection line 152 passes through the upper and side surfaces of the encapsulation layer 120 and the upper and side surfaces of the dam portion DAM to be electrically connected to the touch driving circuit through the touch pad PAD.

[0134] A portion of the touch electrode connection line 152 is provided with a touch driving signal from a touch driving circuit to transmit the touch driving signal to the touch electrodes 155 and 156 and transmit the touch sensing signal in the touch electrodes 155 and 156 to the touch driving circuit.

[0135] A touch protection film 157 may be provided on the touch electrodes 155 and 156. In the drawings, although the touch protection film 157 is shown to be provided only on the touch electrodes 155 and 156, the invention is not limited thereto and the touch protection film 157 may extend before and after the dam portion DAM to be provided on the touch electrode connection line 152.

[0136] A color filter may be further provided on the encapsulation layer 120. The color filter may be located on the touch layer or between the encapsulation layer 120 and the touch layer, but exemplary embodiments of the present disclosure are not limited thereto.

[0137] Figure 3is a diagram illustrating a structure of a gate driver in a display device according to an exemplary embodiment of the present disclosure.

[0138] Reference Figure 3 The gate driver 300 may include a light emission control signal driver 310 and a scan driver 320. The scan driver 320 may include first to fourth scan drivers 321, 322, 323, and 324. The second scan driver 322 may include an odd-numbered second scan driver 322_O and an even-numbered second scan driver 322_E.

[0139] In the gate driver 300, the shift registers may be symmetrically arranged on both sides of the active area AA. Furthermore, the shift registers on one side of the active area AA in the gate driver 300 may include second scan drivers 322_O and 322_E, a fourth scan driver 324, and a light emission control signal driver 310. The shift registers on the other side of the active area AA may include a first scan driver 321, a second scan driver 322_O and 322_E, and a third scan driver 323. However, the present disclosure is not limited thereto, and the light emission control signal driver 310 and the first to fourth scan drivers 321, 322, 323, and 324 may be arranged differently according to exemplary embodiments.

[0140] Each of the stages STG1 to STGn of the shift register may include: a first scan signal generator SC1(1) to SC1(n); a second scan signal generator SC2_O(1) to SC2_O(n), SC2_E(1) to SC2_E(n); a third scan signal generator SC3(1) to SC3(n); a fourth scan signal generator SC4(1) to SC4(n); and a light emitting control signal generator EM(1) to EM(n).

[0141] The first scan signal generators SC1(1) to SC1(n) may output first scan signals SC1(1) to SC1(n) through the first gate line SCL1 of the display panel 100. The second scan signal generators SC2_O(1) to SC2_O(n), SC2_E(1) to SC2_E(n) may output second scan signals SC2(1) to SC2(n) through the second gate line SCL2 of the display panel 100. The third scan signal generators SC3(1) to SC3(n) may output third scan signals SC3(1) to SC3(n) through the third gate line SCL3 of the display panel 100. The fourth scan signal generators SC4(1) to SC4(n) may output fourth scan signals SC4(1) to SC4(n) through the fourth gate line SCL4 of the display panel 100. The emission control signal generators EM(1) to EM(n) may output emission control signals EM(1) to EM(n) through the emission control signal line EML of the display panel 100.

[0142] The first scan signals SC1(1) to SC1(n) may be used as signals for driving the Ath transistor (e.g., compensation transistor) included in the pixel circuit. The second scan signals SC2(1) to SC2(n) may be used as signals for driving the Bth transistor (e.g., data supply transistor) included in the pixel circuit. The third scan signals SC3(1) to SC3(n) may be used as signals for driving the Cth transistor (e.g., bias transistor) included in the pixel circuit. The fourth scan signals SC4(1) to SC4(n) may be used as signals for driving the Dth transistor (e.g., initialization transistor) included in the pixel circuit. The light emission control signals EM(1) to EM(n) may be used as signals for driving the Eth transistor (e.g., light emission control transistor) included in the pixel circuit. For example, when the light emission control transistor of a pixel is controlled using the light emission control signals EM(1) to EM(n), the light emission time of a light emitting diode may be changed.

[0143] Reference Figure 3 A bias voltage bus VobsL, a first initialization voltage bus VarL, and a second initialization voltage bus ViniL may be provided between the gate driver 300 and the active area AA.

[0144] The bias voltage bus VobsL, the first initialization voltage bus VarL, and the second initialization voltage bus ViniL may provide the bias voltage Vobs, the first initialization voltage Var, and the second initialization voltage Vini from the power supply unit 500 to the pixel circuit.

[0145] In the accompanying drawings, the bias voltage bus VobsL, the first initialization voltage bus VarL, and the second initialization voltage bus ViniL are each shown to be disposed on only one side, either the left or right side, of the active area AA. However, the present disclosure is not limited thereto and may be disposed on both sides. Furthermore, although the bias voltage bus VobsL, the first initialization voltage bus VarL, and the second initialization voltage bus ViniL are each disposed on one side, they are not limited to the left or right side.

[0146] Reference Figure 3 One or more optical areas OA1, OA2 may be set in the active area AA.

[0147] The one or more optical areas OA1 , OA2 may be provided to overlap with one or more optical electronic devices (eg, an imaging device such as a camera (image sensor), a detection sensor such as a proximity sensor and an illumination sensor).

[0148] In one or more optical areas OA1 and OA2, a light-transmitting structure having a transmittance above a predetermined level is formed for operation of the optical electronic device. For example, the number of pixels P per unit area in the one or more optical areas OA1 and OA2 may be smaller than the number of pixels P per unit area in the normal area of ​​the active area AA, excluding the optical areas OA1 and OA2. For example, the resolution of the one or more optical areas OA1 and OA2 may be lower than the resolution of the normal area of ​​the active area AA.

[0149] The light-transmitting structure in one or more optical areas OA1 and OA2 can be formed by patterning the cathode electrode in a portion where no pixel P is provided. The cathode electrode to be patterned can be removed using a laser, or the cathode electrode can be selectively formed using a material such as a cathode anti-deposition layer for patterning, but exemplary embodiments of the present disclosure are not limited thereto.

[0150] Furthermore, in one or more optical areas OA1 and OA2, a light-transmitting structure can be formed by separately forming a light-emitting diode (OLED) and a pixel circuit in a pixel P, but exemplary embodiments of the present disclosure are not limited thereto. For example, the light-emitting diode (OLED) of a pixel P can be located in the optical areas OA1 and OA2, and the plurality of transistors (TFTs) constituting the pixel circuit can be arranged around the optical areas OA1 and OA2. Thus, the light-emitting diode (OLED) and the pixel circuit can be electrically connected via a transparent metal layer.

[0151] Figure 4 is a diagram of a pixel circuit in a display device according to an exemplary embodiment of the present disclosure.

[0152] Figure 4For the purpose of description, the pixel circuit is only exemplarily illustrated. There is no particular limitation as long as the structure can control the light emission of the light emitting diode ED by applying the EM signal EM(n). For example, the pixel circuit may include an additional scanning signal and a switching thin film transistor connected thereto, as well as a switching thin film transistor to which an additional initialization voltage is applied. In addition, the connection relationship of the switching element or the connection position of the capacitor can be set in various ways. Hereinafter, for the convenience of description, the pixel circuit with Figure 4 A display device with a pixel circuit structure.

[0153] Reference Figure 4 , each of the plurality of pixels P may include a pixel circuit including a driving transistor DT and a light emitting diode ED connected to the pixel circuit.

[0154] The pixel circuit controls the driving circuit of the light-emitting diode ED to drive the light-emitting diode ED. The pixel circuit may include a driving transistor DT, first to seventh transistors T1 to T7, and a storage capacitor, but exemplary embodiments of the present disclosure are not limited thereto. Each of the transistors DT, T1 to T7 may include a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode may be a source electrode, and the other of the first electrode and the second electrode may be a drain electrode.

[0155] Each of the transistors DT, T1 to T7 may be a P-type thin film transistor or an N-type thin film transistor. Figure 4 In the exemplary embodiment, the first transistor T1, the second transistor T2, and the seventh transistor T7 are N-type thin film transistors, and the remaining transistors DT, T3 to T6 are P-type thin film transistors. However, this is not limiting. According to the exemplary embodiment, all or some of the transistors DT, T1 to T7 may be P-type thin film transistors or N-type thin film transistors. Furthermore, the N-type thin film transistor may be an oxide thin film transistor, and the P-type thin film transistor may be a polysilicon thin film transistor. For example, one of the transistors DT, T1 to T7 may be composed of one of a P-type thin film transistor and an N-type thin film transistor, or a combination thereof.

[0156] Hereinafter, the first transistor T1, the second transistor T2, and the seventh transistor T7 are described as N-type thin film transistors, and the remaining transistors DT, T3 to T6 are P-type thin film transistors, but the exemplary embodiments of the present disclosure are not limited thereto. Therefore, the first transistor T1, the second transistor T2, and the seventh transistor T7 are turned on by applying a high voltage, while the remaining transistors DT, T3 to T6 are turned on by applying a low voltage.

[0157] According to an exemplary embodiment, the first transistor T1 constituting the pixel circuit may function as a compensation transistor, the second transistor T2 may function as a data supply transistor, the third transistor T3 and the fourth transistor T4 may function as emission control transistors, and the fifth transistor T5 may function as a bias transistor. Furthermore, the sixth transistor T6 and the seventh transistor T7 may function as initialization transistors. However, exemplary embodiments of the present disclosure are not limited thereto.

[0158] The light emitting diode ED may include an anode electrode and a cathode electrode. The anode electrode of the light emitting diode ED may be connected to the fifth node N5 and the cathode electrode may be connected to the low potential driving voltage EVSS.

[0159] The driving transistor DT may include a first electrode connected to the second node N2, a second electrode connected to the third node N3, and a gate electrode connected to the first node N1. The driving transistor DT may provide a driving current to the light-emitting diode ED based on the voltage of the first node N1 (or a data voltage stored in the storage capacitor Cst described below). For example, the driving transistor DT may be connected between the second node N2 and the third node N3.

[0160] The first transistor T1 may include a first electrode connected to the first node N1, a second electrode connected to the third node N3, and a gate electrode that receives a first scan signal SC1(n). The first transistor T1 is turned on in response to the first scan signal SC1(n) and is diode-connected between the first node N1 and the third node N3 to sample the threshold voltage (Vth) of the drive transistor DT. The first transistor T1 may be a compensation transistor, but exemplary embodiments of the present disclosure are not limited thereto. For example, the first transistor T1 may be connected between the first node N1 and the third node N3.

[0161] The storage capacitor Cst may be connected or formed between the first node N1 and the fourth node N4. The storage capacitor Cst may store or maintain the supplied high-potential driving voltage EVDD.

[0162] The second transistor T2 may include a first electrode connected to the data line DL (or receiving the data voltage Vdata), a second electrode connected to the second node N2, and a gate electrode receiving the second scan signal SC2(n). The second transistor T2 may be turned on in response to the second scan signal SC2(n) and may transmit the data voltage Vdata to the second node N2. This second transistor T2 may be a data supply transistor, but exemplary embodiments of the present disclosure are not limited thereto. For example, the second transistor T2 may be connected between the data line and the second node N2.

[0163] The third transistor T3 and the fourth transistor T4 (or the first and second light emission control transistors) may be connected between the high potential driving voltage EVDD and the light emitting diode ED and form a current moving path through which the driving current generated by the driving transistor DT moves.

[0164] The third transistor T3 may include a first electrode connected to the fourth node N4 to receive the high potential driving voltage EVDD, a second electrode connected to the second node N2, and a gate electrode receiving the light emitting control signal EM(n). For example, the third transistor T3 may be connected between the fourth node N4 and the second node N2.

[0165] The fourth transistor T4 may include a first electrode connected to the third node N3, a second electrode connected to the fifth node N5 (or the anode electrode of the light emitting diode ED), and a gate electrode receiving the light emitting control signal EM(n). For example, the fourth transistor T4 may be connected between the third node N3 and the fifth node N5.

[0166] The third transistor T3 and the fourth transistor T4 are turned on in response to the light emitting control signal EM(n) and in this case, a driving current is supplied to the light emitting diode ED and the light emitting diode ED may emit light having brightness corresponding to the driving current.

[0167] The fifth transistor T5 may include a first electrode receiving a bias voltage Vobs, a second electrode connected to the second node N2, and a gate electrode receiving the third scan signal SC3(n). The fifth transistor T5 may be a bias transistor, but exemplary embodiments of the present disclosure are not limited thereto. For example, the fifth transistor T5 may be connected between a bias voltage line and the second node N2.

[0168] The sixth transistor T6 may include a first electrode receiving the first initialization voltage Var, a second electrode connected to the fifth node N5, and a gate electrode receiving the third scan signal SC3(n). For example, the sixth transistor T6 may be connected between the initialization voltage line and the fifth node N5.

[0169] Before the light-emitting diode ED emits light (or after the light-emitting diode ED emits light), the sixth transistor T6 is turned on in response to the third scan signal SC3(n) and can initialize the anode electrode (or pixel electrode) of the light-emitting diode ED using the first initialization voltage Var. The light-emitting diode ED may have a parasitic capacitor formed between the anode electrode and the cathode electrode. As the light-emitting diode ED emits light, the parasitic capacitor is charged, causing the anode electrode of the light-emitting diode ED to have a specific voltage. Therefore, the first initialization voltage Var is applied to the anode electrode of the light-emitting diode ED via the sixth transistor T6 to initialize the large amount of charge accumulated in the light-emitting diode ED.

[0170] In the present disclosure, the gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6 are configured to receive the third scan signal SC3(n) in common. However, the present disclosure is not necessarily limited thereto, and the gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6 may be configured to receive separate scan signals and be independently controlled.

[0171] The seventh transistor T7 may include a first electrode receiving the second initialization voltage Vini, a second electrode connected to the first node N1, and a gate electrode receiving the fourth scan signal SC4(n). For example, the seventh transistor T7 may be connected between the initialization voltage line and the first node N1.

[0172] The seventh transistor T7 is turned on in response to the fourth scan signal SC4(n) and can initialize the gate electrode of the driving transistor DT using the second initialization voltage Vini. Unnecessary charge may remain in the gate electrode of the driving transistor DT due to the high potential driving voltage EVDD stored in the storage capacitor Cst. Therefore, the second initialization voltage Vini is applied to the gate electrode of the driving transistor DT via the seventh transistor T7 to initialize the large amount of remaining charge.

[0173] Figure 5A and Figure 5B It means Figure 4 FIG2 is a diagram showing the operation of the scanning signal and the light emission control signal in the refresh period and the hold period in the pixel circuit shown.

[0174] The display device according to an exemplary embodiment of the present disclosure may operate in a variable refresh rate (VRR) mode display device, but the exemplary embodiment of the present disclosure is not limited thereto. In VRR mode, pixels are driven at a constant frequency, and when high-speed driving is necessary, the refresh rate at which the data voltage Vdata is updated is increased to operate the pixels, or when power consumption needs to be reduced or low-speed driving is necessary, the refresh rate is reduced to operate the pixels.

[0175] Each of the plurality of pixels P can be driven within one second using a combination of a refresh frame and a hold frame. In the present disclosure, one set may be defined as a period in which a refresh period in which the data voltage Vdata is updated and a hold period in which the data voltage Vdata is not updated repeat for one second. A set period may be a period in which the combination of a refresh period and a hold period repeats.

[0176] When the refresh rate is 120 Hz, the display can only be driven during the refresh period. For example, the refresh period can be driven 120 times in one second. One refresh period can be 1 / 120 = 8.33 ms (milliseconds), and one group period can also be 8.33 ms.

[0177] When the refresh rate is driven at 60 Hz, the refresh period and the hold period can be driven alternately. For example, the refresh period and the hold period can each be driven alternately 60 times in one second. One refresh period and one hold period can each be 0.5 / 60 = 8.33 ms, and one group period can be 16.66 ms.

[0178] When the refresh rate is driven at 1 Hz, one frame can be driven with one refresh period and 119 hold periods after the refresh period. In addition, when the refresh rate is driven at 1 Hz, one frame can be driven with multiple refresh periods and multiple hold periods. One refresh period and one hold period can each be 1 / 120 = 8.33 ms, and one group period can be 1 s (second).

[0179] In the refresh period, a new data voltage Vdata is loaded, thereby applying the new data voltage Vdata to the driving transistor DT. In the hold period, the data voltage Vdata of the previous frame is retained and used as it is. In the hold period, the process of applying the new data voltage Vdata to the driving transistor DT is omitted, so the hold period can also be called a skip period.

[0180] Each of the plurality of pixels P may initialize a voltage that is charged or remains in the pixel circuit during the refresh period. For example, each of the plurality of pixels P may remove the effects of the data voltage Vdata and the high-potential driving voltage EVDD stored in the previous frame during the refresh period. Therefore, each of the plurality of pixels P may display an image corresponding to the new data voltage Vdata during the hold period.

[0181] Each of the plurality of pixels P supplies a driving current corresponding to the data voltage Vdata to the light emitting diode ED during the maintenance period to display an image and may maintain a turned-on state of the light emitting diode ED.

[0182] First, we will describe Figure 5A The refresh period may include at least one bias period Tobs1, Tobs2; an initialization period Ti; a sampling period Ts; and a light emitting period Te. However, this is merely an exemplary embodiment and is not necessarily limited to this order.

[0183] Reference Figure 5A , the pixel circuit may operate during a refresh period including at least one bias period Tobs1 , Tobs2 .

[0184] At least one bias period Tobs1, Tobs2 is a period in which an on-bias stress operation (OBS) is performed to apply a bias voltage Vobs, the emission control signal EM(n) is a high voltage, and the third transistor T3 and the fourth transistor T4 can be turned off. The first scan signal SC1(n) and the fourth scan signal SC4(n) are low voltages, and the first transistor T1 and the seventh transistor T7 can be turned off. The second scan signal SC2(n) is a low voltage, and the second transistor T2 can be turned off.

[0185] The third scan signal SC3 (n) is input as a low voltage, and the fifth and sixth transistors T5 and T6 may be turned on. As the fifth transistor T5 is turned on, the bias voltage Vobs may be applied to the first electrode of the driving transistor DT connected to the second node N2.

[0186] Here, the bias voltage Vobs is supplied to the third node N3 (i.e., the drain electrode of the driving transistor DT), so that the charging time or charging delay of the voltage of the fifth node N5 (i.e., the anode electrode of the light emitting diode ED) during the light emission period can be reduced. The driving transistor DT maintains a stronger saturation state.

[0187] For example, the higher the bias voltage Vobs is, the higher the voltage of the third node N3 (ie, the drain electrode of the driving transistor DT) is, and the lower the gate-source voltage or drain-source voltage of the driving transistor DT is. Therefore, the bias voltage Vobs may be at least higher than the data voltage Vdata.

[0188] At this time, the drain-source current through the drive transistor DT can be reduced, and the stress of the drive transistor DT is reduced under positive bias stress, thereby resolving the charging delay of the voltage of the third node N3. For example, before sampling the threshold voltage (Vth) of the drive transistor DT, an on-bias stress operation (OBS) can be performed to alleviate the hysteresis of the drive transistor DT.

[0189] Therefore, in at least one bias period Tobs1 , Tobs2 , the on-bias stress operation (OBS) may be referred to as an operation of directly applying an appropriate bias voltage to the driving transistor DT during a non-light emitting period.

[0190] In addition, in at least one bias period Tobs1 , Tobs2 , the sixth transistor T6 is turned on, so that the anode electrode (or pixel electrode) of the light emitting diode ED connected to the fifth node N5 can be initialized to the first initialization voltage Var.

[0191] The gate electrodes of the fifth transistor T5 and the sixth transistor T6 can be configured to receive separate scan signals and be controlled separately. For example, it is not necessary to apply bias voltages to the first electrode of the driving transistor DT and the anode electrode of the light emitting diode ED simultaneously during the bias period.

[0192] Reference Figure 5A , the pixel circuit may operate during the refresh period including the initialization period Ti. The initialization period Ti may be a period in which the voltage of the gate electrode of the driving transistor DT is initialized.

[0193] The first scan signal SC1(n), the third scan signal SC3(n), the fourth scan signal SC4(n), and the light-emitting control signal EM(n) are high voltages, the second scan signal SC2(n) is low voltage, and the first transistor T1 and the seventh transistor T7 may be turned on. The second to sixth transistors T2, T3, T4, T5, and T6 may be turned off. As the first transistor T1 and the seventh transistor T7 are turned on, the gate electrode and the second electrode of the driving transistor DT connected to the first node N1 may be initialized to the second initialization voltage Vini.

[0194] Reference Figure 5A , the pixel circuit may operate during the refresh period including the sampling period Ts. The sampling period may be a period for sampling the threshold voltage (Vth) of the driving transistor DT.

[0195] The first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the emission control signal EM(n) are high voltages, and the fourth scan signal SC4(n) may be input as a low voltage. Consequently, the third to seventh transistors T3, T4, T5, T6, and T7 may be turned off, the first transistor T1 may remain on, and the second transistor T2 may be turned on. For example, the second transistor T2 may be turned on to apply the data voltage Vdata to the drive transistor DT, and the first transistor T1 may be diode-connected between the first node N1 and the third node N3 to sample the threshold voltage (Vth) of the drive transistor DT.

[0196] Reference Figure 5A The pixel circuit may operate during the refresh period including the light emitting period Te. The light emitting period Te may be a period in which the sampled threshold voltage (Vth) is eliminated and a driving current corresponding to the sampled data voltage causes the light emitting diode ED to emit light.

[0197] The light emitting control signal EM(n) is a low voltage, and the third transistor T3 and the fourth transistor T4 perform a turn-on operation.

[0198] As the third transistor T3 is turned on, the high potential driving voltage EVDD connected to the fourth node N4 can be applied to the first electrode of the driving transistor DT connected to the second node N2 through the third transistor T3. The driving current supplied from the driving transistor DT to the light emitting diode ED via the fourth transistor T4 becomes independent of the threshold voltage (Vth) of the driving transistor DT, thereby compensating for the threshold voltage (Vth) of the driving transistor DT.

[0199] Next, we will refer to Figure 5B Driving of the pixel circuit and the light emitting diode during the holding period is described.

[0200] The hold period may include: at least one bias period Tobs3, Tobs4; and a light-emission period Te'. The description of the pixel circuit's operations that are identical to those during the refresh period will be omitted. For example, the at least one bias period Tobs3, Tobs4 and the light-emission period Te' are substantially identical to the at least one bias period Tobs1, Tobs2 and the light-emission period Te, and thus their description will be omitted.

[0201] As described above, in the refresh period, a new data voltage Vdata is loaded, thereby applying the new data voltage Vdata to the gate electrode of the driving transistor DT. In the hold period, the data voltage Vdata of the refresh period is retained and used as it is. Therefore, unlike the refresh period, the hold period does not require the initialization period Ti and the sampling period Ts.

[0202] In the operation of the hold period, a single on-bias stress operation (OBS) is sufficient. However, in the exemplary embodiment, for the convenience of driving the circuit, the third scan signal SC3(n) of the hold period is driven in the same manner as the third scan signal SC3(n) of the refresh period, so that the on-bias stress operation (OBS) can be performed twice as in the refresh period, but the exemplary embodiments of the present disclosure are not limited thereto.

[0203] Reference Figure 5A The driving signal in the refresh period described above is Figure 5B The difference between the drive signals in the hold period in FIG. 1 is the second scan signal SC2(n) and the fourth scan signal SC4(n). In the hold period, the initialization period Ti and the sampling period Ts are unnecessary. Thus, unlike the refresh period, the second scan signal SC2(n) can be always at a low voltage, and the fourth scan signal SC4(n) can be always at a low voltage. For example, the second transistor T2 and the seventh transistor T7 can be operated to be always off.

[0204] Figure 6 is a circuit diagram of a stage of a gate driver of a display device according to an exemplary embodiment of the present disclosure.

[0205] For example, in Figure 6 , a circuit of a fourth scan driver 324 included in each of the plurality of stages of the gate driver is illustrated. The other light emission control signal drivers 310 and scan drivers 321, 322, and 323 included in each of the plurality of stages are also substantially the same as the fourth scan driver 324.

[0206] Each of the plurality of fourth scan drivers of the gate driver of the display device according to an exemplary embodiment of the present disclosure may include first to ninth transistors Ta to Ti, a first capacitor CQN, and a second capacitor CQ.

[0207] In the first transistor Ta, a first electrode may be connected to a gate low voltage (VGL) supply line, a gate electrode may be connected to a Q node Q, and a second electrode may be connected to a scan signal output terminal. Therefore, the first transistor Ta is turned on and off according to the voltage of the Q node Q to output the gate low voltage VGL as the scan signal SRO(n). For example, the first transistor Ta may be connected between the gate low voltage (VGL) supply line and the scan signal output terminal.

[0208] In the second transistor Tb, a first electrode may be connected to a second clock signal (GCLK2) supply line, a gate electrode may be connected to a QN node QN, and a second electrode may be connected to a scan signal output terminal. The second transistor Tb is turned on and off according to the voltage of the QN node QN to output the second clock signal GCLK2 as the scan signal SRO(n). For example, the second transistor Tb may be connected between the second clock signal (GCLK2) supply line and the scan signal output terminal.

[0209] In the third transistor Tc, a first electrode may be connected to an input terminal of a start signal (GVST) or an output terminal of a front-end stage scan signal SRO(n-1), a gate electrode may be connected to a first clock signal (GCLK1) supply line, and a second electrode may be connected to the Q2 node Q2. Therefore, the third transistor Tc is turned on / off according to the first clock signal GCLK1 to apply the start signal GVST or the front-end stage scan signal SRO(n-1) to the Q2 node Q2. For example, the third transistor Tc may be connected between the input terminal of the start signal GVST or the output terminal of the front-end stage scan signal SRO(n-1) and the Q2 node Q2. In the fourth transistor Td, a first electrode may be connected to a gate high voltage (VGH) supply line, a gate electrode may be connected to the Q2 node Q2, and a second electrode may be connected to the Qb node Qb. Therefore, the fourth transistor Td is turned on / off according to the voltage of the Q2 node Q2 to apply the gate high voltage VGH to the Qb node Qb. For example, the fourth transistor Td may be connected between the gate high voltage (VGH) supply line and the Qb node Qb.

[0210] In the fifth transistor Te, a first electrode may be connected to a gate low voltage (VGL) supply line, a gate electrode may be connected to the Q node Q, and a second electrode may be connected to the Qb node Qb. Therefore, the fifth transistor Te is turned on / off according to the voltage of the Q node Q to supply the gate low voltage VGL to the Qb node Qb. For example, the fifth transistor Te may be connected between the gate low voltage (VGL) supply line and the Qb node Qb.

[0211] In the sixth transistor Tf, a first electrode may be connected to the Q2 node Q2, a gate electrode may be connected to a gate low voltage (VGL) supply line, and a second electrode may be connected to the Q node Q. Therefore, the sixth transistor Tf is turned on / off according to the gate low voltage VGL to connect the Q2 node Q2 and the Q node Q. For example, the sixth transistor Tf may be connected between the Q2 node Q2 and the Q node Q. In the seventh transistor Tg, a first electrode may be connected to the Qb node Qb, a gate electrode may be connected to the gate low voltage (VGL) supply line, and a second electrode may be connected to the QN node QN. Therefore, the seventh transistor Tg is turned on / off according to the gate low voltage VGL to connect the Qb node Qb and the QN node QN. For example, the seventh transistor Tg may be connected between the Qb node Qb and the QN node QN.

[0212] In the eighth transistor Th, a first electrode may be connected to a gate low voltage (VGL) supply line, a gate electrode may be connected to the Q node Q, and a second electrode may be connected to the virtual signal output terminal DO. Therefore, the eighth transistor Th is turned on / off according to the voltage of the Q node Q to output the gate low voltage VGL to the virtual signal output terminal DO. For example, the eighth transistor Th may be connected between the gate low voltage (VGL) supply line and the virtual signal output terminal DO.

[0213] In the ninth transistor Ti, a first electrode may be connected to a gate high voltage (VGH) supply line, a gate electrode may be connected to the Qb node Qb, and a second electrode may be connected to the virtual signal output terminal DO. The ninth transistor Ti is turned on / off according to the voltage of the Qb node Qb to output the gate high voltage VGH to the virtual signal output terminal DO. For example, the ninth transistor Ti may be connected between the gate high voltage (VGH) supply line and the virtual signal output terminal DO.

[0214] The fifth transistor Te may be an N-type thin film transistor, and the other transistors Ta, Tb, Tc, Td, Tf, Tg, Th, and Ti may be P-type thin film transistors.

[0215] In addition, the N-type thin film transistor may be an oxide thin film transistor, and the P-type thin film transistor may be a polysilicon thin film transistor.

[0216] Therefore, a high voltage is applied to the fifth transistor Te to perform a turn-on operation, and low voltages are applied to the other transistors Ta, Tb, Tc, Td, Tf, Tg, Th, and Ti to perform a turn-on operation.

[0217] The first capacitor CQN is connected between the gate electrode and the second electrode of the second transistor Tb to bootstrap the QN node QN.

[0218] The second capacitor CQ is connected between the gate electrode and the second electrode of the eighth transistor Th to bootstrap the Q node Q.

[0219] The first transistor Ta, the second transistor Tb, and the first capacitor CQN connected to the scan signal output terminal of each of the plurality of fourth scan drivers 324 are directly related to the output of the scan signal SRO(n). Therefore, the first transistor Ta, the second transistor Tb, and the first capacitor CQN may be referred to as a scan signal output unit.

[0220] The eighth transistor Th, the ninth transistor Ti, and the second capacitor CQ connected to the virtual signal output terminal DO of each of the plurality of fourth scan drivers 324 are directly related to the output of the virtual signal, so that the eighth transistor Th, the ninth transistor Ti, and the second capacitor CQ can be referred to as a virtual signal output unit.

[0221] The third to seventh transistors Tc to Tg are components related to control of the Q node, the QN node, the Q2 node, and the Qb node, and thus the third to seventh transistors Tc to Tg may be referred to as node controllers.

[0222] In the following we will refer to Figures 7 to 8D The operation of each of the plurality of fourth scan drivers 324 configured as described above is described.

[0223] Figure 7 1 is a waveform illustrating signals input to and output from a plurality of stages of a gate driver of a display device according to an exemplary embodiment of the present disclosure.

[0224] Figure 8A is a circuit diagram illustrating operations of a plurality of stages of a gate driver of a display device according to an exemplary embodiment of the present disclosure in a first period.

[0225] Figure 8B is a circuit diagram illustrating operations of a plurality of stages of a gate driver of a display device according to an exemplary embodiment of the present disclosure in a second period.

[0226] Figure 8Cis a circuit diagram illustrating operations of a plurality of stages of a gate driver of a display device according to an exemplary embodiment of the present disclosure in a third period.

[0227] Figure 8D is a circuit diagram illustrating operations of a plurality of stages of a gate driver of a display device according to an exemplary embodiment of the present disclosure in a fourth period.

[0228] exist Figures 8A to 8D In the figure, the transistors indicated by the solid line may be fully on, and the transistors indicated by the dotted line may be partially on. When a transistor is partially on, even if an on-voltage is applied to the gate electrode to turn on the transistor, the gate-source voltage (Vgs) becomes lower than the threshold voltage due to changes in the source electrode voltage, causing the transistor to be turned off.

[0229] like Figure 7 and Figure 8A As shown in FIG, in the first period p1, the first clock signal GCLK1 is input at a low level, so that the third transistor Tc can be turned on. Therefore, the high level of the start signal GVST or the front-end stage scan signal SRO(n-1) can be input to the Q2 node Q2.

[0230] The gate low voltage VGL is applied to the gate electrode of the sixth transistor Tf to fully turn on the sixth transistor Tf, so that the high level of the start signal GVST or the front-end stage scan signal SRO(n-1) can also be input to the Q node Q.

[0231] Therefore, the high level of the start signal GVST or the front-end stage scan signal SRO(n-1) is also input to the Q node Q to turn on the fifth transistor Te so that the gate low voltage VGL can be applied to the Qb node Qb.

[0232] The gate low voltage VGL is applied to the Qb node Qb to fully turn on the ninth transistor Ti so that the gate high voltage VGH can be applied to the virtual signal output terminal DO.

[0233] The gate low voltage VGL is applied to the gate electrode of the seventh transistor Tg to temporarily turn on the seventh transistor Tg, but when the gate-source voltage (Vgs) of the seventh transistor Tg becomes a threshold voltage, the seventh transistor Tg may be turned off.

[0234] Therefore, a voltage corresponding to the sum of the gate low voltage VGL and the threshold voltage of the seventh transistor Tg may be charged in the QN node QN.

[0235] Therefore, a voltage corresponding to the sum of the gate low voltage VGL and the threshold voltage of the seventh transistor Tg may be applied to the gate electrode of the second transistor Tb, and a low level of the second clock signal GCLK2 may be applied to the second electrode of the second transistor Tb. Therefore, the second transistor Tb may not be fully turned on.

[0236] For example, the second transistor Tb is not turned on until the gate-source voltage (Vgs) of the second transistor Tb reaches the threshold voltage. Therefore, the second transistor Tb cannot output the low level of the second clock signal GCLK2 as the scan signal SRO(n), but may output a higher level than the low level of the second clock signal GCLK2 as the scan signal SRO(n).

[0237] For example, as the scan signal SRO(n), a voltage corresponding to the sum of the threshold voltage of the seventh transistor Tg and the threshold voltage of the second transistor Tb may be charged in the low level of the second clock signal GCLK2.

[0238] like Figure 7 and Figure 8B As shown in FIG, in a second period p2 after the first period p1, the second clock signal GCLK2 may rise from a low level to a high level.

[0239] Therefore, a voltage corresponding to the sum of the gate low voltage VGL and the threshold voltage of the seventh transistor Tg is applied to the gate electrode of the second transistor Tb, and a high level of the second clock signal GCLK2 is applied to the second electrode of the second transistor Tb. Therefore, the second transistor Tb can be fully turned on.

[0240] Therefore, the second transistor Tb outputs the high level of the second clock signal GCLK2 as the scan signal SRO(n).

[0241] In the second period p2, the first clock signal GCLK1 may rise from a low level to a high level, and thus the third transistor Tc may be turned off.

[0242] like Figure 7 and Figure 8C As shown in FIG, in a third period p3 after the second period p2, the second clock signal GCLK2 may drop from a high level to a low level.

[0243] For example, in the third period p3, when a voltage lower than the sum of the gate low voltage VGL and the threshold voltage is applied to the QN node QN, the seventh transistor Tg is turned off, thereby floating the QN node QN. The floating QN node QN is bootstrapped by the first capacitor CQN to maintain a voltage lower than the gate low voltage VGL.

[0244] Therefore, the second transistor Tb is fully turned on to output the low level of the second clock signal GCLK2 as the scan signal SRO(n).

[0245] like Figure 7 and Figure 8D As shown in FIG, in the fourth period p4 after the third period p3, the first clock signal GCLK1 is input at a low level, so that the third transistor Tc is turned on. Therefore, the low level of the start signal GVST or the front-end stage scan signal SRO(n-1) can be input to the Q2 node Q2.

[0246] The gate low voltage VGL is applied to the gate electrode of the sixth transistor Tf so that the sixth transistor Tf may not be fully turned on. Therefore, the gate low voltage VGL is applied to the gate electrode of the sixth transistor Tf to temporarily turn on the sixth transistor Tf, but when the gate-source voltage (Vgs) of the sixth transistor Tf becomes a threshold voltage, the sixth transistor Tf may be turned off.

[0247] When a voltage lower than the sum of the gate low voltage VGL and the threshold voltage is applied to the Q node Q, the sixth transistor Tf is turned off, thereby floating the Q node Q. The floating Q node Q is bootstrapped by the second capacitor CQ to maintain a voltage lower than the gate low voltage VGL.

[0248] Therefore, the eighth transistor Th is fully turned on to output the gate low voltage VGL to the dummy signal output terminal DO.

[0249] In addition, the first transistor Ta is also fully turned on to output the gate low voltage VGL as the scan signal SRO(n).

[0250] The low level of the start signal GVST or the front-end stage scan signal SRO(n-1) is input to the Q2 node Q2 to turn on the fourth transistor Td so that the gate high voltage VGH can be applied to the Qb node Qb.

[0251] The gate high voltage VGH is applied to the Qb node Qb so that the ninth transistor Ti can be completely turned off.

[0252] The gate low voltage VGL is applied to the gate electrode of the seventh transistor Tg to fully turn on the seventh transistor Tg, thereby also applying the gate high voltage VGH to the QN node QN. Therefore, the second transistor Tb may be turned off.

[0253] In the display device according to the exemplary embodiment of the present disclosure, the scan signal output unit may be configured using the first transistor Ta and the second transistor Tb which are P-type transistors.

[0254] The P-type transistor has high mobility, so that the rising time and falling time of the scan signal SRO(n) can be minimized in the second period p2 and the third period p3. Thus, the response speed of the display device according to the exemplary embodiment of the present disclosure can be improved.

[0255] According to the present disclosure, the P-type transistor can use a smaller channel area, so that the area of ​​the gate driver can be minimized. Therefore, in the display device according to the exemplary embodiment of the present disclosure, the area occupied by the gate driver is minimized, thereby reducing the frame size of the display device.

[0256] In another exemplary embodiment of the present disclosure, adding a tenth transistor is described.

[0257] The aforementioned exemplary embodiment of the present disclosure and another exemplary embodiment are different from each other only in the configuration of the tenth transistor and an operation using the same, and thus repeated description of the repeated configuration of the first to ninth transistors will be omitted.

[0258] Figure 9 is a circuit diagram of a gate driver stage of a display device according to another exemplary embodiment of the present disclosure.

[0259] Each of the plurality of fourth scan drivers of the gate driver of the display device according to another exemplary embodiment of the present disclosure may include first to tenth transistors Ta to Tj, a first capacitor CQN, and a second capacitor CQ.

[0260] Repetitive description of the configurations of the first to ninth transistors Ta to Ti and the first and second capacitors CQN and CQ, which are the same as those of the above-described exemplary embodiment of the present disclosure, will be omitted.

[0261] In the tenth transistor Tj, a first electrode may be connected to a second clock signal (GCLK2) supply line, a gate electrode may be connected to a Q node Q, and a second electrode may be connected to a scan signal output terminal. The tenth transistor Tj is turned on / off according to the voltage of the Q node Q to output the second clock signal GCLK2 as a scan signal SRO(n). For example, the tenth transistor Tj may be connected between the second clock signal (GCLK2) supply line and the scan signal output terminal.

[0262] The tenth transistor Tj may be an N-type thin film transistor, which may be an oxide thin film transistor. Therefore, a high voltage is applied to the tenth transistor Tj to perform a turn-on operation.

[0263] The first transistor Ta, the second transistor Tb, the tenth transistor Tj, and the first capacitor CQN connected to the scan signal output terminal are directly related to the output of the scan signal SRO(n). Therefore, the first transistor Ta, the second transistor Tb, the tenth transistor Tj, and the first capacitor CQN can be referred to as a scan signal output unit.

[0264] In the following we will refer to Figures 10 to 11D The operation of each of the plurality of fourth scan drivers configured as described above is described.

[0265] Figure 10 1 is a waveform illustrating signals input to and output from a plurality of stages of a gate driver of a display device according to another exemplary embodiment of the present disclosure.

[0266] Figure 11A is a circuit diagram illustrating operations of a plurality of stages of a gate driver of a display device according to another exemplary embodiment of the present disclosure in a first period.

[0267] Figure 11B is a circuit diagram illustrating operations of a plurality of stages of a gate driver of a display device according to another exemplary embodiment of the present disclosure in a second period.

[0268] Figure 11C is a circuit diagram illustrating operations of a plurality of stages of a gate driver of a display device according to another exemplary embodiment of the present disclosure in a third period.

[0269] Figure 11D is a circuit diagram illustrating operations of a plurality of stages of a gate driver of a display device according to another exemplary embodiment of the present disclosure in a fourth period.

[0270] exist 11A to 11D In the figure, the transistors indicated by the solid line may be fully on, and the transistors indicated by the dotted line may be partially on. When a transistor is partially on, even if an on-voltage is applied to the gate electrode to turn on the transistor, the gate-source voltage (Vgs) becomes lower than the threshold voltage due to changes in the source electrode voltage, causing the transistor to be turned off.

[0271] like Figure 10 and Figure 11A As shown in FIG, in the first period p1, the first clock signal GCLK1 is inputted at a low level, so that the third transistor Tc can be turned on. Therefore, the high level of the start signal GVST or the front-end stage scan signal SRO(n-1) can be inputted to the Q2 node Q2.

[0272] The gate low voltage VGL is applied to the gate electrode of the sixth transistor Tf to fully turn on the sixth transistor Tf, so that the high level of the start signal GVST or the front-end stage scan signal SRO(n-1) can also be input to the Q node Q.

[0273] Therefore, the high level of the start signal GVST or the front-end stage scan signal SRO(n-1) is also input to the Q node Q to turn on the fifth transistor Te so that the gate low voltage VGL can be applied to the Qb node Qb.

[0274] The gate low voltage VGL is applied to the Qb node Qb to fully turn on the ninth transistor Ti so that the gate high voltage VGH can be applied to the virtual signal output terminal DO.

[0275] The gate low voltage VGL is applied to the gate electrode of the seventh transistor Tg to temporarily turn on the seventh transistor Tg, but when the gate-source voltage (Vgs) of the seventh transistor Tg becomes a threshold voltage, the seventh transistor Tg may be turned off.

[0276] Therefore, a voltage corresponding to the sum of the gate low voltage VGL and the threshold voltage of the seventh transistor Tg may be charged in the QN node QN.

[0277] Therefore, a voltage corresponding to the sum of the gate low voltage VGL and the threshold voltage of the seventh transistor Tg is applied to the gate electrode of the second transistor Tb, and a low level of the second clock signal GCLK2 is applied to the second electrode of the second transistor Tb. Therefore, the second transistor Tb may not be fully turned on.

[0278] The high level of the start signal GVST or the front-end scan signal SRO(n-1) is input to the Q node Q, so that the tenth transistor Tj is fully turned on. Therefore, the tenth transistor Tj can output the low level of the second clock signal GCLK2 as the scan signal SRO(n).

[0279] like Figure 10 and Figure 11B As shown in FIG, in a second period p2 after the first period p1, the second clock signal GCLK2 may rise from a low level to a high level.

[0280] Therefore, a voltage corresponding to the sum of the gate low voltage VGL and the threshold voltage of the seventh transistor Tg is applied to the gate electrode of the second transistor Tb, and a high level of the second clock signal GCLK2 is applied to the second electrode of the second transistor Tb. Therefore, the second transistor Tb can be fully turned on.

[0281] Therefore, the second transistor Tb outputs the high level of the second clock signal GCLK2 as the scan signal SRO(n).

[0282] In the second period p2, the first clock signal GCLK1 may rise from a low level to a high level, and thus the third transistor Tc may be turned off.

[0283] like Figure 10 and Figure 11C As shown in FIG, in a third period p3 after the second period p2, the second clock signal GCLK2 may drop from a high level to a low level.

[0284] For example, in the third period p3, when a voltage lower than the sum of the gate low voltage VGL and the threshold voltage is applied to the QN node QN, the seventh transistor Tg is turned off, thereby floating the QN node QN. The floating QN node QN is bootstrapped by the first capacitor CQN to maintain a voltage lower than the gate low voltage VGL.

[0285] Therefore, the second transistor Tb is fully turned on to output the low level of the second clock signal GCLK2 as the scan signal SRO(n).

[0286] like Figure 10 and Figure 11D As shown in FIG, in the fourth period p4 after the third period p3, the first clock signal GCLK1 is input at a low level, so that the third transistor Tc can be turned on. Therefore, the low level of the start signal GVST or the front-end stage scan signal SRO(n-1) can be input to the Q2 node Q2.

[0287] The gate low voltage VGL is applied to the gate electrode of the sixth transistor Tf so that the sixth transistor Tf may not be fully turned on. Therefore, the gate low voltage VGL is applied to the gate electrode of the sixth transistor Tf to temporarily turn on the sixth transistor Tf, but when the gate-source voltage (Vgs) of the sixth transistor Tf becomes a threshold voltage, the sixth transistor Tf may be turned off.

[0288] When a voltage lower than the sum of the gate low voltage VGL and the threshold voltage is applied to the Q node Q, the sixth transistor Tf is turned off, thereby floating the Q node Q. The floating Q node Q is bootstrapped by the second capacitor CQ to maintain a voltage lower than the gate low voltage VGL.

[0289] Therefore, the eighth transistor Th is fully turned on to output the gate low voltage VGL to the dummy signal output terminal DO.

[0290] In addition, the first transistor Ta is also fully turned on to output the gate low voltage VGL as the scan signal SRO(n).

[0291] Therefore, the tenth transistor Tj may be turned off.

[0292] The low level of the start signal GVST or the front-end stage scan signal SRO(n-1) is input to the Q2 node Q2 to turn on the fourth transistor Td so that the gate high voltage VGH can be applied to the Qb node Qb.

[0293] The gate high voltage VGH is applied to the Qb node Qb so that the ninth transistor Ti can be completely turned off.

[0294] The gate low voltage VGL is applied to the gate electrode of the seventh transistor Tg to fully turn on the seventh transistor Tg, thereby also applying the gate high voltage VGH to the QN node QN. Therefore, the second transistor Tb may be turned off.

[0295] In another exemplary embodiment according to the present disclosure, the P-type second transistor Tb and the N-type tenth transistor Tj may constitute a transmission gate connected in parallel between the scan signal output terminal and the second clock signal common line.

[0296] In the first period p1 of the display device according to another exemplary embodiment of the present disclosure, the second transistor Tb is not completely turned on, but the tenth transistor Tj may be completely turned on.

[0297] For example, the transmission gate composed of the second transistor Tb and the tenth transistor Tj is completely turned on in the first period p1 to output a complete low level of the scan signal SRO(n).

[0298] Therefore, in another exemplary embodiment according to the present disclosure, a complete low level is output in all periods except the second period p2 , thereby suppressing positive bias temperature stress of the gate driver, so that driving reliability can be improved.

[0299] A display device according to another exemplary embodiment of the present disclosure may solve a problem in which a complete low level of the scan signal SRO(n) cannot be output in the first period p1 , causing a screen defect in a predetermined period.

[0300] According to the present disclosure, a tenth transistor configured to output a completely low level of the scan signal SRO(n) in the first period p1 is added to output a completely low level of the scan signal SRO(n) in the first period p1.

[0301] In the following, reference will be made to Figure 12 Still another exemplary embodiment of the present disclosure is described.

[0302] Yet another exemplary embodiment of the present disclosure is different from another exemplary embodiment only in the configuration of the third capacitor, and thus repeated descriptions of the configurations and operating methods of the first to tenth transistors will be omitted.

[0303] Figure 12 is a circuit diagram of a gate driver stage of a display device according to still another exemplary embodiment of the present disclosure.

[0304] Each of the plurality of fourth scan drivers of the gate driver of the display device according to still another exemplary embodiment of the present disclosure may include first to tenth transistors Ta to Tj, a first capacitor CQN, a second capacitor CQ, and a third capacitor CQB.

[0305] Repetitive description of the configurations of the first to tenth transistors Ta to Tj and the first and second capacitors CQN and CQ, which are substantially the same as those of another exemplary embodiment of the present disclosure, will be omitted.

[0306] The third capacitor CQB may be connected between the Qb node Qb and the gate high voltage (VGH) supply line. Therefore, the third capacitor CQB is connected between the node as a constant power source and the gate high voltage (VGH) supply line to minimize noise of the Qb node Qb.

[0307] Therefore, the voltage fluctuation of the Qb node Qb of the gate driver according to still another exemplary embodiment of the present disclosure is minimized, thereby improving the driving stability of the gate driver.

[0308] Exemplary embodiments of the present disclosure may also be described as follows:

[0309] According to one aspect of the present disclosure, a gate driver includes: multiple stages, each of the multiple stages includes: a node controller, the node controller is configured to control the voltages of the Q node, the Q2 node, the Qb node and the QN node connected to the transistor based on a first clock signal and a second clock signal; a virtual signal output unit, the virtual signal output unit is configured to output a virtual signal based on the voltages of the Q node and the Qb node; and a scan signal output unit, the scan signal output unit is configured to output a scan signal to a scan line based on the voltages of the Q node and the QN node, and in the structure of the scan signal output unit, the transistor configured to output a gate low voltage as the scan signal according to the voltage of the Q node can be a P-type transistor.

[0310] The scan signal output unit may include: a first transistor connected between a gate low voltage supply line and a scan signal output terminal; a second transistor connected between a second clock signal supply line and the scan signal output terminal; and a first capacitor connected between a gate electrode and a second electrode of the second transistor.

[0311] The first transistor may be configured to output the gate low voltage as the scan signal according to a voltage of the Q node, and the second transistor may be configured to output the second clock signal as the scan signal according to a voltage of the QN node.

[0312] Each of the first transistor and the second transistor may be a P-type transistor.

[0313] The P-type transistor may be a polysilicon transistor.

[0314] The node controller may include: a third transistor connected between the start signal input terminal or the scan signal output terminal of the front-end stage and the Q2 node; a fourth transistor connected between the gate high voltage supply line and the Qb node; a fifth transistor connected between the gate low voltage supply line and the Qb node; a sixth transistor connected between the Q2 node and the Q node; and a seventh transistor connected between the Qb node and the QN node.

[0315] The fifth transistor may be an N-type oxide transistor, and each of the third transistor, the fourth transistor, the sixth transistor, and the seventh transistor may be a P-type polysilicon transistor.

[0316] The node controller may be connected between the Qb node and the gate high voltage supply line.

[0317] The virtual signal output unit may include: an eighth transistor connected between a gate low voltage supply line and a virtual signal output terminal; a ninth transistor connected between a gate high voltage supply line and the virtual signal output terminal; and a second capacitor connected between a gate electrode and a second electrode of the eighth transistor.

[0318] Each of the eighth transistor and the ninth transistor may be a P-type polysilicon transistor.

[0319] The dummy signal output unit may further include a third capacitor connected between the Qb node and the gate high voltage supply line.

[0320] The scan signal output unit may further include a tenth transistor connected between the second clock signal supply line and the scan signal output terminal.

[0321] The tenth transistor may be an N-type oxide transistor.

[0322] According to one aspect of the present disclosure, a display device includes: a display panel including an effective area provided with a plurality of pixels; and a gate driver including a plurality of stages, each of the plurality of stages including: a node controller, the node controller being configured to control the voltages of a Q node, a Q2 node, a Qb node, and a QN node connected to a transistor based on a first clock signal and a second clock signal; a virtual signal output unit, the virtual signal output unit being configured to output a virtual signal based on the voltages of the Q node and the Qb node; and a scan signal output unit, the scan signal output unit being configured to output a scan signal to a scan line based on the voltages of the Q node and the QN node, and in the structure of the scan signal output unit, the transistor configured to output a gate low voltage as the scan signal according to the voltage of the Q node may be a P-type transistor.

[0323] The scan signal output unit may include: a first transistor connected between a gate low voltage supply line and a scan signal output terminal; a second transistor connected between a second clock signal supply line and the scan signal output terminal; and a first capacitor connected between a gate electrode and a second electrode of the second transistor.

[0324] The first transistor may be configured to output the gate low voltage as the scan signal according to a voltage of the Q node, and the second transistor may be configured to output the second clock signal as the scan signal according to a voltage of the QN node.

[0325] Each of the first transistor and the second transistor may be a P-type transistor.

[0326] The P-type transistor may be a polysilicon transistor.

[0327] The node controller may include: a third transistor connected between the start signal input terminal or the scan signal output terminal of the front-end stage and the Q2 node; a fourth transistor connected between the gate high voltage supply line and the Qb node; a fifth transistor connected between the gate low voltage supply line and the Qb node; a sixth transistor connected between the Q2 node and the Q node; and a seventh transistor connected between the Qb node and the QN node.

[0328] The fifth transistor may be an N-type oxide transistor, and each of the third transistor, the fourth transistor, the sixth transistor, and the seventh transistor may be a P-type polysilicon transistor.

[0329] The node controller may be connected between the Qb node and the gate high voltage supply line.

[0330] The virtual signal output unit may include: an eighth transistor connected between a gate low voltage supply line and a virtual signal output terminal; a ninth transistor connected between a gate high voltage supply line and the virtual signal output terminal; and a second capacitor connected between a gate electrode and a second electrode of the eighth transistor.

[0331] Each of the eighth transistor and the ninth transistor may be a P-type polysilicon transistor.

[0332] The dummy signal output unit may further include a third capacitor connected between the Qb node and the gate high voltage supply line.

[0333] Each of the plurality of pixels may include one or a combination of a P-type transistor and an N-type transistor.

[0334] The scan signal output unit may further include a tenth transistor connected between the second clock signal supply line and the scan signal output terminal.

[0335] The tenth transistor may be an N-type oxide transistor.

[0336] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto. Without departing from the technical concept of the present disclosure, the present disclosure can be implemented in many different forms. Therefore, the exemplary embodiments of the present disclosure are provided only for the purpose of illustration and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are merely illustrative in all aspects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be interpreted as falling within the scope of the present disclosure.

Claims

1. A gate driver comprising: Multiple levels, wherein each of the plurality of stages comprises: a node controller configured to control voltages of a Q node, a Q2 node, a Qb node, and a QN node connected to the transistor based on a first clock signal and a second clock signal; a dummy signal output unit configured to output a dummy signal based on voltages of the Q node and the Qb node; and a scan signal output unit configured to output a scan signal to a scan line based on the voltages of the Q node and the QN node, and In the structure of the scan signal output unit, the transistor configured to output a gate low voltage as the scan signal according to the voltage of the Q node is a P-type transistor.

2. The gate driver according to claim 1, The scanning signal output unit includes: a first transistor connected between the gate low voltage supply line and the scan signal output terminal; a second transistor connected between a second clock signal supply line and the scan signal output terminal; and A first capacitor is connected between the gate electrode and the second electrode of the second transistor.

3. The gate driver according to claim 2 , wherein the first transistor is configured to output the gate low voltage as the scan signal according to the voltage of the Q node, and the second transistor is configured to output the second clock signal as the scan signal according to the voltage of the QN node.

4. The gate driver according to claim 2, Each of the first transistor and the second transistor is a P-type transistor. The gate driver according to claim 4 , wherein the P-type transistor is a polysilicon transistor.

6. The gate driver according to claim 1, The node controller includes: a third transistor connected between the start signal input terminal or the scan signal output terminal of the front-end stage and the Q2 node; a fourth transistor connected between a gate high voltage supply line and the Qb node; a fifth transistor connected between a gate low voltage supply line and the Qb node; a sixth transistor connected between the Q2 node and the Q node; and A seventh transistor is connected between the Qb node and the QN node.

7. The gate driver according to claim 6, The fifth transistor is an N-type oxide transistor, and each of the third transistor, the fourth transistor, the sixth transistor, and the seventh transistor is a P-type polysilicon transistor.

8. The gate driver according to claim 1, Wherein the virtual signal output unit comprises: an eighth transistor connected between the gate low voltage supply line and the dummy signal output terminal; a ninth transistor connected between the gate high voltage supply line and the dummy signal output terminal; and A second capacitor is connected between the gate electrode and the second electrode of the eighth transistor.

9. The gate driver according to claim 8, Each of the eighth transistor and the ninth transistor is a P-type polysilicon transistor.

10. The gate driver according to claim 8, further comprising: A third capacitor is connected between the Qb node and the gate high voltage supply line.

11. The gate driver according to claim 2, The scanning signal output unit further includes: A tenth transistor is connected between the second clock signal supply line and the scan signal output terminal.

12. The gate driver according to claim 11, The tenth transistor is an N-type oxide transistor.

13. A display device comprising: A display panel including an active area having a plurality of pixels; and A gate driver according to any one of claims 1 to 12.

14. The display device according to claim 13, Each of the plurality of pixels includes one of a P-type transistor and an N-type transistor, or a combination thereof.

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