Display device including multiplexed signal blocking portion and method of manufacturing same

Abstract

A display device including a multiplexed signal blocking portion and a method of manufacturing the same are disclosed. The display device includes: a timing control circuit for generating image data, a data control signal, and a gate control signal; a data driving circuit for generating a data signal using the image data and the data control signal; the gate driving circuit is used for generating a gate signal by utilizing the gate control signal; and a display panel, the display panel is configured to display an image using the data signal and the gate signal and includes a plurality of multiplexing test lines, a plurality of multiplexing enable transistors respectively connected to the plurality of multiplexing test lines, and a plurality of multiplexing pads respectively connected to the plurality of multiplexing enable transistors.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0028277, filed on February 27, 2024, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present invention relates to a display device, and more particularly, to a display device including a multiplexer signal blocking portion and a method for manufacturing the same, wherein deterioration such as line defects caused by coupling of a multiplexer line and a film line is prevented by blocking application of a multiplexer signal to the multiplexer line using the multiplexer signal blocking portion located between the multiplexer line and a multiplexer pad. Background Art

[0004] With the recent advent of an information-oriented society, there has been a growing interest in information displays for processing and displaying large amounts of information, as well as a growing demand for portable information media. As a result, the display industry has experienced rapid development. Consequently, various lightweight and thin flat-panel display devices have been developed and are gaining popularity.

[0005] Among various flat panel display devices, organic light emitting diode (OLED) display devices are light emitting devices that do not include a backlight unit used in non-light emitting devices such as liquid crystal display (LCD) devices. As a result, OLED display devices have advantages in viewing angle, contrast, and power consumption, making them suitable for various fields.

[0006] In a display device, to reduce the number of output terminals of a data driving unit and the number of data connection lines of a display panel, the data driving unit may sequentially output red, green, and blue data signals to one data connection line via one output terminal, and multiple data lines of the display panel may be connected to the one data connection line via multiple multiplexing transistors (mux transistors). As a result, the red, green, and blue data signals may be sequentially provided to the multiple data lines.

[0007] Multiplexing transistors switch according to the multiplexing signal. Because the multiplexing lines used to transmit the multiplexing signal overlap with the film lines of the flexible printed circuit, coupling occurs between the multiplexing lines and the film lines. This coupling between the multiplexing lines and the film lines distorts the data signal, resulting in line defects such as dark lines. Summary of the Invention

[0008] Accordingly, the present invention is directed to a display device that substantially obviates one or more problems due to limitations and disadvantages of the related art.

[0009] More specifically, the present invention is directed to a display device including a multiplexed signal blocking portion, wherein degradation such as line defects due to coupling of a multiplexed line and a film line is prevented by providing a multiplexed signal blocking portion that selectively blocks the multiplexed signal between a multiplexed line transmitting the multiplexed signal during an illumination test and a multiplexed pad receiving the multiplexed signal from a data driving unit.

[0010] In addition, the present invention is directed to a display device, in which coupling between a multiplexing line and a film line is prevented, power consumption is reduced, and relatively low power consumption is obtained by providing a multiplexing signal blocking portion that selectively blocks the multiplexing signal between the multiplexing line and the multiplexing pad, by transmitting the multiplexing signal through the multiplexing signal blocking portion during an illumination test, and blocking the multiplexing signal after attaching a data driving unit.

[0011] Additional features and advantages of the invention will be set forth in the following description, and in part will be apparent from the following description, or may be learned by practice of the invention. These and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims and the accompanying drawings.

[0012] To achieve these and other advantages, according to the purposes of the present invention, as embodied and broadly described herein, a display device includes: a timing control circuit for generating image data, a data control signal and a gate control signal; a data driving circuit for generating a data signal using the image data and the data control signal; a gate driving circuit for generating a gate signal using the gate control signal; and a display panel, the display panel being used to display an image using the data signal and the gate signal and including a plurality of multiplexing test lines, a plurality of multiplexing enable transistors respectively connected to the plurality of multiplexing test lines, and a plurality of multiplexing pads respectively connected to the plurality of multiplexing enable transistors.

[0013] In another aspect of the present invention, a method for manufacturing a display device includes: forming a plurality of multiplexing test lines, a plurality of multiplexing enable transistors respectively connected to the plurality of multiplexing test lines, and a plurality of multiplexing pads respectively connected to the plurality of multiplexing enable transistors on a display panel; connecting the plurality of multiplexing test pads of the test substrate to the plurality of multiplexing test lines of the display panel by setting a test substrate adjacent to the display panel; performing an illumination test of the display panel by turning on the plurality of multiplexing enable transistors and applying a plurality of multiplexing signals from the test substrate to the plurality of multiplexing pads; connecting a plurality of multiplexing film lines of the flexible printed circuit to the plurality of multiplexing pads by attaching a flexible printed circuit to the display panel; and driving the display panel by turning off the plurality of multiplexing enable transistors and applying a plurality of multiplexing signals from the flexible printed circuit to the plurality of multiplexing pads.

[0014] It is to be understood that both the foregoing general description and the following detailed description are explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and together with the description serve to explain the principle of the invention.

[0016] In the attached figure:

[0017] Figure 1 is a view showing a display device according to an embodiment of the present invention, which may be an organic light emitting diode (OLED) display device;

[0018] Figure 2 is a cross-sectional view showing a display panel of a display device according to an embodiment of the present invention;

[0019] Figure 3 is a block diagram illustrating first and second gate driving units and a display panel of a display device according to an embodiment of the present invention;

[0020] Figure 4 is a circuit diagram showing a sub-pixel of a display device according to an embodiment of the present invention;

[0021] Figure 5 is a circuit diagram showing a sub-pixel of a display device according to an embodiment of the present invention;

[0022] Figure 6 is a view showing a data driving unit and a display panel of a display device according to an embodiment of the present invention;

[0023] Figure 7 is a view showing a lighting test step of a display device according to an embodiment of the present invention;

[0024] Figure 8 is a view showing an attaching step of a data driving unit of a display device according to an embodiment of the present invention;

[0025] Figure 9 It is along Figure 8 A sectional view taken along line IX-IX. DETAILED DESCRIPTION

[0026] The advantages and features of the present invention, as well as methods for implementing the same, will be apparent from the exemplary aspects described below with reference to the accompanying drawings. However, the present invention may be implemented in various forms and should not be construed as limited to the exemplary aspects set forth herein. Rather, these exemplary aspects are provided so that the disclosure of the present invention will be thorough and complete enough to assist those skilled in the art in fully understanding the scope of the present invention. Furthermore, the present invention is limited only by the scope of the claims.

[0027] The shapes, sizes, proportions, angles, quantities, etc. shown in the drawings for the purpose of describing the exemplary aspects of the present invention are given by way of example only. Therefore, the present invention is not limited to what is shown in the drawings. Similar reference numerals refer to similar elements throughout the specification unless otherwise defined.

[0028] In the following description, if a detailed description of a related known function or configuration may unnecessarily obscure features or aspects of the present invention, a detailed description about such known function or configuration may be omitted or may be provided as a brief description.

[0029] When the terms "comprising," "having," "including," etc. are used, one or more other elements may be added unless a term such as "only" is used. Elements described in the singular are intended to include plural elements and vice versa unless the context clearly indicates otherwise.

[0030] When interpreting an element, even if there is no explicit description about an error or tolerance range, the element is interpreted as including such error or tolerance range.

[0031] When describing a positional relationship, for example, when using terms such as "on," "above," "below," "upper," "lower," "beside," or "adjacent" to describe the positional relationship between two parts, one or more other parts may be disposed between the two parts, unless more restrictive terms such as "immediately," "directly," or "closely" are used. For example, when one element or layer is disposed "on" another element or layer, a third layer or element may be interposed therebetween.

[0032] Although the terms first, second, A, B, (a), (b), etc. may be used herein to refer to various elements, these elements should not be construed as being limited by these terms because they are not intended to define a particular order or priority. These terms are merely used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present invention.

[0033] The term "at least one of" should be understood to include all combinations of one or more related elements. For example, the term "at least one of the first, second, and third elements" can include all combinations of two or more of the first, second, and third elements as well as the first element, the second element, or the third element.

[0034] The term "display device" may include display devices in a narrow sense, such as a liquid crystal module (LCM), an organic light emitting diode (OLED) module, and a quantum dot (QD) module including a display panel and a driving unit for driving the display panel. In addition, the term "display device" may include finished products (or final products) including LCM, OLED modules, and QD modules, such as notebook computers, televisions, computer monitors, display devices of equipment (equipment) including automobile display devices or in forms other than vehicles, and set electronic devices (set electronic apparatus) or set devices (or set devices) such as mobile electronic devices such as smart phones or electronic tablets.

[0035] Therefore, the display device of the present invention may include not only display devices such as LCM, OLED module and QD module in a narrow sense, but also unit devices or application products of end-user devices including LCM, OLED module and QD module.

[0036] Depending on the situation, an LCM, OLED module, or QD module having a display panel and a drive unit may be referred to as a "display device," and an electronic device including the finished product of the LCM, OLED module, or QD module may be referred to as a "unit device." For example, a display device in a narrow sense may include a display panel of liquid crystal, organic light-emitting diodes, or quantum dots, and a source printed circuit board (PCB) for a control unit driving the display panel. The unit device may further include a unit PCB electrically connected to the source PCB for controlling a unit control unit that controls the entire unit device.

[0037] The display panel of the present invention may include all types of display panels, such as liquid crystal display panels, organic light-emitting diode display panels, quantum dot display panels, and electroluminescent display panels. The display panel of the present invention is not limited to a specific display panel having a flexible substrate for an organic light-emitting diode display panel and a curved frame of a lower backplane support portion. The shape or size of the display panel used in the display device of the present invention is not limited thereto.

[0038] For example, when the display panel is an organic light emitting diode display panel, the display panel may include a plurality of gate lines, a plurality of data lines, and sub-pixels in the intersection of the plurality of gate lines and the plurality of data lines. The display panel may include: an array having a thin film transistor as an element for selectively applying a voltage to each sub-pixel; a light emitting element layer on the array; and an encapsulation substrate or an encapsulation portion covering the light emitting element layer. The encapsulation portion may protect the thin film transistor and the light emitting element layer from external impacts and may prevent or at least reduce the penetration of moisture or oxygen into the light emitting element layer. In addition, the light emitting element layer on the array may include an inorganic light emitting layer, for example, a nano-sized material layer or quantum dots.

[0039] The thin film transistor of the present invention may include one of an oxide thin film transistor, an amorphous silicon thin film transistor and a low temperature polysilicon thin film transistor.

[0040] The features of various aspects of the present invention may be combined or incorporated with one another, in part or in whole. These features may be technically connected and operated in a variety of ways, as will be readily understood by those skilled in the art. These aspects may be implemented independently of one another or in conjunction with one another in various combinations.

[0041] Hereinafter, a display device according to exemplary aspects of the present invention will be described in detail with reference to the accompanying drawings, wherein the influence on the oxide semiconductor layer of the thin film transistor of the driving element part is reduced by shielding light emitted and transmitted from the sub-pixels and / or light input from the outside.

[0042] Figure 1 1 is a diagram illustrating a display device according to an embodiment of the present invention. The display device may be an organic light emitting diode (OLED) display device.

[0043] exist Figure 1 In the embodiment of the present invention, the display device 110 includes a timing control unit (or circuit) 120, a data driving unit (or circuit) 125, a first gate driving unit (or circuit) 130 and a second gate driving unit (or circuit) 135, and a display panel 140.

[0044] The timing control unit 120 generates image data, data control signals, and gate control signals using an image signal transmitted from an external system such as a graphics card or a television system and a plurality of timing signals including a data enable signal, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. The image data and the data control signal are transmitted to the data driving unit 125, and the gate control signal is transmitted to the first gate driving unit 130 and the second gate driving unit 135.

[0045] The data driving unit 125 generates a data signal (data voltage) Vdata (see FIG. 1 ) using the data control signal and the image data transmitted from the timing control unit 120. Figure 4 and 5 ), and transmits the data signal to the data line DL of the display panel 140.

[0046] The first gate driving unit 130 and the second gate driving unit 135 generate gate signals (gate voltages) Sc (see Figure 4 ), Sc1, Sc2, Em1 and Em2 (see Figure 5 ), and applies gate signals Sc, Sc1, Sc2, Em1, and Em2 to the gate lines GL of the display panel 140.

[0047] The first and second gate driving units 130 and 135 may have a gate in panel (GIP) type formed in a non-display area NDA of a substrate of a display panel 140 having the gate lines GL, the data lines DL, and the pixels P.

[0048] Although the first gate driving unit 130 and the second gate driving unit 135 Figure 1 In one embodiment, the gate driving units are disposed in both sides of the display panel 140 , but in another embodiment, one gate driving unit may be disposed in one side of the display panel 140 .

[0049] The display panel 140 may include a display area DA at its center and a non-display area NDA surrounding the display area DA. The display panel 140 displays an image using gate signals Sc, Sc1, Sc2, Em1, and Em2 and a data signal Vdata. To display an image, the display panel 140 includes a plurality of pixels P in the display area DA, a plurality of gate lines GL, and a plurality of data lines DL.

[0050] Each of the plurality of pixels P includes first to fourth subpixels SP1 to SP4. Gate lines GL and data lines DL intersect each other to define the first to fourth subpixels SP1 to SP4. Each of the first to fourth subpixels SP1 to SP4 is connected to the gate lines GL and the data lines DL. For example, the first to fourth subpixels SP1 to SP4 may correspond to red, green, blue, and white, respectively.

[0051] When the display device 110 is an OLED display device, each of the first to fourth sub-pixels SP1 to SP4 may include a switching transistor Ts (see FIG. Figure 4 ), driving transistor Td (see Figure 4 ) and a plurality of transistors such as a sensing transistor; a storage capacitor Cs (see Figure 4 ); and light emitting diode De (see Figure 4 )

[0052] The structures of the display panel 140 and the sub-pixels SP of the display device 110 will be illustrated with reference to the drawings.

[0053] Figure 2 is a cross-sectional view showing a display panel of a display device according to an embodiment of the present invention; Figure 3 is a block diagram illustrating first and second gate driving units and a display panel of a display device according to an embodiment of the present invention; Figure 4 is a circuit diagram showing a sub-pixel of a display device according to an embodiment of the present invention; Figure 5 is a circuit diagram illustrating a sub-pixel of a display device according to an embodiment of the present invention.

[0054] exist Figure 2 In the embodiment of the present invention, the display panel 140 of the display device 110 includes a first thin film transistor TFT1, a second thin film transistor TFT2, and a storage capacitor CST. The first thin film transistor TFT1 and the second thin film transistor TFT2 may include a polycrystalline semiconductor material or an oxide semiconductor material. For example, the first thin film transistor TFT1 may include a polycrystalline semiconductor material, and the second thin film transistor TFT2 may include an oxide semiconductor material.

[0055] The first thin film transistor TFT1 is connected to the light emitting diode OLED, and the second thin film transistor TFT2 is connected to the storage capacitor CST.

[0056] Each sub-pixel SP includes a light emitting diode (OLED) and a pixel circuit for providing a driving current to the light emitting diode (OLED). The pixel circuit is disposed on a substrate 211, and the light emitting diode (OLED) is disposed in the pixel circuit. An encapsulation layer 220 is disposed on the light emitting diode (OLED) to protect the light emitting diode (OLED).

[0057] The pixel circuit may include a driving thin film transistor, a switching thin film transistor, and a storage capacitor. The light emitting diode OLED may include an anode, a cathode, and a light emitting layer located between the anode and the cathode.

[0058] The driver thin film transistor and at least one switching thin film transistor use an oxide semiconductor material as their active layer. Thin film transistors using an oxide semiconductor material as their active layer have an excellent blocking effect on leakage current and have lower manufacturing costs than thin film transistors using a polycrystalline semiconductor material as their active layer. Consequently, to reduce power consumption and manufacturing costs, a pixel circuit may include a driver thin film transistor and at least one switching thin film transistor using an oxide semiconductor material.

[0059] For example, all thin film transistors of a pixel circuit may be formed of an oxide semiconductor material, or a portion of a switching thin film transistor may be formed of an oxide semiconductor material.

[0060] Thin film transistors using oxide semiconductor materials have relatively low reliability, while thin film transistors using polycrystalline semiconductor materials have relatively fast operating speeds and relatively high reliability. As a result, the pixel circuit in the embodiment may include both switching thin film transistors using oxide semiconductor materials and switching thin film transistors using polycrystalline semiconductor materials.

[0061] The substrate 211 may include a plurality of layers of organic layers and inorganic layers alternately laminated. For example, the substrate 211 may include organic layers of an organic insulating material such as polyimide and inorganic layers of an inorganic insulating material such as silicon oxide (SiO2) alternately laminated.

[0062] The lower buffer layer 212a is disposed on the substrate 211. The lower buffer layer 212a can block moisture permeable from the outside and may have multiple layers including silicon oxide (SiO2). An auxiliary buffer layer 212b for protecting the element from moisture is disposed on the lower buffer layer 212a.

[0063] The first thin film transistor TFT1 is disposed on the substrate 211. The first thin film transistor TFT1 may use a polycrystalline semiconductor material as an active layer. The first thin film transistor TFT1 includes a first active layer ACT1 having a channel in which electrons or holes move, a first gate GE1, a first source SE1, and a first drain DE1.

[0064] The first active layer ACT1 includes a first channel region, a first source region at one side of the first channel region, and a first drain region at the other side of the first channel region.

[0065] The first source region and the first drain region include an intrinsic polycrystalline semiconductor material doped with impurities of Group III or V, such as boron (B) or phosphorus (P). The first channel region includes an intrinsic polycrystalline semiconductor material to provide a path in which electrons or holes move.

[0066] The first thin film transistor TFT1 includes a first gate electrode GE1 overlapping a first channel region of the first active layer ACT1. A first gate insulating layer 213 is provided between the first gate electrode GE1 and the first active layer ACT1. The first gate insulating layer 213 may include a single layer or multiple layers of an inorganic insulating material such as silicon oxide (SiO2) and silicon nitride (SiNx).

[0067] The first thin-film transistor TFT1 has a top-gate structure, in which the first gate electrode GE1 is disposed on the first active layer ACT1. As a result, the first capacitor electrode CST1 of the storage capacitor CST and the light shielding layer LS of the second thin-film transistor TFT2 can be made of the same material as the first gate electrode GE1. By forming the first gate electrode GE1, the first capacitor electrode CST1, and the light shielding layer LS through a single mask process, the manufacturing process can be simplified.

[0068] The first gate GE1 may include a metal material, for example, a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

[0069] The first interlayer insulating layer 214 is disposed on the first gate electrode GE1. For example, the first interlayer insulating layer 214 may include an inorganic insulating material such as silicon oxide (SiO2) and silicon nitride (SiNx).

[0070] The display panel 140 may further include an upper buffer layer 215, a second gate insulating layer 216, and a second interlayer insulating layer 217 sequentially disposed on the first interlayer insulating layer 214. The first thin film transistor TFT1 may include a first source electrode SE1 and a first drain electrode DE1 located on the second interlayer insulating layer 217. The first source electrode SE1 and the first drain electrode DE1 may be connected to the first source region and the first drain region, respectively.

[0071] For example, the first source electrode SE1 and the first drain electrode DE1 may have a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

[0072] The upper buffer layer 215 separates the second active layer ACT2 of the oxide semiconductor material of the second thin film transistor TFT2 from the first active layer ACT1 of the polycrystalline semiconductor material and provides a base for the second active layer ACT2 .

[0073] The second gate insulating layer 216 covers the second active layer ACT2 of the second thin film transistor TFT2. Since the second gate insulating layer 216 is disposed on the second active layer ACT2 of the oxide semiconductor material, the second gate insulating layer 216 includes an inorganic insulating material. For example, the second gate insulating layer 216 may include silicon oxide (SiO2) and silicon nitride (SiNx).

[0074] The second gate GE2 includes a metal material. For example, the second gate GE2 may include a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

[0075] The second thin film transistor TFT2 is disposed on the upper buffer layer 215 and includes a second active layer ACT2 of an oxide semiconductor material, a second gate GE2 on the second gate insulating layer 216 , and a second source SE2 and a second drain DE2 on the second interlayer insulating layer 217 .

[0076] The second active layer ACT2 includes a second channel region, a second source region, and a second drain region. The second channel region includes an intrinsic oxide semiconductor material that is not doped with impurities, and the second source and the second drain are doped with impurities to be conductive.

[0077] The second thin-film transistor TFT2 is disposed above the upper buffer layer 215 and further includes a light-shielding layer LS that overlaps the second active layer ACT2. The light-shielding layer LS blocks light from entering the second active layer ACT2, thereby ensuring the reliability of the second thin-film transistor TFT2. The light-shielding layer LS may include the same material as the first gate electrode GE1 and may be disposed on the top surface of the first gate insulating layer 213. The light-shielding layer LS may be electrically connected to the second gate electrode GE2 to form a dual-gate structure.

[0078] By forming the second source electrode SE2 and the second drain electrode DE2 on the second interlayer insulating layer 217 simultaneously with the first source electrode SE1 and the first drain electrode DE1 through one mask process, the manufacturing process may be simplified.

[0079] The second capacitor electrode CST2 is disposed on the first interlayer insulating layer 214. The second capacitor electrode CST2 overlaps the first capacitor electrode CST1 to form a storage capacitor CST. For example, the second capacitor electrode CST2 may include a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

[0080] The storage capacitor CST stores a data signal supplied via the data line DL and supplies the data signal to the light emitting diode OLED. The storage capacitor CST includes two electrodes corresponding to each other and a dielectric layer located between the two electrodes. A first interlayer insulating layer 214 is provided between the first capacitor electrode CST1 and the second capacitor electrode CST2.

[0081] One of the first capacitor electrode CST1 and the second capacitor electrode CST2 of the storage capacitor CST may be electrically connected to one of the second source electrode SE2 and the second drain electrode DE2 of the second thin film transistor TFT2. In another embodiment, the connection of the storage capacitor CST may vary depending on the pixel circuit.

[0082] The first planarization layer 218 and the second planarization layer 219 are sequentially disposed on the pixel circuit for planarizing the pixel circuit. For example, the first planarization layer 218 and the second planarization layer 219 may include an organic insulating material such as polyimide and acrylic resin.

[0083] The light emitting diode OLED is disposed on the second planarization layer 219 .

[0084] The light emitting diode OLED includes an anode ANO, a cathode CAT, and a light emitting layer EL located between the anode ANO and the cathode CAT. Figure 4 ), the anode ANO may be provided as a separate electrode in each sub-pixel. When the pixel circuit uses a high-level voltage commonly connected to the anode ANO, the cathode CAT may be provided as a separate electrode in each sub-pixel.

[0085] The light emitting diode OLED is electrically connected to the driving element via the central electrode CNE on the first planarization layer 218. The anode electrode ANO of the light emitting diode OLED and the first source electrode SE1 of the first thin film transistor TFT1 of the pixel circuit are connected to each other via the central electrode CNE.

[0086] The anode electrode ANO is connected to the central electrode CNE via a contact hole in the second planarization layer 219. The central electrode CNE is connected to the first source electrode SE1 via a contact hole in the first planarization layer 218.

[0087] The center electrode CNE connects the first source electrode SE1 and the anode electrode ANO. For example, the center electrode CNE may include a conductive material such as copper (Cu), silver (Ag), molybdenum (Mo), and titanium (Ti).

[0088] The anode ANO may have a multilayer including a transparent conductive layer and an opaque conductive layer having excellent reflectivity. For example, the transparent conductive layer may include a material having a relatively high work function such as indium tin oxide (ITO) and indium zinc oxide (IZO). The opaque conductive layer may have a single layer or multiple layers of one of aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti) and alloys thereof. The anode ANO may have a structure in which a transparent conductive layer, an opaque conductive layer and a transparent conductive layer are laminated in sequence, or a structure in which a transparent conductive layer and an opaque conductive layer are laminated in sequence.

[0089] The light emitting layer EL includes a hole-related layer, an organic light emitting layer, and an electron-related layer, which are laminated in this order or in the reverse order.

[0090] The bank layer BNK may be referred to as a pixel-defining layer for exposing the anode electrode ANO of each sub-pixel SP1 to SP4. The bank layer BNK may include an opaque material (e.g., a black material) to prevent light interference between adjacent sub-pixels SP1 to SP4. The bank layer BNK may include a shielding material such as at least one of a color pigment, organic black, and carbon. Spacers may be provided on the bank layer BNK.

[0091] The cathode CAT is disposed on the top and side surfaces of the light-emitting layer EL and is opposite to the anode ANO. The cathode CAT may be integrally disposed throughout the display area DA. In a top-emission display device, the cathode CAT may include a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0092] An encapsulation layer 220 for preventing moisture penetration may be disposed on the cathode electrode CAT.

[0093] The encapsulation layer 220 can prevent external moisture or oxygen from penetrating into the light-emitting layer EL. The encapsulation layer 220 can include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In the display device 110, the encapsulation layer 220 can illustratively include a first encapsulation layer 221, a second encapsulation layer 222, and a third encapsulation layer 223.

[0094] The first encapsulation layer 221 is provided on the substrate 211 having the cathode CAT. The third encapsulation layer 223 is provided on the substrate 211 having the second encapsulation layer 222 and wraps around the first encapsulation layer 221.

[0095] The top surface, bottom surface, and side surface of the second encapsulation layer 222. The first encapsulation layer 221 and the third encapsulation layer 223 can minimize or prevent the penetration of external moisture or oxygen into the light-emitting layer EL. For example, the first encapsulation layer 221 and the third encapsulation layer 223 can include inorganic insulating materials that can be applied to low-temperature deposition, such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and aluminum oxide (Al2O3). By depositing the first encapsulation layer 221 and the third encapsulation layer 223 at a relatively low temperature, degradation of the light-emitting layer EL, which is susceptible to relatively high temperatures, can be prevented.

[0096] The second encapsulation layer 222 can reduce stress between layers of the display device 110 caused by bending and can flatten the step differences of the layers of the display device 110. For example, the second encapsulation layer 222 can be provided on the substrate 211 having the first encapsulation layer 221 and can include a non-photosensitive organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyethylene, and silicon oxycarbide (SiOC) or a photosensitive organic insulating material such as photoacryl. When the second encapsulation layer 222 is formed by an inkjet method, a weir DAM can be provided to prevent the liquid material for the second encapsulation layer 222 from spreading to the edge portion of the substrate 211. The weir DAM can be provided closer to the edge portion of the substrate 211 than the second encapsulation layer 222. Due to the weir DAM, the second encapsulation layer 222 is prevented from spreading to the pad area of ​​the outermost edge portion of the substrate 211 where the conductive pad is provided.

[0097] Although the weir DAM is provided to prevent diffusion of the second encapsulation layer 222, when the second encapsulation layer 222 is formed higher than the weir DAM, moisture may penetrate into the light emitting layer through the exposed second encapsulation layer 222. As a result, the weir DAM may be formed to have a number of at least ten.

[0098] A bank DAM may be provided on the second interlayer insulating layer 217 in the non-display area NDA.

[0099] The weir DAM may be formed simultaneously with the first planarization layer 218 and the second planarization layer 219. For example, the lower layer of the weir DAM may be formed simultaneously with the first planarization layer 218, and the upper layer of the weir DAM may be formed simultaneously with the second planarization layer 219, so that the weir DAM has a double-layer structure.

[0100] As a result, the bank DAM may have the same material as the first planarization layer 218 and the second planarization layer 219 .

[0101] The weir DAM may be disposed to overlap with the low-level voltage line VSS. For example, the low-level voltage line VSS may be disposed below the weir DAM in the non-display area NDA.

[0102] The low-level voltage line VSS and the first and second gate driving units 130 and 135 having a gate-in-panel (GIP) type are provided to surround the display area DA of the display panel 140, and the low-level voltage line VSS may be provided outside the first and second gate driving units 130 and 135. In addition, the low-level voltage line VSS may be connected to the cathode CAT to provide a common voltage. Although Figure 1 , the first gate driving unit 130 and the second gate driving unit 135 are shown to have a simple structure, but the first gate driving unit 130 and the second gate driving unit 135 may include thin film transistors having the same structure as those of the display area DA.

[0103] For example, the low-level voltage line VSS may have the same material as the first gate electrode GE1 , or the same material as the second capacitor electrode CST2 , the first source electrode SE1 , and the first drain electrode DE1 .

[0104] The low-level voltage line VSS may provide a low-level voltage Vss to the sub-pixels SP1 to SP4 in the display area DA (see FIG. Figure 4 ).

[0105] The touch layer may be disposed on the encapsulation layer 220. The touch buffer layer 251 of the touch layer may be disposed between the touch sensor metal and the cathode CAT of the light emitting diode OLED, and the touch sensor metal may include touch connection lines 252 and 254 and touch electrodes 255 and 256.

[0106] The touch buffer layer 251 can block the penetration of a solution (developing solution or etching solution) used in the manufacturing process of the touch sensor metal located on the touch buffer layer 251 or external moisture from penetrating into the light-emitting layer EL including an organic material. As a result, the touch buffer layer 251 can prevent the light-emitting layer EL, which is susceptible to the solution or moisture, from being degraded.

[0107] Touch buffer layer 251 comprises an organic insulating material suitable for low temperatures below approximately 100°C and having a dielectric constant of approximately 1 to 3. This prevents degradation of the light-emitting layer (EL), which comprises an organic material susceptible to relatively high temperatures. For example, touch buffer layer 251 may comprise a material comprising an acrylic group, an epoxy group, or a siloxane group. The touch buffer layer 251, made of an organic insulating material with planarizing properties, prevents degradation of the encapsulation layer 220 due to bending of the display device 110 and damage to the touch sensor metal on the touch buffer layer 251.

[0108] In a mutual capacitance-based touch sensor structure, the touch electrodes 255 and 256 may be disposed on the touch buffer layer 251 and may alternate with each other.

[0109] The touch connection lines 252 and 254 may connect the touch electrodes 255 and 256. The touch connection lines 252 and 254 and the touch electrodes 255 and 256 may be provided in different layers, and a touch insulating layer 253 may be provided therebetween.

[0110] The touch link lines 252 and 254 may be disposed to overlap the bank layer BNK to prevent a reduction in aperture ratio.

[0111] The touch electrodes 255 and 256 may be electrically connected to a touch driving circuit (not shown) via portions of touch connection lines 252 connected to touch pads PAD through top and side surfaces of the encapsulation layer 220 and the top and side surfaces of the dam DAM.

[0112] The portion of the touch connection line 252 may receive a touch drive signal from the touch drive circuit and transmit the touch drive signal to the touch electrodes 255 and 256. The portion of the touch connection line 252 may transmit touch sensing signals of the touch electrodes 255 and 256 to the touch drive circuit.

[0113] A touch protection layer 257 may be provided on the touch electrodes 255 and 256. Figure 2 In the embodiment, the touch protection layer 257 is disposed on the touch electrodes 255 and 256 , but the touch protection layer 257 may extend to the front or rear of the dam DAM to be disposed on the touch connection line 252 .

[0114] A color filter (not shown) may be provided on the encapsulation layer 220. The color filter may be provided on the touch layer or may be provided between the encapsulation layer 220 and the touch layer.

[0115] exist Figure 3 In the embodiment, the first gate driving unit 130 of the display device 110 includes a second scanning block Bsc2 and a second light-emitting block Bem2, and the second gate driving unit 135 of the display device 110 includes a first scanning block Bsc1 and a first light-emitting block Bem1. The display area DA of the display panel 140 is disposed between the first gate driving unit 130 and the second gate driving unit 135.

[0116] In another embodiment, the configuration structures of the first scanning block Bsc1 , the second scanning block Bsc2 , the first light-emitting block Bem1 , and the second light-emitting block Bem2 in the first gate driving unit 130 and the second gate driving unit 135 may be variously changed.

[0117] For example, in Figure 3In an embodiment, the second light-emitting block Bem2 is disposed farther away from the display panel 140 than the second scanning block Bsc2, and the first light-emitting block Bem1 is disposed farther away from the display panel 140 than the first scanning block Bsc1. In another embodiment, the second scanning block Bsc2 may be disposed farther away from the display panel 140 than the second light-emitting block Bem2, or the first scanning block Bsc1 may be disposed farther away from the display panel 140 than the first light-emitting block Bem1.

[0118] Each of the second scanning block Bsc2 and the second light-emitting block Bem2 of the first gate driving unit 130 and the first scanning block Bsc1 and the first light-emitting block Bem1 of the second gate driving unit 135 may be a stage of a shift register, and the shift register may include a plurality of stages connected to each other in a cascade manner.

[0119] In the first gate driving unit 130, the second scanning block Bsc2 and the second light-emitting block Bem2 generate the second scanning signal Sc2 (see Figure 5 ) and the second luminous signal Em2 (see Figure 5 ).

[0120] In the second gate driving unit 135, the first scanning block Bsc1 and the first light-emitting block Bem1 generate the first scanning signal Sc1 (see Figure 5 ) and the first luminous signal Em1 (see Figure 5 ).

[0121] The first scan signal Sc1 of the first scan block Bsc1 is supplied to the third transistor T3 and the fourth transistor T4 (see FIG. 1 ) in each of the sub-pixels SP1 to SP4 in the display area DA via the gate line GL. Figure 5 The second scan signal Sc2 of the second scan block Bsc2 is supplied to the second transistor T2 in each sub-pixel SP1 to SP4 of the display area DA via the gate line GL (see Figure 5 ).

[0122] The first light emitting signal Em1 of the first light emitting block Bem1 is supplied to the sixth transistor T6 (see FIG. 1 ) in each of the sub-pixels SP1 to SP4 of the display area DA via the gate line GL. Figure 5 ), the second light emitting signal Em2 of the second light emitting block Bem2 is supplied to the fifth transistor T5 in each sub-pixel SP1 to SP4 in the display area DA via the gate line GL (see Figure 5 ).

[0123] In another embodiment, the first gate driving unit 130 and the second gate driving unit 135 may have a symmetrical structure. For example, each of the first gate driving unit 130 and the second gate driving unit 135 may include a first scanning block Bsc1, a second scanning block Bsc2, a first light-emitting block Bem1, and a second light-emitting block Bem2.

[0124] exist Figure 4 In the embodiment of the present invention, each of the first subpixel SP1, the second subpixel SP2, the third subpixel SP3, and the fourth subpixel SP4 of the display panel 140 of the display device 110 includes a switching transistor Ts, a driving transistor Td, a compensation portion Pc, a storage capacitor Cs, and a light emitting diode De. The active layers of the switching transistor Ts and the driving transistor Td may be formed of a semiconductor material such as an oxide semiconductor material, an amorphous semiconductor material, a polycrystalline semiconductor material, or an organic semiconductor material.

[0125] Oxide semiconductor materials can have an excellent effect of preventing leakage current and have a relatively low manufacturing cost. Oxide semiconductors can be formed by metal oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn) and titanium (Ti) or a combination of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn) or titanium (Ti) and their oxides. Specifically, oxide semiconductors may include zinc oxide (ZnO), zinc tin oxide (ZTO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO) and indium gallium oxide (IGO).

[0126] Polycrystalline semiconductor materials have a fast moving speed of carriers such as electrons and holes, thus having high mobility, low energy consumption, and excellent reliability. Polycrystalline semiconductors can be formed of polycrystalline silicon (poly-Si).

[0127] The amorphous semiconductor material may be formed of amorphous silicon (a-Si).

[0128] For example, the switching transistor Ts and the driving transistor Td may be oxide semiconductor thin film transistors, amorphous silicon thin film transistors, or low-temperature polysilicon thin film transistors.

[0129] The switching transistor Ts is switched according to the scan signal Sc as a gate signal. The gate of the switching transistor Ts is connected to the scan signal Sc, the source of the switching transistor Ts is connected to the first capacitor electrode of the storage capacitor Cs and the compensation part Pc, and the drain of the switching transistor Ts is connected to the data signal Vdata.

[0130] The driving transistor Td is switched according to the voltage of the first capacitor electrode of the storage capacitor Cs. The gate of the driving transistor Td is connected to the first capacitor electrode of the storage capacitor Cs and the compensation part Pc, the source of the driving transistor Td is connected to the anode of the light emitting diode De, and the drain of the driving transistor Td is connected to the high-level voltage Vdd.

[0131] The compensation part Pc is connected between the switching transistor Ts, the driving transistor Td, and the storage capacitor Cs, and compensates for variations in the threshold voltage Vth of the driving transistor Td.

[0132] The storage capacitor Cs stores the data signal Vdata. A first capacitor electrode of the storage capacitor Cs is connected to the source of the switching transistor Ts and the compensation part Pc, and a second capacitor electrode of the storage capacitor Cs is connected to the compensation part Pc.

[0133] The light emitting diode De is connected between the driving transistor Td and the low-level voltage Vss and emits light with a brightness proportional to the current of the driving transistor Td. The anode of the light emitting diode De is connected to the source of the driving transistor Td, and the cathode of the light emitting diode De is connected to the low-level voltage Vss.

[0134] The data signal Vdata is supplied from the data driving unit 125 to each subpixel SP1 to SP4 of the display panel 140 , and the scan signal Sc is supplied from the first and second gate driving units 130 and 135 to each subpixel SP1 to SP4 of the display panel 140 .

[0135] In the pixel circuit of the present invention, various configurations of the internal compensation circuit are possible. For example, the number of transistors TFT in the pixel circuit of the present invention can be three or more, and the number of capacitors can be one or more. For example, each of the first to fourth sub-pixels SP1 to SP4 can have one of a 3T1C structure including three transistors (3T) and one capacitor (1C), a 6T1C structure including six transistors and one capacitor, a 7T1C structure including seven transistors and one capacitor, and an 8T1C structure including eight transistors and one capacitor.

[0136] exist Figure 5 In the embodiment of the present invention, each of the first to fourth sub-pixels SP1 to SP4 of the display panel 140 of the display device 110 includes first to sixth transistors T1 to T6, a storage capacitor Cs, and a light-emitting diode De. At least one of the first to sixth transistors T1 to T6 may be an oxide semiconductor thin film transistor, and the rest of the first to sixth transistors T1 to T6 may be low-temperature polysilicon thin film transistors.

[0137] For example, the first transistor T1 , the second transistor T2 , the fifth transistor T5 and the sixth transistor T6 may be negative (N) type low temperature polysilicon thin film transistors, and the third transistor T3 and the fourth transistor T4 may be negative (N) type oxide semiconductor thin film transistors.

[0138] The first transistor T1 as a driving transistor switches according to the voltage of the first capacitor electrode of the storage capacitor Cs. The gate of the first transistor T1 is connected to the second node N2, the source of the first transistor T1 is connected to the third node N3, and the drain of the first transistor T1 is connected to the first node N1.

[0139] The second transistor T2 as a switching transistor is switched according to the second scan signal Sc2. The gate of the second transistor T2 is connected to the second scan signal Sc2, the source of the second transistor T2 is connected to the third node N3, and the drain of the second transistor T2 is connected to the data signal Vdata.

[0140] The third transistor T3 as a sensing transistor is switched according to the first scan signal Sc1. The gate of the third transistor T3 is connected to the first scan signal Sc1, the source of the third transistor T3 is connected to the first node N1, and the drain of the third transistor T3 is connected to the second node N2.

[0141] The fourth transistor T4 is switched according to the first scanning signal Sc1 , has a gate connected to the first scanning signal Sc1 , a drain connected to the initial signal (initial voltage) Vini, and a source connected to a fourth node N4 .

[0142] The fifth transistor T5 as a light emitting transistor is switched according to the second light emitting signal Em2. The gate of the fifth transistor T5 is connected to the second light emitting signal Em2, the source of the fifth transistor T5 is connected to the first node N1, and the drain of the fifth transistor T5 is connected to the high level signal (high level voltage) Vdd.

[0143] The sixth transistor T6 as a light emitting transistor is switched according to the first light emitting signal Em1. The gate of the sixth transistor T6 is connected to the first light emitting signal Em1, the source of the sixth transistor T6 is connected to the fourth node N4, and the drain of the sixth transistor T6 is connected to the third node N3.

[0144] The storage capacitor Cs stores the data signal Vdata and the threshold voltage Vth. A first capacitor electrode of the storage capacitor Cs is connected to the second node N2, and a second capacitor electrode of the storage capacitor Cs is connected to the fourth node N4.

[0145] The light emitting diode De is connected between the fourth transistor T4, the sixth transistor T6 and the low level signal Vss to emit light with a brightness proportional to the current of the first transistor T1. The anode of the light emitting diode De is connected to the fourth node N4, and the cathode of the light emitting diode De is connected to the low level signal Vss.

[0146] The drain of the first transistor T1, the source of the third transistor T3, and the source of the fifth transistor T5 constitute a first node N1, the gate of the first transistor T1, the drain of the third transistor T3, and the first capacitor electrode of the storage capacitor Cs constitute a second node N2. The source of the first transistor T1, the source of the second transistor T2, and the drain of the sixth transistor T6 constitute a third node N3, and the source of the fourth transistor T4, the source of the sixth transistor T6, the second capacitor electrode of the storage capacitor Cs, and the anode of the light emitting diode De constitute a fourth node N4.

[0147] In each of the first to fourth sub-pixels SP1 to SP4, during a period in which the first transistor T1, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are turned on and the second transistor T2 and the sixth transistor T6 are turned off, the second node N2 may be initialized by the high-level signal Vdd and the fourth node N4 may be initialized by the initial signal Vini (initialization period).

[0148] During a period in which the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned on and the fifth transistor T5 and the sixth transistor T6 are turned off, the sum of the data signal Vdata and the threshold voltage Vth (Vdata+Vth) can be stored in the storage capacitor Cs, and the fourth node N4 can be initialized by the initial signal Vini (sampling period).

[0149] The light emitting diode De may emit light corresponding to the data signal Vdata during a period in which the first transistor T1 , the fifth transistor T5 , and the sixth transistor T6 are turned on and the second transistor T2 , the third transistor T3 , and the fourth transistor T4 are turned off (a light emitting period).

[0150] In the display device 110 , in order to reduce the number of output terminals of the data driving unit 125 and the number of data connection lines of the display panel 140 , a plurality of multiplexing transistors are used to transmit data signals.

[0151] Figure 6 is a view illustrating a data driving unit and a display panel of a display device according to an embodiment of the present invention.

[0152] exist Figure 6In FIG. 1 , the data driving unit 125 of the display device 110 according to the embodiment of the present invention includes a plurality of output terminals OT1 and OT2 in which the data signal Vdata is output.

[0153] The display panel 140 of the display device 110 is divided into a display area DA and a non-display area NDA located outside the display area DA. A plurality of sub-pixels SP11 to SP16, a plurality of data lines DL1 to DL6, and a plurality of gate lines GL1 are provided in the display area DA, while a plurality of data link lines DLL1 and DLL2 and a plurality of multiplexing transistors Tm1, Tm2, ​​and Tm3 are provided in the non-display area NDA. The plurality of multiplexing transistors Tm1, Tm2, ​​and Tm3 are provided in a multiplexing area MA within the non-display area NDA.

[0154] The first and second data link lines DLL1 and DLL2 may be connected to the first and second output terminals OT1 and OT2 , respectively, and each of the first and second data link lines DLL1 and DLL2 may be connected to the first, second, and third multiplexing transistors Tm1 , Tm2 , and Tm3 .

[0155] The first, second, and third multiplexing transistors Tm1, Tm2, ​​and Tm3 are switched according to the first, second, and third test multiplexing signals Mu1, Mu2, and Mu3, respectively. The first multiplexing transistor Tm1 can be connected to each of the first and fourth data lines DL1 and DL4. The second multiplexing transistor Tm2 can be connected to each of the second and fifth data lines DL2 and DL5. The third multiplexing transistor Tm3 can be connected to each of the third and sixth data lines DL3 and DL6.

[0156] The first, second, and third multiplexing transistors Tm1, Tm2, ​​and Tm3 may have a negative (N) type. The gates of the first, second, and third multiplexing transistors Tm1, Tm2, ​​and Tm3 may be connected to the first, second, and third test multiplexing signals Mu1, Mu2, and Mu3, respectively. The drains of the first, second, and third multiplexing transistors Tm1, Tm2, ​​and Tm3 may be connected to each of the first and second data link lines DLL1 and DLL2. The sources of the first, second, and third multiplexing transistors Tm1, Tm2, ​​and Tm3 may be connected to the first to sixth data lines DL1 to DL6, respectively.

[0157] The 1st-1st subpixel SP11 connected to the first data line DL1 and the first gate line GL1 may correspond to red, the 1st-2nd subpixel SP12 connected to the second data line DL2 and the first gate line GL1 may correspond to green, and the 1st-3rd subpixel SP13 connected to the third data line DL3 and the first gate line GL1 may correspond to blue. The 1st-4th subpixel SP14 connected to the fourth data line DL4 and the first gate line GL1 may correspond to red, the 1st-5th subpixel SP15 connected to the fifth data line DL5 and the first gate line GL1 may correspond to green, and the 1st-6th subpixel SP16 connected to the sixth data line DL6 and the first gate line GL1 may correspond to blue.

[0158] When the first multiplexing transistor Tm1 is turned on according to the first test multiplexing signal Mu1 synchronized with the first red data signal Vdata(r1) and the second red data signal Vdata(r2), the first red data signal Vdata(r1) and the second red data signal Vdata(r2) of the first and second data link lines DLL1 and DLL2 can be provided to the 1-1th sub-pixel SP11 and the 1-4th sub-pixel SP14 via the first data line DL1 and the fourth data line DL4, respectively.

[0159] Next, when the second multiplexing transistor Tm2 is turned on according to the second test multiplexing signal Mu2 synchronized with the first green data signal Vdata(g1) and the second green data signal Vdata(g2), the first green data signal Vdata(g1) and the second green data signal Vdata(g2) of the first and second data link lines DLL1 and DLL2 can be provided to the 1st-2nd sub-pixel SP12 and the 1st-5th sub-pixel SP15 via the second data line DL2 and the fifth data line DL5, respectively.

[0160] Next, when the third multiplexing transistor Tm3 is turned on according to the third test multiplexing signal Mu3 synchronized with the first blue data signal Vdata(b1) and the second blue data signal Vdata(b2), the first blue data signal Vdata(b1) and the second blue data signal Vdata(b2) of the first and second data link lines DLL1 and DLL2 can be provided to the 1st-3rd sub-pixels SP13 and the 1st-6th sub-pixels SP16 via the third data line DL3 and the sixth data line DL6, respectively.

[0161] In the display device 110 according to an embodiment of the present invention, the multiple output terminals OT1 and OT2 of the data driving unit 125 are connected to the multiple multiplexing transistors Tm1, Tm2 and Tm3 via the multiple data link lines DLL1 and DLL2 of the display panel 140, and the multiple multiplexing transistors Tm1, Tm2 and Tm3 are connected to the multiple data lines DL1 to DL6.

[0162] The red, green, and blue data signals Vdata(r1), Vdata(g1), and Vdata(b1), as well as Vdata(r2), Vdata(g2), and Vdata(b2), are sequentially output from each of the plurality of output terminals OT1 and OT2. Multiplexing transistors Tm1, Tm2, ​​and Tm3 transmit the red, green, and blue data signals Vdata(r1), Vdata(g1), and Vdata(b1), as well as Vdata(r2), Vdata(g2), and Vdata(b2), to the plurality of sub-pixels SP11 to SP16 via the plurality of data lines DL1 to DL6. As a result, the number of the plurality of output terminals OT1 and OT2 of the data driver unit 125 and the number of the plurality of data link lines DLL1 and DLL2 of the display panel 140 can be reduced.

[0163] Despite Figure 6 In an embodiment, the plurality of data lines DL are classified into three types and the plurality of multiplexing transistors include first, second and third multiplexing transistors Tm1, Tm2 and Tm3 respectively connected to the three types of the plurality of data lines DL, but in another embodiment, the plurality of data lines DL may be classified into six types, and the plurality of multiplexing transistors may include first to sixth multiplexing transistors connected to the six types of the plurality of data lines DL.

[0164] The display device 110 may be manufactured through a lighting test step and an attaching step of a data driving unit.

[0165] Figure 7 is a view showing a lighting test step of a display device according to an embodiment of the present invention; Figure 8 is a view showing an attaching step of a data driving unit of a display device according to an embodiment of the present invention; Figure 9 It is along Figure 8 A sectional view taken along line IX-IX.

[0166] exist Figure 7 In the illumination test step of the manufacturing process of the display device 110 according to the embodiment of the present invention, the test substrate 280 is disposed adjacent to and connected to the display panel 140 .

[0167] The display panel 140 includes a display area DA in which a plurality of sub-pixels SP11 to SP16 are disposed, and a non-display area NDA adjacent to the display area DA. The non-display area NDA includes a gate area GA in which a first gate driving unit 130 and a second gate driving unit 135 are disposed; a multiplexing area MA in which a plurality of multiplexing transistors Tm1 to Tm3 are disposed; a routing area RA in which a plurality of signal lines are disposed; a bending area BA that provides flexibility to the display panel 140; a pad area PA in which a plurality of gate pads Pg, a plurality of multiplexing pads Pm, and a plurality of data pads Pd are disposed; and a data enable area DEA in which a plurality of data enable transistors are disposed.

[0168] The test substrate 280 includes a plurality of gate test pads Pgt, a plurality of multiplexing test pads Pmt, a plurality of data test pads (not shown), and a plurality of multiplexing enable pads Pme.

[0169] The plurality of gate test pads Pgt may be connected to the plurality of gate test lines GTL, respectively, and the plurality of gate test lines GTL may be connected to the plurality of gate pads Pg, respectively. The plurality of gate pads Pg may be connected to the plurality of blocks Bsc1, Bsc2, Bem1, and Bem2 of the first gate driving unit 130 and the second gate driving unit 135, respectively, via the plurality of gate connection lines GLL.

[0170] In the lighting test step, a plurality of test gate control signals including a gate clock may be transmitted from the plurality of gate test pads Pgt to the plurality of blocks Bsc1 , Bsc2 , Bem1 , and Bem2 of the first and second gate driving units 130 and 135 .

[0171] Multiple multiplexing test pads Pmt may be connected to multiple multiplexing test lines MTL, and multiple multiplexing test lines MTL may be connected to multiple multiplexing pads Pm via multiple multiplexing enable transistors Tme. Multiple multiplexing pads Pm may be connected to multiple multiplexing transistors Tm1 to Tm3 via multiple multiplexing connection lines MLL.

[0172] Each of the multiplexing enabling transistors Tme may be of a negative (N) type. The gates of the multiplexing enabling transistors Tme may be connected to multiple multiplexing enabling pads Pme to receive a multiplexing enable signal Me. The drains of the multiplexing enabling transistors Tme may be connected to multiple multiplexing test lines MTL, and the sources of the multiplexing enabling transistors Tme may be connected to multiple multiplexing pads Pm.

[0173] In the lighting test step, the plurality of multiplexing enable transistors Tme may be turned on by the multiplexing enable signal Me (Me(on)) of a logic high level, and the test multiplexing signals Mu1, Mu2, and Mu3 may be transmitted from the plurality of multiplexing test pads Pmt to the plurality of multiplexing transistors Tm1, Tm2, ​​and Tm3.

[0174] The plurality of data test pads may be connected to a plurality of data test lines (not shown), respectively, and the plurality of data test lines may be connected to a plurality of data pads Pd via a plurality of data enable transistors. Each of the plurality of data pads Pd may be connected to a plurality of multiplexing transistors Tm1, Tm2, ​​and Tm3 via a plurality of data link lines DLL1 and DLL2, and the plurality of multiplexing transistors Tm1, Tm2, ​​and Tm3 may be connected to a plurality of data lines DL1 to DL6, respectively.

[0175] In the lighting test step, the plurality of data enable transistors may be turned on, and the test data signal Vdata may be transmitted from the plurality of data test pads to the plurality of data lines DL1 to DL6 .

[0176] In the illumination test step, the plurality of gate test pads Pgt of the test substrate 280 are respectively connected to the plurality of blocks Bsc1, Bsc2, Bem1 and Bem2 of the first gate driving unit 130 and the second gate driving unit 135 via the plurality of gate test lines GTL, the plurality of gate pads Pg and the plurality of gate connection lines GLL of the display panel 140, and the plurality of test gate control signals are transmitted from the plurality of gate test pads Pgt to the plurality of blocks Bsc1, Bsc2, Bem1 and Bem2 of the first gate driving unit 130 and the second gate driving unit 135.

[0177] The multiple multiplexing test pads Pmt of the test substrate 280 are respectively connected to the multiple multiplexing transistors Tm1, Tm2 and Tm3 via the multiple multiplexing test lines MTL of the display panel 140, the multiple multiplexing enable transistors Tme that are turned on, the multiple multiplexing pads Pm and the multiple multiplexing connection lines MLL, and the multiple test multiplexing signals Mu1, Mu2 and Mu3 are respectively transmitted from the multiple multiplexing test pads Pmt to the multiple multiplexing transistors Tm1, Tm2 and Tm3.

[0178] The plurality of data test pads of the test substrate 280 are connected to a plurality of multiplexing transistors Tm1, Tm2, ​​and Tm3 via a plurality of data test lines of the display panel 140, a plurality of turned-on data enable transistors Tme, a plurality of data pads Pd, and a plurality of data link lines DLL1 and DLL2. The plurality of multiplexing transistors Tm1, Tm2, ​​and Tm3 are connected to a plurality of data lines DL1 to DL6, respectively. Furthermore, a plurality of test data signals Vdata are transmitted from the plurality of data test pads Pdt to the plurality of data lines DL1 to DL6, respectively.

[0179] As a result, the plurality of test data signals Vdata are provided to the plurality of sub-pixels SP11 to SP16 of the display panel 140 , and degradation of the display panel 140 may be judged by detecting whether the plurality of sub-pixels SP11 to SP16 emit light.

[0180] After the lighting test step, the test substrate 280 is detached from the display panel 140 .

[0181] exist Figure 8 and 9 In the embodiment, the attaching step of the data driving unit 125 is performed for the display panel 140 judged as a good product in the lighting test step by using a connection unit such as a flexible printed circuit (FPC) 290 .

[0182] The data driving unit 125 such as an integrated circuit (IC) may be mounted on the FPC 290 , and a printed circuit board (PCB) on which the timing control unit 120 is mounted may be connected to the FPC 290 .

[0183] The FPC 290 includes a plurality of gate lines (GFL), multiplexing lines (MFL), and data lines (DFL). The gate lines (GFL) transmit gate control signals, the multiplexing lines (MFL) transmit multiplexing signals (Mu1, Mu2, and Mu3), and the data lines (DFL) transmit data signals (Vdata).

[0184] The plurality of gate film lines GFL of the FPC 290 may be respectively connected to the plurality of gate pads Pg of the display panel 140. The plurality of multiplexing film lines MFL of the FPC 290 may be respectively connected to the plurality of multiplexing pads Pm of the display panel 140. The plurality of data film lines DFL of the FPC 290 may be respectively connected to the plurality of data pads Pd of the display panel 140.

[0185] During the data driver unit 125 attachment process, the plurality of gate film lines GFL, the plurality of multiplexing film lines MFL, and the plurality of data film lines DFL of the FPC 290 can be connected to the plurality of gate pads Pg, the plurality of multiplexing pads Pm, and the plurality of data pads Pd of the display panel 140, respectively. A plurality of gate control signals can be transmitted from the plurality of gate film lines GFL via the plurality of gate pads Pg to the plurality of blocks Bsc1, Bsc2, Bem1, and Bem2 of the first gate driver unit 130 and the second gate driver unit 135, respectively. A plurality of multiplexing signals Mu1, Mu2, and Mu3 can be transmitted from the plurality of multiplexing film lines MFL via the plurality of multiplexing pads Pm to the plurality of multiplexing transistors Tm1, Tm2, ​​and Tm3, respectively. A plurality of data signals Vdata can be transmitted from the plurality of data film lines DFL via the plurality of data pads Pd to the plurality of data lines DL1 to DL6, respectively.

[0186] The plurality of data film lines DFL of the FPC 290 and the plurality of multiplexing test lines MTL of the display panel 140 overlap each other.

[0187] Although not shown, a protection layer may be provided on the plurality of multiplexing test lines MTL.

[0188] As a result, when a multiplexing signal blocking unit such as a plurality of multiplexing enable transistors Tme is not provided, a plurality of multiplexing signals Mu1, Mu2, and Mu3 of a plurality of multiplexing film lines MFL may be transmitted to a plurality of multiplexing test lines MTL via a plurality of multiplexing pads Pm. Since the data signals Vdata of the plurality of data film lines DFL are distorted by coupling between the plurality of multiplexing signals Mu1, Mu2, and Mu3 of the plurality of multiplexing test lines MTL and the data signals Vdata of the plurality of data film lines DFL, degradation such as line defects may occur in the display panel 140.

[0189] In the display device 110 according to an embodiment of the present invention, multiplexing enable transistors Tme are provided between multiple multiplexing test lines MTL and multiple multiplexing pads Pm. The multiple multiplexing enable transistors Tme are turned off during the attachment process of the data driver unit 125. This prevents multiplexing signals Mu1, Mu2, and Mu3 from being transmitted to the multiple multiplexing test lines MTL, and allows the multiple multiplexing test lines MTL to be in a floating state. As a result, coupling between the multiple data film lines DFL and the multiple multiplexing test lines MTL can be minimized, preventing degradation such as line defects.

[0190] Although not shown, the pad area PA may include a multiplexing enable pad connected to the gates of the plurality of multiplexing enable transistors Tme, the FPC 290 may include a multiplexing enable film line, and the multiplexing enable film line of the FPC 290 may be connected to the multiplexing enable pad of the display panel 140. A multiplexing enable signal Me (Me(off)) of a logic low level may be transmitted from the multiplexing enable film line of the FPC 290 to the gates of the plurality of multiplexing enable transistors Tme via the multiplexing enable pad of the display panel 140.

[0191] In the display device 110 according to an embodiment of the present invention, a plurality of multiplexing enable transistors Tme are provided between a plurality of multiplexing test lines MTL and a plurality of multiplexing pads Pm. During an illumination test step, the plurality of multiplexing enable transistors Tme are turned on, and a plurality of test multiplexing signals Mu1, Mu2, and Mu3 are transmitted from the plurality of multiplexing test pads Pmt of the test substrate 280 to the plurality of multiplexing transistors Tm1, Tm2, ​​and Tm3 of the display panel 140, respectively.

[0192] During the attachment process of the data driver unit 125 and subsequent processes, the multiplexed signals Mu1, Mu2, and Mu3 are transmitted from the multiplexed film lines MFL of the FPC 290 to the multiplexed transistors Tm1, Tm2, ​​and Tm3 of the display panel 140, respectively. However, since the multiplexed enable transistors Tme are turned off, the multiplexed signals Mu1, Mu2, and Mu3 are not transmitted from the multiplexed film lines MFL of the FPC 290 to the multiplexed test lines MTL of the display panel 140, and the multiplexed test lines MTL are in a floating state. As a result, the coupling between the multiple data film lines DFL and the multiplexed test lines MTL is minimized.

[0193] Therefore, in the illumination test step of the display device 110 according to an embodiment of the present invention, since the multiplexing signal blocking unit for selectively blocking the multiplexed signal is provided between the multiplexing test line for sending the multiplexed signal and the multiplexing pad for receiving the multiplexed signal, degradation such as line defects due to coupling between the multiplexing line and the film line is prevented.

[0194] Furthermore, a multiplexing signal blocking unit for selectively blocking multiplexing signals is provided between the multiplexing lines and the multiplexing pads. Due to the multiplexing signal blocking unit, the multiplexing signals are transmitted during the lighting test step and then blocked after the data driver unit is attached. This prevents coupling between the multiplexing lines and the film lines, reduces power consumption, and achieves low-power drive.

[0195] It will be clear to those skilled in the art that various modifications and variations can be made in the present invention without departing from the scope of the present invention. Therefore, the present invention is intended to cover modifications and variations of the present invention that fall within the scope of the appended claims and their equivalents.

Claims

1. A display device comprising: A timing control circuit for generating image data, data control signals and gate control signals; a data driving circuit for generating a data signal using the image data and the data control signal; a gate driving circuit for generating a gate signal using the gate control signal; as well as A display panel is provided for displaying an image using the data signal and the gate signal and includes a plurality of multiplexing test lines, a plurality of multiplexing enabling transistors respectively connected to the plurality of multiplexing test lines, and a plurality of multiplexing pads respectively connected to the plurality of multiplexing enabling transistors.

2. The display device according to claim 1, wherein the display panel further comprises: a plurality of gate lines and a plurality of data lines crossing each other to define a plurality of sub-pixels; a plurality of multiplexing connection lines respectively connected to the plurality of multiplexing pads; and a plurality of multiplexing transistors respectively connected between the plurality of multiplexing connection lines and the plurality of data lines. 3 . The display device according to claim 2 , wherein the plurality of multiplexing transistors are switched according to a plurality of multiplexing signals transmitted from the plurality of multiplexing pads.

4. The display device according to claim 3 , wherein the display panel further comprises a plurality of data connection lines connected to the plurality of multiplexing transistors and a plurality of data pads connected to the plurality of data connection lines, wherein the plurality of multiplexing pads are connected to a plurality of multiplexing film lines of a flexible printed circuit to receive the plurality of multiplexing signals, The plurality of data pads are connected to a plurality of data film lines of the flexible printed circuit to receive the data signals.

5. The display device according to claim 4 , wherein the plurality of multiplexing test lines and the plurality of data film lines overlap each other, The multiplexing enabling transistors are turned on in the lighting test step and turned off in the data driving circuit attaching step. 6 . The display device according to claim 5 , wherein in the attaching step of the data driving circuit, the plurality of multiplexing test lines have a floating state.

7. The display device according to claim 4, wherein the display panel is divided into a display area and a non-display area located at the periphery of the display area, The plurality of sub-pixels, the plurality of data lines, and the plurality of gate lines are disposed in the display area, and the plurality of data connection lines and the plurality of multiplexing transistors are disposed in the non-display area.

8. The display device according to claim 1 , wherein the gate signal comprises a first scanning signal, a second scanning signal, a first light emitting signal, and a second light emitting signal. The display panel further comprises a plurality of sub-pixels. Each of the plurality of sub-pixels comprises: storage capacitors; a first transistor that switches according to a voltage of a first capacitor electrode of the storage capacitor; a second transistor switched according to the second scan signal and connected to the data signal and the first transistor; a third transistor switched according to the first scan signal and connected to the storage capacitor and the first transistor; a fourth transistor switched according to the first scan signal and connected to the storage capacitor and an initial signal; a fifth transistor, the fifth transistor being switched according to the second light emitting signal and connected to the high level signal and the first transistor; a sixth transistor, the sixth transistor being switched according to the first light emitting signal and connected to the first transistor; as well as A light emitting diode is connected to the sixth transistor and a low-level signal. 9 . The display device according to claim 8 , wherein at least one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor is an oxide semiconductor thin film transistor. 10 . The display device according to claim 8 , wherein the first transistor, the second transistor, the fifth transistor, and the sixth transistor are negative-type low-temperature polysilicon thin film transistors, and the third transistor and the fourth transistor are negative-type oxide semiconductor thin film transistors.

11. The display device according to claim 1 , wherein the gate signal comprises a first scanning signal, a second scanning signal, a first light emitting signal, and a second light emitting signal. The gate driving circuit includes a first gate driving circuit and a second gate driving circuit arranged on both sides of the display panel. The first gate driving circuit includes a second scanning block for generating the second scanning signal and a second light-emitting block for generating the second light-emitting signal. The second gate driving circuit includes a first scanning block for generating the first scanning signal and a first light-emitting block for generating the first light-emitting signal.

12. The display device according to claim 11 , wherein the second scanning block is disposed farther from the display panel than the second light-emitting block, or the second light-emitting block is disposed farther from the display panel than the second scanning block. The first scanning block is disposed farther from the display panel than the first light-emitting block, or the first light-emitting block is disposed farther from the display panel than the first scanning block. 13 . The display device according to claim 11 , wherein the display panel further comprises a plurality of gate connection lines connected to the first gate driving circuit and the second gate driving circuit, and a plurality of gate pads connected to the plurality of gate connection lines. 14 . The display device according to claim 13 , wherein the plurality of gate pads are connected to a plurality of gate film lines of a flexible printed circuit for transmitting the gate control signals.

15. The display device according to claim 1, wherein gates of the plurality of multiplexing enabling transistors are respectively connected to a plurality of multiplexing enabling pads of a test substrate to receive multiplexing enabling signals, drains of the plurality of multiplexing enabling transistors are respectively connected to the plurality of multiplexing test lines, and sources of the plurality of multiplexing enabling transistors are respectively connected to the plurality of multiplexing pads.

16. A method for manufacturing a display device, comprising: forming a plurality of multiplexing test lines, a plurality of multiplexing enabling transistors respectively connected to the plurality of multiplexing test lines, and a plurality of multiplexing pads respectively connected to the plurality of multiplexing enabling transistors on the display panel; By disposing a test substrate adjacent to the display panel, a plurality of multiplexed test pads of the test substrate are connected to a plurality of multiplexed test lines of the display panel; performing an illumination test of the display panel by turning on the plurality of multiplexing enable transistors and applying a plurality of multiplexing signals from the test substrate to the plurality of multiplexing pads; connecting a plurality of multiplexing film lines of the flexible printed circuit to the plurality of multiplexing pads by attaching the flexible printed circuit to the display panel; as well as The display panel is driven by turning off the multiplexing enable transistors and applying multiplexing signals from the flexible printed circuit to the multiplexing pads.

17. The method according to claim 16, further comprising: A plurality of gate lines and a plurality of data lines crossing each other to define a plurality of sub-pixels, a plurality of multiplexing connection lines respectively connected to the plurality of multiplexing pads, and a plurality of multiplexing transistors respectively connected between the plurality of multiplexing connection lines and the plurality of data lines are formed on the display panel. 18 . The method of claim 17 , wherein the plurality of multiplexing transistors are switched according to a plurality of multiplexing signals transmitted from the plurality of multiplexing pads.

19. The method according to claim 18, further comprising: forming a plurality of data connection lines connected to the plurality of multiplexing transistors and a plurality of data pads connected to the plurality of data connection lines on the display panel, wherein the plurality of multiplexing pads are connected to a plurality of multiplexing film lines of a flexible printed circuit to receive the plurality of multiplexing signals, The plurality of data pads are connected to a plurality of data film lines of the flexible printed circuit to receive the data signals.

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