Electric leakage compensation method of display circuit

Abstract

The invention discloses an electric leakage compensation method of a display circuit. The electric leakage compensation method comprises the steps of obtaining a display pixel voltage of a current frame and a data signal voltage of a next frame; calculating the leakage voltage of the current frame based on the display pixel voltage and the data signal voltage; generating a compensation data signal voltage corresponding to the current frame pixel voltage based on the leakage voltage; and inputting the compensation data signal voltage to a display circuit. The beneficial effects of the invention are that when the display circuit is used, the display pixel voltage and the data signal voltage are compared, the leakage current direction is determined based on the comparison result, and the real-time leakage voltage is obtained through the leakage current direction, so that the pixel voltage of the circuit is dynamically calibrated; therefore, accurate picture brightness is obtained, and a high-quality and stable picture is obtained.

Description

Technical Field

[0001] The present invention relates to the field of pixel display technology, and in particular to a leakage compensation method for a display circuit. Background Art

[0002] In traditional field or color sequential display drive technologies, the traditional pixel driver circuit requires that all screen data be written and the liquid crystal deflection reaches a stable state before the backlight can be turned on. Otherwise, the screen will be chaotic. Therefore, the time required for data writing and liquid crystal deflection greatly compresses the backlight on time, making it difficult to increase display brightness, refresh rate and resolution, increase power consumption, and increase backlight material costs. Therefore, how to speed up the LCD drive time and increase the backlight on time is a very important issue.

[0003] Especially in traditional displays, when a frame is displayed, data signal voltages are written line by line to charge the pixels in order to maintain the grayscale brightness voltage of the pixels in that frame. As the resolution of current products is getting higher and higher, the storage capacitance of pixels is getting smaller and smaller, and the impact of leakage on pixel voltage is getting greater and greater. That is, when the pixel charging is completed and the gate is closed, the leakage effect of the tube in the subthreshold region causes the pixel voltage to be inaccurate due to leakage during the frame display.

[0004] Therefore, the present invention proposes a leakage compensation method for a display circuit to further stabilize the screen brightness and optimize the display. Summary of the Invention

[0005] The purpose of the present invention is to provide a leakage compensation method for a display circuit, thereby achieving stable picture brightness and optimized display.

[0006] The present invention aims to implement a leakage compensation method for a display circuit through the following technical solutions, including: Obtaining the display pixel voltage of the current frame and the data signal voltage of the next frame; Calculating the leakage voltage of the current frame based on the display pixel voltage and the data signal voltage; generating a compensation data signal voltage corresponding to a pixel voltage of a current frame based on the leakage voltage; The compensated data signal voltage is input to the display circuit.

[0007] Furthermore, the calculating the leakage voltage of the current frame based on the pixel voltage and the data signal voltage includes: When the data signal voltage is less than the display pixel voltage, the leakage current flows out of the pixel voltage, and a first leakage current is generated based on the gate control voltage, threshold voltage and thermal voltage of the transistor; When the data signal voltage is equal to the display pixel voltage, there is no voltage difference across the transistor. At this time, the transistor does not leak electricity and does not generate leakage current, so no further calculation is required in the subsequent section. When the data signal voltage is greater than the display pixel voltage, the leakage current flows into the pixel voltage, and a second leakage current is generated based on the gate control voltage, threshold voltage, thermal voltage and feed-through voltage of the transistor; A leakage voltage of a current frame is generated based on the first leakage current / the second leakage current.

[0008] Furthermore, when a leakage compensation method for a display circuit is applied to a display circuit of a conventional display panel, generating a leakage voltage of a current frame based on the first leakage current / the second leakage current includes: generating a negative leakage component voltage based on the first leakage current and the row charging time; Further, calculating the negative leakage component voltage based on the first leakage current includes: The formula for calculating the negative leakage component voltage based on the first leakage current is configured as: ; in, is the first leakage current of the conventional display panel, For the row charging time, is the capacitance value of the storage capacitor Cst; The first leakage current of the conventional display panel is: ; in, is the reference current, is the gate control voltage of the transistor, is the threshold voltage of the transistor, is the thermal voltage, is the data signal voltage of the next frame.

[0009] generating a forward leakage component voltage based on the second leakage current and the row charging time; The formula for calculating the forward leakage component voltage based on the second leakage current is configured as: ; in, is the second leakage current of the conventional display panel; The second leakage current of the conventional display panel is: ; in, To display the pixel voltage, is the feed-through voltage.

[0010] generating a leakage voltage of a current frame based on the leakage component voltage; The leakage voltage formula is configured as: ; in, , is the directional coefficient, satisfying: = -1 and = 0 (data signal voltage < display pixel voltage); = 0 and = 1 (data signal voltage > display pixel voltage); is the negative leakage component voltage, is the forward leakage component voltage, and m is the number of rows in the display circuit.

[0011] Furthermore, when the leakage method is applied to a display circuit of a conventional display panel, generating a compensation data signal voltage corresponding to a pixel voltage of a current frame based on the leakage voltage includes: generating a compensated data signal voltage based on the leakage voltage and a data signal voltage of a current frame; ,Right now ; Where ΔV is the leakage voltage of all rows.

[0012] Furthermore, when a leakage compensation method for a display circuit is applied to a display circuit of a field sequential display panel, generating a leakage voltage of a current frame based on the first leakage current / the second leakage current includes: When the display circuit is writing in a positive frame, the leakage voltage of the pixel capacitor Clc of the current frame and the leakage voltage of the pre-storage capacitor Cs1 are generated based on the first leakage current and the leakage time within the frame; The leakage voltage of the pixel capacitor Clc in the positive frame is: ;

[0013] The leakage voltage of the pre-storage capacitor Cs1 during the positive frame is: ; in, is the leakage time, is the pixel voltage, is the actual pixel voltage, The voltage of the preset pre-storage capacitor Cs1 is the data signal voltage of the current frame. is the actual voltage of the pre-storage capacitor Cs1, is the capacitance value of the pre-storage capacitor Cs1, To maintain the sum of the capacitances of capacitor Cs2 and pixel capacitor Clc, C2=Cs2+Clc, is the first leakage current of the field sequential display panel; The first leakage current of the field sequential display panel is: ; in, is the reference current, is the gate control voltage of the transistor, is the threshold voltage of the transistor, is the thermal voltage.

[0014] When the display circuit is in negative frame writing, the leakage voltage of the pixel capacitor Clc of the current frame and the leakage voltage of the pre-storage capacitor Cs1 are generated based on the second leakage current and the leakage time within the frame; The leakage voltage of the pixel capacitor Clc during the negative frame is: ; The leakage voltage of the pre-storage capacitor Cs1 during the negative frame is: ; in, is the leakage time, is the pixel voltage, is the actual pixel voltage, The voltage of the preset pre-storage capacitor Cs1 is the data signal voltage of the current frame. is the actual voltage of the pre-storage capacitor Cs1, is the capacitance value of the pre-storage capacitor Cs1, To maintain the sum of the capacitance of the capacitor and the pixel capacitance Clc, C2=Cs2+Clc, is the second leakage current of the field sequential display panel; The second leakage current of the field sequential display panel is: ; in, is the reference current, is the gate control voltage of the transistor, is the threshold voltage of the transistor, is the thermal voltage, To display the pixel voltage, is the feed-through voltage.

[0015] Furthermore, when applied to a display circuit of a field sequential display panel, generating a compensation data signal voltage corresponding to a pixel voltage of a current frame based on the leakage voltage includes: Generate a compensation data signal voltage corresponding to the pixel voltage of the current frame based on the charge conservation principle, the leakage voltage of the pixel capacitor Clc of the current frame, and the leakage voltage of the pre-storage capacitor Cs1; When the display circuit is in the positive frame writing state: ; When the display circuit is negative frame writing: ; in is the first leakage current of the field sequential display panel, is the second leakage current of the field sequential display panel, is the pixel voltage of the previous frame, is the pixel voltage of the current frame, is the pixel voltage of the next frame, m=Cs2 / Cs1, p=Clc / Cs1, C1=Cs1, C2=Cs2+Clc.

[0016] Furthermore, the display circuit of the conventional display panel includes: a first transistor T1, a storage capacitor Cst and a pixel capacitor Clc; A first source and drain of the first transistor T1 is coupled to the data signal line Data, a gate of the first transistor T1 is coupled to the row gate signal line Scan, a second source and drain of the first transistor T1 is coupled to one end of a storage capacitor Cst, and the other end of the storage capacitor Cst is coupled to the common signal line Com; The second source and drain of the first transistor T1 are also coupled to one end of the pixel capacitor Clc, and the other end of the pixel capacitor Clc is coupled to the common signal line Com.

[0017] Furthermore, the display circuit of the field sequential display panel includes: a first transistor T1, a second transistor T2, a pre-storage capacitor Cs1, a holding capacitor Cs2 and a pixel capacitor Clc; A first source and drain of the first transistor T1 is coupled to the data signal line Data, a gate of the first transistor T1 is coupled to the row gate signal line Scan, a second source and drain of the first transistor T1 is coupled to one end of the pre-storage capacitor Cs1, and the other end of the pre-storage capacitor Cs1 is coupled to the reference signal line Couple; The second source and drain of the first transistor T1 are coupled to the first source and drain of the second transistor T2, the gate of the second transistor T2 is coupled to the transfer signal line Tran, the second source and drain of the second transistor T2 are coupled to one end of the pixel capacitor Clc and the holding capacitor Cs2, and the other ends of the pixel capacitor Clc and the holding capacitor Cs2 are coupled to the common signal line Com.

[0018] The present invention has the following advantages: After the panel is prepared, it is found during actual use that the current frame pixel voltage of the 2T field sequential display circuit will be affected by the residual charge of the previous frame, so that the actual voltage value is not the preset voltage value, thereby affecting the final target brightness; therefore, the present invention provides a method for field sequential display grayscale brightness correction, which pre-displays the brightness of the panel before it is put into use to further stabilize the picture brightness and optimize the display.

[0019] The present invention first constructs a scheme for obtaining leakage voltage by constructing a leakage current, compares the voltage of the actual pixel capacitor Clc with the data signal voltage, determines the leakage current direction based on the comparison result, and obtains the corresponding first leakage current and second leakage current, ensuring the leakage voltage is accurate to offset the accumulated error and thus achieve dynamic calibration of the pixel voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A diagram showing the steps of the method of the present invention; Figure 2 is a display circuit diagram of a conventional display panel of the present invention; Figure 3 FIG. 4 is a display circuit diagram of the field sequential display panel of the present invention. DETAILED DESCRIPTION

[0021] The present invention will be further described below in conjunction with the accompanying drawings, but the protection scope of the present invention is not limited to the following description.

[0022] It should be noted that the directions or positional relationships indicated by “left”, “right”, etc. are based on the directions or positional relationships shown in the accompanying drawings, or are the directions or positional relationships in which the invented product is usually placed when in use, or are the directions or positional relationships commonly understood by those skilled in the art. Such terms are only used to facilitate the description of the present invention and simplify the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0023] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features and technical solutions therein may be combined with each other.

[0024] Example 1 See Figure 1 The present invention provides a leakage compensation method for a display circuit, which is applied to a display circuit of a conventional display panel. Figure 2As shown, the display circuit includes: a first transistor T1, a storage capacitor Cst and a pixel capacitor Clc; the first source and drain of the first transistor T1 are coupled to the data signal line Data, the gate of the first transistor T1 is coupled to the row gate signal line Scan, the second source and drain of the first transistor T1 are coupled to one end of the storage capacitor Cst, and the other end of the storage capacitor Cst is coupled to the common signal line Com; the second source and drain of the first transistor T1 are also coupled to one end of the pixel capacitor Clc, and the other end of the pixel capacitor Clc is coupled to the common signal line Com.

[0025] In conventional display current, when a pixel is charged and the gate of the first transistor T1 is closed, the pixel voltage is inaccurate due to leakage in the subthreshold region of the transistor during the frame display. A method for leakage compensation of a display circuit is provided.

[0026] S1. Obtain the display pixel voltage of the current frame and the data signal voltage of the next frame.

[0027] S2. Calculate the leakage voltage of the current frame based on the pixel voltage and the data signal voltage.

[0028] S21: When the data signal voltage is less than the display pixel voltage, the leakage current flows out of the pixel voltage. At this time, the first leakage current of the conventional display panel is generated based on the gate control voltage, threshold voltage and thermal voltage of the first transistor T1. ; The first leakage current of the conventional panel for: ; in, is the reference current of the first transistor T1, is the gate control voltage of the first transistor T1, is the threshold voltage of the first transistor T1, is the thermal voltage of the first transistor T1, is the data signal voltage of the next frame.

[0029] S22: When the data signal voltage is greater than the display pixel voltage, the leakage current flows into the pixel voltage. At this time, a second leakage current of a conventional display panel is generated based on the gate control voltage, threshold voltage, thermal voltage and feed-through voltage of the first transistor T1. ; The second leakage current of the conventional display panel for: ; in, To display the pixel voltage, is the feed-through voltage.

[0030] S23: Generate a leakage voltage of a current frame based on the first leakage current / the second leakage current.

[0031] S231: First leakage current based on a conventional display panel The negative leakage component voltage is calculated based on the row charging time. The formula for calculating the negative leakage component voltage is configured as: ; in, For the row charging time, is the capacitance value of the storage capacitor Cst.

[0032] S232: Second leakage current based on a conventional display panel The forward leakage component voltage is generated by the row charging time, and the forward leakage component voltage calculation formula is configured as: .

[0033] S233, generating a leakage voltage of the current frame based on the positive / negative leakage component voltage; The leakage voltage formula is configured as: ; in, , is the directional coefficient, satisfying: = -1 and = 0 (data signal voltage < Display pixel voltage ); = 0 and = 1 (data signal voltage > Display pixel voltage ); is the negative leakage component voltage, is the forward leakage component voltage, and m is the number of rows in the display circuit.

[0034] S3, generating a compensation data signal voltage corresponding to the pixel voltage of the current frame based on the leakage voltage; ,Right now ; Where ΔV is the leakage voltage of all rows.

[0035] S4. Input the compensation data signal voltage to the display circuit.

[0036] The present invention solves the capacitor leakage problem caused by transistors by generating a first leakage current / a second leakage current to obtain a corresponding leakage voltage. By comparing the displayed pixel voltage with the data signal voltage of the next frame, the direction of charge flow in the pixel capacitor Clc when the next frame is written, that is, the leakage current direction, is determined. The directional coefficients bi and ci are dynamically assigned to ensure that the leakage voltage ΔV accurately offsets the accumulated error, thereby achieving dynamic pixel voltage calibration.

[0037] Example 2 The present invention provides a method for compensating leakage of a display circuit, which is applied to a display circuit of a field sequential display panel. The display circuit of the field sequential display panel is as follows: Figure 3 As shown, the display circuit includes: a first transistor T1, a second transistor T2, a pre-storage capacitor Cs1, a holding capacitor Cs2 and a pixel capacitor Clc; the first source and drain of the first transistor T1 are coupled to the data signal line Data, the gate of the first transistor T1 is coupled to the row gate signal line Scan, the second source and drain of the first transistor T1 are coupled to one end of the pre-storage capacitor Cs1, and the other end of the pre-storage capacitor Cs1 is coupled to the reference signal line Couple; the second source and drain of the first transistor T1 are coupled to the first source and drain of the second transistor T2, the gate of the second transistor T2 is coupled to the transfer signal line Tran, the second source and drain of the second transistor T2 are coupled to one end of the pixel capacitor Clc and the holding capacitor Cs2, and the other ends of the pixel capacitor Clc and the holding capacitor Cs2 are both coupled to the common signal line Com.

[0038] In a field sequential display panel, it is necessary to pre-charge each row before displaying after charge sharing. When the current frame is displayed, the data signal voltage of the next frame is pre-written into the pre-storage capacitor Cs1. At this time, the data signal voltage that affects the leakage in the pixel capacitor Clc is only affected by the data signal voltage charged from the n-1th row to the first row. The leakage time is the leakage time within the frame. The charge flowing away during this leakage time causes the pixel voltage to change. Therefore, a leakage compensation method is proposed.

[0039] S1. Obtain the display pixel voltage of the current frame and the data signal voltage of the next frame.

[0040] S2. Generate the leakage voltage of the current frame based on the pixel voltage and the data signal voltage.

[0041] S21, when the data signal voltage is less than the display pixel voltage, the leakage current flows out of the pixel voltage, and at this time, a first leakage current of the field sequential panel is obtained based on the gate control voltage, threshold voltage and thermal voltage of the transistor; The first leakage current of the field sequential panel is: ; in, is the reference current, is the gate control voltage of the transistor, is the threshold voltage of the transistor, is the thermal voltage, is the data signal voltage of the next frame.

[0042] S22, when the data signal voltage is greater than the display pixel voltage, the leakage current flows into the pixel voltage, and at this time, a second leakage current of the display panel is displayed in a field sequence based on the gate control voltage, threshold voltage, thermal voltage and feed-through voltage of the transistor; The second leakage current of the field sequential display panel is: ; in, To display the pixel voltage, is the feed-through voltage.

[0043] S23: Obtain a leakage voltage of a current frame based on the first leakage current / the second leakage current.

[0044] S231, when the display circuit is writing in a positive frame, generating a leakage voltage of the pixel capacitor Clc of the current frame and a leakage voltage of the pre-storage capacitor Cs1 based on the first leakage current and the leakage time within the frame; The leakage voltage of the pixel capacitor Clc in the positive frame is: ; The leakage voltage of the pre-storage capacitor Cs1 during the positive frame is: ; in, is the leakage time, is the pixel voltage, is the actual pixel voltage, The voltage of the preset pre-storage capacitor Cs1 is the data signal voltage of the current frame. is the actual voltage of the pre-storage capacitor Cs1, is the capacitance value of the pre-storage capacitor Cs1, To maintain the sum of the capacitance values ​​of capacitor Cs2 and pixel capacitor Clc, is the first leakage current of the field sequential display panel.

[0045] S232: When the display circuit is in negative frame writing, the leakage voltage of the pixel capacitor Clc of the current frame and the leakage voltage of the pre-storage capacitor Cs1 are generated based on the second leakage current and the leakage time within the frame: The leakage voltage of the pixel capacitor Clc during the negative frame is: ; The leakage voltage of the pre-storage capacitor Cs1 during the negative frame is: ; in, is the leakage time, is the pixel voltage, is the actual pixel voltage, The voltage of the preset pre-storage capacitor Cs1 is the data signal voltage of the current frame. is the actual voltage of the pre-storage capacitor Cs1, is the capacitance value of the pre-storage capacitor Cs1, To maintain the sum of the capacitance values ​​of capacitor Cs2 and pixel capacitor Clc, is the second leakage current of the field sequential display panel.

[0046] S3, generating a compensation data signal voltage corresponding to the pixel voltage of the current frame based on the charge conservation principle, the leakage voltage of the pixel capacitor Clc of the current frame, and the leakage voltage of the pre-storage capacitor Cs1; When the field sequential display circuit is in the N-1th frame, and the N-1th frame is a positive frame, the voltage equation of the data signal voltage of the Nth frame can be obtained according to the charge conservation principle: ; A compensation data signal voltage corresponding to the leakage voltage of the pixel capacitor Clc of the current frame and the leakage voltage of the pre-storage capacitor Cs1 based on the voltage equation; ; When the field sequential display circuit is in the Nth frame and the Nth frame is a negative frame, according to the charge conservation principle, the voltage equation of the data signal voltage of the Nth frame is: ; A compensation data signal voltage corresponding to the leakage voltage of the pixel capacitor Clc of the current frame and the leakage voltage of the pre-storage capacitor Cs1 based on the voltage equation; ; in, : Data signal voltage of the N-1th frame; : Data signal voltage of the Nth frame; : Display pixel voltage of the N+1th frame; : Display pixel voltage of the Nth frame; : Display pixel voltage of the N-1th frame; : The capacitance ratio of the holding capacitor Cs2 to the pre-storage capacitor Cs1, ; : Capacitance ratio of pixel capacitor Clc to pre-storage capacitor Cs1, ; : coupling voltage; : feed-through voltage; in, , : The turn-on voltage of the second transistor T2; : The off-voltage of the second transistor T2; : Gate-source capacitance of the second transistor T2.

[0047] S4. Input the compensation data signal voltage to the display circuit.

[0048] In field sequential display, the leakage of the pixel voltage in the current frame will affect the charge sharing process of the next frame. The present invention quantifies the leakage voltage by calculating the leakage current, eliminating the voltage offset between frames. By correcting the voltage deviation between frames in real time through leakage compensation of the second transistor T2, a dynamic leakage voltage is obtained to ensure color accuracy during color sequence switching. In addition, the present invention calculates the leakage impact of alternating polarity driving of positive and negative frames, and the difference in leakage voltage under different leakage directions. The voltage stress is balanced by different compensation data signal voltages in positive and negative frames, reducing liquid crystal ghosting.

[0049] The above embodiments merely represent preferred implementations, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art will be able to make various modifications and improvements without departing from the present invention, and these modifications and improvements are all within the scope of protection of the present invention.

Claims

1. A leakage compensation method for a display circuit, characterized in that: include: Obtaining the display pixel voltage of the current frame and the data signal voltage of the next frame; Calculating the leakage voltage of the current frame based on the display pixel voltage and the data signal voltage; generating a compensation data signal voltage corresponding to a pixel voltage of a current frame based on the leakage voltage; The compensated data signal voltage is input to the display circuit.

2. The leakage compensation method for a display circuit according to claim 1, wherein: The calculating the leakage voltage of the current frame based on the display pixel voltage and the data signal voltage includes: When the data signal voltage is less than the display pixel voltage, the leakage current flows out of the pixel voltage, and a first leakage current is generated based on the gate control voltage, threshold voltage and thermal voltage of the transistor; When the data signal voltage is equal to the display pixel voltage, the transistor does not leak; When the data signal voltage is greater than the display pixel voltage, the leakage current flows into the pixel voltage, and a second leakage current is generated based on the gate control voltage, threshold voltage, thermal voltage and feed-through voltage of the transistor; A leakage voltage of a current frame is generated based on the first leakage current / the second leakage current.

3. The leakage compensation method for a display circuit according to claim 2, wherein: When applied to a display circuit of a conventional display panel, generating a leakage voltage of a current frame based on the first leakage current / the second leakage current includes: generating a negative leakage component voltage based on the first leakage current and the row charging time; generating a forward leakage component voltage based on the second leakage current and the row charging time; The leakage voltage of the current frame is generated based on the positive / negative leakage component voltage.

4. The method for compensating leakage of a display circuit according to claim 3, wherein: When applied to a display circuit of a conventional display panel, generating a compensation data signal voltage corresponding to a pixel voltage of a current frame based on the leakage voltage includes: A compensated data signal voltage is generated based on the leakage voltage and a data signal voltage of a current frame.

5. The leakage compensation method for a display circuit according to claim 2, wherein: When applied to a display circuit of a field sequential display panel, generating a leakage voltage of a current frame based on the first leakage current / the second leakage current includes: When the display circuit is writing in a positive frame, the leakage voltage of the pixel capacitor Clc of the current frame and the leakage voltage of the pre-storage capacitor Cs1 are generated based on the first leakage current and the leakage time within the frame; When the display circuit is in negative frame writing, the leakage voltage of the current frame pixel capacitor Clc and the leakage voltage of the pre-storage capacitor Cs1 are generated based on the second leakage current and the intra-frame leakage time.

6. The method for compensating leakage of a display circuit according to claim 5, wherein: Generating a compensation data signal voltage corresponding to a pixel voltage of a current frame based on the leakage voltage includes: The compensation data signal voltage corresponding to the target pixel voltage of the current frame is generated based on the charge conservation principle, the leakage voltage of the pixel capacitor of the current frame and the leakage voltage of the pre-storage capacitor.

7. The leakage compensation method for a display circuit according to claim 3, wherein: The display circuit of the conventional display panel includes: a first transistor T1, a storage capacitor Cst and a pixel capacitor Clc; A first source and drain of the first transistor T1 is coupled to the data signal line Data, a gate of the first transistor T1 is coupled to the row gate signal line Scan, a second source and drain of the first transistor T1 is coupled to one end of the storage capacitor Cst, and the other end of the storage capacitor Cst is coupled to the common signal line Com; The second source and drain of the first transistor T1 are further coupled to one end of the pixel capacitor Clc, and the other end of the pixel capacitor Clc is coupled to the common signal line Com.

8. The leakage compensation method for a display circuit according to claim 5, characterized in that: The display circuit of the field sequential display panel includes: a first transistor T1, a second transistor T2, a pre-storage capacitor Cs1, a holding capacitor Cs2 and a pixel capacitor Clc; A first source and drain of the first transistor T1 is coupled to the data signal line Data, a gate of the first transistor T1 is coupled to the row gate signal line Scan, a second source and drain of the first transistor T1 is coupled to one end of the pre-storage capacitor Cs1, and the other end of the pre-storage capacitor Cs1 is coupled to the reference signal line Couple; The second source and drain of the first transistor T1 are coupled to the first source and drain of the second transistor T2, the gate of the second transistor T2 is coupled to the transfer signal line Tran, the second source and drain of the second transistor T2 are coupled to one end of the pixel capacitor Clc and the holding capacitor Cs2, and the other ends of the pixel capacitor Clc and the holding capacitor Cs2 are coupled to the common signal line Com.

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