Write clock bias generator and memory device including same

Abstract

A write clock bias generator for providing a write clock bias to a first buffer and a memory device including the same are provided. The write clock bias generator includes: a voltage regulator receiving a reference voltage and outputting a feedback voltage; a resistor string connected between a first node from which a feedback voltage is output and a second node; a multiplexer performing a switching operation on the resistor string and outputting a write clock bias; and a compensation circuit connected to the second node. The compensation circuit includes a first string and a second string. The first string includes a first transistor including a drain electrode and a gate electrode connected to the second node, and the second string includes a second transistor including a drain electrode connected to the second node and driven based on a feedback voltage, and a third transistor including a drain electrode and a gate electrode connected to a source electrode of the second transistor.

Description

[0001] This application is based on and claims the benefit of Korean Patent Application No. 10-2024-0030212 filed on February 29, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The disclosed embodiments described herein relate to electronic circuits, and more particularly, to a write clock bias generator capable of compensating for a change in a threshold voltage of a transistor due to a change in temperature and a memory device including the same. Background Art

[0003] With the recent trend toward high-performance and high-capacity memory devices, such as dynamic random access memory (DRAM), the operating frequency of these devices is increasing. Furthermore, to meet the low-power requirements of mobile devices, standards are being adopted in which the frequency of the clock signal CK used to transmit commands and addresses to the memory device differs from the frequency of the write clock WCK required for write operations.

[0004] The above memory device includes a write clock (WCK) buffer for receiving a write clock WCK, and a WCK bias generator for supplying a bias voltage to the WCK buffer. The WCK buffer includes elements such as transistors, and the threshold voltage of the transistors varies with temperature. To address the above issues, various techniques are employed to compensate for temperature-dependent changes in threshold voltage.

[0005] For example, calibration for locking the WCK bias is performed during initialization of the memory device. Calibration is performed only during initialization. That is, after initialization, calibration is not performed during normal operation of the memory device. Furthermore, existing techniques for compensating the WCK bias in real time after initialization cannot adequately track changes in threshold voltage. Therefore, in order to stably receive the write clock WCK and improve the performance of the memory device, it is important to compensate for changes in threshold voltage due to temperature changes. Summary of the Invention

[0006] The disclosed embodiments provide a write clock bias generator capable of compensating for a change in the threshold voltage of a transistor due to a change in temperature and a memory device including the same.

[0007] According to one aspect of the disclosure, a write clock bias generator is provided, which is used to provide a write clock bias to a first buffer, and the write clock bias generator includes: a voltage regulator, configured to receive a reference voltage and output a feedback voltage; a resistor string, including a first end connected to a first node and a second end connected to a second node, and the feedback voltage is output at the first node; a multiplexer, configured to perform a switching operation corresponding to the resistor string and output a write clock bias based on the switching operation; and a compensation circuit, connected to the second node, the compensation circuit including: a first string, including a first transistor, the first transistor including a first drain electrode and a first gate electrode, the first drain electrode and the first gate electrode being connected to the second node; and a second string, including a second transistor and a third transistor, the second transistor including a second drain electrode connected to the second node, the third transistor including a third drain electrode and a third gate electrode, the third drain electrode and the third gate electrode being connected to the second source electrode of the second transistor, and the second transistor being driven based on the feedback voltage.

[0008] According to another aspect of the disclosure, a memory device is provided, comprising: a buffer die configured to communicate with a memory controller through a plurality of channels; and a plurality of core dies disposed on the buffer die, each of the plurality of core dies comprising a memory cell array corresponding to at least one of the plurality of channels, wherein the buffer die comprises: a command / address receiver configured to receive a command and an address based on a clock signal received from at least one of the plurality of channels; a write clock buffer configured to receive a write clock through at least one of the plurality of channels; and a write clock bias generator configured to provide a write clock bias to the write clock buffer, the write clock bias generator comprising a voltage regulator configured to output a feedback voltage, a resistor string and a multiplexer configured to output the write clock bias based on the feedback voltage, a first string connected to the resistor string and comprising a first transistor, and a second string connected to the resistor string and comprising a third transistor and a second transistor driven based on the feedback voltage, wherein the first transistor and the third transistor are diode-connected transistors.

[0009] According to another aspect of the disclosure, a write clock bias generator is provided, comprising: a voltage regulator configured to receive a reference voltage and output a feedback voltage; a voltage divider circuit configured to output a write clock bias based on the feedback voltage, the write clock bias varying based on temperature changes; and a compensation circuit connected to the voltage divider circuit, the compensation circuit comprising a first string connected to the voltage divider circuit and including a first transistor, and a second string connected to the voltage divider circuit and including a third transistor and a second transistor driven based on the feedback voltage, wherein the first transistor and the third transistor are diode-connected transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects and features of the disclosure will become apparent by describing in detail embodiments of the disclosure with reference to the accompanying drawings.

[0011] Figure 1 is a block diagram illustrating a memory system according to a disclosed embodiment.

[0012] Figure 2 is a flowchart illustrating an operating method of a memory system according to a disclosed embodiment.

[0013] Figure 3 It shows Figure 1 Block diagram of the interface circuit.

[0014] Figure 4 It shows Figure 1 A block diagram of a memory device.

[0015] Figure 5 It shows Figure 4 Circuit diagram of the configuration of the write clock (WCK) bias generator.

[0016] Figure 6 It shows Figure 5 Circuit diagram of the resistor string and multiplexer configuration.

[0017] Figure 7 is shown and by Figure 5 A diagram of the waveform of the signal associated with the calibration performed by the WCK bias generator.

[0018] Figure 8 It shows Figure 5 Circuit diagram of the compensation circuit.

[0019] Figure 9 It shows Figure 5 Circuit diagram of the compensation circuit.

[0020] Figure 10A is a graph comparing voltage levels of WCK bias formed by compensation performed at high temperature.

[0021] Figure 10B is a graph comparing voltage levels of WCK bias formed by compensation performed at a low temperature.

[0022] Figure 11 It shows Figure 5 Circuit diagram of the compensation circuit.

[0023] Figure 12 It shows Figure 5 Circuit diagram of the compensation circuit.

[0024] Figure 13 It shows Figure 5 Circuit diagram of the compensation circuit.

[0025] Figure 14 It shows Figure 4 Circuit diagram of the WCK bias generator configuration.

[0026] Figure 15 It shows Figure 14 Circuit diagram of the resistor string and multiplexer configuration.

[0027] Figure 16 is a flow chart illustrating a method of operation of a WCK bias generator according to a disclosed embodiment.

[0028] Figure 17 is a diagram illustrating a stacked memory device according to a disclosed embodiment.

[0029] Figure 18 is a diagram illustrating a semiconductor package according to a disclosed embodiment.

[0030] Figure 19 are diagrams illustrating implementation examples of semiconductor packages according to disclosed embodiments.

[0031] Figure 20 is a diagram illustrating a semiconductor package according to another disclosed embodiment.

[0032] Figure 21 is a diagram illustrating a system to which a memory device according to an embodiment of the disclosure is applied. DETAILED DESCRIPTION

[0033] Hereinafter, the disclosed embodiments will be described in detail and clearly to the extent that a person having ordinary skill in the art can easily carry out the disclosure.

[0034] The embodiments herein and their various features and advantageous details are explained more fully with reference to the non-limiting embodiments shown in the accompanying drawings and described in detail in the following description. Descriptions of well-known components and processing techniques are omitted so as not to unnecessarily obscure the embodiments herein. The examples used herein are intended only to facilitate understanding of the manner in which the embodiments herein may be practiced and to further enable those skilled in the art to practice the embodiments herein. Therefore, the examples should not be construed as limiting the scope of the embodiments herein.

[0035] For purposes of interpreting this specification, the definitions (as defined herein) will apply, and whenever appropriate, terms used in the singular will also include the plural, and vice versa. It will be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. Unless otherwise specified, the terms "including," "having," and "comprising" are to be construed as open-ended terms.

[0036] The words / phrases "exemplary," "example," "illustrative," "in one instance," "etc," "such as," "et al," "the like," "for example," and "i.e." are used herein merely to mean "serving as an example, instance, or illustration." Any embodiment or implementation of the subject matter described herein using the words / phrases "exemplary," "example," "illustrative," "in one instance," "etc," "such as," "et al," "the like," "for example," and "i.e." are not necessarily to be construed as preferred or advantageous over other embodiments.

[0037] The embodiments herein may be described and illustrated in terms of blocks that perform one or more of the described functions. These blocks, which may be referred to herein as managers, units, modules, hardware components, etc., are physically implemented using analog and / or digital circuitry (such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hard-wired circuitry, etc.) and may be selectively driven by firmware. For example, the circuitry may be implemented in one or more semiconductor chips or on a substrate support (such as a printed circuit board). The circuitry comprising a block may be implemented using dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware for performing some of the block's functions and a processor for performing other functions of the block. Each block of the embodiments may be physically divided into two or more interacting and discrete blocks without departing from the scope of the disclosure. Similarly, the blocks of the embodiments may be physically combined into more complex blocks without departing from the scope of the disclosure.

[0038] It should be noted that the elements in the accompanying drawings are shown for the purposes of this specification and ease of understanding and may not necessarily be drawn to scale. For example, a flow chart / sequence diagram illustrates a method in terms of operations required to understand aspects of the disclosed embodiments. Furthermore, in terms of the construction of the device, one or more components of the device may have been represented in the accompanying drawings by conventional symbols, and the accompanying drawings may only show those specific details relevant to understanding the present embodiments so as not to obscure the drawings due to details that would be readily apparent to one of ordinary skill in the art having the benefit of the description herein. Furthermore, in terms of the system, one or more components / modules comprising the system may have been represented in the accompanying drawings by conventional symbols, and the accompanying drawings may only show those specific details relevant to understanding the present embodiments so as not to obscure the drawings due to details that would be readily apparent to one of ordinary skill in the art having the benefit of the description herein.

[0039] The accompanying drawings are used to facilitate easy understanding of various technical features, and it should be understood that the embodiments presented herein are not limited by the accompanying drawings. Therefore, the disclosure should be interpreted as extending to any modifications, equivalents, and alternatives other than those specifically described in the drawings and corresponding descriptions. The use of words (such as first, second, third, etc.) to describe components / elements / operations is for the purpose of this specification and should not be interpreted as sequential ordering / placement / occurrence unless otherwise specified.

[0040] Figure 1 is a block diagram illustrating a memory system according to an embodiment of the disclosure. Figure 1 , the memory system 10 may include a memory controller 100 and a memory device 200. The memory controller 100 may control one or more operations of the memory device 200. For example, the memory controller 100 may control all operations of the memory device 200. For example, the memory controller 100 may control the memory device 200 to output data from the memory device 200 or store data in the memory device 200. For example, the memory controller 100 may be implemented as part of a system on a chip (SoC), but the disclosure is not limited thereto. Therefore, the memory controller 100 may be implemented in various other ways.

[0041] The memory controller 100 may include an interface (I / F) circuit 110. The memory controller 100 may transmit various signals to the memory device 200 through the interface circuit 110, and may receive various signals from the memory device 200 through the interface circuit 110. For example, Figure 1 As shown in FIG, the memory controller 100 may transmit a clock signal CK, a command / address signal C / A, a write clock WCK, and a data signal DQ to the memory device 200. In addition, the memory controller 100 may receive a read data strobe signal RDQS and a data signal DQ from the memory device 200. For example, one or more lines between the memory controller 100 and the memory device 200 may be bidirectional lines. For example, a line for transmitting the data signal DQ may be a bidirectional line.

[0042] The memory device 200 may operate under the control of the memory controller 100. For example, the memory device 200 may output stored data under the control of the memory controller 100 or may store data provided from the memory controller 100.

[0043] The memory device 200 may include an interface circuit 210 and a memory cell array 230. The memory device 200 may transmit various signals to the memory controller 100 through the interface circuit 210, and may receive various signals from the memory controller 100 through the interface circuit 210. For example, the memory device 200 may transmit a read data strobe signal RDQS and a data signal DQ to the memory controller 100 through the interface circuit 210, and may receive a clock signal CK, a command / address signal C / A, a write clock signal WCK, and a data signal DQ from the memory controller 100 through the interface circuit 210. The interface circuit 210 may generate a control signal iCTRL based on signals provided from the memory controller 100. For example, the control signal iCTRL may be an internal signal generated in the memory device 200 for accessing the memory cell array 230. For example, based on the control signal iCTRL, the memory cell array 230 may store data or output the stored data.

[0044] The memory cell array 230 may include a plurality of memory cells. For example, the memory cells may be dynamic random access memory (DRAM) cells. In this case, the interface circuit 110 and the interface circuit 210 may communicate with each other based on one of the standards such as double data rate (DDR), low power double data rate (LPDDR), graphics double data rate (GDDR), wide input / output (I / O), high bandwidth memory (HBM), hybrid memory cube (HMC), etc.

[0045] The interface circuit 110 may generate a clock signal CK and transmit the clock signal CK to the memory device 200. The clock signal CK may be a differential signal. The clock signal CK may be a signal that periodically switches between a high level and a low level. The interface circuit 110 may transmit a command / address signal C / A to the memory device 200 based on the switching timing of the clock signal CK.

[0046] The interface circuit 110 may generate a write clock WCK and transmit the write clock WCK to the memory device 200. The write clock WCK may be a differential signal. The interface circuit 110 may generate a write clock WCK that periodically switches between a high level and a low level. The write clock WCK may be a clock used to perform a write operation and / or a read operation on the memory device 200. The interface circuit 110 may transmit the data signal DQ to the memory device 200 based on the switching timing of the write clock WCK.

[0047] The interface circuit 110 may receive a read data strobe signal RDQS from the memory device 200. The read data strobe signal RDQS may be a differential signal. The interface circuit 110 may receive a data signal DQ from the memory device 200 and latch the received data signal DQ based on the timing of the switching of the read data strobe signal RDQS (which may be referred to as the "switching timing"). Therefore, the interface circuit 110 may receive the data "DATA" included in the data signal DQ.

[0048] The interface circuit 210 may receive a clock signal CK from the memory controller 100. The interface circuit 210 may also receive a command / address signal C / A from the memory controller 100 and may latch the command / address signal C / A based on a switching timing of the clock signal CK. For example, the switching timing may include, but is not limited to, a rising edge of the clock signal CK and / or a falling edge of the clock signal CK. Thus, the interface circuit 210 may obtain a command or address included in the command / address signal C / A.

[0049] although Figure 1 The example in which the command and address are transmitted from the memory controller 100 to the memory device 200 using the same input / output channel is shown, but the disclosure is not limited thereto. Therefore, according to another embodiment, the command and address may be transmitted from the memory controller 100 to the memory device 200 using different input / output channels.

[0050] The interface circuit 210 may receive a write clock WCK from the memory controller 100. The interface circuit 210 may receive a data signal DQ and latch the data signal DQ based on the switching timing of the write clock WCK. For example, the switching timing may include, but is not limited to, a rising edge of the write clock WCK and / or a falling edge of the write clock WCK. Thus, the interface circuit 210 may obtain the data "DATA" included in the data signal DQ.

[0051] The interface circuit 210 may generate a read data strobe signal RDQS and transmit the read data strobe signal RDQS to the memory controller 100. The read data strobe signal RDQS may be a differential signal. The interface circuit 210 may generate the read data strobe signal RDQS that periodically switches between a high level and a low level during a read operation of the memory device 200. In one embodiment, the interface circuit 210 may generate the read data strobe signal RDQS based on a write clock WCK received from the memory controller 100. The interface circuit 210 may transmit the data signal DQ to the memory controller 100 based on the switching timing of the read data strobe signal RDQS.

[0052] In one embodiment, the frequency of each of the write clock WCK and the read data strobe signal RDQS may be twice as high as the frequency of the clock signal CK. In the example case where the data signal DQ is transmitted based on the signals WCK and RDQS, the memory controller 100 and the memory device 200 can send / receive data at high speed.

[0053] Figure 2 is a flowchart illustrating an operating method of a memory system according to a disclosed embodiment.

[0054] Reference Figure 1 and Figure 2 In operation S11, the method may include performing initialization. For example, the memory system 10 may perform initialization. In the example case where the memory system 10 is powered on, the memory controller 100 and the memory device 200 may perform initialization according to a given scheme. During initialization, the memory controller 100 may provide a power supply voltage to the memory device 200, may perform various initial setup operations, and may read necessary information from the memory device 200 or set necessary information to the memory device 200.

[0055] In operation S12, the method may include performing a write clock (WCK) bias calibration. For example, the memory system 10 may perform the WCK bias calibration. In one embodiment, the WCK bias calibration may include providing a bias voltage to a buffer of the interface circuit 210 (hereinafter referred to as a "WCK buffer" or a "first buffer") to stably receive the write clock WCK from the memory controller 100. However, the disclosure is not limited thereto, and therefore, the WCK bias calibration may be performed in another manner. The disclosed interface circuit 210 may detect a change in the threshold voltage of a transistor of the WCK buffer due to a temperature change, and may uniformly maintain the current of the WCK buffer. For example, even if a change is detected in the threshold voltage of the transistor of the WCK buffer, the WCK buffer may keep the current constant.

[0056] In operation S13, the method may include performing command / address training. For example, the memory system 10 may perform a command / address training operation. For example, the memory controller 100 and the memory device 200 may perform a command / address training operation so that the command / address signals C / A can be latched at a desired timing based on the clock signal CK.

[0057] In operation S14, the method may include performing write clock to clock signal (WCK2CK) alignment training. For example, the memory system 10 may perform a write clock to clock signal (WCK2CK) alignment training operation. For example, the memory device 200 may receive a clock signal CK and a write clock WCK from the memory controller 100 and adjust the timing of transmitting the write clock WCK so that the clock signal CK and the write clock WCK are aligned. For example, the frequency of the write clock WCK may be "N" times the frequency of the clock signal CK (N is a natural number greater than 0).

[0058] In operation S15, the method may include performing write clock (WCK) duty cycle training. For example, the memory system 10 may perform the write clock (WCK) duty cycle training operation. For example, the interface circuit 110 may perform the duty cycle training using a duty cycle corrector (DDC) or a duty cycle adjuster (DCA). According to embodiments, the WCK duty cycle training may include delaying a read data strobe signal RDQS received from the memory device 200. For example, the interface circuit 110 may delay the read data strobe signal RDQS received from the memory device 200. For example, the interface circuit 110 may delay the read data strobe signal RDQS using components such as logic gates.

[0059] In operation S16, the method may include performing read gate training. For example, the memory system 10 may perform a read gate training operation. For example, the interface circuit 110 may determine when to observe the read DQ and read data strobe signals RDQS and may control the timing for receiving the read DQ and read data strobe signals RDQS from the memory device 200. To this end, the memory controller 100 may include a component for controlling the timing for receiving the read data strobe signal RDQS. This component may include, but is not limited to, a logic gate or a delay circuit.

[0060] In operation S17, the method may include performing first-in, first-out (FIFO) training. For example, the memory system 10 may perform a FIFO training operation. For example, due to the design (or structure) of the memory device 200 and / or the design (or structure) of the package including the memory controller 100 and the memory device 200, the delay of the data signal DQ may differ from the delay of the write clock WCK. FIFO training may be used to correct for delays caused by differences in the paths of the write clock WCK and the data signal DQ. FIFO training may include read FIFO training and write FIFO training.

[0061] In one embodiment, during read FIFO training, memory controller 100 may control the timing for receiving read DQ and / or read data strobe signal RDQS by delaying the read DQ and / or read data strobe signal RDQS received from memory device 200. During write FIFO training, memory controller 100 may control the timing for transmitting write DQ and write clock WCK by delaying the write DQ to be transmitted to memory device 200. After FIFO training is completed, memory system 10 may perform normal operations.

[0062] Figure 3 is a block diagram showing an interface circuit of a memory controller. For example, the interface circuit may be Figure 1 The interface circuit 110. Figure 3 The interface circuit 110 may include a phase-locked loop (PLL) 111, a clock divider 112, a phase controller 113, a command / address signal (C / A) transmitter (or referred to as a command / address transmitter) 114, a clock transmitter 115, a write clock (WCK) transmitter 116, a read data strobe signal (RDQS) receiver 117, and a data transceiver 118. According to one embodiment, Figure 3 One or more of the components shown in FIG. 5 may be implemented as a circuit.

[0063] The phase-locked loop 111 may generate a first internal clock signal ICS1 .

[0064] The clock divider 112 can divide the first internal clock signal ICS1 and generate a first divided internal clock signal dICS1 and a second divided internal clock signal dICS2. For example, the first divided internal clock signal dICS1 and the second divided internal clock signal dICS2 can have different phases. The first divided internal clock signal dICS1 can be associated with the clock signal CK to be transmitted to the memory device 200, and the second divided internal clock signal dICS2 can be associated with the command CMD and address ADD to be transmitted to the memory device 200. For example, the clock signal CK can be generated based on the first divided internal clock signal dICS1, and the command / address signal C / A can be generated based on the second divided internal clock signal dICS2 as well as the command CMD and / or address ADD. The clock divider 112 can be referred to as an internal clock divider.

[0065] The phase controller 113 may generate a second internal clock signal ICS2 based on the first internal clock signal ICS1. The second internal clock signal ICS2 may have a different phase from the first internal clock signal ICS1. For example, the first internal clock signal ICS1 and the second internal clock signal ICS2 may have a phase difference of 90 degrees, but the disclosure is not limited thereto.

[0066] The command / address transmitter 114 may transmit a command CMD and / or an address ADD based on the second divided internal clock signal dICS2 . Therefore, the command / address transmitter 114 may transmit a command / address signal C / A including the command CMD and / or the address ADD to the memory device 200 .

[0067] The clock transmitter 115 may transmit the first divided internal clock signal dICS1 as the clock signal CK to the memory device 200. For example, the clock transmitter 115 may generate the clock signal CK based on the first divided internal clock signal dICS1. For example, the clock transmitter 115 may generate a plurality of clocks (e.g., CK_t and CK_c) in a differential scheme based on the first divided internal clock signal dICS1, and may transmit the clocks CK_t and CK_c to the memory device 200.

[0068] The write clock transmitter 116 may transmit the first internal clock signal ICS1 as the write clock WCK to the memory device 200. For example, the write clock transmitter 116 may generate the write clock signal based on the first internal clock signal ICS1. For example, the write clock transmitter 116 may generate a plurality of write clocks (e.g., WCK_t and WCK_c) using a differential scheme based on the first internal clock signal ICS1, and may transmit the write clocks WCK_t and WCK_c to the memory device 200. For example, the frequency of the write clock WCK may be twice the frequency of the clock signal CK, but the disclosure is not limited thereto. For example, the frequency of the write clock WCK may be different from the frequency of the clock signal CK.

[0069] The read data strobe signal receiver 117 may receive a read data strobe signal RDQS from the memory device 200. For example, a data signal DQ corresponding to read data from the memory device 200 may be received based on the read data strobe signal RDQS. For example, the read data strobe signal RDQS may be used to receive a data signal DQ as read data from the memory device 200. The read data strobe signal RDQS may be a signal based on the phase division of the clock signal CK by the memory device 200.

[0070] The data transceiver 118 may transmit data “DATA” to the memory device 200 based on the second internal clock signal ICS2, or may receive data “DATA” from the memory device 200 based on the second internal clock signal ICS2. Therefore, the data transceiver 118 may transmit a data signal DQ including the data “DATA” to the memory device 200, or may receive a data signal DQ including the data “DATA” from the memory device 200.

[0071] As described above, the clock signal CK and the write clock WCK may be generated by one phase-locked loop 111. This may mean that the operating current of the memory controller 100 is reduced.

[0072] Figure 4 It shows Figure 1 Block diagram of a memory device. Figure 4 , the memory device 200 may include a command / address signal (C / A) receiver 211, a control logic circuit 212, a WCK buffer 213, a phase splitter 214, a read data strobe signal (RDQS) transmitter 215, a data transceiver 216, and a memory cell array 230. According to an embodiment, the C / A receiver 211, the control logic circuit 212, the phase splitter 214, the RDQS transmitter 215, and the data transceiver 216 may be included in Figure 1 According to the embodiment, Figure 4 One or more of the components shown in FIG. 5 may be implemented as a circuit.

[0073] The command / address signal receiver 211 can receive a command CMD by latching the command / address signal C / A based on the clock signal CK. The received command CMD can be provided to the control logic circuit 212. The command / address signal receiver 211 can receive an address by latching the command / address signal C / A based on the clock signal CK. The received address can be provided to an address register for decoding. The address register can be provided inside or outside the control logic circuit 212.

[0074] The control logic circuit 212 may decode the received command CMD and, based on the decoded command CMD, generate one or more control signals for controlling the remaining components of the memory device 200. For example, the control logic circuit 212 may generate a control signal iCTRL for storing data "DATA" in the memory cell array 230 or outputting data "DATA" from the memory cell array 230. For example, the control logic circuit 212 may decode an activate command, a read command, a write command, a precharge command, a mode register write command, a multi-purpose command (MPC), and the like. However, the present disclosure is not limited thereto, and therefore, the control logic circuit 212 may be configured to decode other commands or perform other operations.

[0075] The WCK buffer 213 may receive the write clock WCK. For example, the write clock WCK may include differential signals WCK_t and WCK_c. For example, the WCK buffer 213 may receive the write clock WCK and provide the write clock WCK to the phase splitter 214. The WCK buffer 213 may operate based on a WCK bias (e.g., a bias voltage).

[0076] According to an embodiment, memory device 200 may include a WCK bias generator 240. WCK bias generator 240 may generate a bias voltage required to operate WCK buffer 213. In one embodiment, WCK bias generator 240 may be configured to generate the bias voltage using a voltage regulator. Therefore, compared to a replica-type bias generator, WCK bias generator 240 may generate a bias voltage with relatively low power consumption and provide a high power supply rejection ratio (PSRR).

[0077] The WCK bias generator 240 can detect a change in the threshold voltage of the transistors constituting the WCK buffer 213 and can perform calibration to compensate for the detected change. For example, the calibration of the WCK bias generator 240 can be performed once during the initialization of the memory device 200. Therefore, the WCK bias generator 240 can include a separate compensation circuit for compensating for the change in the threshold voltage of the transistors constituting the WCK buffer 213 in real time after the initialization of the memory device 200. For example, the WCK bias generator 240 can include an N-channel metal oxide semiconductor (NMOS) transistor connected to the lower end of the voltage regulator. Figure 5 The configuration and operation of the individual compensation circuits are described in detail in the following figures.

[0078] The phase splitter 214 may generate a plurality of internal write clocks WCK0, WCK90, WCK180, and WCK270 based on the write clock WCK. For example, the phase splitter 214 may generate the internal write clocks WCK0, WCK90, WCK180, and WCK270 that are switched based on the switching of the write clock WCK. The phase splitter 214 may divide the frequency of the write clock WCK and may generate the internal write clocks WCK0, WCK90, WCK180, and WCK270 with different phases. For example, the phase splitter 214 may halve the frequency of the write clock WCK and may generate the internal write clocks WCK0, WCK90, WCK180, and WCK270 with different phases. In this case, the phases of the internal write clocks WCK0, WCK90, WCK180, and WCK270 may be 0 degrees, 90 degrees, 180 degrees, and 270 degrees, respectively.

[0079] The RDQS transmitter 215 may generate a read data strobe signal RDQS based on the internal write clocks WCK0, WCK90, WCK180, and WCK270, and may transmit the read data strobe signal RDQS to the memory controller 100. For example, the RDQS transmitter 215 may transmit the read data strobe signal RDQS based on the rising edge and / or falling edge of at least one of the internal write clocks WCK0, WCK90, WCK180, and WCK270. The read data strobe signal RDQS may include a differential signal (e.g., RDQS_t and RDQS_c). The frequency of the read data strobe signal RDQS transmitted to the memory controller 100 may be the same as (or equivalent to) the frequency of the write clock WCK. However, the present disclosure is not limited thereto, and therefore, the frequency of the read data strobe signal RDQS may be different from the frequency of the write clock WCK.

[0080] The data transceiver 216 may transmit / receive a data signal DQ including data “DATA” based on the internal write clocks WCK0 , WCK90 , WCK180 , and WCK270 .

[0081] During a write operation, the data transceiver 216 can receive data "DATA" by latching the data signal DQ based on the internal write clocks WCK0, WCK90, WCK180, and WCK270. For example, the data transceiver 216 can latch the data signal DQ received from the memory controller 100 based on the rising edge and / or falling edge of the internal write clocks WCK0, WCK90, WCK180, and WCK270. The received data "DATA" can be transferred to and stored in the memory cell array 230. In the example case where the data "DATA" is transferred to the memory cell array 230, the data "DATA" can be transferred based on the switching timing of the clock signal CK. That is, when the data "DATA" is transferred to the memory cell array 230, a domain change can be made from the write clock (WCK) domain to the clock signal (CK) domain.

[0082] During a read operation, the data transceiver 216 may transmit a data signal DQ including data "DATA" to the memory controller 100 based on the internal write clocks WCK0, WCK90, WCK180, and WCK270. The data "DATA" may be read from the memory cell array 230. For example, the data transceiver 216 may transmit the data "DATA" based on the rising edge and / or falling edge of at least one of the internal write clocks WCK0, WCK90, WCK180, and WCK270. Therefore, the data "DATA" may be transmitted to the memory controller 100 in a state aligned with the switching timing of the read data strobe signal RDQS. In the example case where the data "DATA" is read from the memory cell array 230, the data "DATA" may be read based on the switching timing of the clock signal CK. The data transceiver 216 may align the read data "DATA" with the switching timing of the read data strobe signal RDQS to transmit the read data "DATA" to the memory controller 100. That is, in case data “DATA” is transmitted to the memory controller 100 , a domain change may be made from a clock signal (CK) domain to a read data strobe signal (RDQS) domain (eg, a write clock (WCK) domain).

[0083] As described above, the memory device 200 can generate the read data strobe signal RDQS and the data signal DQ based on the internal write clocks WCK0, WCK90, WCK180, and WCK270. According to an embodiment, since the internal write clocks WCK0, WCK90, WCK180, and WCK270 are generated based on the write clock WCK, the read data strobe signal RDQS and the data signal DQ can be generated based on the write clock WCK. In this case, compared to a case where the read data strobe signal RDQS and the data signal DQ are generated based on the clock signal CK, the power consumption of the memory device 200 can be reduced.

[0084] According to an embodiment, the memory device 200 may further include a write (WR) buffer 217 and a read (RD) buffer 218. For example, the write buffer 217 may receive a data signal DQ as write data from the data transceiver 216. The write buffer 217 may parallelize the data signal DQ and store the parallelized data signal DQ in a FIFO of the write buffer 217. The write buffer 217 may provide the write data stored in the FIFO to the write driver (WDRV) 223.

[0085] For example, the read buffer 218 may receive read data from the input / output sense amplifier (IOSA) 224. The read buffer 218 may store the received read data in a FIFO of the read buffer 218. The read buffer 218 may serialize the read data and provide the serialized read data to the data transceiver 216.

[0086] According to an embodiment, the memory device 200 may further include a row decoder 221, a column decoder 222, a write driver 223, an input / output sense amplifier 224, and a memory cell array 230. For example, the row decoder 221 may decode a row address under the control of the control logic circuit 212. The row decoder 221 may select and activate at least one word line corresponding to the row address.

[0087] For example, the column decoder 222 may decode the column address under the control of the control logic circuit 212. The column decoder 222 may select and activate at least one column select line corresponding to the column address. Two or more bit lines may be connected to the column select line. For example, a memory cell corresponding to the row address and the column address may be selected, and a data input / output operation may be performed on the selected memory cell.

[0088] For example, the write driver 223 may receive write data from the write buffer 217 and may write the write data into the selected memory cell through the input / output line GIO. The input / output sense amplifier 224 may sense read data output from the selected memory cell through the input / output line GIO and may provide the read data to the read buffer 218.

[0089] For example, the memory cell array 230 may include a plurality of memory cells connected to word lines and bit lines. For example, the memory cells may be dynamic random access memory (DRAM) cells. In this case, the interface circuit 110 (refer to Figure 1 ) and the memory device 200 may communicate with each other based on one of standards such as double data rate (DDR), low power double data rate (LPDDR), graphics double data rate (GDDR), wide I / O, high bandwidth memory (HBM), hybrid memory cube (HMC), etc.

[0090] Figure 5 It shows Figure 4 Circuit diagram of the WCK bias generator configuration. Figure 6 It shows Figure 5 The following is a circuit diagram of the configuration of the resistor string RS and the multiplexer (MUX) 243. Figure 5 and Figure 6 The operation of the WCK bias generator 240 is described. According to an embodiment, Figure 5One or more of the components shown in FIG. 5 may be implemented as a circuit.

[0091] In one embodiment, WCK bias generator 240 may include an error amplifier 241, a P-channel metal oxide semiconductor (PMOS) transistor MP1, a feedback resistor RFB, a resistor string RS, a multiplexer 243, a replica buffer (or second buffer) 245, a comparator (COMP) 247, a counter 248, and a compensation circuit 249. Error amplifier 241 may represent an operational amplifier for error detection. PMOS transistor MP1 may be referred to as a "pass transistor." In one embodiment, replica buffer 245 may be structurally identical to WCK buffer 213. This disclosure is not limited thereto, and therefore, WCK bias generator 240 may include one or more other components, or omit one or more other components. Depending on the embodiment, transistor MP1 is not limited to a PMOS transistor. Therefore, other types of transistors may be used.

[0092] According to an embodiment, the error amplifier 241, the PMOS transistor MP1, and the feedback resistor RFB may constitute a voltage regulator. The voltage regulator may receive a reference voltage Vref and output a voltage for turning on the PMOS transistor MP1. The PMOS transistor MP1 may output a voltage (e.g., the power supply voltage VDD) to a node N1 based on the output voltage of the error amplifier 241 (that is, the PMOS transistor MP1 may be driven based on the output voltage of the error amplifier 241). The voltage level (e.g., the voltage level) of the node N1 may be the same as that of the reference voltage Vref. For example, the reference voltage Vref may be generated from a bandgap reference circuit. In one embodiment, the feedback resistor RFB may be connected between the PMOS transistor MP1 and the node N1.

[0093] The resistor string RS may include a plurality of resistors r1 to rn (refer to Figure 6 and Figure 8 ). Here, "n" is a natural number greater than 0. In one embodiment, the multiplexer 243 may perform a switching operation corresponding to the resistor string RS and output the WCK bias based on the switching operation. In one embodiment, the multiplexer 243 may be configured to (for example, based on the count value of the counter 248) perform a switching operation between the node N1, the node N2, and the nodes between the multiple resistors r1 to rn constituting the resistor string RS, so that the resistance value of the resistor string RS changes. In one embodiment, the multiplexer 243 may include a plurality of switches S1 to Sn+1 and a decoder 244. For example, the plurality of switches S1 to Sn+1 may be connected to a plurality of nodes of the resistor string RS (for example, the node N1, the node N2, and the nodes between the resistors r1 to rn).

[0094] In one embodiment, the plurality of switches S1 to Sn+1 may be controlled by the control logic circuit 212 (refer to Figure 4 ) is controlled by a control signal generated by a resistor string RS. For example, multiple switches S1 to Sn+1 can be controlled individually. In this case, the WCK bias can be output via multiplexer 243 from one of the nodes between node N1, node N2, and the multiple resistors r1 to rn that make up resistor string RS. In other words, resistor string RS and multiplexer 243 can be considered a voltage divider circuit that outputs the WCK bias based on a feedback voltage (e.g., the voltage at node N1). In one embodiment, error amplifier 241 can receive a reference voltage Vref and a feedback voltage.

[0095] For example, the replica buffer 245 may replicate the target bias current flowing to the WCK buffer 213 to generate the current ICML. The replica buffer 245 may also output an output voltage WCKO based on the power supply voltage VDD and the ground voltage. For example, the replica buffer 245 may be configured to receive the power supply voltage VDD and the ground voltage and output the output voltage WCKO. In one embodiment, the replica buffer 245 may include a first load resistor R1, a second load resistor R2, a first transistor MN1, a second transistor MN2, a third transistor MN3, and a fourth transistor MN4. The third transistor MN3 may be driven by the WCK bias, and the fourth transistor MN4 may be turned on or off by the transmission gate switching signal SW_PG. According to an embodiment, the first transistor MN1 to the fourth transistor MN4 may be NMOS switching elements. However, the disclosure is not limited thereto, and therefore, the transistors and / or switching elements may be implemented in various ways. In one embodiment, a first end of the first load resistor R1 and a first end of the second load resistor R2 may be connected to a power supply voltage VDD, a first end of the first transistor MN1 may be connected to a second end of the first load resistor R1, a first end of the second transistor MN2 may be connected to a second end of the second load resistor R2, and a first end of the third transistor MN3 may be connected to a second end of the first transistor MN1 and a second end of the second transistor MN2.

[0096] The WCK bias generator 240 may be configured in the memory device 200 (refer to Figure 1 ) is performed during initialization. For example, in the memory device 200 (refer to Figure 1), calibration may begin when a WCK bias is input to transistor MN3 and a transmission gate switching signal SW_PG is input to transistor MN4 during initialization. According to an embodiment, because transistor MN1 is turned off by ground voltage and transistor MN2 is turned on by power supply voltage VDD, current ICML may flow through a path formed by power supply voltage VDD, second load resistor R2, and the second through fourth transistors MN2, MN3, and MN4. In this case, a voltage drop may be caused by second load resistor R2, and output voltage WCKO may be output via node N3 between second load resistor R2 and transistor MN2.

[0097] The comparator 247 may compare the output voltage WCKO with the reference voltage VIL and may output the comparison result to the counter 248. The reference voltage VIL may be a target voltage.

[0098] The comparator 247 may be implemented with various logic elements that perform the above comparison operation. The counter 248 may perform a counting operation based on the comparison result received from the comparator 247 and output a count value or a count result based on the counting operation.

[0099] In the example case where the current ICML is smaller than the reference current, the value of the voltage of the node N3 or the output voltage WCKO can be obtained by VDD-ICML×R2 denoted by . The reference current may be a target current intended to flow along a path formed by the second load resistor R2 and transistors MN2, MN3, and MN4. In this case, the voltage at node N3 may be greater than the value of the target voltage VIL. That is, a relationship expressed by the following equation 1 may be established between the voltage at node N3 and the target voltage VIL. Counter 248 may increase the count value by "1." Counter 248 may output the count value to multiplexer 243.

[0100] [Equation 1] VDD-ICML×R2>VIL Multiplexer 243 decodes the count value received from counter 248 and generates signals for controlling switches S1 through Sn+1. For example, decoder 244 (e.g., based on the count value received from counter 248) generates signals for controlling switches S1 through Sn+1 so that the level of the WCK bias increases by one step. For example, assume that initially, switches S3 and Sn+1 are closed, and the remaining switches are open. In this case, the value of the WCK bias can be expressed as VFB - (r1 + r2) × IRS, where IRS represents the current flowing through resistor string RS. Here, VFB represents the feedback voltage, which is the voltage at node N1. In the example case where the count value increases by "1" during calibration, switches S2 and Sn+1 can be closed, and the remaining switches can be opened. As a result, the value of the WCK bias can increase to VFB - r1 × IRS. As the value of the WCK bias increases, the value of current ICML can increase, and the value of output voltage WCKO can decrease.

[0101] On the other hand, in another example case where the current ICML is greater than the reference current, a relationship represented by the following equation 2 may be established between the voltage of the node N3 and the target voltage. In this case, the counter 248 may decrease the count value by "1." The counter 248 may output the count value (e.g., -1) to the multiplexer 243.

[0102] [Equation 2] VDD-ICML×R2 <VIL The multiplexer 243 can decode the count value received from the counter 248 and generate a signal for controlling switches S1 to Sn+1. For example, the decoder 244 can generate a signal for controlling switches S1 to Sn+1 so that the level of the WCK bias is reduced by one step. For example, assuming that initially, switches S3 and Sn+1 are closed and the remaining switches are open, when the count value decreases by "1", switches S4 and Sn+1 can be closed, and the remaining switches can be opened. As a result, the value of the WCK bias can be reduced to VFB-(r1+r2+r3)×IRS. As the value of the WCK bias decreases, the value of the current ICML can become smaller, and the value of the output voltage WCKO can become larger.

[0103] The above calibration loop may be performed at least once, and may be performed until the value of the WCK bias converges to a specific value and stabilizes.

[0104] Figure 7 is shown and by Figure 5 FIG2 is a diagram of the waveform of a signal associated with the calibration performed by the WCK bias generator 240. For example, Figure 71 and 2. The input signal of the comparator 247 and the operation of the counter 248 are shown. The counter 248 can operate based on the internal clock UCLK.

[0105] Reference Figure 5 and Figure 7 In the initialization of the memory device, at time point t0, the WCK bias generator 240 may start calibration. In one embodiment, based on the initial WCK bias output by the multiplexer 243, the replica buffer 245 may output an initial output voltage WCKO having a value of V1.

[0106] During the time interval from t0 to t1, WCK bias generator 240 may compare the value (e.g., V1) of output voltage WCKO of replica buffer 245 with target voltage VIL and output the comparison result. Because output voltage WCKO value V1 is greater than target voltage VIL, counter 248 may increase the count value (UP). Multiplexer 243 may output a WCK bias value increased by one step based on the count value.

[0107] At time t1, the value of current ICML may increase due to the increased WCK bias, and at the same time, the value of output voltage WCKO may decrease from V1 to V2. The above calibration cycle may be repeatedly performed until time t4. As a result, the value of WCK bias may continuously increase, and the value of output voltage WCKO corresponding to the WCK bias may continuously decrease to V5.

[0108] During the time interval from t4 to t5, WCK bias generator 240 may compare the value of output voltage WCKO (e.g., V5) of replica buffer 245 with target voltage VIL and output the comparison result. Because output voltage WCKO value V5 is smaller than target voltage VIL, counter 248 may decrement count value (DN). Multiplexer 243 may output a WCK bias value reduced by one step based on the count value.

[0109] At the time point t5 , the value of the current ICML may be reduced by the WCK bias having a reduced value, and simultaneously, the value of the output voltage WCKO may be increased from V5 to V4 .

[0110] According to an embodiment, after time t5, the value of output voltage WCKO may switch between V4 and V5 based on calibration. In this case, memory device 200 may determine that the value of output voltage WCKO is locked. In one embodiment, memory device 200 may determine that the value of output voltage WCKO is locked based on the value of output voltage WCKO switching for a reference number of times. For example, if the value of output voltage WCKO switches for four cycles, memory device 200 may determine that the value of output voltage WCKO is locked. In another embodiment, memory device 200 may determine that the value of output voltage WCKO is locked based on a reference amount of time having passed since calibration was performed at time t0. For example, memory device 200 may determine that the value of output voltage WCKO is locked after a first period of time from the start of calibration at time t0. In the example case where the value of output voltage WCKO is determined to be locked, calibration performed using replica buffer 245, comparator 247, and counter 248 may be terminated. In one embodiment, whether a given time (eg, a reference amount of time) has passed may be determined based on whether the number of toggles of the internal clock UCLK used for the counter 248 to operate exceeds a given number.

[0111] Figure 8 It shows Figure 5 In order to simplify the drawings, the circuit diagram of the compensation circuit 249 is shown in FIG. Figures 5 to 7 Components that do not operate after the described calibration is terminated (eg, comparator 247 and counter 248 ) are omitted, and only a portion of the replica buffer 245 (eg, MN3 ) is shown.

[0112] Compensation circuit 249 may include a plurality of transistors M1 to M3. Transistors M1 to M3 may be NMOS transistors. Transistors M1 and M2 may be diode-connected and connected in series. In one embodiment, the drain and gate electrodes of transistor M1 may be connected to node N2. Transistor M3 may be a switching element for controlling the operation of compensation circuit 249. Transistor M3 may be connected to transistor M2. Transistor M3 may be controlled by a compensation switching signal SW_CPS. Transistors M1, M2, and M3 may form a first branch.

[0113] In the example case where the WCK bias is locked by compensation performed in the initialization of the memory device 200, temperature compensation may be performed by the compensation circuit 249. In the example case where the ambient temperature rises, the replica buffer 245 (refer to Figure 5) can reduce the threshold voltage of transistor MN3. Therefore, the current Id flowing in the compensation circuit 249 should increase to maintain the level of the current ICML flowing in the replica buffer 245. This is because the level of the WCK bias can be reduced by increasing the voltage drop of the resistor string RS through the increase in the magnitude of the current Id.

[0114] In another example case where the ambient temperature decreases, the replica buffer 245 (refer to Figure 5 ) increases the threshold voltage of the transistor MN3. That is, the current Id flowing in the compensation circuit 249 should be reduced to maintain the level of the current ICML flowing in the replica buffer 245. This is because the level of the WCK bias can be increased by reducing the voltage drop of the resistor string RS through the reduction in the magnitude of the current Id.

[0115] When using Figure 8 In the case where the above temperature compensation scheme is implemented using the diode-connected transistors M1 and M2 shown in FIG, the current Id flowing through the transistors M1 and M2 can be expressed by the following equation 3.

[0116] [Equation 3]

[0117] In equation 3 above, It indicates the current Id flowing through transistors M1 and M2. Can indicate the mobility of the transistor, The value of the oxide's capacitance is indicated. "W" indicates the width of the channel, "L" indicates the length of the channel, and V th Can indicate the threshold voltage of the transistor, V GS It indicates the gate-source voltage of the transistor, and V DS Indicates the drain-source voltage of the transistor.

[0118] Referring to Equation 3 above, in the example case where the ambient temperature rises, the threshold voltage V th The magnitude of V is reduced, and the level of the current Id flowing through the compensation circuit 249 is increased. In another example case where the ambient temperature is reduced, the threshold voltage V th The magnitude of increases, and the level of the current Id flowing through the compensation circuit 249 decreases. As a result, the above temperature compensation scheme can be implemented.

[0119] However, in the case of implementing a temperature compensation scheme by using only diode-connected transistors M1 and M2, it may be difficult to fully compensate for changes in ambient temperature. For example, because the gate electrodes of the diode-connected transistors M1 and M2 are commonly connected to the node N2, in the example case where the level of the threshold voltage of the transistor decreases due to an increase in temperature, the magnitude of the current Id increases, and the drain-source voltage V of the transistors M1 and M2 increases. DS As understood from the above equation 3, when the drain-source voltage V DS In the example case where the level of the current Id is reduced, a negative feedback is formed in which the level of the current Id is reduced. According to the embodiment, since the drain-source voltage V DS and the gate-source voltage V GS The ratio (for example, V DS / V GS ) are consistent, so the gate-source voltages V GS According to the drain-source voltage V DS As a result, negative feedback may be strongly formed. This may mean that the fluctuation of the current Id according to the change of temperature (or threshold voltage) may be smaller than expected.

[0120] Therefore, in order to solve the above problem of reducing the fluctuation of the current Id according to the change of temperature (or threshold voltage), the compensation circuit 249 according to the disclosed embodiment may further include the following: Figure 9 The branch shown in .

[0121] Figure 9 It shows Figure 5 The circuit diagram of an example of the compensation circuit 249 is shown in FIG. Figure 8 As in the above description given, in order to simplify the drawings, some components (eg, the comparator 247 and the counter 248 ) are omitted, and only a portion (eg, MN3 ) of the replica buffer 245 is shown.

[0122] Compensation circuit 249 may include NMOS transistors M1 to M6. Transistors M1 and M2 may be diode-connected and connected in series. Transistor M3 may be a switching element for controlling the operation of compensation circuit 249 and may be connected to transistor M2. Transistor M3 may be controlled by a compensation switching signal SW_CPS. Transistors M1, M2, and M3 may form a first branch (or a first string).

[0123] In one embodiment, a first terminal of transistor M4 (e.g., the drain electrode of transistor M4) may be connected to node N2, and a second terminal of transistor M4 (e.g., the source electrode of transistor M4) may be connected to a first terminal of transistor M5 (e.g., the drain and gate electrodes of transistor M5). Transistor M5 may be a diode-connected transistor. The gate electrode of transistor M4 may be connected to node N1, and transistor M4 may be driven by a feedback voltage. For example, the feedback voltage may be the voltage at node N1. A second terminal of transistor M5 (e.g., the source electrode of transistor M5) may be connected to transistor M6, which is a switching element for controlling the operation of compensation circuit 249. Transistor M6 may be controlled by a compensation switching signal SW_CPS. Transistors M4, M5, and M6 may form a second branch (or second string). Meanwhile, transistors M3 and M6 may be individually controlled by the compensation switching signal SW_CPS. However, depending on the embodiment, this may not necessarily mean that transistors M3 and M6 should be turned on or off at the same time.

[0124] In one embodiment, transistors M1 and M4 may be formed in a first layer, transistors M2 and M5 may be formed in a second layer, and transistors M3 and M6 may be formed in a third layer. That is, transistors M1 to M6 may be formed in a three-level stack.

[0125] In the example case where the first branch and the second branch are connected in parallel, Figure 9 The operation of the compensation circuit 249 can be related to Figure 8 The operation of the compensation circuit 249 is slightly different. For example, the drain-source voltage V of the transistor M4 driven by the feedback voltage (eg, the voltage of the node N1) is DS and gate-source voltage V GS Proportional to the threshold voltage (e.g., V DS / V GS ∝V th ). Therefore, the level of the current Id2 flowing through the transistor M4 can be varied to be sensitive to the change in the threshold voltage. In addition, since the gate-source voltage V GS , so the fluctuation of the current Id2 flowing through the transistor M4 due to the change of temperature or threshold voltage may become larger. For example, since the feedback voltage of the driving transistor M4 is consistent with the reference voltage Vref regardless of the change of pressure, volume and temperature (PVT), the gate-source voltage V GS It can also maintain consistency.

[0126] Since the change in the threshold voltage of the transistor is compensated by the operation of the compensation circuit 249, the level of the WCK bias can be compensated. Therefore, the WCK buffer 213 driven by the WCK bias can stably generate the target bias current.

[0127] Figure 10A is a graph comparing voltage levels of WCK bias formed by compensation performed at high temperature. Figure 10B is a graph comparing the voltage level of the WCK bias formed by compensation performed at low temperature. Figure 10A and Figure 10B , the unit on the horizontal axis is degrees Celsius, and the unit on the vertical axis is millivolts.

[0128] Reference Figure 10A In the example case where calibration is performed at a high temperature (e.g., 120°C) during the process of initializing a memory device, the WCK bias may be locked at approximately 440 mV. Thereafter, as the temperature decreases, compensation may be performed by the compensation circuit. In this case, the threshold voltage level of the transistor may increase, and the WCK bias level may also increase.

[0129] In compensation by Figure 8 In the example case where the compensation circuit 249 shown in FIG. 1 is implemented, when the temperature decreases from 120° C. to −40° C., the value of the WCK bias may increase to a value that does not reach approximately 480 mV. Figure 8 The compensation circuit 249 operates as described above to compensate for the change in the threshold voltage, but the value of the WCK bias is not sufficiently compensated due to a negative feedback caused by the decrease in the level of the current Id.

[0130] In compensation by Figure 9 In the example case of the compensation circuit 249 shown in FIG, the value of the WCK bias may increase to a value exceeding about 500 mV when the temperature decreases from 120°C to -40°C. In this case, it is observed that: Figure 8 Compared with the case of the compensation circuit 249, a further compensation of about 28 mV is performed.

[0131] Reference Figure 10B In the example case where calibration is performed at a low temperature (e.g., 40°C) during the process of initializing a memory device, the WCK bias may be locked at approximately 520 mV. Thereafter, as the temperature increases, compensation may be performed by the compensation circuit; in this case, the threshold voltage level of the transistor may decrease, and the level of the WCK bias may also decrease.

[0132] like Figure 10B As shown in Figure 8 In the example case of the compensation circuit 249 shown in FIG, when the temperature increases from -40°C to 120°C, the value of the WCK bias can be reduced to about 490mV. Figure 8The compensation circuit 249 operates as described above to compensate for the change in the threshold voltage, but the value of the WCK bias is not sufficiently compensated due to a negative feedback caused by the increase in the level of the current Id.

[0133] In compensation by Figure 9 In the example case of the compensation circuit 249 shown in FIG, the value of the WCK bias can be reduced to about 450 mV when the temperature increases from -40°C to 120°C. In this case, it is observed that: Figure 8 Compared with the case where the compensation circuit 249 operates, compensation of about 35 mV is further performed.

[0134] Figure 11 It shows Figure 5 1 is a circuit diagram of the compensation circuit 249. To simplify the drawing, some components (eg, the comparator 247 and the counter 248) are omitted, and only a portion (eg, MN3) of the replica buffer 245 is shown.

[0135] Compensation circuit 249 may include NMOS transistors M1 and M3 to M6. Transistor M1 may be a diode-connected transistor. Transistor M3 may be a switching element for controlling the operation of compensation circuit 249 and may be connected to transistor M1. Transistor M3 may be controlled by a compensation switching signal SW_CPS. Transistors M1 and M3 may form a first branch.

[0136] A first terminal of transistor M4 may be connected to node N2, and a second terminal of transistor M4 may be connected to a first terminal of diode-connected transistor M5. A gate electrode of transistor M4 may be connected to node N1. A second terminal of transistor M5 may be connected to transistor M6, which is a switching element for controlling the operation of compensation circuit 249. Transistor M6 may be controlled by compensation switching signal SW_CPS. Transistors M4, M5, and M6 may form a second branch.

[0137] Figure 11 The operation of the compensation circuit 249 is Figure 9 The operation of the compensation circuit 249 shown in FIG. 2 is mostly similar, and therefore, additional description will be omitted to avoid redundancy.

[0138] Figure 12 It shows Figure 5 1 is a circuit diagram of an example of a compensation circuit 249. To simplify the drawing, some components (eg, comparator 247 and counter 248) are omitted, and only a portion (eg, MN3) of the replica buffer 245 is shown.

[0139] The compensation circuit 249 may include NMOS transistors M1 to M7 and a resistor R4. In one embodiment, the resistor R4 may be implemented as an actual resistor serving as a passive element rather than a transistor having resistance. The transistors M1 and M2 may be diode-connected. A transistor M3 serving as a switching element for controlling the operation of the compensation circuit 249 may be connected to the transistor M2. The transistor M3 may be controlled by a compensation switching signal SW_CPS. The transistors M1, M2, and M3 may form a first branch.

[0140] A first terminal of transistor M4 may be connected to node N2, and a second terminal of transistor M4 may be connected to a first terminal of diode-connected transistor M5. A gate electrode of transistor M4 may be connected to node N1. A second terminal of transistor M5 may be connected to transistor M6, which is a switching element for controlling the operation of compensation circuit 249. Transistor M6 may be controlled by compensation switching signal SW_CPS. Transistors M4, M5, and M6 may form a second branch.

[0141] A first end of resistor R4 may be connected to node N2, and a second end of resistor R4 may be connected to transistor M7, which is a switching element for controlling the operation of compensation circuit 249. Transistor M7 may be controlled by compensation switching signal SW_CPS. Resistor R4 and transistor M7 may form a third branch (or third string).

[0142] Figure 12 The operation of the compensation circuit 249 can be related to Figure 9 The operation of the compensation circuit 249 shown in FIG is largely similar. However, because the first branch, the second branch, and the third branch are connected in parallel, the WCK bias can be compensated by sensitively reacting to temperature changes, and the WCK bias can also be stably maintained (or locked) at a given temperature.

[0143] Figure 13 It shows Figure 5 1 is a circuit diagram of the compensation circuit 249. To simplify the drawing, some components (eg, the comparator 247 and the counter 248) are omitted, and only a portion (eg, MN3) of the replica buffer 245 is shown.

[0144] Figure 13 The configuration and operation of the compensation circuit 249 can be compared with Figure 9 The configuration and operation of the compensation circuit 249 are substantially the same. However, the gate electrode of the transistor M4 may be connected to a node to which the reference voltage Vref is input, instead of the node N1. In the example case where "the error amplifier 241 is ideal", the voltage levels of the negative input terminal and the positive input terminal of the error amplifier 241 may be the same. Therefore, because Figure 13 The WCK bias generator 240 is used with Figure 9The WCK bias generator 240 operates in essentially the same manner, so Figure 13 The WCK bias generator 240 can provide Figure 9 The WCK bias generator 240 has the same function.

[0145] Figure 14 It shows Figure 4 Circuit diagram of the WCK bias generator configuration. Figure 15 It shows Figure 14 Circuit diagram of the configuration of the resistor string RS and the multiplexer 243. Figure 14 The configuration and operation of the WCK bias generator 240 can be compared with Figure 5 The configuration and operation of the WCK bias generator 240 are similar, so the differences will be mainly described. Figure 14 and Figure 15 The operation of the WCK bias generator 240 is described.

[0146] In one embodiment, the WCK bias generator 240 may include an error amplifier 241, a PMOS transistor MP1, a resistor string RS, a multiplexer 243, a replica buffer 245, a comparator 247, a counter 248, and a compensation circuit 249. The error amplifier 241 and the PMOS transistor MP1 may constitute a voltage regulator. Alternatively, at least part of the error amplifier 241, the PMOS transistor MP1, and the resistor string RS may constitute a voltage regulator.

[0147] In one embodiment, the plurality of switches S1 to Sn+1 connected to the node of the resistor string RS may be controlled by, for example, the control logic circuit 212 (see Figure 4 ) are individually controlled. As a result, some of the resistors r1 to rn constituting the resistor string RS can perform the same Figure 5 The feedback resistor RFB shown in FIG has essentially the same function. Therefore, by Figure 14 and Figure 15 The embodiment can make Figure 5 The WCK bias generator 240 shown in FIG. 2 may be implemented with a value of the feedback resistor RFB varied.

[0148] Figure 16 is a flow chart illustrating the method of operation of the WCK bias generator according to the disclosed embodiment. Figure 4 、 Figure 5 and Figure 16 Describes the operation of the WCK bias generator.

[0149] In operation S110, the method may include performing initialization. For example, the memory device 200 may perform initialization. In the example case where the memory device 200 is powered on, the memory device 200 may perform initialization in accordance with a given method. During initialization, the memory controller may provide a power supply voltage to the memory device 200, may perform various initial setup operations, and may read necessary information from the memory device 200 or set necessary information to the memory device 200.

[0150] In operation S120, the method may include comparing the output voltage WCKO of the replica buffer 245 with a reference voltage (eg, the target voltage VIL). For example, the output voltage WCKO of the replica buffer 245 and the target voltage VIL may be compared by a comparator 247. The comparator 247 may output the comparison result to a counter 248.

[0151] In operation S130, based on the comparison result indicating that the level of the output voltage WCKO is higher than the level of the target voltage VIL ("Yes" in operation S120), the level of the WCK bias may be increased. For example, the counter 248 may increase the count value by "1", and the multiplexer 243 may increase the level of the WCK bias by performing a switching operation according to the increased count value.

[0152] In operation S140, based on the comparison result indicating that the level of the output voltage WCKO is lower than the level of the target voltage VIL ("No" in operation S120), the level of the WCK bias may be reduced. For example, the counter 248 may reduce the count value by "1", and the multiplexer 243 may reduce the level of the WCK bias by performing a switching operation according to the reduced count value.

[0153] In operation S150, the method may include determining whether the output voltage WCKO is locked. For example, the WCK bias generator may determine whether the value of the output voltage WCKO is locked. For example, as the above calibration cycle is repeated, the value of the output voltage WCKO may gradually converge to the value of the target voltage VIL. In operation S170, if the value of the output voltage WCKO is locked ("Yes" in operation S150), the calibration may be terminated. In operation S160, if the value of the output voltage WCKO is not locked ("No" in operation S150), the method may include determining whether the value of the output voltage WCKO has switched a reference number of times. Furthermore, in operation S170, if the value of the output voltage WCKO has switched a reference number of times ("Yes" in operation S160), it may be determined that the value of the output voltage WCKO is locked. As a result, the calibration may be terminated. On the other hand, if the value of the output voltage WCKO has not switched a reference number of times ("No" in operation S160), operation S120 may be repeated.

[0154] In another embodiment, even if it is determined that the value of the output voltage WCKO is not locked ("No" in operation S150), in the example case where a reference time period has passed after the start of calibration, it may be determined that the calibration is terminated (operation S170). For example, it may be determined based on the number of toggles of the internal clock UCLK whether a given time has passed (reference time). Figure 7 ).

[0155] In operation S180, the method may include compensating for a change in threshold voltage due to temperature change based on calibration. For example, the compensation circuit 249 may compensate for a change in threshold voltage due to temperature change. The compensation circuit 249 may include, for example, a first branch including at least one diode-connected transistor (e.g., Figure 9 M1 and / or M2), the second branch includes a transistor M4 driven by the feedback voltage of the voltage regulator and a diode-connected transistor M5.

[0156] Figure 17 3 is a diagram illustrating a stacked memory device according to a disclosed embodiment. The stacked memory device 300 may include a buffer die 310 and a plurality of core dies 320 to 350. For example, the buffer die 310 may also be referred to as an "interface die," a "base die," a "logic die," or a "master die," and each of the core dies 320 to 350 may also be referred to as a "memory die" or a "slave die." Figure 17 3. In the example shown in FIG. 3, the stacked memory device 300 includes four core dies 320 to 350, but the number of core dies may be changed variously. For example, the stacked memory device 300 may include 8 core dies, 12 core dies, or 16 core dies.

[0157] The buffer die 310 and the core dies 320 to 350 may be stacked and electrically connected using through-silicon vias (TSVs). Thus, the stacked memory device 300 may have a three-dimensional memory structure with multiple dies 310 to 350 stacked. For example, the stacked memory device 300 may be implemented in accordance with the HBM standard or the HMC standard.

[0158] The stacked memory device 300 can support multiple channels (or vaults) that are functionally independent of each other. Figure 17As shown in , the stacked memory device 300 can support eight channels, CH0 to CH7. If each of the channels CH0 to CH7 supports 128 data transmission paths, the stacked memory device 300 can support 1204 data transmission paths. However, the disclosure is not limited thereto. For example, the stacked memory device 300 can support 1024 or more data transmission paths and can support eight or more channels (e.g., 16 channels). If the stacked memory device 300 supports 16 channels, each channel can support 64 data transmission paths.

[0159] Each of the core dies 320 to 350 may support at least one channel. Figure 17 As shown in FIG, core die 320 may support two channels, CH0 and CH2, core die 330 may support two channels, CH1 and CH3, core die 340 may support two channels, CH4 and CH6, and core die 350 may support two channels, CH5 and CH7. In this case, core dies 320 to 350 may support different channels. However, the disclosure is not limited thereto. For example, at least two of core dies 320 to 350 may support the same channel. For example, each of core dies 320 to 350 may support the first channel, CH0.

[0160] Each channel can form an independent command and data interface. For example, each channel can be independently clocked based on independent timing requirements, and the channels may not be synchronized with each other. For example, based on independent commands, each channel can change power state or perform refresh operations.

[0161] Each channel may include a plurality of memory banks 301 (e.g., first bank Bank1 to eighth bank Bank8). Each memory bank 301 may include memory cells connected to word lines and bit lines, row decoders, column decoders, sense amplifiers, etc. For example, Figure 17 As shown in FIG, each of channels CH0 to CH7 may include 8 memory banks 301. However, the disclosure is not limited thereto. For example, each of channels CH0 to CH7 may include 8 or more memory banks 301. An example in which memory banks included in one channel are included in one core die is shown in FIG. Figure 17 , but the memory banks included in one channel may be distributed to a plurality of core dies. In the example case where each of the core dies 320 to 350 supports the first channel CH0, the memory banks included in the first channel CH0 may be distributed to the core dies 320 to 350.

[0162] In one embodiment, a channel can be divided into two pseudo-channels that operate independently of each other. For example, the pseudo-channels can share command and clock inputs (e.g., clock signal CK and clock enable signal CKE) but can independently decode and execute commands. In an example where a channel supports 128 data transmission paths, each pseudo-channel can support 64 data transmission paths. In an example where a channel supports 64 data transmission paths, each pseudo-channel can support 32 data transmission paths.

[0163] Each of the core dies 320 to 350 and the buffer die 310 may include a TSV area 302. TSVs configured to penetrate the dies 310 to 350 may be provided in the TSV area 302. The buffer die 310 may exchange signals and / or data with the core dies 320 to 350 through the TSVs. Each of the core dies 320 to 350 may exchange signals and / or data with the buffer die 310 and any other core die through the TSVs. In this case, signals and / or data may be independently sent / received through the TSVs of each channel. In the example case where an external host device sends a command and an address to the first channel CH0 through the TSV corresponding to the first channel CH0 to access the memory cells of the first core die 320, the buffer die 310 may send a control signal to the first core die 320 and may access the memory cells of the first core die 320.

[0164] The buffer die 310 may include a physical layer (PHY) 311. The physical layer 311 may include an interface circuit for communicating with an external host device. For example, the physical layer 311 may include a reference Figures 1 to 16 The components corresponding to the described interface circuit 210 may be transmitted to the core dies 320 to 350 through TSVs.

[0165] In one embodiment, the buffer die 310 may include a channel controller corresponding to each channel. The channel controller may manage memory reference operations of the corresponding channel and may determine timing requirements of the corresponding channel.

[0166] In one embodiment, the buffer die 310 may include multiple pins for receiving signals from an external host device. Through the multiple pins, the buffer die 310 may receive a clock signal CK, command / address signals C / A, a write clock WCK, and a data signal DQ, and may transmit a read data strobe signal RDQS and a data signal DQ. For example, for each channel, the buffer die 310 may include two pins for receiving the clock signal CK, 14 pins for receiving the command / address signals C / A, eight pins for receiving the write clock WCK, eight pins for transmitting the read data strobe signal RDQS, and 128 pins for transmitting and receiving the data signal DQ.

[0167] Figure 18 FIG is a diagram showing a semiconductor package according to an embodiment of the disclosure. Figure 18 The semiconductor package 1000 may include a stacked memory device 1100, a system on chip 1200, an interposer 1300, and a package substrate 1400. The stacked memory device 1100 may include a buffer die 1110 and core dies 1120 to 1150. The buffer die 1110 may be connected to the core die 1120 to 1150. Figure 17 The buffer die 310 corresponds to the core die 1120 to 1150, and the core die 1120 to 1150 can be respectively Figure 17 The core dies 320 to 350 correspond to each other.

[0168] Each of the core dies 1120 to 1150 may include a memory cell array. The buffer die 1110 may include a physical layer 1111 and a direct access area (DAB) 1112. The physical layer 1111 may be electrically connected to the physical layer 1210 of the system on chip 1200 through the intermediary 1300. Through the physical layer 1111, the stacked memory device 1100 may receive a signal from the system on chip 1200 or may transmit a signal to the system on chip 1200. The physical layer 1111 may include a reference Figure 17 The interface circuitry of the buffer die 310 is described.

[0169] Direct access area 1112 can provide an access path that enables testing of stacked memory device 1100 without going through system-on-chip 1200. Direct access area 1112 may include conductive devices (e.g., ports or pins) that enable direct communication with external test equipment. Test signals and data received through direct access area 1112 can be transmitted to core dies 1120 to 1150 via TSVs. To test core dies 1120 to 1150, data read from core dies 1120 to 1150 can be transmitted to a test equipment via TSVs and direct access area 1112. Thus, direct access testing of core dies 1120 to 1150 can be performed.

[0170] The buffer die 1110 and the core dies 1120 to 1150 can be electrically connected to each other using TSVs 1101 and bumps 1102. The buffer die 1110 can receive a signal provided to each channel from the system on chip 1200 through the bumps 1102 allocated to each channel. For example, the bumps 1102 can be micro bumps.

[0171] The system on chip 1200 may execute applications supported by the semiconductor package 1000 by using the stacked memory device 1100. For example, the system on chip 1200 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a neural processing unit (NPU), a tensor processing unit (TPU), a vision processing unit (VPU), an image signal processor (ISP), and a digital signal processor (DSP), and may perform specialized operations.

[0172] The system-on-chip 1200 may include a physical layer (PHY) 1210 and a memory controller 1220. The physical layer 1210 may include an input / output circuit for exchanging signals with the physical layer 1111 of the stacked memory device 1100. The system-on-chip 1200 may provide various signals to the physical layer 1111 through the physical layer 1210. The signals provided to the physical layer 1111 may be transmitted to the core dies 1120 to 1150 through the interface circuit of the physical layer 1111 and the TSV 1101.

[0173] The memory controller 1220 may control all operations of the stacked memory device 1100. The memory controller 1220 may provide signals for controlling the stacked memory device 1100 to the stacked memory device 1100 through the physical layer 1210. The memory controller 1220 may communicate with the memory device 1100. Figure 1 Corresponding to the memory controller 100.

[0174] The interposer 1300 can connect the stacked memory device 1100 and the system-on-chip 1200. The interposer 1300 can connect the physical layer 1111 of the stacked memory device 1100 and the physical layer 1210 of the system-on-chip 1200, and can provide a physical path formed by using a conductive material. Therefore, the stacked memory device 1100 and the system-on-chip 1200 can be stacked on the interposer 1300 and can exchange signals with each other.

[0175] Bumps 1103 may be attached to the upper surface of package substrate 1400, and solder balls 1104 may be attached to the lower surface of package substrate 1400. For example, bumps 1103 may be flip-chip bumps. Interposer 1300 may be stacked on package substrate 1400 via bumps 1103. Semiconductor package 1000 may exchange signals with other external packages or semiconductor devices via solder balls 1104. For example, package substrate 1400 may be a printed circuit board (PCB).

[0176] Figure 19 2 is a diagram illustrating an example implementation of a semiconductor package according to a disclosed embodiment. A semiconductor package 2000 may include a plurality of stacked memory devices 2100 and a system-on-chip (SoC) 2200. The stacked memory devices 2100 and the SoC 2200 may be stacked on an interposer 2300, and the interposer 2300 may be stacked on a package substrate 2400. The semiconductor package 2000 may exchange signals with other external packages or semiconductor devices via solder balls 2001 attached to the lower surface of the package substrate 2400.

[0177] Each stacked memory device 2100 may be implemented in accordance with the HBM standard. However, the disclosure is not limited thereto. For example, each stacked memory device 2100 may be implemented based on the GDDR standard, the HMC standard, or the wide I / O standard. Each stacked memory device 2100 may be implemented in accordance with the HBM standard. Figure 17 The stacked memory device 300 or Figure 18 Corresponding to the stacked memory device 1100.

[0178] The system on chip 2200 may include at least one processor (such as a CPU, AP, GPU, or NPU) and a plurality of memory controllers for controlling the plurality of stacked memory devices 2100. The system on chip 2200 may exchange signals with the corresponding stacked memory devices through the memory controllers. Figure 18 Corresponding to the system-on-chip 1200.

[0179] Figure 20 3 is a diagram illustrating a semiconductor package according to another embodiment of the disclosure. The semiconductor package 3000 may include a stacked memory device 3100, a host die 3200, and a package substrate 3300. The stacked memory device 3100 may include a buffer die 3110 and core dies 3120 to 3150. The buffer die 3110 may include a physical layer 3111 for communicating with the host die 3200, and each of the core dies 3120 to 3150 may include a memory cell array. The stacked memory device 3100 may communicate with the host die 3200. Figure 17 The stacked memory device 300 corresponds to .

[0180] The host die 3200 may include a physical layer 3210 for communicating with the stacked memory device 3100 and a memory controller 3220 for controlling all operations of the stacked memory device 3100. In addition, the host die 3200 may control all operations of the semiconductor package 3000 and may include a processor for executing applications supported by the semiconductor package 3000. For example, the host die 3200 may include at least one processor (such as a CPU, AP, GPU, or NPU).

[0181] The stacked memory device 3100 may be disposed on the host die 3200 based on the TSVs 3001 so as to be vertically stacked on the host die 3200. Therefore, the buffer die 3110, the core dies 3120 to 3150, and the host die 3200 may be electrically connected to one another through the TSVs 3001 and the bumps 3002 without an interposer. For example, the bumps 3002 may be microbumps.

[0182] Bumps 3003 may be attached to the upper surface of the package substrate 3300, and solder balls 3004 may be attached to the lower surface of the package substrate 3300. For example, the bumps 3003 may be flip-chip bumps. The host die 3200 may be stacked on the package substrate 3300 via the bumps 3003. The semiconductor package 3000 may exchange signals with other external packages or semiconductor devices via the solder balls 3004.

[0183] In another embodiment, the stacked memory device 3100 may be implemented with only the core dies 3120 to 3150 without the buffer die 3110. In this case, each of the core dies 3120 to 3150 may include a Figures 1 to 17 An interface circuit for communicating with the host die 3200 is described. Each of the core dies 3120 to 3150 can exchange signals with the host die 3200 through the TSV 3001.

[0184] Figure 21 is a diagram of a system 4000 to which a storage device is applied according to an embodiment. Figure 21 The system 4000 may basically be a mobile system such as a portable communication terminal (eg, mobile phone), a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of Things (IoT) device. However, Figure 21 The system 4000 is not necessarily limited to a mobile system and may be a PC, a laptop, a server, a media player, or an automotive device (eg, a navigation device).

[0185] Reference Figure 21The system 4000 may include a main processor 4100, memories (e.g., 4200a and 4200b), and storage devices (e.g., 4300a and 4300b). In addition, the system 4000 may include at least one of an image capture device 4410, a user input device 4420, a sensor 4430, a communication device 4440, a display 4450, a speaker 4460, a power supply device 4470, and a connection interface 4480.

[0186] The main processor 4100 may control all operations of the system 4000 (more specifically, operations of other components in the system 4000). The main processor 4100 may be implemented as a general-purpose processor, a dedicated processor, or an application processor.

[0187] The main processor 4100 may include at least one CPU core 4110 and a controller 4120 configured to control memories 4200a and 4200b and / or storage devices 4300a and 4300b. In some embodiments, the main processor 4100 may also include an accelerator 4130, which is a dedicated circuit for high-speed data operations (such as artificial intelligence (AI) data operations). The accelerator 4130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and may be implemented as a chip physically separate from other components of the main processor 4100.

[0188] Memories 4200a and 4200b may be used as main memory devices of the system 4000. Although each of the memories 4200a and 4200b may include volatile memory (such as static random access memory (RAM) (SRAM) and / or dynamic RAM (DRAM)), each of the memories 4200a and 4200b may include non-volatile memory (such as flash memory, phase change RAM (PRAM) and / or resistive RAM (RRAM)). The memories 4200a and 4200b may be implemented in the same package as the main processor 4100.

[0189] Memory devices 4300a and 4300b can function as nonvolatile memory devices configured to store data regardless of whether power is supplied thereto, and have a greater storage capacity than memories 4200a and 4200b. Memory devices 4300a and 4300b can include memory controllers (STRG CTRL) 4310a and 4310b, respectively, and NVMs (nonvolatile memories) 4320a and 4320b, respectively, configured to store data under the control of memory controllers 4310a and 4310b. While NVMs 4320a and 4320b may include flash memory having a two-dimensional (2D) structure or a three-dimensional (3D) V-NAND structure, NVMs 4320a and 4320b may include other types of NVMs, such as PRAM and / or RRAM.

[0190] The storage devices 4300a and 4300b may be physically separated from the main processor 4100 and included in the system 4000 or implemented in the same package as the main processor 4100. In addition, the storage devices 4300a and 4300b may have various types of solid-state devices (SSDs) or memory cards and be removably combined with other components of the system 4000 through an interface (such as the connection interface 4480 described below). The storage devices 4300a and 4300b may be devices to which a standard protocol (such as Universal Flash Storage (UFS), embedded MultiMediaCard (eMMC), or Non-Volatile Memory Express (NVMe)) is applied, but are not limited thereto.

[0191] The image capture device 4410 may capture still images or moving images. The image capture device 4410 may include a camera, a camcorder, and / or a webcam.

[0192] The user input device 4420 may receive various types of data input by a user of the system 4000 and include a touch pad, a keypad, a keyboard, a mouse, and / or a microphone.

[0193] The sensor 4430 may detect various types of physical quantities that may be obtained from outside the system 4000 and convert the detected physical quantities into electrical signals. The sensor 4430 may include a temperature sensor, a pressure sensor, an illumination sensor, a position sensor, an acceleration sensor, a biosensor, and / or a gyroscope sensor.

[0194] The communication device 4440 may transmit and receive signals between other devices outside the system 4000 according to various communication protocols. The communication device 4440 may include an antenna, a transceiver, and / or a modem.

[0195] Display 4450 and speaker 4460 may serve as output devices configured to output visual information and auditory information, respectively, to a user of system 4000 .

[0196] The power supply device 4470 may appropriately convert power supplied from a battery embedded in the system 4000 and / or an external power source, and supply the converted power to each component of the system 4000 .

[0197] The connection interface 4480 may provide a connection between the system 4000 and an external device, which is connected to the system 4000 and capable of transmitting and receiving data to and from the system 4000. The connection interface 4480 may be implemented by using various interface schemes such as an Advanced Technology Attachment (ATA) interface, a Serial ATA (SATA) interface, an external SATA (e-SATA) interface, a Small Computer System Interface (SCSI) interface, a Serial Attached SCSI (SAS) interface, a Peripheral Component Interconnect (PCI) interface, a PCI Express (PCIe) interface, an NVMe interface, an IEEE 1394 interface, a Universal Serial Bus (USB) interface, a Secure Digital (SD) card interface, a MultiMediaCard (MMC) interface, an eMMC interface, a UFS interface, an embedded UFS (eUFS) interface, and a Compact Flash (CF) card interface.

[0198] According to the disclosed embodiments, a write clock bias generator capable of compensating for a change in the threshold voltage of a transistor due to a change in temperature and a memory device including the same can be provided.

[0199] While the disclosure has been described with reference to the disclosed embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure as set forth in the following claims.

Claims

1. A write clock bias generator, configured to provide a write clock bias to a first buffer, the write clock bias generator comprising: a voltage regulator configured to receive a reference voltage and output a feedback voltage; a resistor string including a first end connected to a first node and a second end connected to a second node, the feedback voltage being output at the first node; a multiplexer configured to perform a switching operation corresponding to the resistor string and output a write clock bias based on the switching operation; as well as A compensation circuit is connected to the second node, and the compensation circuit includes: a first string including a first transistor, the first transistor including a first drain electrode and a first gate electrode, the first drain electrode and the first gate electrode being connected to a second node; as well as The second string includes a second transistor and a third transistor, the second transistor including a second drain electrode connected to the second node, the third transistor including a third drain electrode and a third gate electrode, the third drain electrode and the third gate electrode being connected to the second source electrode of the second transistor, and the second transistor being driven based on the feedback voltage.

2. The write clock bias generator according to claim 1, wherein: The voltage regulator includes: an error amplifier configured to receive a reference voltage and a feedback voltage; a pass transistor configured to be driven based on an output of the error amplifier; and A feedback resistor is connected between the pass transistor and the first node.

3. The write clock bias generator according to claim 1 , wherein: The first string further includes a fourth transistor including a fourth drain electrode and a fourth gate electrode, the fourth drain electrode being connected to the first source electrode of the first transistor, and the fourth gate electrode being connected to the second node.

4. The write clock bias generator according to claim 1 , wherein: The compensation circuit further includes: a third string including a resistor.

5. The write clock bias generator according to any one of claims 1 to 4, further comprising: A second buffer, which is identical in structure to the first buffer; a comparator configured to compare the output voltage of the second buffer with a target voltage and output a comparison result based on the comparison between the output voltage of the second buffer and the target voltage; as well as a counter configured to perform a counting operation based on the comparison result and output a count value based on the counting operation, The multiplexer is further configured to perform a switching operation based on a count value of the counter.

6. The write clock bias generator according to claim 5, wherein: The resistor string includes a plurality of resistors, and The multiplexer includes: a plurality of switches, each of the plurality of switches being connected to a respective one of the plurality of nodes of the resistor string; and The decoder is configured to generate a plurality of signals for controlling the plurality of switches based on a count value of the counter.

7. The write clock bias generator according to claim 5, wherein: The second buffer includes: a first load resistor including a first terminal connected to a supply voltage; a first NMOS transistor including a first terminal connected to the second terminal of the first load resistor; a second load resistor including a first terminal connected to a supply voltage; a second NMOS transistor including a first terminal connected to the second terminal of the second load resistor; and a third NMOS transistor including a first terminal connected to the second terminal of the first NMOS transistor and the second terminal of the second NMOS transistor, the third NMOS transistor being driven based on a write clock bias, and The output voltage of the second buffer is output from a node between the second load resistor and the second NMOS transistor.

8. The write clock bias generator according to claim 5, wherein: Based on the output voltage switching a reference number of times, the write clock bias is determined to be locked.

9. The write clock bias generator according to claim 5, wherein: The write clock bias is determined to be locked based on the internal clock used by the counter toggling a reference number of times.

10. A memory device comprising: a buffer die configured to communicate with a memory controller via a plurality of channels; as well as a plurality of core dies disposed on the buffer die, each of the plurality of core dies including a memory cell array corresponding to at least one channel of the plurality of channels, The buffer die includes: a command / address receiver configured to receive a command and an address based on a clock signal received from at least one of the plurality of channels, a write clock buffer configured to receive a write clock through at least one of the plurality of channels, and A write clock bias generator is configured to provide a write clock bias to a write clock buffer, the write clock bias generator comprising: a voltage regulator configured to output a feedback voltage; a resistor string and a multiplexer configured to output a write clock bias based on the feedback voltage; a first string connected to the resistor string and comprising a first transistor; and a second string connected to the resistor string and comprising a second transistor and a third transistor, the second transistor being driven based on the feedback voltage. The first transistor and the third transistor are diode-connected transistors. The memory device according to claim 10 , wherein: The voltage regulator includes: an error amplifier configured to receive a reference voltage and a feedback voltage; a pass transistor configured to be driven based on an output of the error amplifier; and The feedback resistor is connected between the pass transistor and the first node, and the feedback voltage is output from the first node.

12. The memory device according to claim 10, wherein: The first string also includes a fourth transistor, which is a diode-connected transistor.

13. The memory device according to claim 10, wherein: The write clock bias generator further includes a third string connected to the resistor string and including resistors.

14. The memory device according to any one of claims 10 to 13, further comprising: The replica buffer is structurally identical to the write clock buffer; a comparator configured to compare an output voltage of the replica buffer with a target voltage and output a comparison result based on the comparison between the output voltage of the replica buffer and the target voltage; as well as The counter is configured to perform counting based on the comparison result to output a count value.

15. The memory device according to claim 14, wherein The resistor string includes a plurality of resistors, and The multiplexer includes: a plurality of switches, each switch of the plurality of switches connected to one of the plurality of nodes of the resistor string; and The decoder is configured to generate a plurality of signals for controlling the plurality of switches based on a count value of the counter.

16. The memory device according to claim 14, wherein The copy buffer includes: a first load resistor including a first terminal connected to a supply voltage; a first NMOS transistor including a first terminal connected to the second terminal of the first load resistor; a second load resistor including a first terminal connected to a supply voltage; a second NMOS transistor including a first terminal connected to the second terminal of the second load resistor; and a third NMOS transistor including a first terminal connected to the second terminal of the first NMOS transistor and the second terminal of the second NMOS transistor, the third NMOS transistor being bias-driven by a write clock, and The output voltage of the replica buffer is output from a node between the second load resistor and the second NMOS transistor.

17. A write clock bias generator, comprising: a voltage regulator configured to receive a reference voltage and output a feedback voltage; a voltage divider circuit configured to output a write clock bias based on a feedback voltage, the write clock bias varying based on a temperature change; as well as The compensation circuit is connected to the voltage divider circuit, and the compensation circuit includes: a first string connected to the voltage divider circuit and comprising a first transistor; and a second string connected to the voltage dividing circuit and including a second transistor and a third transistor, the second transistor being driven based on the feedback voltage, The first transistor and the third transistor are diode-connected transistors.

18. The write clock bias generator according to claim 17, wherein: The first string further includes a fourth transistor including a drain electrode and a gate electrode, the drain electrode being connected to the source electrode of the first transistor, and the gate electrode being connected to the drain electrode and the gate electrode of the first transistor.

19. The write clock bias generator according to claim 17, wherein: The compensation circuit further includes a third string connected to the voltage dividing circuit and including a resistor.

20. The write clock bias generator according to any one of claims 17 to 19, further comprising: a replica buffer configured to output an output voltage; a comparator configured to compare an output voltage of the replica buffer with a target voltage and output a comparison result based on the comparison between the output voltage of the replica buffer and the target voltage; as well as a counter configured to perform counting based on the comparison result and output the counting result, The voltage divider circuit is configured to adjust the level of the write clock bias based on a counting result of the counter.

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