Memory control method and storage device

Abstract

The invention provides a memory control method and a storage device. The method comprises the following steps: reading first data from a first entity unit in a memory module; after the first data is obtained from the memory module, on the premise that decoding operation is not executed on the first data through the decoding circuit, data quality analysis is executed on the first data so as to obtain a quality analysis result; and if the quality analysis result is a first result, directly starting a rereading operation aiming at the first entity unit so as to reread the first entity unit through the rereading voltage to obtain second data. Therefore, the data reading efficiency of the storage device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a memory control method and a storage device. Background Art

[0002] Flash memory (NAND flash) is a non-volatile memory widely used in electronic devices such as memory cards, solid-state drives (SSDs), and portable multimedia players. Solid-state drives (SSDs), a new type of storage medium, use NAND flash as their data storage medium and are widely used in various fields such as PCs, laptops, and servers. They are gradually replacing mechanical hard drives and becoming the mainstream application product in the storage field.

[0003] As NAND flash memory cell manufacturing processes move toward stacking architectures exceeding 300 layers, the threshold voltage distribution distortion problem in solid-state drives (SSDs) caused by multi-bit storage technology (QLC / PLC), device endurance degradation, and read / write crosstalk has become increasingly prominent, leading to an exponential increase in the raw bit error rate (RBER). The current mainstream solution uses a read retry mechanism that dynamically adjusts the read reference voltage (Vref) to compensate for voltage distribution deviation. Its core implementation methods include: (1) Off-chip ECC-dependent mode: The data page must be transferred to the off-chip ECC engine via the DMA channel for complete decoding, and the reread process is triggered only after the decoding fails. Experimental data shows that this process causes a 32%-47% decrease in effective bandwidth utilization (Micron ZNS SSD measured data); (2) Traversal voltage adjustment: Based on the manufacturer's preset Vref search sequence, multiple voltage points are traversed, which introduces additional delays; (3) Passive trigger mechanism: The reread operation is completely dependent on the ECC decoding result, and it is impossible to predict the page quality before the data is transmitted at the physical layer. According to JEDEC JESD219A standard testing, invalid transmission of unrecoverable data pages accounts for 19.7%-34.6% of the total channel bandwidth.

[0004] Therefore, there is an urgent need to develop a reread optimization solution with the ability to predict data quality, which can break through the systematic limitations of existing technologies in bandwidth efficiency and response speed by implementing non-decoding-dependent real-time quality assessment within the flash memory controller. Summary of the Invention

[0005] The present invention provides a memory control method and a memory device, which can improve the above-mentioned problem and further enhance the data reading efficiency of the memory device.

[0006] An embodiment of the present invention provides a memory control method for a storage device, wherein the storage device includes a memory module, and the memory control method includes: reading first data from a first physical unit in the memory module; after obtaining the first data from the memory module, performing data quality analysis on the first data without performing a decoding operation on the first data through a decoding circuit to obtain a quality analysis result; if the quality analysis result is a first result, directly initiating a reread operation on the first physical unit to re-read the first physical unit through a reread voltage to obtain second data; and if the quality analysis result is a second result, performing the decoding operation on the first data through the decoding circuit.

[0007] An embodiment of the present invention further provides a storage device comprising a connection interface, a memory module, and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory controller is used to: read first data from a first physical unit in the memory module; after obtaining the first data from the memory module, perform data quality analysis on the first data without performing a decoding operation on the first data through a decoding circuit to obtain a quality analysis result; if the quality analysis result is the first result, directly initiate a reread operation on the first physical unit to reread the first physical unit through a reread voltage to obtain second data; and if the quality analysis result is the second result, perform the decoding operation on the first data through the decoding circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0009] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0010] Figure 3 is a schematic diagram of a management memory module according to an embodiment of the present invention;

[0011] Figure 4 is a schematic diagram of comparing target data with reference data according to an embodiment of the present invention;

[0012] Figure 5 is a schematic diagram of parity checking according to an embodiment of the present invention;

[0013] Figure 6 is a schematic diagram of adjusting a reread voltage according to an embodiment of the present invention;

[0014] Figure 7 is a schematic diagram of a memory control circuit according to an embodiment of the present invention;

[0015] Figure 8 FIG. 4 is a flowchart of a memory control method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0016] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0017] Figure 1 Schematic diagram of a data storage system according to an embodiment of the present invention. Figure 1 The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, a tablet computer, a laptop computer, a desktop computer, an industrial computer, a game console, a server, or a computer system installed in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host system 11 is not limited to this. In addition, the storage device 12 can include a solid-state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0018] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 may support an embedded Multi-Media Card (eMMC), Universal Flash Storage (UFS), Peripheral Component Interconnect Express (PCI Express), Non-Volatile Memory Express (NVM express), Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 (e.g., exchange signals, instructions, and / or data) via the connection interface 121.

[0019] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of a voltage (also known as a threshold voltage). For example, the memory module 122 may include a single-level cell (SLC) NAND flash memory module, a multi-level cell (MLC) NAND flash memory module, a triple-level cell (TLC) NAND flash memory module, a quad-level cell (QLC) NAND flash memory module, and / or other memory modules having the same or similar characteristics.

[0020] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be considered the control core of the memory device 12 and is used to control the memory device 12. For example, the memory controller 123 can be used to control or manage all or part of the operation of the memory device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, a digital signal processor (DSP), a programmable controller, an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or other similar devices or a combination of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0021] The memory controller 123 can send a command sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write command sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read command sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase command sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can send other types of command sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, and the present invention is not limited thereto. The memory module 122 can receive the command sequence from the memory controller 123 and access the memory cells within the memory module 122 according to the command sequence.

[0022] Figure 2 FIG is a schematic diagram of a memory controller according to an embodiment of the present invention. Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0023] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 can be used to control or manage all or part of the operation of the memory controller 123. For example, the memory control circuit 23 can communicate with the host system 11 via the host interface 21 and access the memory module 122 via the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0024] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and is used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0025] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data accuracy. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check Code (LDPC code), BCH code, Reed-Solomon code (RS code), and Exclusive OR (XOR) code. In one embodiment, the memory controller 123 may also include various other types of circuit modules (such as power management circuits), and the present invention is not limited thereto.

[0026] Figure 3 FIG is a schematic diagram of a management memory module according to an embodiment of the present invention. Figures 1 to 3 The memory module 122 includes a plurality of physical units 301 ( 1 ) to 301 (B). Each physical unit includes a plurality of storage cells and is used for non-volatile data storage.

[0027] In one embodiment, a physical unit may include one or more physical programming units. A physical erase unit may include multiple physical programming units.

[0028] In one embodiment, a physical programming unit may include multiple physical sectors. For example, the data capacity of a physical sector may be 512 bytes (B), and a physical programming unit may include 32 physical sectors. However, the data capacity of a physical sector and / or the total number of physical sectors included in a physical programming unit may be adjusted according to practical needs and are not limited by the present invention. In one embodiment, a physical programming unit may be considered a physical page. For example, the storage capacity of a physical programming unit may be 16 kilobytes, but the present invention is not limited to this.

[0029] In one embodiment, a physical programming unit is the smallest unit to which data is written synchronously in the memory module 122. For example, when a programming operation (also referred to as a write operation) is performed on a physical programming unit to write data to the physical programming unit, multiple memory cells in the physical programming unit may be programmed synchronously to store corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to the physical programming unit to change the threshold voltage of at least some of the memory cells in the physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in the memory cell.

[0030] In one embodiment, multiple physical programming cells within a physical erase unit can be erased simultaneously. For example, when performing an erase operation on a physical erase unit, an erase voltage can be applied to multiple physical programming cells within the physical erase unit to change the threshold voltages of at least some of the memory cells within the physical programming cells. By performing an erase operation on a physical erase unit, data stored in the physical erase unit can be cleared. In one embodiment, a physical erase unit can be considered a physical block.

[0031] In one embodiment, the memory control circuit 23 can logically associate the physical units 301(1)-301(A) and 301(A+1)-301(B) with the data area 31 and the idle area 32, respectively. The physical units 301(1)-301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any physical unit in the data area 31 can store valid data and / or invalid data. In addition, the physical units 301(A+1)-301(B) in the idle area 32 do not store data (e.g., valid data).

[0032] In one embodiment, if a physical unit does not store valid data, the physical unit may be associated with the idle area 32. Furthermore, the physical units in the idle area 32 may be erased to clear the data in the physical units. In one embodiment, the physical units in the idle area 32 are also referred to as idle physical units. In one embodiment, the idle area 32 is also referred to as a free pool.

[0033] In one embodiment, when data is to be stored, the memory control circuit 23 may select one or more physical cells from the idle area 32 and instruct the memory module 122 to store the data in the selected physical cells. After the data is stored in the physical cells, the physical cells may be associated with the data area 31. In other words, one or more physical cells may be used alternately between the data area 31 and the idle area 32.

[0034] In one embodiment, the memory control circuit 23 may configure a plurality of logical units 302(1)-302(C) to map the physical units (i.e., physical units 301(1)-301(A)) in the data area 31. For example, a logical unit may correspond to a logical block address (LBA) or other logical management unit. A logical unit may be mapped to one or more physical units.

[0035] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 may determine that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is currently not mapped by any logical unit, the memory control circuit 23 may determine that the physical unit does not currently store any valid data.

[0036] In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical units and the physical units in at least one management table (also referred to as a logical-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data read, write, or erase based on the information in the management table (i.e., the logical-to-physical mapping table).

[0037] In one embodiment, the memory control circuit 23 may send a read instruction sequence to the memory module 122. The read instruction sequence is used to instruct to read data (also referred to as first data) from a physical unit (also referred to as a first physical unit) in the memory module 122. For example, according to the read instruction sequence, the memory module 122 may read the first data from the first physical unit based on a read voltage (also referred to as a preset read voltage) and transmit the first data to the memory control circuit 23. For example, the first physical unit may include Figure 3 At least one of the entity elements 301(1) to 301(A) in.

[0038] In one embodiment, after obtaining the first data from the memory module 122, the memory control circuit 23 may perform a data quality analysis on the first data, without performing a decoding operation on the first data through the decoding circuit 25, to obtain a quality analysis result. For example, without performing a decoding operation on the first data through the decoding circuit 25, the quality analysis result may (roughly) reflect the error rate and / or reliability of the first data. Based on the quality analysis result, the memory control circuit 23 may dynamically determine whether to directly initiate a reread operation on the first physical cell or to perform a decoding operation on the first data through the decoding circuit 25. For example, the reread operation may be used to reread data from the first physical cell using a reread voltage that is different from the aforementioned preset read voltage. Furthermore, the decoding operation may be used to decode the first data in an attempt to correct errors (e.g., erroneous bits) in the first data.

[0039] In one embodiment, if the quality analysis result is a certain result (also referred to as a first result), the memory control circuit 23 may directly initiate a reread operation on the first physical cell to reread the first physical cell using the reread voltage to obtain another data (also referred to as second data). For example, if the quality analysis result predicts that the error rate of the first data is relatively high (e.g., higher than an error rate threshold) and / or the reliability is relatively low (e.g., lower than a reliability threshold) (i.e., the quality analysis result is the first result), the memory control circuit 23 may directly initiate a reread operation on the first physical cell to resend a read command sequence to reread data from the first physical cell in an attempt to obtain second data having a relatively low error rate (e.g., lower than an error rate threshold) and / or a relatively high reliability (e.g., higher than a reliability threshold).

[0040] In one embodiment, a reread operation on the first physical unit is directly initiated in response to the aforementioned first result. If the error rate of the first data is relatively high (e.g., higher than an error rate threshold), the reliability is relatively low (e.g., lower than a reliability threshold), and / or the current estimated decoding success rate is relatively low (e.g., lower than a preset decoding success rate), the decoding operation on the first data may be skipped and the data may be reread. This can improve the data reading efficiency of the storage device.

[0041] In one embodiment, if the quality analysis result is another result (also referred to as a second result), the memory control circuit 23 may instruct the decoding circuit 25 to perform a decoding operation on the first data. For example, if the quality analysis result predicts that the error rate of the first data is relatively low (e.g., below an error rate threshold) and / or the reliability is relatively high (e.g., above a reliability threshold) (i.e., the quality analysis result is the second result), the memory control circuit 23 may instruct the decoding circuit 25 to perform a decoding operation on the first data, thereby attempting to decode the first data to obtain decoded data. For example, compared to the original data (i.e., the original first data), errors in the decoded data (i.e., the decoded first data) have been corrected.

[0042] In one embodiment, by directly performing a decoding operation on the first data in response to the aforementioned second result, errors in the first data can be quickly corrected by decisively performing a decoding operation when the error rate of the first data is relatively low (e.g., below an error rate threshold), the reliability is relatively high (e.g., above a reliability threshold), and / or the current decoding success rate is relatively high (e.g., above a preset decoding success rate). This can also improve the data reading efficiency of the storage device.

[0043] In other words, in one embodiment, after obtaining the first data from the memory module 122, the first data will not be directly input into the decoding circuit 25 for decoding (i.e., performing a decoding operation). On the contrary, after obtaining the first data from the memory module 122, before inputting the first data into the decoding circuit 25 (i.e., without performing a decoding operation on the first data through the decoding circuit 25), the memory control circuit 23 may first perform a data quality analysis on the first data to obtain the quality analysis result. In particular, the data quality analysis for the first data does not involve the operation of the decoding circuit 25. Then, based on the current situation (e.g., the quality analysis result), it is dynamically determined whether to directly initiate a reread operation for the first physical unit or to perform a decoding operation on the first data through the decoding circuit 25. In this way, the data reading efficiency of the storage device 12 can be significantly improved.

[0044] In one embodiment, after obtaining the first data from the memory module 122, the memory control circuit 23 may read the reference data from the management table according to the logical unit to which the first data belongs (also referred to as the first logical unit). For example, the first logical unit is mapped to the first physical unit. For example, the first logical unit may include Figure 3 At least one of the logic units 302(1) to 302(C) in.

[0045] In one embodiment, the reference data includes feature data corresponding to the first data. This feature data is obtained by performing feature extraction on the first data during the storage of the first data. For example, during the period when the data belonging to the first logical unit (i.e., the first data) is previously stored in the memory module 122, the memory control circuit 23 may perform feature extraction on the first data (i.e., extract data features from the first data) to obtain the reference data corresponding to the first data. For example, the reference data (or feature data) may reflect the data features of at least part of the first data. After obtaining the reference data, the memory control circuit 23 may record the reference data in the management table by binding or matching the reference data with the first logical unit.

[0046] Thereafter, while performing data quality analysis on the first data, the memory control circuit 23 may retrieve the reference data from the management table. For example, the memory control circuit 23 may query the management table based on the identification information of the first logical unit (e.g., the logical unit number or address information) to retrieve the reference data associated with or matching the first logical unit. The memory control circuit 23 may then perform data quality analysis on the first data based on the reference data.

[0047] In one embodiment, after obtaining the reference data, the memory control circuit 23 may compare the first data with the reference data to obtain the quality analysis result. For example, without processing the first data by the decoding circuit 25, the memory control circuit 23 may compare the first data with the reference data to obtain an evaluation value (also referred to as a first evaluation value). For example, without processing the first data by the decoding circuit 25, the memory control circuit 23 may compare each bit in the first data with each bit in the reference data to confirm whether the two are identical. The memory control circuit 23 may then obtain the first evaluation value based on the comparison results.

[0048] In one embodiment, the first evaluation value may reflect the degree of difference between the first data and the reference data. For example, the first evaluation value may be positively correlated with the degree of difference between the first data and the reference data. That is, a larger first evaluation value indicates a greater degree of difference between the first data and the reference data (i.e., a smaller total number of identical bits between the first data and the reference data).

[0049] In one embodiment, the memory control circuit 23 may determine a relative numerical relationship between the first evaluation value and a threshold value (also referred to as the first threshold value) based on the first evaluation value. The memory control circuit 23 may then obtain the quality analysis result based on this relative numerical relationship. For example, the memory control circuit 23 may obtain a corresponding quality analysis result based on different relative numerical relationships between the first evaluation value and the first threshold value (e.g., the first evaluation value is greater than the first threshold value, the first evaluation value is less than the first threshold value, or the first evaluation value is equal to the first threshold value).

[0050] In one embodiment, if the numerical relative relationship reflects that the first evaluation value is greater than the first critical value, the memory control circuit 23 may determine that the degree of difference between the first data and the reference data is relatively large (for example, greater than the critical degree). If the numerical relative relationship reflects that the first evaluation value is less than the first critical value, the memory control circuit 23 may determine that the degree of difference between the first data and the reference data is relatively small (for example, less than the critical degree). In addition, if the numerical relative relationship reflects that the first evaluation value is equal to the first critical value, the memory control circuit 23 may determine that the degree of difference between the first data and the reference data is neither large nor small (for example, approaching the critical degree). Thereafter, the memory control circuit 23 may determine the quality analysis result based on the numerical relative relationship (or the degree of difference between the first data and the reference data). In other words, the quality analysis result may reflect the degree of difference between the first data and the reference data.

[0051] In one embodiment, the degree of difference (or first evaluation value) between the first data and the reference data may be positively correlated with the error rate of the first data and / or negatively correlated with the reliability of the first data. That is, if the degree of difference (or first evaluation value) between the first data and the reference data is relatively large (e.g., the first evaluation value is greater than a first threshold), the memory control circuit 23 may determine that the error rate of the first data is relatively high (e.g., greater than an error rate threshold) and / or the reliability of the first data is relatively low (e.g., less than a reliability threshold). Conversely, if the degree of difference (or first evaluation value) between the first data and the reference data is relatively small (e.g., the first evaluation value is less than a first threshold), the memory control circuit 23 may determine that the error rate of the first data is relatively low (e.g., less than an error rate threshold) and / or the reliability of the first data is relatively high (e.g., greater than a reliability threshold).

[0052] In one embodiment, the memory control circuit 23 may determine a sampling window (also referred to as a dynamic sampling window) based on the first logical unit. For example, the management table may record configuration information of a dynamic sampling window corresponding to or matching the first logical unit. The memory control circuit 23 may then query the management table based on the first logical unit to determine the dynamic sampling window. The memory control circuit 23 may then determine at least a portion of the data (also referred to as target data) from the first data based on the dynamic sampling window.

[0053] In one embodiment, after determining the target data, the memory control circuit 23 may compare the target data with the reference data to obtain the quality analysis result. For example, the quality analysis result (or first evaluation value) may reflect the degree of difference between the target data and the reference data.

[0054] Figure 4 is a schematic diagram of comparing target data with reference data according to an embodiment of the present invention. Figure 4 In one embodiment, assume that the first data includes data 41. After reading data 41 from memory module 122, memory control circuit 23 may query the management table to determine a sampling window W (i.e., a dynamic sampling window). For example, sampling window W is used to define a bit range R (also referred to as a target bit range) in data 41.

[0055] In one embodiment, after determining the sampling window W, the memory control circuit 23 may determine or identify (all) data in the data 41 that are within the bit range R as target data 401 based on the sampling window W. At the same time, the memory control circuit 23 may determine or identify (all) data in the data 41 that are not within the bit range R as non-target data 402 based on the sampling window W. Then, the memory control circuit 23 may compare the target data 401 in the data 41 that are within the bit range R with the reference data 42 to obtain a comparison result (or a first evaluation value). For example, this comparison result (or first evaluation value) may reflect the degree of difference between the target data 401 and the reference data 42. Then, the memory control circuit 23 may obtain the quality analysis result based on this comparison result. In other words, Figure 4 In the embodiment, the quality analysis result may reflect the degree of difference between the target data 401 and the reference data 42 .

[0056] It should be noted that in Figure 4 In the embodiment, the overall error rate and / or reliability of the data 41 is evaluated based on the degree of difference between the target data 401 and the reference data 42. However, depending on the type of data 41, the relative position of the sampling window W (or bit range R) in the data 41 and / or the total number of sampling windows W (or bit range R) can be adjusted according to practical needs.

[0057] In one embodiment, after obtaining the first data from the memory module 122, the memory control circuit 23 may further perform a parity check on the first data to obtain another evaluation value (also referred to as a second evaluation value). The second evaluation value may reflect the error rate and / or reliability of the first data. For example, the second evaluation value may be positively correlated with the error rate of the first data and / or negatively correlated with the reliability of the first data. That is, a larger second evaluation value indicates a higher error rate of the first data and / or a lower reliability of the first data. The memory control circuit 23 may then obtain the quality analysis result based on the second evaluation value. It should be noted that the parity check may be performed by the memory control circuit 23, but not by the decoding circuit 25.

[0058] Figure 5 FIG is a schematic diagram of parity checking according to an embodiment of the present invention. Figure 5 In one embodiment, the memory control circuit 23 may obtain a matrix 51 (also referred to as a parity check matrix H) and assume that the first data includes a data vector 52. For example, the matrix 51 may be a (j+1)×(i+1) matrix, where i and j may be set as needed. Each element in the matrix 51 may be "1" or "0." Furthermore, the data vector 52 includes bits V(0) to V(j).

[0059] In one embodiment, during the parity check, the memory control circuit 23 may perform a matrix multiplication on the matrix 51 and the data vector 52 to obtain a check vector 53. For example, the check vector 53 may reflect the result of performing the matrix multiplication on the matrix 51 and the data vector 52. For example, the check vector 53 includes a plurality of elements S(0) to S(j). The elements S(0) to S(j) may also be referred to as syndromes. For example, each of the elements S(0) to S(j) may be "1" or "0."

[0060] In one embodiment, the memory control circuit 23 may obtain the quality analysis result based on the check vector 53. For example, the memory control circuit 23 may extract elements S(0) to S(j) from the check vector 53 and obtain the sum of the elements S(0) to S(j). For example, the sum of the elements S(0) to S(j) may reflect (or be the same as) the total number of "1"s in the elements S(0) to S(j). In particular, the sum of the elements S(0) to S(j) may reflect the error rate and / or reliability of the first data. For example, if the sum of the elements S(0) to S(j) is larger, it means that the error rate of the first data is higher and / or the reliability of the first data is lower.

[0061] In one embodiment, the memory control circuit 23 may obtain the quality analysis result based on the sum of the elements S(0)-S(j). In one embodiment, the memory control circuit 23 may obtain a second evaluation value based on the sum of the elements S(0)-S(j). For example, the second evaluation value may be the same as or positively correlated with the sum of the elements S(0)-S(j). Then, the memory control circuit 23 may obtain the quality analysis result based on the second evaluation value.

[0062] In one embodiment, the memory control circuit 23 may determine a relative numerical relationship between the second evaluation value and a threshold value (also referred to as the second threshold value) based on the second evaluation value. The memory control circuit 23 may then obtain the quality analysis result based on this relative numerical relationship. For example, the memory control circuit 23 may obtain a corresponding quality analysis result based on different relative numerical relationships between the second evaluation value and the second threshold value (e.g., the second evaluation value is greater than the second threshold value, the second evaluation value is less than the second threshold value, or the second evaluation value is equal to the second threshold value).

[0063] In one embodiment, if the numerical relative relationship reflects that the second evaluation value is greater than the second critical value, the memory control circuit 23 may determine that the error rate of the first data is relatively high (for example, higher than the error rate critical value) and / or the reliability of the first data is relatively low (for example, lower than the reliability critical value). If the numerical relative relationship reflects that the second evaluation value is less than the second critical value, the memory control circuit 23 may determine that the error rate of the first data is relatively low (for example, lower than the error rate critical value) and / or the reliability of the first data is relatively high (for example, higher than the reliability critical value). Thereafter, without involving the decoding circuit 25 in processing the first data, the memory control circuit 23 may determine, based on the quality analysis result, whether to directly initiate a reread operation for the first physical unit or to perform a decoding operation on the first data through the decoding circuit 25. In this way, the data reading efficiency of the storage device 12 can be significantly improved.

[0064] In one embodiment, after obtaining the second data, the memory control circuit 23 may further compare the first data with the second data to obtain a comparison result. This comparison result may reflect the difference between the first data and the second data. The memory control circuit 23 may then adjust the reread voltage used for the reread operation based on this comparison result. This can further reduce errors in the read data during a reread operation that skips decoding the first data and directly executes the reread operation, thereby improving the data read efficiency of the memory device 12.

[0065] In one embodiment, if the comparison result indicates that the data difference between the first data and the second data is decreasing, it means that the first data and the second data are converging. In this case, the memory control circuit 23 may maintain the current voltage adjustment direction for the reread voltage. For example, assuming that the current voltage adjustment direction for the reread voltage is to gradually increase the voltage value of the reread voltage. If the comparison result indicates that the data difference between the first data and the second data is decreasing, the memory control circuit 23 may not change the current voltage adjustment direction for the reread voltage (i.e., gradually increase the voltage value of the reread voltage).

[0066] In one embodiment, if the comparison result indicates that the data difference between the first data and the second data is increasing, it means that the difference between the first data and the second data is increasing. In this case, the memory control circuit 23 may change the current voltage adjustment direction for the reread voltage. For example, assuming that the current voltage adjustment direction for the reread voltage is to gradually increase the voltage value of the reread voltage. If the comparison result indicates that the data difference between the first data and the second data is increasing, the memory control circuit 23 may switch to gradually decreasing the voltage value of the reread voltage. Alternatively, assuming that the current voltage adjustment direction for the reread voltage is to gradually decrease the voltage value of the reread voltage. If the comparison result indicates that the data difference between the first data and the second data is increasing, the memory control circuit 23 may switch to gradually increasing the voltage value of the reread voltage.

[0067] Figure 6 is a schematic diagram showing adjustment of the reread voltage according to an embodiment of the present invention. Figure 6 , assuming that the threshold voltage distribution of the plurality of memory cells in the first physical unit includes states 61 and 62. States 61 and 62 correspond to different bits (or bit combinations).

[0068] In one embodiment, assume that first data is read from a first physical cell based on a read voltage 601, and in a reread operation on the first physical cell, second data is read from the first physical cell based on a read voltage 602. After comparing the first data with the second data, if the comparison result indicates that the data difference between the first data and the second data gradually increases, this indicates that the current voltage adjustment direction of adding the voltage difference ΔV to the read voltage 601 to obtain the read voltage 602 is incorrect. In this case, the memory control circuit 23 may change the current voltage adjustment direction for the reread voltage, for example, by subtracting the voltage difference ΔV from the read voltage 601 to obtain the read voltage 603. In a subsequent reread operation on the first physical cell, the error rate of the data read from the first physical cell based on the read voltage 603 is more likely to be lower than the error rate of the data read from the first physical cell based on the read voltage 602 (and / or 601). Alternatively, in a subsequent reread operation on the first physical cell, the reliability of the data read from the first physical cell based on the read voltage 603 is likely to be higher than the reliability of the data read from the first physical cell based on the read voltage 602 (and / or 601). Thus, in a reread operation that skips decoding the first data and directly executes the reread operation, errors in the read data can be further reduced, thereby improving the data reading efficiency of the storage device 12.

[0069] In one embodiment, after obtaining the second data, the memory control circuit 23 may perform the data quality analysis on the second data to update the quality analysis result without performing a decoding operation on the second data by the decoding circuit 25. It should be noted that the relevant operational details regarding how to perform the data quality analysis on specific data (e.g., the first data and / or the second data) to obtain or update the quality analysis result have been described above and will not be repeated here.

[0070] In one embodiment, after updating the quality analysis result, if the updated quality analysis result is the aforementioned first result (e.g., if the error rate of the second data is predicted to be relatively high (e.g., higher than an error rate threshold) and the reliability is relatively low (e.g., lower than a reliability threshold)), and / or the current decoding success rate is assessed to be relatively low (e.g., lower than a predetermined decoding success rate), the memory control circuit 23 may re-initiate a reread operation on the first physical unit to attempt to re-read data with a lower error rate and / or higher reliability (also referred to as third data) directly based on a different reread voltage before decoding the second data via the decoding circuit 25. This can improve the data reading efficiency of the memory device 12.

[0071] On the other hand, if the updated quality analysis result is the aforementioned second result (e.g., if the error rate of the second data is predicted to be relatively low (e.g., below the error rate threshold) and / or the reliability is relatively high (e.g., above the reliability threshold)), the memory control circuit 23 may perform a decoding operation on the first data via the decoding circuit 25. Thus, while ensuring that the current decoding success rate is relatively high (e.g., above the reliability threshold), errors in the second data can be quickly corrected by decisively performing a decoding operation. This also improves the data reading efficiency of the storage device 12.

[0072] In one embodiment, the first data and the second data may also refer to any two data sequentially read from the first physical unit (or memory module 122) based on different reread voltages during the reread operation. The remaining operation details have been described above and will not be repeated here.

[0073] Figure 7 FIG is a schematic diagram of a memory control circuit according to an embodiment of the present invention. Figure 7In one embodiment, the memory control circuit 23 may include at least two of an XOR logic gate array 71, a bit flip counter 72, and a threshold comparator 73 to support the aforementioned data quality analysis. For example, the XOR logic gate array 71 is configured to perform a bit-by-bit comparison between two data items and output the comparison result. The bit flip counter 72 is configured to count the total number of different bits at the same position between the two data items. The threshold comparator 73 is configured to compare the total number with a threshold value to obtain a comparison result.

[0074] In one embodiment, the XOR logic gate array 71, the bit flip counter 72, and / or the threshold comparator 73 may also provide corresponding computational behavior based on their own performance. In one embodiment, the memory control circuit 23 may also include other types of circuit modules (e.g., a matrix multiplication circuit module). This allows the memory control circuit 23 to perform the aforementioned data quality analysis without requiring the decoding circuit 25.

[0075] Figure 8 FIG is a flow chart of a memory control method according to an embodiment of the present invention. Figure 8 In step S801, first data is read from a first physical unit in a memory module. After obtaining the first data from the memory module, in step S802, data quality analysis is performed on the first data without performing a decoding operation on the first data through a decoding circuit to obtain a quality analysis result. In step S803, it is determined whether the quality analysis result is the first result (or the second result). If the quality analysis result is the first result, in step S804, a reread operation is directly initiated for the first physical unit to reread the first physical unit through a reread voltage to obtain the second data. However, if the quality analysis result is not the first result (i.e., the second result), in step S805, a decoding operation is performed on the first data through a decoding circuit.

[0076] However, Figure 8 The steps have been described in detail above and will not be repeated here. Figure 8 Each step can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Figure 8 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0077] In summary, the control method and storage device proposed in the embodiments of the present invention can improve technical issues such as poor decoding efficiency and / or occupied transmission bandwidth between the decoding circuit and the memory control circuit, which is caused by the indiscriminate transmission of data read from the memory module to the decoding circuit for decoding, thereby improving the overall data reading efficiency of the storage device.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory control method, characterized in that: For use in a storage device, wherein the storage device includes a memory module, and the memory control method includes: Reading first data from a first physical unit in the memory module; After obtaining the first data from the memory module, without performing a decoding operation on the first data by a decoding circuit, performing data quality analysis on the first data to obtain a quality analysis result; If the quality analysis result is the first result, directly starting a reread operation on the first physical cell to reread the first physical cell using a reread voltage to obtain second data; and If the quality analysis result is the second result, the decoding operation is performed on the first data by the decoding circuit.

2. The memory control method according to claim 1 , wherein the step of performing the data quality analysis on the first data to obtain the quality analysis result comprises: Reading reference data from a management table according to a first logical unit, wherein the first logical unit is mapped to the first physical unit, the reference data including feature data corresponding to the first data, and the feature data being obtained by performing feature extraction on the first data during storage of the first data; as well as The first data is compared with reference data to obtain the quality analysis result.

3. The memory control method according to claim 2 , wherein the step of comparing the first data with the reference data to obtain the quality analysis result comprises: comparing the first data with reference data to obtain a first evaluation value, wherein the first evaluation value reflects a degree of difference between the first data and the reference data; as well as The quality analysis result is obtained according to the relative numerical relationship between the first evaluation value and the critical value.

4. The memory control method according to claim 2 , wherein the step of comparing the first data with the reference data to obtain the quality analysis result comprises: determining a dynamic sampling window according to the first logic unit; determining target data from the first data according to the dynamic sampling window; as well as The target data is compared with the reference data to obtain the quality analysis result.

5. The memory control method according to claim 1 , wherein the step of performing the data quality analysis on the first data to obtain the quality analysis result comprises: performing a parity check on the first data to obtain a second evaluation value, wherein the parity check is not performed by the decoding circuit; as well as The quality analysis result is obtained according to the second evaluation value.

6. The memory control method according to claim 1 , further comprising: After obtaining the second data, comparing the first data with the second data to obtain a comparison result; as well as The reread voltage is adjusted according to the comparison result.

7. The memory control method according to claim 6 , wherein the step of adjusting the re-read voltage according to the comparison result comprises: If the comparison result indicates that the data difference between the first data and the second data increases, the voltage adjustment direction of the re-read voltage is changed.

8. The memory control method according to claim 1 , further comprising: After obtaining the second data, without performing the decoding operation on the second data by a decoding circuit, performing the data quality analysis on the second data to update the quality analysis result; If the updated quality analysis result is the first result, restarting the rereading operation on the first physical unit; as well as If the updated quality analysis result is the second result, the decoding operation is performed on the second data by the decoding circuit. 9 . The memory control method according to claim 1 , wherein the step of performing the data quality analysis on the first data to obtain the quality analysis result is performed by a memory control circuit inside the memory device. 10 . The memory control method according to claim 9 , wherein the memory control circuit comprises at least two of an XOR logic gate array, a bit flip counter, and a threshold comparator to support the data quality analysis.

11. A storage device, characterized in that: include: A connection interface for connecting to a host system; Memory module; as well as a memory controller connected to the connection interface and the memory module, The memory controller is configured to: Reading first data from a first physical unit in the memory module; After obtaining the first data from the memory module, without performing a decoding operation on the first data by a decoding circuit, performing data quality analysis on the first data to obtain a quality analysis result; If the quality analysis result is the first result, directly starting a reread operation on the first physical unit to reread the first physical unit using a reread voltage to obtain second data; as well as If the quality analysis result is the second result, the decoding operation is performed on the first data by the decoding circuit.

12. The storage device according to claim 11, wherein the memory controller performs the data quality analysis on the first data to obtain the quality analysis result, comprising: Reading reference data from a management table according to a first logical unit, wherein the first logical unit is mapped to the first physical unit, the reference data including feature data corresponding to the first data, and the feature data being obtained by performing feature extraction on the first data during storage of the first data; as well as The first data is compared with reference data to obtain the quality analysis result.

13. The storage device according to claim 12, wherein the operation of the memory controller comparing the first data with the reference data to obtain the quality analysis result comprises: comparing the first data with reference data to obtain a first evaluation value, wherein the first evaluation value reflects a degree of difference between the first data and the reference data; as well as The quality analysis result is obtained according to the relative numerical relationship between the first evaluation value and the critical value.

14. The storage device according to claim 12, wherein the memory controller compares the first data with the reference data to obtain the quality analysis result, comprising: determining a dynamic sampling window according to the first logic unit; determining target data from the first data according to the dynamic sampling window; as well as The target data is compared with the reference data to obtain the quality analysis result.

15. The storage device according to claim 11, wherein the memory controller performs the data quality analysis on the first data to obtain the quality analysis result, comprising: performing a parity check on the first data to obtain a second evaluation value, wherein the parity check is not performed by the decoding circuit; as well as The quality analysis result is obtained according to the second evaluation value.

16. The storage device according to claim 11, wherein the memory controller is further configured to: After obtaining the second data, comparing the first data with the second data to obtain a comparison result; and The reread voltage is adjusted according to the comparison result.

17. The memory device according to claim 16, wherein the memory controller adjusts the re-read voltage according to the comparison result, comprising: If the comparison result indicates that the data difference between the first data and the second data increases, the voltage adjustment direction of the re-read voltage is changed.

18. The storage device according to claim 11, wherein the memory controller is further configured to: After obtaining the second data, without performing the decoding operation on the second data by a decoding circuit, performing the data quality analysis on the second data to update the quality analysis result; If the updated quality analysis result is the first result, restarting the rereading operation on the first physical unit; as well as If the updated quality analysis result is the second result, the decoding operation is performed on the second data by the decoding circuit.

19. The storage device according to claim 11, wherein the memory controller performs the data quality analysis on the first data to obtain the quality analysis result, which is performed by a memory control circuit within the memory controller. 20 . The memory device of claim 19 , wherein the memory control circuit comprises at least two of an XOR logic gate array, a bit flip counter, and a threshold comparator to support the data quality analysis.

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