Packaging structure and electronic equipment

Abstract

According to the packaging structure and the electronic equipment provided by the invention, separation of power supply wiring and signal wiring is realized, the wiring density and the degree of freedom are greatly improved, the utilization rate of the first interconnection layer and the second interconnection layer is improved, and thus the signal quality and the power supply quality can be improved. The packaging structure can comprise a first interconnection layer, a first chip and a second interconnection layer which are arranged in a stacked mode in the first direction. Wherein the first interconnection layer can be used for providing power supply wiring for the first chip. The second interconnection layer can be used for providing signal wiring for the first chips and can also be used for providing a supporting effect for the first chips so as to reduce the stress of gaps between different first chips.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more particularly, to a packaging structure and an electronic device. Background Art

[0002] In order to fix, seal, protect the bare chip (die), or to improve the electrical performance of the bare chip, it is often necessary to use a packaging process to package the bare chip to form a packaging structure, which can also improve the integration of the packaging structure and reduce the area of ​​the packaging structure.

[0003] The packaging structure provided by the related art can be a fan-out package (FOP) structure (which can be referred to as the FOP structure) and a die on interposer on substrate (DOIOS) structure (which can be referred to as the DOIOS structure). Among them, in the FOP structure, the power lines and signal lines are both led out through the redistribution layer (RDL). In the DOIOS structure, the power lines and signal lines are both led out through the interposer. Compared with the FOP structure, the DOIOS structure has a relatively high routing density and a shorter power supply path, which can guarantee the power quality to a certain extent. However, in the FOP structure and the DOIOS structure, the power lines and signal lines are not separated, which greatly limits the density and freedom of wiring in the packaging structure, resulting in low utilization of the redistribution layer or the interposer (which can be collectively referred to as the interconnection layer), resulting in poor signal quality and power quality. Summary of the Invention

[0004] In order to overcome the above-mentioned shortcomings, the present application provides a packaging structure and an electronic device to realize the separation of power routing and signal routing, greatly improve the wiring density and freedom, and improve the utilization rate of the first interconnection layer and the second interconnection layer, thereby improving the signal quality and power quality.

[0005] In a first aspect, the present application provides a packaging structure, which may include a first interconnection layer, a first chip, and a second interconnection layer stacked along a first direction.

[0006] The first interconnect layer may be used to: provide power routing for the first chip (which may be a bare chip, that is, a packaged chip);

[0007] The second interconnection layer can be used to provide signal routing for the first chip.

[0008] It can be seen that the present application provides power routing for the first chip through the first interconnection layer and provides signal routing for the first chip through the second interconnection layer, that is, the separation of power routing and signal routing is achieved through the first interconnection layer and the second interconnection layer, which not only greatly improves the wiring density and freedom, and improves the utilization rate of the first interconnection layer and the second interconnection layer, but also reduces the crosstalk between the power routing and the signal routing, thereby improving the signal quality and power quality.

[0009] In a possible implementation, the first interconnect layer may be made of a dielectric material such as polyimide and provided with a power supply line, wherein the power supply line may be made of a metal material such as copper.

[0010] In another possible implementation, the second interconnect layer may be made of the first dielectric material and provided with signal traces, wherein the signal traces may be made of metal materials such as copper.

[0011] Optionally, the first dielectric material may be a silicon-based semiconductor material such as silicon, silicon oxide, silicon nitride, or silicon carbide. The first dielectric material may also be a dielectric material such as polyimide. The dielectric material may be an organic dielectric material. Of course, the first dielectric material may also be other materials, and this application does not limit this.

[0012] In yet another possible implementation, the packaging structure may further include a plurality of first connectors.

[0013] The first end of each of the multiple first connectors can be connected to the first chip, and the second end of each first connector can be connected to the second interconnect layer. As can be seen, the first connectors can connect the first chip and the second interconnect layer. A second dielectric material is provided between the multiple first connectors. The second dielectric material can be epoxy resin, for example, and can provide insulation, thereby isolating the multiple first connectors.

[0014] Exemplarily, the package structure may include a plurality of first chips. The plurality of first chips may be disposed on the first interconnect layer in the same layer, with a gap between two adjacent first chips in the plurality of first chips.

[0015] Therefore, the second interconnect layer can be used to adjust the stress of the gap. In other words, the support of the second interconnect layer can reduce the stress of two adjacent first chips, thereby reducing the stress of the first chips and improving the reliability of the entire packaging structure.

[0016] Optionally, the package structure may further include a dielectric layer. The dielectric layer may be disposed on a surface of the second interconnect layer along a first direction. The surface of the second interconnect layer may be used to indicate that the second interconnect layer is away from the surface of the first chip. The dielectric layer may be made of a material such as resin or silicon to protect and support the second interconnect layer.

[0017] Furthermore, the package structure may further include a second chip. The second chip may be disposed on a surface of the second interconnection layer along the first direction.

[0018] The second chip can be used to connect two adjacent first chips among the plurality of first chips. Therefore, the second chip can also be called an interconnection chip.

[0019] It is conceivable that the number of second chips can be determined according to the number of first chips, and this application does not limit this.

[0020] Optionally, the packaging structure may further include a plurality of second connecting members.

[0021] The first end of each of the plurality of second connectors can be connected to the second interconnect layer, and the second end of each of the second connectors can be connected to the second chip. As can be seen, the second connectors can serve to connect the second chip and the second interconnect layer. A third dielectric material can be provided between the plurality of second connectors. Similar to the second dielectric material, the third dielectric material can be epoxy resin, etc., and can provide insulation, thereby isolating the plurality of second connectors.

[0022] In one possible implementation, the package structure may further include a third chip. The third chip may be disposed on a surface of the second interconnect layer along the first direction. The second chip and the third chip may be disposed on the same layer.

[0023] The third chip can be used to dissipate heat for the first chip. Therefore, the third chip can also be called a heat dissipation chip.

[0024] Furthermore, the packaging structure may further include a plurality of third connecting members.

[0025] The first end of each of the multiple third connectors can be connected to the second interconnect layer, and the second end of each third connector can be connected to the third chip. As can be seen, the third connectors can connect the third chip to the second interconnect layer. A fourth dielectric material is provided between the multiple third connectors. Similar to the second and third dielectric materials, the fourth dielectric material can be epoxy resin, etc., and can provide insulation, thereby isolating the multiple third connectors.

[0026] Optionally, the first connecting member, the second connecting member, and the third connecting member may all be made of metal materials such as copper. Of course, other conductive metal materials may also be used, which is not limited in this application.

[0027] In some possible implementations, the first chip may be provided with through silicon vias (TSVs), and the TSVs may contain metal materials such as copper, thereby realizing power supply, signal input, and signal output of the first chip.

[0028] The package structure provided herein may further include a dielectric material such as epoxy resin disposed between the first interconnect layer and the second interconnect layer, surrounding the first chip. The dielectric material may include through molding vias (TMVs). The TMVs may include metal materials such as copper to facilitate signal input and output from the first chip. These signals may include serial and deserialization signals.

[0029] In a second aspect, the present application provides an electronic device, which may include a substrate and a packaging structure provided by the first aspect and possible implementations thereof. The packaging structure may be provided on the substrate.

[0030] Optionally, the electronic device may be a base station, a mobile phone, etc., which is not limited in this application.

[0031] It should be understood that the second aspect of this application is consistent with the technical solution of the first aspect of this application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation methods are similar, which will not be repeated. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the present application or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 A schematic structural diagram of a packaging structure in an embodiment of the present application;

[0034] Figure 2 is another schematic structural diagram of the packaging structure in an embodiment of the present application;

[0035] Figure 3 A schematic diagram of the paths of power supply, input signal, and output signal of the packaging structure in an embodiment of the present application;

[0036] Figure 4 A schematic diagram of the paths of power supply, input signal, and output signal of the packaging structure in an embodiment of the present application;

[0037] Figure 5 This is a schematic structural diagram of an electronic device in an embodiment of the present application. DETAILED DESCRIPTION

[0038] The technical solution in this application will be described below with reference to the accompanying drawings.

[0039] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0040] The terms "first," "second," and the like in the description, embodiments, claims, and drawings of this application are used solely for descriptive purposes and are not to be construed as indicating or implying relative importance or order. Furthermore, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions, such as, for example, inclusion of a series of steps or units. A method, system, product, or apparatus is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0041] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0042] In order to fix, seal, protect the bare chip (die), or to improve the electrical performance of the bare chip, it is often necessary to use a packaging process to package the bare chip to form a packaging structure, which can also improve the integration of the packaging structure and reduce the area of ​​the packaging structure.

[0043] The packaging structure provided by the related art can be a fan-out package (FOP) structure (which can be referred to as the FOP structure) and a die on interposer on substrate (DOIOS) structure (which can be referred to as the DOIOS structure). Among them, in the FOP structure, the power lines and signal lines are both led out through the redistribution layer (RDL). In the DOIOS structure, the power lines and signal lines are both led out through the interposer. Compared with the FOP structure, the DOIOS structure has a relatively high routing density and a shorter power supply path, which can guarantee the power quality to a certain extent. However, in the FOP structure and the DOIOS structure, the power lines and signal lines are not separated, which greatly limits the density and freedom of wiring in the packaging structure, resulting in low utilization of the redistribution layer or the interposer (which can be collectively referred to as the interconnection layer), resulting in poor signal quality and power quality.

[0044] In order to overcome the above shortcomings, the present invention provides a packaging structure, such as Figure 1 The package structure 100 may include a first direction (which may be Figure 1 A first interconnection layer 1, a plurality of first chips (which may be bare chips, that is, packaged chips) and a second interconnection layer 2 are stacked (in a thickness direction in FIG).

[0045] The plurality of first chips may include chip 31, chip 32 and chip 33. Figure 1 Chip 31, chip 32, and chip 33 can be arranged on the same layer on the first interconnect layer 1. There is a gap G1 between chip 31 and chip 32, and there is a gap G2 between chip 32 and chip 33. In other words, there is a gap between two adjacent first chips. Of course, there can be only one first chip, but the present embodiment uses multiple chips as an example for description.

[0046] Chip 31 , chip 32 and chip 33 may all be provided with through silicon vias (TSVs), which may contain metal materials such as copper, thereby realizing power supply, signal input and signal output of chip 31 , chip 32 and chip 33 .

[0047] Optionally, the first interconnection layer 1 may be used to provide power supply lines for the chip 31 , the chip 32 , and the chip 33 .

[0048] The second interconnect layer 2 can be used to provide signal routing for chips 31, 32, and 33. It is conceivable that providing signal routing for the second interconnect layer 2 can reduce the number of layers of the first interconnect layer 1, thereby reducing the cost of the entire package structure 100.

[0049] It can be seen that the embodiment of the present application can provide power lines for chips 31, 32 and 33 through the first interconnection layer 1, and provide signal lines for chips 31, 32 and 33 through the second interconnection layer 2, that is, the separation of power lines and signal lines is achieved through the first interconnection layer 1 and the second interconnection layer 2, which not only greatly improves the wiring density and freedom, and improves the utilization rate of the first interconnection layer 1 and the second interconnection layer 2, but also reduces the crosstalk between the power lines and the signal lines, thereby improving the signal quality and power quality of the packaging structure 100.

[0050] In some embodiments, the first interconnect layer 1 can be made of a dielectric material such as polyimide and be provided with a power supply line. The power supply line can be made of a metal material such as copper. The first interconnect layer 1 can be called a redistribution layer (RDL). Of course, the first interconnect layer 1 can also be made of other dielectric materials, and the power supply line can also be made of other metal materials, which are not limited in the present embodiment.

[0051] In other embodiments, the second interconnect layer 2 may be made of a first dielectric material and provided with signal traces, wherein the signal traces may be made of a metal material such as copper.

[0052] Optionally, the first dielectric material can be a silicon-based semiconductor material such as silicon, silicon oxide, silicon nitride, or silicon carbide. The first dielectric material can also be a dielectric material such as polyimide. In other words, the first dielectric material can be a silicon-based semiconductor material or a dielectric material (which can be an organic dielectric material). When the first dielectric material is a dielectric material, the second interconnect layer 2 can also be called a redistribution layer. Of course, the first dielectric material can also be other materials, and the embodiments of the present application are not limited thereto.

[0053] It is conceivable that, since there is a gap between two adjacent first chips, the second interconnect layer 2 can be used to adjust the stress of gap G1 and gap G2. In other words, the support provided by the second interconnect layer 2 can reduce the stress between the two adjacent first chips, thereby reducing the stress of the first chips and further improving the reliability of the entire package structure 100.

[0054] like Figure 1 As shown, the package structure may further include multiple first connectors. The multiple first connectors may include multiple connectors 41, multiple connectors 42, and multiple connectors 43. The first end of each connector 41 may be connected to the chip 31, the first end of each connector 42 may be connected to the chip 32, and the first end of each connector 43 may be connected to the chip 33. The second end of each connector 41, each connector 42, and each connector 43 may be connected to the second interconnect layer 2.

[0055] It can be seen that the connector 41 can connect the chip 31 and the second interconnection layer 2. The connector 42 can connect the chip 32 and the second interconnection layer 2. The connector 43 can connect the chip 33 and the second interconnection layer 2.

[0056] Optionally, a second dielectric material may be provided between the plurality of connectors 41, the plurality of connectors 42, and the plurality of connectors 43. The second dielectric material may also be epoxy resin, etc., which can play an insulating role, that is, to isolate different connectors.

[0057] In one possible implementation, Figure 1 As shown, the package structure 100 may further include a dielectric layer 5. The dielectric layer 5 may be disposed along a first direction on the surface of the second interconnection layer 2. The surface of the second interconnection layer 2 may be used to indicate the surface of the second interconnection layer 2 away from the chips 31, 32, and 33.

[0058] Optionally, the dielectric layer 5 may be made of materials such as resin and silicon, and may be used to protect and support the second interconnect layer 2 .

[0059] In another possible implementation, Figure 2 As shown, package structure 100 may further include multiple second chips. The multiple second chips may include chip 61 and chip 62. Chip 61 and chip 62 may be disposed on the surface of second interconnect layer 2 along the first direction. Of course, there may be one or more second chips, and the number of second chips may be determined by the number of first chips. This embodiment of the present application takes the package structure 100 including two second chips as an example for description.

[0060] Chip 61 can be used to connect chip 31 and chip 32 .

[0061] Similarly, chip 62 can be used to connect chip 32 and chip 33 .

[0062] That is, the second chip can be used to connect two adjacent first chips. Therefore, the second chip can also be called an interconnection chip.

[0063] In some embodiments, the package structure 100 may further include a plurality of second connectors. The plurality of second connectors may include a plurality of connectors 71 and a plurality of connectors 72, such as Figure 2 As shown, the first end of each connector 71 can be connected to the second interconnect layer 2, and the second end of each connector 71 can be connected to the chip 61. Similarly, the first end of each connector 72 can be connected to the second interconnect layer 2, and the second end of each connector 72 can be connected to the chip 62.

[0064] As can be seen, connector 71 can connect chip 61 and second interconnect layer 2, while connector 72 can connect chip 62 and second interconnect layer 2. A third dielectric material can be provided between the multiple connectors 71 and 72. Similar to the second dielectric material, the third dielectric material can also be epoxy resin, etc., to provide insulation, that is, to isolate the multiple connectors 71 from the multiple connectors 72.

[0065] In other embodiments, continue to refer to Figure 2 The package structure 100 may further include multiple third chips. The multiple third chips may include chip 81 and chip 82. Chip 81 and chip 82 may be arranged on the surface of the second interconnect layer 2 along the first direction. Chip 61, chip 62, chip 81, and chip 82 may be arranged on the same layer.

[0066] Chip 81 can be used primarily to dissipate heat for chip 31. Similarly, chip 82 can be used primarily to dissipate heat for chip 33. Of course, both chips 81 and 82 can also dissipate heat for chip 32. Therefore, chips 81 and 82 can also be referred to as heat dissipation chips.

[0067] Furthermore, the package structure 100 may further include a plurality of third connectors, which may include a plurality of connectors 91 and a plurality of connectors 92 .

[0068] The first end of each connector 91 can be connected to the second interconnect layer 2, and the second end of each connector 91 can be connected to the chip 81. Similarly, the first end of each connector 92 can be connected to the second interconnect layer 2, and the second end of each connector 92 can be connected to the chip 82.

[0069] It can be seen that the plurality of connectors 91 can function to connect the chip 81 and the second interconnection layer 2. The plurality of connectors 92 can function to connect the chip 82 and the second interconnection layer 2.

[0070] Optionally, a fourth dielectric material may be provided between the plurality of connectors 91 and the plurality of connectors 92. Similar to the second dielectric material and the third dielectric material, the fourth dielectric material may also be epoxy resin, etc., which may serve as an insulator, that is, to isolate the plurality of connectors 91 from the plurality of connectors 92.

[0071] For example, the connectors 41, 42, 43, 71, 72, 91, and 92 can all be made of metal materials such as copper. Of course, other conductive metal materials can also be used, and this embodiment of the application does not limit this.

[0072] Optionally, a gap G3 exists between chip 81 and chip 61, a gap G4 exists between chip 61 and chip 62, and a gap G5 exists between chip 62 and chip 82. It is conceivable that the second interconnect layer 2 can also be used to adjust the stress of gaps G3, G4, and G5. In other words, the second interconnect layer 2 can reduce the stress between two adjacent chips, thereby reducing the stress of the chips and further improving the reliability of the entire package structure 100.

[0073] like Figure 1 and Figure 2 As shown, the package structure 100 provided in the embodiment of the present application can also be provided with a dielectric material such as epoxy resin between the first interconnect layer 1 and the second interconnect layer 2, surrounding the chips 31, 32, and 33. The dielectric material can be provided with through molding vias (TMVs). The TMVs can contain metal materials such as copper to enable signal input and output. The signals can be serial and deserial signals, etc.

[0074] Exemplary, reference Figure 1 and Figure 2 The package structure 100 may further include solder balls 10, which may be used to connect the chips 31, 32, and 33 to the substrate ( Figure 1 and Figure 2 ) connections are not shown.

[0075] In some embodiments, Figure 1 The package structure 100 shown, the power supply (PS), the input signal S in and the output signal S out The path can be as follows Figure 3 As shown. Figure 3 It can be seen that the vertical power supply of chips 31, 32 and 33 is realized through the first interconnection layer 1, and the input signal S is realized through the second interconnection layer 2. in and the output signal S out transmission.

[0076] In other embodiments, Figure 2 The package structure 100 shown, the power supply PS, the input signal S in and the output signal S out The respective paths can be Figure 4 As shown. Figure 4 It can be seen that the vertical power supply of chips 31, 32 and 33 is realized through the first interconnection layer 1, and the input signal S is realized through the second interconnection layer 2. in and the output signal S out transmission.

[0077] from Figure 3 and Figure 4 It can be seen that the package structure 100 provided in the embodiment of the present application can achieve separation of power routing and signal routing, significantly improving the wiring density and degree of freedom, and increasing the utilization of the first interconnect layer 1 and the second interconnect layer 2, thereby improving the signal quality and power quality of the package structure 100. At the same time, the embodiment of the present application can improve the electrical performance of the package structure 100, such as the signal processing rate, even when limited layout and wiring space is limited.

[0078] It is conceivable that the embodiment of the present application separates the power lines and the signal lines, which can reduce the size of the entire packaging structure 100, thereby reducing the stress received by the chip 31 and the like, thereby improving the reliability of the packaging structure 100.

[0079] An embodiment of the present application further provides an electronic device, which may include a substrate and a packaging structure 100. The packaging structure 100 may be disposed on the substrate.

[0080] Optionally, the electronic device may be an intermediate frequency conversion module in a base station (such as a baseband processing unit (BBU)), a mobile phone, etc. This embodiment of the present application is not limited thereto. This embodiment of the present application is described using a mobile phone as an example.

[0081] like Figure 5 As shown, the mobile phone 1000 may include a bus 1001 , a system on chip (SoC) 1100 connected to the bus 1001 , a second RAM 1200 , a communication chip 1300 , and a power management chip 1400 .

[0082] Among them, SoC 1100 can be used to process data, such as processing application data, processing image data, and caching temporary data. SoC 110 may include an application processor (AP) 1101 for processing applications, a graphics processing unit (GPU) 1102 for processing image data, and a first random access memory (RAM) 1103 for caching high-speed data. AP 1101, GPU 1102, and first RAM 1103 can be integrated into a single die or separately arranged in multiple dies. The above-mentioned SoC 1100 can adopt the packaging structure 100 provided in an embodiment of the present application.

[0083] The first RAM 1103 may be a dynamic random access memory (DRAM). The second RAM 1200 may be a dynamic random access memory (DRAM). The power management chip 1400 may be used to supply power to other chips.

[0084] Of course, the packaging structure 100 provided in the embodiment of the present application can be used not only for electronic devices such as mobile phones, but also for artificial intelligence (AI), image processing, high-performance computing modules (HPC), etc., which will not be described in detail in this application.

[0085] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A packaging structure, characterized in that: It includes a first interconnection layer, a first chip and a second interconnection layer stacked along a first direction; The first interconnection layer is used to: provide power supply wiring for the first chip; The second interconnection layer is used to provide signal routing for the first chip.

2. The packaging structure according to claim 1, wherein: The second interconnection layer is made of a first dielectric material and is provided with the signal wiring.

3. The packaging structure according to claim 2, wherein: The first dielectric material is a semiconductor material or a dielectric material.

4. The packaging structure according to any one of claims 1 to 3, characterized in that: The packaging structure further includes a plurality of first connecting members; A first end of each of the plurality of first connectors is connected to the first chip, and a second end of each of the first connectors is connected to the second interconnect layer; a second dielectric material is provided between the plurality of first connectors.

5. The packaging structure according to any one of claims 1 to 4, characterized in that: The packaging structure includes a plurality of first chips, wherein the plurality of first chips are arranged on the first interconnection layer in the same layer, and there is a gap between two adjacent first chips in the plurality of first chips; The second interconnection layer is used to adjust the stress of the gap.

6. The packaging structure according to claim 5, wherein: The package structure further includes a second chip; the second chip is arranged on the surface of the second interconnection layer along the first direction; wherein the surface of the second interconnection layer is used to indicate that the second interconnection layer is away from the surface of the first chip; The second chip is used to connect two adjacent first chips among the plurality of first chips.

7. The packaging structure according to claim 6, wherein: The packaging structure further includes a plurality of second connecting members; A first end of each second connector among the plurality of second connectors is connected to the second interconnect layer, and a second end of each second connector is connected to the second chip; a third dielectric material is provided between the plurality of second connectors.

8. The packaging structure according to any one of claims 1 to 7, characterized in that: The package structure further includes a third chip; the third chip is arranged on the surface of the second interconnection layer along the first direction; wherein the surface of the second interconnection layer is used to indicate that the second interconnection layer is away from the surface of the first chip; The third chip is used to dissipate heat for the first chip.

9. The packaging structure according to claim 8, wherein: The packaging structure further includes a plurality of third connecting members; A first end of each of the plurality of third connectors is connected to the second interconnect layer, and a second end of each of the third connectors is connected to the third chip; and a fourth dielectric material is provided between the plurality of third connectors.

10. The packaging structure according to any one of claims 1 to 5, characterized in that: The packaging structure further includes a dielectric layer, which is disposed on a surface of the second interconnection layer along the first direction; wherein the surface of the second interconnection layer is used to indicate that the second interconnection layer is away from the surface of the first chip.

11. The packaging structure according to any one of claims 1 to 10, characterized in that: The signal wiring is made of metal material.

12. An electronic device, characterized in that: The invention comprises a substrate and a packaging structure according to any one of claims 1 to 11; the packaging structure is arranged on the substrate.

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