High-density double-sided fine wiring fan-out chip packaging structure and method

Abstract

The invention discloses a high-density double-sided fine wiring fan-out chip packaging structure and method. The packaging structure comprises a silicon wafer, the silicon wafer is provided with a silicon through hole, the silicon through hole is filled with a conductive column, and the back surface of the silicon wafer is etched with a groove; the dielectric layer is arranged on the front surface of the silicon wafer; the first redistribution line layer is stacked on the dielectric layer, and a first passivation layer covers the first redistribution line layer; the at least one first chip is mounted on the first rewiring layer; the first plastic package body covers the first passivation layer and the first rewiring layer, and the first chip is plastically packaged in the first plastic package body; the second chip is embedded in the groove; the second plastic package body covers the second chip; the second redistribution layer is arranged on the second plastic package body; the second rewiring layer is covered with a second passivation layer; and the signal export structure is arranged on the second passivation layer and is electrically connected with the second rewiring layer. According to the method, high-density three-dimensional stacked fan-out packaging and wiring of fine lines on the upper surface and the lower surface can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chip packaging, and in particular to a high-density double-sided fine wiring fan-out chip packaging structure and method. Background Art

[0002] With the rapid development of semiconductor electronics technology, the demand for fan-out packaging with smaller dimensions, higher integration, and greater functionality is becoming increasingly significant. Traditional silicon-based fan-out packaging involves first digging a trench in the silicon substrate, embedding the chip, and then installing a redistribution layer. However, after the chip is embedded in the silicon trench, the large height difference between the chip and the silicon platform results in significant undulations on the wafer surface, making it impossible to achieve precise, high-density wiring.

[0003] Therefore, it is necessary to develop a chip packaging method and structure that can achieve higher density and fine wiring. Summary of the Invention

[0004] To solve the above technical problems, the present invention aims to provide a high-density double-sided fine wiring fan-out chip packaging structure and method. The method can realize high-density three-dimensional stacked fan-out packaging and wiring of fine circuits on both the upper and lower surfaces.

[0005] In order to achieve the above technical objectives and the above technical effects, the present invention is implemented through the following technical solutions:

[0006] On one hand, the present invention provides a high-density double-sided fine wiring fan-out chip packaging structure, comprising:

[0007] A silicon wafer having through-silicon vias (TSVs) formed thereon, the TSVs being filled with conductive pillars, and a groove being etched on the backside of the silicon wafer;

[0008] a dielectric layer, the dielectric layer being disposed on the front side of the silicon wafer;

[0009] At least one first redistribution layer, wherein the first redistribution layer is stacked on the dielectric layer, and the first redistribution layer is covered with a first passivation layer;

[0010] at least one first chip, wherein the first chip is mounted on the first redistribution layer and electrically connected to the first redistribution layer and the conductive pillar;

[0011] a first plastic package, the first plastic package covering the first passivation layer and the first redistribution layer, and plastic-sealing the first chip therein;

[0012] at least one second chip, wherein the second chip is embedded in the groove of the silicon wafer;

[0013] a second plastic package body, wherein the second plastic package body covers the second chip;

[0014] at least one second redistribution layer, the second redistribution layer being disposed on the second plastic package and electrically connected to the conductive pillars and the second chip; the second redistribution layer being covered with a second passivation layer;

[0015] A signal derivation structure is provided on the second passivation layer and is electrically connected to the second redistribution layer.

[0016] Furthermore, the bottom of the first chip is filled with a filling structure layer.

[0017] Furthermore, the groove is a trapezoidal groove.

[0018] Furthermore, an insulating layer covering the sidewalls of the through-silicon vias and the groove surfaces of the recesses is provided on the back side of the silicon wafer.

[0019] Furthermore, the signal derivation structure is a solder ball.

[0020] Furthermore, the dielectric layer is made of SiN or SiO.

[0021] Furthermore, the first passivation layer and the second passivation layer are made of PI glue or solid dry film.

[0022] Furthermore, the conductive pillar is made of copper.

[0023] Another aspect of the present invention provides a high-density double-sided fine wiring fan-out chip packaging method, comprising the following steps:

[0024] S1: Depositing a dielectric layer on the front side of the silicon wafer;

[0025] S2: sequentially preparing a first passivation layer and a first redistribution layer on the dielectric layer, wherein a bonding pad is formed on the outermost surface of the first redistribution layer;

[0026] S3: Mounting a first chip having bumps on the surface of the first redistribution layer, so that the bumps of the first chip are connected to the pads of the first redistribution layer;

[0027] S4: using a plastic packaging material to plasticize the first chip to form a first plastic packaging body;

[0028] S5: Thinning the back side of the silicon wafer to prepare through-silicon vias and grooves;

[0029] S6: burying the second chip in the groove; filling the through-silicon via with metal material to form a conductive column, the conductive column being electrically connected to the first redistribution layer and the first chip;

[0030] S7: Using a plastic packaging material to plasticize the second chip to form a second plastic packaging body;

[0031] S8: preparing a second redistribution layer and a second passivation layer on the second plastic package, wherein the second redistribution layer is electrically connected to the conductive pillars and the second chip;

[0032] S9: forming a pad on the outermost surface of the second redistribution layer, and preparing a signal lead-out structure at a position corresponding to the pad.

[0033] Furthermore, in step S5, an insulating layer is deposited on the back side of the silicon wafer to cover the sidewalls of the through silicon via and the groove surface of the recess.

[0034] The beneficial effects of the present invention are:

[0035] 1. This invention directly forms a redistribution layer on the front side of the silicon wafer. Due to the good flatness of the bare silicon wafer, the line width and line spacing can be as small as 0.4μm or even finer. The number of redistribution layers can be two or more, which is very friendly to the integrated packaging of high-I / O density chips and can eliminate the yield loss of high-I / O density chips caused by redistribution defects.

[0036] 2. The backside process of the present invention forms a trapezoidal groove on the silicon wafer and then buries the chip in the trapezoidal groove. The trapezoidal groove can better disperse stress, reduce chip displacement and damage during the packaging process, and is easy to manufacture.

[0037] 3. The present invention uses plastic encapsulation material on both the front and back sides of the silicon wafer to encapsulate the chip, making it easier to carry out high-precision and high-density wiring, and can achieve relatively fine lines with a line width and line spacing of less than 2μm;

[0038] 4. The present invention can realize three-dimensional stacking packaging of high I / O density chips and low I / O density chips, and can realize the wiring of fine lines on the upper and lower sides and high-density three-dimensional stacking fan-out packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is a schematic diagram of the structure prepared after step S1 of the high-density double-sided fine wiring fan-out chip packaging method of the present invention.

[0040] Figure 2 This is a schematic diagram of the structure prepared after step S2 of the high-density double-sided fine wiring fan-out chip packaging method of the present invention.

[0041] Figure 3 This is a schematic diagram of the structure prepared after step S3 of the high-density double-sided fine wiring fan-out chip packaging method of the present invention.

[0042] Figure 4 This is a schematic diagram of the structure prepared after step S4 of the high-density double-sided fine wiring fan-out chip packaging method of the present invention.

[0043] Figure 5This is a schematic diagram of the structure prepared after step S5 of the high-density double-sided fine wiring fan-out chip packaging method of the present invention.

[0044] Figure 6 This is a schematic diagram of the structure prepared after step S6 of the high-density double-sided fine wiring fan-out chip packaging method of the present invention.

[0045] Figure 7 This is a schematic diagram of the structure prepared after step S7 of the high-density double-sided fine wiring fan-out chip packaging method of the present invention.

[0046] Figure 8 This is a schematic diagram of the structure prepared after step S9 of the high-density double-sided fine wiring fan-out chip packaging method of the present invention.

[0047] In the figure, 1-silicon wafer, 2-dielectric layer, 3-first passivation layer, 4-first redistribution layer, 5-solder pad, 6 / 7-first chip, 8-bump, 9-filling structure layer, 10-first plastic package, 11-groove, 12-through silicon via, 13-insulating layer, 14-second chip, 15-adhesive material, 16-conductive column, 17-second plastic package, 18-metal pad, 19-second redistribution layer, 20-second passivation layer, 21-signal lead-out structure. DETAILED DESCRIPTION

[0048] The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more precise definition of the protection scope of the present invention.

[0049] like Figures 1 to 8 A preferred embodiment of a high-density double-sided fine wiring fan-out chip package structure is shown, comprising:

[0050] A silicon wafer 1 having a through-silicon via 12 formed thereon, the through-silicon via 12 being filled with a conductive pillar 16, and a groove 11 being etched on the backside of the silicon wafer 1. In this embodiment, the conductive pillar 16 is preferably made of copper; the groove 11 is a trapezoidal groove.

[0051] A dielectric layer 2 is provided on the front surface of the silicon wafer 1; the dielectric layer 2 is preferably made of SiN or SiO material and serves as an insulator;

[0052] a first redistribution layer 4, wherein the first redistribution layer 4 is stacked on the dielectric layer 2, and the first passivation layer 3 is covered on the first redistribution layer 4; in this embodiment, the first redistribution layer 4 has two layers, and the first passivation layer 3 has two layers; in other embodiments, the first redistribution layer 4 and the first passivation layer 3 may have more layers; furthermore, in this embodiment, the first redistribution layer 4 is a Cu circuit, and the first passivation layer 3 may be made of a PI film or a solid dry film;

[0053] First chips 6 and 7 are mounted on the outermost pad 5 of the first redistribution layer 4 via a flip-chip process. The first chips 6 and 7 have bumps 8. The first chips 6 and 7 are electrically connected to the first redistribution layer 4 and the conductive pillars 16 via the bumps 8 for signal transmission. The first chip is a high I / O density chip, and the number of mounted chips may be two or more. The bumps of the first chip are made of materials such as Cu, Ni, Sn, and Ag.

[0054] A first plastic package 10, which covers the first passivation layer 3 and the first redistribution layer 4 and plastic-encapsulates the first chips 6 and 7; the first plastic package 10 can protect the chips and support the entire reconstructed wafer;

[0055] A second chip 14, wherein the second chip 14 is embedded in the groove 11 of the silicon wafer 1;

[0056] A second plastic package 17 , the second plastic package 17 covering the second chip 14 ;

[0057] A second redistribution layer 19 is provided on the second plastic package 17 and is electrically connected to the conductive pillars 16 and the second chip 14. The second redistribution layer 19 is covered with a second passivation layer 20. The second redistribution layer 19 may be one layer, two layers, or more layers.

[0058] The signal derivation structure 21 is disposed on the second passivation layer 20 and is electrically connected to the second redistribution layer 19 . In this embodiment, the signal derivation structure 21 is a solder ball.

[0059] In the above structure, the bottoms of the first chips 6 and 7 are further filled with a filling structure layer 9; filling the bottom of the chip can reduce the warping of the package after plastic encapsulation.

[0060] In the above structure, an insulating layer 13 covering the sidewalls of the through silicon via 12 and the surface of the groove 11 is further provided on the back side of the silicon wafer 1 . The insulating layer 13 is made of SiN or SiO.

[0061] The high-density double-sided fine wiring fan-out chip packaging method for preparing the above-mentioned packaging structure comprises the following steps:

[0062] S1: If Figure 1 As shown, a dielectric layer 2 is deposited on the front surface of the silicon wafer 1; the dielectric layer 2 is made of SiN or SiO material and plays an insulating role;

[0063] S2: If Figure 2 As shown, a first passivation layer 3 and a first redistribution layer 4 are sequentially formed on the dielectric layer 2, and a pad 5 is formed on the outermost surface of the first redistribution layer 4. The first redistribution layer 4 is a Cu circuit, and the first passivation layer 3 can be made of a PI film or a solid dry film. The first redistribution layer 4 and the first passivation layer 3 can have two or more layers. The line width and line spacing of the first redistribution layer 4 can be as small as 0.4 μm / 0.4 μm, or even finer.

[0064] S3: If Figure 3 As shown, first chips 6 and 7 having bumps 8 are mounted on the surface of the first redistribution layer 4, so that the bumps 8 of the first chips are connected to the pads 5 of the first redistribution layer 4; the first chips 6 and 7 are electrically connected to the first redistribution layer 4 through the bumps 8 for signal transmission; the first chips 6 and 7 are both high I / O density chips, and the number of mounted chips can be 2 or more; the bumps of the first chips are made of materials such as Cu, Ni, Sn, and Ag;

[0065] S4: As Figure 4 As shown, the bottom of the first chip is filled with bottom filling material to form a filling structure layer 9, which can reduce the warping of the package after plastic packaging; then the plastic packaging material is plastic-sealed to form a first plastic packaging body 10, which wraps the first chips 6 and 7. The first plastic packaging body 10 can protect the chip and support the entire reconstructed wafer.

[0066] S5: If Figure 5 As shown, the back side of the silicon wafer 1 is thinned. After thinning, a through-silicon via 12 and a trapezoidal groove 11 are prepared using a Bosch etching process, a yellow light process, etc., and an insulating layer 13 covering the through-silicon via surface and the groove surface is deposited on the back side of the silicon wafer 1. Then, the insulating layer 13 at the bottom of the through-silicon via 12 is etched away by an etching process to expose the first redistribution layer 4; the insulating layer 13 is made of a material such as SiN or SiO;

[0067] S6: As Figure 6As shown, a second chip 14 is embedded in the groove 11 and secured with adhesive 15, leaving a gap between the second chip 14 and the sidewalls of the groove 11. Through-silicon vias 12 are filled with metal material through a metal sputtering and electroplating process to form conductive pillars 16, which are electrically connected to the first redistribution layer 4 and the first chips 6 and 7. The metal material filling the through-silicon vias 12 is preferably copper. The metal pad 18 on the surface of the second chip 14 needs to be substantially flush with the metal material on the surface of the through-silicon via. The raised metal material can be removed by methods such as chemical mechanical polishing or reverse electrolysis.

[0068] S7: As Figure 7 As shown, the second chip 14 is encapsulated with a plastic encapsulation material, and the plastic encapsulation material is leveled by a chemical mechanical polishing method to form a second plastic encapsulation body 17;

[0069] S8: Figure 8 As shown, laser drilling is used to expose the positions of the chip pads and the through-silicon vias of the second plastic package 17, and a second redistribution layer 19 is provided on the second plastic package 17. The second redistribution layer 19 is electrically connected to the conductive pillars 16 and the second chip 14. The second redistribution layer 19 is covered with a second passivation layer 20. The second redistribution layer 19 can be one layer, two layers, or more layers.

[0070] S9: As Figure 8 As shown, an opening is set on the second passivation layer 20, a pad is formed at the opening corresponding to the outermost surface of the second redistribution layer 19, and a signal lead-out structure 21 is prepared at a position corresponding to the pad for electrical signal transmission; in this embodiment, the signal lead-out structure 21 is a solder ball.

[0071] The method of the present invention directly prepares a redistribution layer on the front side of a silicon wafer. Due to the good flatness of the bare silicon wafer, the line width and line spacing can be 0.4 μm or even finer. The number of redistribution layers can be 2 or more, which is very friendly to the integrated packaging of high I / O density chips and can eliminate the yield loss of high I / O density chips caused by redistribution defects. The back side process of the present invention forms a trapezoidal groove on the silicon wafer and then buries the chip in the trapezoidal groove. The trapezoidal groove can better disperse stress and reduce chip offset and damage during the packaging process. The present invention uses plastic encapsulation material to encapsulate the chip on both the front and back sides of the silicon wafer, which is more convenient for high-precision and high-density wiring and can realize finer circuits with a line width and line spacing of less than 2 μm.

[0072] The present invention can realize three-dimensional stacking packaging of high I / O density chips and low I / O density chips, and can realize wiring of fine lines on the upper and lower sides and high-density three-dimensional stacking fan-out packaging.

[0073] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention's description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A high-density double-sided fine wiring fan-out chip packaging structure, characterized in that: include: A silicon wafer having through-silicon vias (TSVs) formed thereon, the TSVs being filled with conductive pillars, and a groove being etched on the backside of the silicon wafer; a dielectric layer, the dielectric layer being disposed on the front side of the silicon wafer; At least one first redistribution layer, wherein the first redistribution layer is stacked on the dielectric layer, and the first redistribution layer is covered with a first passivation layer; at least one first chip, wherein the first chip is mounted on the first redistribution layer and electrically connected to the first redistribution layer and the conductive pillar; a first plastic package, the first plastic package covering the first passivation layer and the first redistribution layer, and plastic-sealing the first chip therein; at least one second chip, wherein the second chip is embedded in the groove of the silicon wafer; a second plastic package body, wherein the second plastic package body covers the second chip; at least one second redistribution layer, the second redistribution layer being disposed on the second plastic package and electrically connected to the conductive pillars and the second chip; the second redistribution layer being covered with a second passivation layer; A signal derivation structure is provided on the second passivation layer and is electrically connected to the second redistribution layer.

2. A high-density double-sided fine wiring fan-out chip packaging structure according to claim 1, characterized in that: The bottom of the first chip is filled with a filling structure layer.

3. The high-density double-sided fine wiring fan-out chip packaging structure according to claim 1, characterized in that: The groove is a trapezoidal groove.

4. The high-density double-sided fine wiring fan-out chip packaging structure according to claim 1, characterized in that: An insulating layer covering the sidewalls of the through silicon vias and the groove surfaces of the recesses is also provided on the back side of the silicon wafer.

5. The high-density double-sided fine wiring fan-out chip packaging structure according to claim 1, characterized in that: The signal derivation structure is a solder ball.

6. The high-density double-sided fine wiring fan-out chip packaging structure according to claim 1, characterized in that: The dielectric layer is made of SiN or SiO.

7. The high-density double-sided fine wiring fan-out chip packaging structure according to claim 1, characterized in that: The first passivation layer and the second passivation layer are made of PI glue or solid dry film.

8. The high-density double-sided fine wiring fan-out chip packaging structure according to claim 1, characterized in that: The conductive pillars are made of copper.

9. A high-density double-sided fine wiring fan-out chip packaging method, characterized in that: The steps include: S1: Depositing a dielectric layer on the front side of the silicon wafer; S2: sequentially preparing a first passivation layer and a first redistribution layer on the dielectric layer, wherein a bonding pad is formed on the outermost surface of the first redistribution layer; S3: Mounting a first chip having bumps on the surface of the first redistribution layer, so that the bumps of the first chip are connected to the pads of the first redistribution layer; S4: using a plastic packaging material to plasticize the first chip to form a first plastic packaging body; S5: Thinning the back side of the silicon wafer to prepare through-silicon vias and grooves; S6: burying the second chip in the groove; filling the through-silicon via with metal material to form a conductive column, the conductive column being electrically connected to the first redistribution layer and the first chip; S7: Using a plastic packaging material to plasticize the second chip to form a second plastic packaging body; S8: preparing a second redistribution layer and a second passivation layer on the second plastic package, wherein the second redistribution layer is electrically connected to the conductive pillars and the second chip; S9: forming a pad on the outermost surface of the second redistribution layer, and preparing a signal lead-out structure at a position corresponding to the pad.

10. A high-density double-sided fine wiring fan-out chip packaging method according to claim 9, characterized in that: In step S5 , an insulating layer is deposited on the back side of the silicon wafer to cover the sidewalls of the through silicon via and the groove surface of the recess.

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