A semiconductor module packaging structure and a semiconductor module packaging method

Abstract

This invention provides a semiconductor module packaging structure and a semiconductor module packaging method. The semiconductor module packaging structure includes a first substrate, a second substrate, and a metal casing. The first substrate includes a first surface and a second surface facing away from each other, and the second substrate includes a third surface and a fourth surface facing away from each other. The fourth surface is recessed towards the third surface to form a groove, and the unrecessed portion of the fourth surface is electrically connected to the first surface. This structure, in which the first substrate and the second substrate are directly interconnected, replaces the traditional copper pillar interconnect structure, solving the problems of low reliability and high parasitic parameters and high thermal resistance risks associated with vertically stacked semiconductor packaging structures in the prior art.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a semiconductor module packaging structure and a semiconductor module packaging method. Background Technology

[0002] Existing vertical stacking semiconductor packaging technology significantly improves device density and performance by vertically integrating multiple layers of chips or wafers, becoming a key technology in the fields of power modules, high-performance computing, and memory.

[0003] As one of the mainstream interconnect structures in vertically stacked semiconductor packaging, copper pillars are widely used in advanced packaging scenarios requiring high-density, high-reliability interconnects. However, when the thermal expansion coefficients of the copper pillars and the substrate material do not match, their stability is poor and they are easily damaged. This not only reduces the reliability of the vertically stacked semiconductor packaging structure but also poses a risk of excessively high parasitic parameters. Furthermore, the limitations of the copper pillars' own heat conduction path or interfacial thermal resistance issues can also adversely affect heat dissipation efficiency. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a semiconductor module packaging structure and a semiconductor module packaging method, which solves the problems of low reliability and high parasitic parameters and thermal resistance risks of vertically stacked semiconductor packaging structures in existing technologies.

[0005] According to an embodiment of the present invention, a first aspect provides a semiconductor module packaging structure, comprising:

[0006] The first substrate includes a first surface and a second surface facing away from each other, and the first surface is provided with a first bonding finger;

[0007] The second substrate includes a third surface and a fourth surface facing away from each other. The fourth surface is recessed towards the third surface to form a groove. The unrecessed portion of the fourth surface is electrically connected to the first surface to form a cavity that is open from front to back. The third surface is provided with a second bonding finger. The fourth surface is adjacent to the first surface, and the third surface is away from the first surface.

[0008] A metal casing has a cavity for accommodating the first substrate and the second substrate. The first substrate is mounted in the cavity, and the second surface is in contact with the bottom of the metal casing. Each of the two opposite sidewalls of the metal casing is provided with an external pin, and the second bonding finger is also connected to the external pin via a bonding wire. The other two opposite sidewalls of the metal casing face the cavity that connects the front and back.

[0009] The first substrate is used to set a target unit in the target semiconductor module that performs the same function, and the second substrate is used to set another target unit in the target semiconductor module that performs the same function. The target unit set on the first surface is electrically connected to the first bonding finger through bonding leads, and the target unit set on the third surface is electrically connected to the second bonding finger through bonding leads.

[0010] A second aspect provides a semiconductor module packaging method, using the semiconductor module packaging structure described above, comprising:

[0011] The target semiconductor module is modularly decomposed to obtain target units that perform one identical function and target units that perform another identical function.

[0012] A target unit that performs the same function is disposed on a first substrate, and a target unit that performs another function is disposed on a second substrate.

[0013] Compared to existing technologies, this invention offers the following advantages: It proposes a novel structure for the second substrate, wherein the unrecessed portion of the fourth surface of the second substrate is electrically connected to the first surface of the first substrate. This direct interconnection between the first and second substrates replaces the traditional copper pillar interconnection structure, eliminating the need to consider the thermal expansion coefficients between various materials and improving the reliability of the semiconductor module packaging structure. Furthermore, it creates a structure where the interconnected first and second substrates are vertically stacked with the metal casing, significantly increasing integration density. It also places target units performing the same function within the target semiconductor module on the same substrate, resulting in clearer functional division and facilitating effectiveness verification and debugging. In addition, this three-dimensional, multi-faceted, cavity-based structure enables gradient heat dissipation, reduces module thermal resistance, and effectively reduces parasitic parameters. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the semiconductor module packaging structure according to an embodiment of the present invention;

[0015] Figure 2 This is a schematic diagram of the semiconductor module packaging structure according to an embodiment of the present invention;

[0016] Figure 3 This is a schematic diagram of the semiconductor module packaging structure according to an embodiment of the present invention;

[0017] Figure 4 This is a schematic diagram of the semiconductor module packaging structure according to an embodiment of the present invention;

[0018] Figure 5 This is a schematic diagram illustrating the implementation process of the semiconductor module packaging method according to an embodiment of the present invention;

[0019] Figure 6This is a layout diagram of a GaN power module on a first surface of a first substrate according to an embodiment of the present invention.

[0020] Figure 7 This is a layout diagram of the GaN power module on the third surface of the second substrate according to an embodiment of the present invention.

[0021] Figure 8 This is a layout diagram of the GaN power module on the fourth surface of the second substrate according to an embodiment of the present invention. Detailed Implementation

[0022] The technical solutions of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0023] like Figure 1 As shown, this embodiment of the invention proposes a semiconductor module packaging structure, including a first substrate 10, a second substrate 20, and a metal casing 30. The first substrate 10 includes a first surface m1 and a second surface m2 facing away from each other. The first surface m1 is provided with a first bonding finger 11. The second substrate 20 includes a third surface m3 and a fourth surface m4 facing away from each other. The fourth surface m4 is recessed towards the third surface m3 to form a groove 40. The unrecessed portion m41 of the fourth surface m4 is electrically connected to the first surface m1, forming a cavity with front and rear connections. The third surface m3 is provided with a second bonding finger 21. The metal casing 30 has a cavity for accommodating the first substrate 10 and the second substrate 20. The first substrate 10 is installed in the cavity, and the second surface m2 is in contact with the bottom 31 of the metal casing 30. Two opposing sidewalls of the metal casing 30, such as sidewall 32 and sidewall 33, are each provided with an external pin 34. The second bonding finger 21 on the second substrate 20 is also connected to the external pin 34 via bonding wires. The other two opposing sidewalls of the metal casing 30 (…) Figure 1 (Not shown in the image) is directly opposite the cavity that connects the front and back.

[0024] The detailed working process of this invention embodiment is as follows: When the target semiconductor module is packaged using the above-described semiconductor module packaging structure, the target unit with the same function in the target semiconductor module is disposed on the first substrate 10 or the second substrate 20. Since the second surface is in contact with the bottom 31 of the metal shell 30, the target unit with the same function in the target semiconductor module can be disposed on the first surface, the third surface and the fourth surface, or it can be disposed on the first surface and the third surface. The target unit 51 disposed on the first surface m1 is electrically connected to the first bonding finger 11 through bonding wires, and the target unit 52 disposed on the third surface m3 is electrically connected to the second bonding finger 21 through bonding wires, thereby constructing an electrical interconnection path between the internal circuit of the module and the external system.

[0025] This invention proposes a novel structure for the second substrate 20, wherein the unrecessed portion m41 of the fourth surface m4 of the second substrate 20 is electrically connected to the first surface m1 of the first substrate 10. This direct interconnection structure between the first substrate 10 and the second substrate 20 replaces the traditional copper pillar interconnection structure, eliminating the need to consider the thermal expansion coefficients between various materials and improving the reliability of the semiconductor module packaging structure. It also forms a structure where the first substrate 10 and the second substrate 20 are interconnected and vertically stacked with the metal casing 30, significantly increasing integration density. Furthermore, by placing target units performing the same function in the target semiconductor module on the same substrate, the functional division is clearer, facilitating effectiveness verification and debugging. In addition, this three-dimensional, multi-faceted, cavity-based structure enables gradient heat dissipation, reduces module thermal resistance, and effectively reduces parasitic parameters.

[0026] like Figure 1 As shown, a target unit that performs the same function, such as target unit 51, is disposed on the first surface m1; another target unit that performs the same function, such as target unit 52, is disposed on both the third surface m3 and the fourth surface m4, and is disposed in the recessed portion of the fourth surface m4. In a preferred implementation, the target unit that performs the same function is disposed in the recessed portion of the fourth surface and the third surface, further improving the integration density, which can reach 200%.

[0027] Please see Figure 1 The fourth surface m4 of the second substrate 20 is recessed towards the third surface m3 to form a groove 40. In one implementation, such as Figure 1 As shown, the groove 40 is rectangular in shape. In practical applications, when manufacturing the second substrate 20, a portion can be hollowed out by milling to form... Figure 1 The left vertical sidewall 41 and right vertical sidewall 42 are based on a rectangular groove 40. The groove 40 is rectangular in shape, and the upper and lower ends of the left vertical sidewall 41 and right vertical sidewall 42 have the same cross-sectional size. Based on this, the structure of the first substrate 10 and the second substrate 20 interconnected and longitudinally stacked with the metal casing 30 is more reliable, resisting the adverse effects of cyclic stress, thermomechanical fatigue, and other factors. It is understood that the upper ends of the left and right vertical sidewalls are closer to the second substrate 20, and the lower ends are closer to the first substrate 10.

[0028] In another implementation, such as Figure 2 As shown, the groove 40 is trapezoidal in shape. In practical applications, when manufacturing the second substrate 20, a portion can be hollowed out by milling to form... Figure 2The left trapezoidal sidewall 41' and right trapezoidal sidewall 42' are based on the trapezoidal groove 40. The groove 40 is trapezoidal in shape, so the left sidewall is the left trapezoidal sidewall 41' and the right sidewall is the right trapezoidal sidewall 42'. The upper and lower ends of the left sidewall have different cross-sectional sizes, and the upper and lower ends of the right sidewall have different cross-sectional sizes, so that the structure of the first substrate 10 and the second substrate 20 interconnected and stacked longitudinally with the metal shell 30 is more stable. It is understood that the upper ends of the left trapezoidal sidewall 41' and the right trapezoidal sidewall 42' are closer to the second substrate 20, and the lower ends of the left trapezoidal sidewall 41' and the right trapezoidal sidewall 42' are closer to the first substrate 10. Furthermore, depending on the remaining layout area of ​​the first substrate 10 and the second substrate 20, the cross-sectional size of the upper end of the left trapezoidal sidewall and the right trapezoidal sidewall can be selected to be greater than the cross-sectional size of the lower end of the left trapezoidal sidewall and the right trapezoidal sidewall, or the cross-sectional size of the upper end of the left trapezoidal sidewall and the right trapezoidal sidewall can be selected to be less than the cross-sectional size of the lower end of the left trapezoidal sidewall and the right trapezoidal sidewall.

[0029] Please see Figure 1 and Figure 2 This diagram illustrates one implementation structure of a metal casing 30 in a semiconductor module packaging structure. The bottom 31 of the metal casing 30 includes an extension 35, which is formed by extending a predetermined length away from the bottom 31 of the metal casing 30 and two opposing sidewalls of the metal casing 30 with external pins 34, such as sidewalls 32 and 33. This allows for rapid heat dissipation through the large area of ​​the metal portion at the bottom 31 of the metal casing 30. In a preferred implementation, target units can be ranked according to their heat dissipation requirements, with the target unit having the highest heat dissipation requirement positioned on the first surface m1. The target unit with the highest heat dissipation requirement, the first substrate 10, and the bottom 31 of the metal casing 30 then constitute a gradient heat dissipation design, structurally maximizing heat dissipation. For example, ranking the target units by their heat dissipation requirements includes: calculating the heat dissipation requirement based on the target unit's power processing capability and its own operating power consumption; using the calculation result to quantify the heat dissipation requirement of each target unit; and determining whether the heat dissipation requirement of a target unit performing the same function is higher than that of another target unit performing the same function based on the calculation result.

[0030] Please see Figures 1 to 3 The detailed structure of the metal casing 30 in the above semiconductor module packaging structure will be described. For example... Figure 1 and Figure 2 As shown, in one detailed structure, a metal cover plate 36 is also included. The metal cover plate 36 is sealed to the top of the metal housing 30 by parallel seam welding, thereby adapting to high-frequency application scenarios. Figure 3 As shown, in a detailed structure, the surface of the extension 35 near the outer pin 34 is provided with a package pin 61 and a mounting hole 62. Figure 3 As shown, in one detailed structure, the external pin 34 includes a connection portion located within the inner cavity of the metal housing 30, and a heat dissipation portion exposed from the inner cavity of the metal housing 30. Furthermore, Figure 3 It is also exemplarily shown that the portion of the external pin 34 within the cavity of the metal housing 30 is a bonded finger structure. Furthermore, Figure 3 In the diagram, A represents the position of the interconnected first substrate 10 and second substrate 20 within the inner cavity of the metal casing 30, projected onto the bottom 31 of the metal casing 30.

[0031] It is understandable that, such as Figures 1 to 3 As shown, the metal cover plate 36, extension 35 and external pin 34 described above can be simultaneously implemented in the metal casing 30 of the semiconductor module package structure.

[0032] In one embodiment, the electrical connection method of the above-described semiconductor module packaging structure is further defined. The solder used to set the target unit on the first substrate 10 and the second substrate 20, the solder used to attach the second surface m2 to the bottom 31 of the metal casing 30, and the solder used to electrically connect the unrecessed portion m41 of the fourth surface m4 to the first surface m1 are all different. For example, the solder used to set the target unit on the first substrate 10 and the second substrate 20 is solder paste. Based on this, the target unit is mounted on the first substrate 10 and the second substrate 20 by applying solder paste and then reflow soldering. The solder used to attach the second surface m2 to the bottom 31 of the metal casing 30 is gold solder pad. Based on this, the first substrate 10 is mounted in the inner cavity of the metal casing by the gold solder pad. The solder used to electrically connect the unrecessed portion m41 of the fourth surface m4 to the first surface m1 is another solder paste with better electrical connection performance. Based on this, the first substrate 10 and the second substrate 20 are interconnected in the vertical direction by applying solder paste to the unrecessed portion m41 of the fourth surface m4.

[0033] Another embodiment of the present invention also provides a semiconductor module packaging structure, based on such Figure 1 The three-dimensional, multi-faceted, cavity-based semiconductor packaging structure shown is further optimized and realized to achieve a higher integration density, not limited to the integration density of 200% mentioned in the above embodiments.

[0034] like Figure 4 As shown, another embodiment of the semiconductor module packaging structure provided by the present invention includes a plurality of second substrates, and the structure of the first substrate is similar to that of the second substrate. Figures 1 to 3As shown, a target unit that performs the same function, such as target unit 51, is disposed on the first surface m (1), and the second surface m (2) is attached to the bottom 31 of the metal shell 30. Other structures are not described here. Among them, the first second substrate 20 (1) includes a third surface m (3) and a fourth surface m (4) facing away from each other. The fourth surface m (4) is recessed in the direction of the third surface m (3) to form a groove 40 (1). The unrecessed part m (41) of the fourth surface m (4) is electrically connected to the first surface m (1). The third surface m (3) is provided with a second bonding finger 21 (1). Another target unit that performs the same function, such as target unit 52, is disposed on the third surface m (3) and the fourth surface m (4). The (n+1)th second substrate 20 (n+1) includes an (n+4)th surface m (n+4) and an (n+5)th surface m (n+5) facing away from each other. The (n+4)th surface m (n+4) is provided with an (n+2)th functional chip and an (n+2)th bonding finger 21 (n+1). The (n+2)th functional chip is electrically connected to an (n+2)th bonding finger 21 (n+1) via a bonding wire. The (n+5)th surface m (n+5) is recessed towards the (n+4)th surface m (n+4). The groove 40(n+1) is formed after the (n+5)th surface is recessed. The unrecessed portion m(k1), k=(n+5) of the (n+5)th surface m(n+5) is electrically connected to the (n+2)th surface m(n+2). The recessed portion of the (n+5)th surface m(n+5) is provided with the (n+2)th peripheral resistive device. The (n+5)th surface m(n+5) is adjacent to the (n+2)th surface m(n+2), and the (n+4)th surface m(n+4) is far from the (n+2)th surface m(n+2). Here, N is a positive integer greater than or equal to 1, n+1≤N, and N second substrates are used to set the target units in the target semiconductor module that implement the same function.

[0035] It should be noted that, structurally, if only one second substrate is included, the second bonding finger of the first second substrate is still connected to the external pin 34 through the bonding wire. If at least two second substrates are included, the second bonding finger of the first second substrate is not connected to the external pin 34 through the bonding wire, but the bonding finger of the last second substrate is connected to the external pin 34 through the bonding wire. Figure 4 In the example, the bonding fingers of the last second substrate are connected to the external pin 34 via bonding leads.

[0036] In practical applications, the target semiconductor module typically integrates multiple chips with complementary functions. Therefore, the target semiconductor module may include target units that implement multiple functions. In this case, the above-mentioned... Figure 4 The semiconductor module packaging structure shown, and in terms of the functions of the first substrate and the second substrate, the first substrate is used to set a target unit for one of the functions, and... Figures 1 to 3As shown, N second substrates are all used to set target units in the target semiconductor module that perform the same function. This means that: the first second substrate is used to set a target unit with a different function; the second second substrate and the remaining multiple second substrates can be the same as the first second substrate and used to set a target unit with a different function; or they can be different from the first second substrate and used to set a target unit with yet another or multiple functions. This embodiment of the invention does not limit these uses.

[0037] In a preferred implementation, the two opposing surfaces of the second substrate are interconnected via pre-defined vias. For example, if only one second substrate is included, its third and fourth surfaces are interconnected vias; if multiple second substrates are included, the two opposing surfaces of each second substrate, such as the (n+4)th and (n+5)th surfaces, are interconnected vias. The pre-defined vias refer to the number and location of vias designed in advance according to the target cells to be installed on the second substrate. It is understood that when multiple second substrates are included, the number and location of the pre-defined vias on each second substrate are different, and this is not limited here.

[0038] In a preferred implementation, the target unit that performs the same function is disposed in the recessed portion of each (n+5)th surface and on each (n+4)th surface. That is, in a preferred embodiment, the target unit is disposed on both opposite surfaces of each second substrate, rather than on only one surface of the second substrate.

[0039] For ease of understanding, Figure 4 The marking of the second substrate is shown, i.e., n=1, and the target unit on the second substrate has the same third function. Therefore, the target unit on the second substrate is denoted as target unit 53. Figure 4 In the middle, the second substrate 20(2) includes a fifth surface m(5) and a sixth surface m(6) facing away from each other, and a third functional chip is disposed on the fifth surface m(5). Figure 4 The target unit (53) and the third bonding finger 21 (2) are shown in the middle. The third functional chip is electrically connected to a third bonding finger 21 (2) through a bonding lead. The sixth surface m (6) is recessed towards the fifth surface m (5) to form a groove 40 (2). After the sixth surface is recessed, the unrecessed part m (61) of the sixth surface m (6) is electrically connected to the third surface m (3). The recessed part of the sixth surface m (6) is provided with a third peripheral resistor component ( Figure 4 The target unit is 53). Among them, the 6th surface m(6) is adjacent to the 3rd surface m(3), and the 5th surface m(5) is far away from the 3rd surface m(3).

[0040] Understandable, Figure 4 The semiconductor module packaging structure shown is also applicable to the shape of the groove 40 shown in the above embodiments, the target unit arrangement shown in the above embodiments, the bottom 31 structure of the metal casing 30, the sealing method of the metal cover 36 shown in the above embodiments, and the electrical connection method shown in the above embodiments.

[0041] The target unit placement method refers to placing the target unit with the highest heat dissipation requirements on the first surface. It should be noted that... Figure 4 When the semiconductor module packaging structure shown above is applied to the target unit setting method, adjustments are made according to the function implemented by the target unit, which is not limited to two types. In this case, the heat dissipation requirement level is sorted. For example, the heat dissipation requirement of the target unit implementing each function is quantified according to the power processing capability of the target unit and its own operating power consumption. The heat dissipation requirements of the target unit implementing function a1, the target unit implementing function a2, ..., the target unit implementing function ab are sorted to obtain the target unit implementing function ax (x∈b) with the highest heat dissipation requirement level.

[0042] like Figure 5 As shown, another embodiment of the present invention also provides a semiconductor module packaging method, using the semiconductor module packaging structure shown in the above embodiment, the method including but not limited to the following steps:

[0043] S501. Modularly decompose the target semiconductor module to obtain a target unit that performs one function and another target unit that performs the same function.

[0044] S502. A target unit that performs the same function is disposed on a first substrate, and a target unit that performs another function is disposed on a second substrate.

[0045] In a preferred implementation, embodiments of the present invention further sort target units implementing one or more functions according to their heat dissipation requirements, and classify each target unit according to its device characteristics. Thus, in step S501, the target unit implementing one function includes a first functional chip and a first peripheral resistor / capacitor, and the target unit implementing another function includes a second functional chip and a second peripheral resistor / capacitor. Step S502 is implemented as follows: the first functional chip and the first peripheral resistor / capacitor are disposed on a first surface of a first substrate, and the first functional chip is electrically connected to a first bonding finger via bonding leads; the second functional chip is disposed on a third surface of a second substrate and is electrically connected to a second bonding finger via bonding leads; the second peripheral resistor / capacitor is disposed in a recessed portion of a fourth surface of the second substrate. This further improves the integration density; in practical applications, the integration density can reach 200%.

[0046] The process involves sorting target units that perform one or more functions according to their heat dissipation requirements. This includes calculating heat dissipation requirements based on the target unit's power processing capacity and operating power consumption. The calculation results are used to quantify the heat dissipation requirements of each target unit, thereby determining whether the heat dissipation requirement level of a target unit performing one function is higher than that of a target unit performing another function. Each target unit is then categorized according to its device characteristics. This includes classifying all devices within any given target unit based on whether they function as resistors or capacitors. Target units performing one function are categorized as first functional chips and first peripheral resistor / capacitor devices; target units performing another function are categorized as second functional chips and second peripheral resistor / capacitor devices.

[0047] It should be noted that when using, such as Figures 1 to 3 The semiconductor module packaging structure shown indicates that the target semiconductor module mainly includes target units that implement two functions. The results of modular decomposition, sorting by heat dissipation requirements, and classification by device characteristics are shown above. When using... Figure 4 The semiconductor module packaging structure shown indicates that the target semiconductor module may include target units that implement multiple functions. Therefore, after modular decomposition of the target semiconductor module, we can obtain target units that implement function a1, target units that implement function a2, ..., and target units that implement functions ab. At this point, using... Figure 4The semiconductor module packaging structure shown uses multiple second substrates for packaging. All N second substrates are used to house target units that perform the same function in the target semiconductor module. This means that: the first second substrate is used to house a target unit with a different function; the second second substrate and the remaining multiple second substrates can be the same as the first second substrate and used to house a target unit with a different function, or they can be different from the first second substrate and used to house another type or multiple types of target units. This embodiment of the invention does not limit this. When using... Figure 4 The semiconductor module packaging structure shown sorts the target units implementing functions a1, a2, ..., and ab according to their heat dissipation requirements. This includes quantifying the heat dissipation requirements of each function based on the target unit's power processing capability and its own operating power consumption, and sorting the heat dissipation requirements of the target units implementing functions a1, a2, ..., and ab to obtain the target unit implementing function ax (x∈b) with the highest heat dissipation requirement. When using... Figure 4 The semiconductor module packaging structure shown above classifies each of the target units implementing function a1, function a2, ..., and function ab according to device characteristics. This includes classifying all devices included in the target unit implementing function a1 as a first functional chip and a first peripheral resistor / capacitor; classifying all devices included in the target unit implementing function a2 as a second functional chip and a second peripheral resistor / capacitor; and classifying all devices included in the target unit implementing function ab as a b-th functional chip and b-th peripheral resistor / capacitor.

[0048] The embodiments of the present invention exemplarily illustrate several target semiconductor modules, including but not limited to power modules, sensor modules, power management modules, and wireless communication modules, to illustrate the above-described semiconductor module packaging method.

[0049] First, the core functional chips of the power module include a driver chip and a power chip; the core functional chips of the sensor module include a sensor chip and a signal processing chip; the core functional chips of the power management module include a power management chip and a battery management chip; and the core functional chips of the wireless communication module include a radio frequency chip and a baseband chip. Therefore, when packaging the target semiconductor modules according to the above packaging method, the target units obtained after modular decomposition include at least two types of core functional chips. For example, after modular decomposition of the power module, target units including a driver chip and its peripheral resistors and capacitors, and target units including a power chip and its peripheral resistors and capacitors can be obtained; after modular decomposition of the sensor module, target units including a sensor chip and its peripheral resistors and capacitors, and target units including a signal processing chip and its peripheral resistors and capacitors can be obtained; after modular decomposition of the power management module, target units including a power management chip and its peripheral resistors and capacitors, and target units including a battery management chip and its peripheral resistors and capacitors can be obtained; and after modular decomposition of the wireless communication module, target units including a radio frequency chip and its peripheral resistors and capacitors, and target units including a baseband chip and its peripheral resistors and capacitors can be obtained.

[0050] Secondly, in this embodiment of the invention, the first functional chip and the first peripheral resistor are disposed on the first surface of the first substrate, indicating that after the target semiconductor module is modularly decomposed, the target unit including the first functional chip and the first peripheral resistor has the highest heat dissipation requirement. Therefore, in specific applications, before disposing the first functional chip and the first peripheral resistor on the first surface of the first substrate, the invention further includes: sorting the target units that implement one function and the target units that implement another function according to their heat dissipation requirement, to obtain a first target unit including the first functional chip and the first peripheral resistor, and a second target unit including the second functional chip and the second peripheral resistor, wherein the first target unit has the highest heat dissipation requirement, and thus the first functional chip and the first peripheral resistor are disposed on the first surface. For example, for a power module, the heat dissipation requirement of the power chip is greater than that of the driver module. In this case, the first functional chip and the first peripheral resistor in the above steps correspond to the power chip and its peripheral resistor, respectively. That is, a target unit that achieves the same function is a target unit including the power chip and its peripheral resistor, and the power chip is the first functional chip, and its peripheral resistor is the first peripheral resistor. In the above steps, the second functional chip and the second peripheral resistor correspond to the driver chip and its peripheral resistor, respectively. That is, a target unit that achieves another function is a target unit including the driver chip and its peripheral resistor, and the driver chip is the second functional chip, and its peripheral resistor is the second peripheral resistor. Furthermore, the power chip and its peripheral resistor are disposed on the first surface. For the sensor module, the heat dissipation requirement of the signal processing chip is greater than that of the sensor chip. Therefore, the first functional chip and the first peripheral resistor / capacitor in the above steps correspond to the signal processing chip and its peripheral components, respectively. That is, the target unit that achieves the same function is a target unit including the signal processing chip and its peripheral resistor / capacitor, and the signal processing chip is the first functional chip, and its peripheral components are the first peripheral resistor / capacitor. Similarly, the second functional chip and the second peripheral resistor / capacitor in the above steps correspond to the sensor chip and its peripheral resistor / capacitor, respectively. That is, the target unit that achieves another identical function is a target unit including the sensor chip and its peripheral resistor / capacitor, and the sensor chip is the second functional chip, and its peripheral resistor / capacitor is the second peripheral resistor / capacitor. Thus, the signal processing chip and its peripheral resistor / capacitor are disposed on the first surface. Likewise, for the power management module and the wireless communication module, the heat dissipation requirement of the power management chip in the power management module is greater than that of the battery management chip, and thus the power management chip is the first functional chip disposed on the first surface; the heat dissipation requirement of the RF chip in the wireless communication module is greater than that of the baseband chip, and thus the RF chip is the first functional chip disposed on the first surface. Other similar content will not be elaborated here.

[0051] Finally, regarding the case where the target semiconductor module includes target units that implement multiple functions, the above-mentioned power module is used as an example in the actual application scenario of industrial robots. In this actual application scenario, the number of target units based on the driver chip usually corresponds to the number of joint axes of the industrial robot, and is responsible for the specific control of each joint axis. Therefore, the power module includes target units that implement two functions, such as target units that implement power supply functions and target units that implement motor drive functions. Among them, the target units that implement motor drive functions include multiple units depending on the joint axis, such as target units that implement specific control of joint axis 1, target units that implement specific control of joint axis 2, target units that implement specific control of joint axis 3, etc. This is applicable to the structure of multiple second substrates. For example, in the final packaging structure, a first functional chip (power chip) and a first peripheral resistor / capacitor are disposed on the first surface of the first substrate. The target units disposed on the first and remaining second substrates have the same functions as those on the first and second substrates. The target units that implement the specific control of the joint axis 1 are disposed on the first and second substrates. Specifically, the second functional chip (the driving chip that drives the joint axis 1) is disposed on the third surface of the first and second substrates, the second peripheral resistor / capacitor is disposed on the fourth surface of the first and second substrates, the third functional chip (the driving chip that drives the joint axis 2) is disposed on the fifth surface of the second and second substrates, and the third peripheral resistor / capacitor is disposed on the sixth surface of the second and second substrates. The rest will not be described in detail. Similarly, in the actual application scenario of industrial robots, for automatic welding, a sensor module in an industrial robot typically uses multiple sensor chips to improve the accuracy of weld seam positioning and the stability of welding quality. In this actual application scenario, at least laser tracking sensors, infrared temperature sensors, and arc sensors are included. Therefore, this sensor module in an industrial robot includes target units that implement four functions, such as a target unit for weld seam positioning, a target unit for temperature monitoring, and a target unit for current and voltage control.For example, in the final packaging structure, a first functional chip (signal processing chip) and a first peripheral resistive capacitor are disposed on the first surface of the first substrate. The target units disposed on the second and remaining second substrates have different functions than those on the first second substrate. For instance, a target unit for weld seam positioning is disposed on the first second substrate; specifically, a second functional chip (laser tracking sensor chip) is disposed on the third surface of the first second substrate, and a second peripheral resistive capacitor is disposed on the fourth surface of the first second substrate. A target unit for temperature monitoring is disposed on the second second substrate; specifically, a third functional chip (infrared temperature sensor chip) is disposed on the fifth surface of the second second substrate, and a third peripheral resistive capacitor is disposed on the sixth surface of the second second substrate. A target unit for current and voltage control is disposed on the third second substrate; specifically, a fourth functional chip (arc sensor chip) is disposed on the seventh surface of the third second substrate, and a third peripheral resistive capacitor is disposed on the eighth surface of the third second substrate. Therefore, the above-described method is preferred for practical application scenarios involving target units implementing two or more functions. Figure 4 The three-dimensional, multi-faceted, multi-cavity semiconductor packaging structure shown is used for packaging.

[0052] In this embodiment of the invention, the power module can be a GaN power module, a SiC power module, or a Ga2O3 power module. GaN power modules, in particular, possess high frequency, high efficiency, and high power density characteristics. Compared to traditional silicon-based devices, they can achieve higher breakdown electric fields and temperature resistance. Furthermore, their electron mobility and saturation velocity are significantly superior to silicon, enabling operation at MHz-level high frequencies. Switching losses are reduced by more than 50%, and the size of passive components is greatly reduced, achieving system-level miniaturization. In addition, the near-zero reverse recovery charge and low on-resistance characteristics of GaN power modules further improve energy efficiency in low- and medium-voltage scenarios (such as fast charging and automotive power supplies), achieving efficiencies of over 95%.

[0053] In practical applications, for GaN power modules, AlN ceramic is used to fabricate the first and second substrates. AlN ceramic has high thermal conductivity, a high degree of matching between its coefficient of thermal expansion and that of the GaN chip, making it suitable for high-frequency applications. Therefore, embodiments of the present invention are particularly used to optimize the packaging structure of GaN power modules, and also to optimize substrate material selection based on the packaging structure of GaN power modules. Combining the advantages of GaN power modules in high temperature resistance (e.g., >200℃) and low drive power consumption, this can provide more compact and efficient solutions for fields such as 5G communication, new energy vehicles, and renewable energy.

[0054] In one embodiment, for a GaN power module, this embodiment of the invention provides a preferred circuit structure implementation, including a primary-side driving circuit, a pulse width modulation control circuit, a synchronous rectification driving circuit, and a half-bridge current multiplier synchronous rectification main power circuit. The half-bridge current multiplier synchronous rectification main power circuit includes a power chip and its peripheral resistors and capacitors. Therefore, according to the semiconductor module packaging method provided by this embodiment of the invention, the power chip and its peripheral resistors and capacitors included in the half-bridge current multiplier synchronous rectification main power circuit are disposed on the first surface of the first substrate. The primary-side driving circuit, pulse width modulation control circuit, and synchronous rectification driving circuit belong to the driving chip and its peripheral resistors and capacitors. Therefore, according to the semiconductor module packaging method provided by this embodiment of the invention, the primary-side driving circuit is disposed on the third surface of the second substrate, and the pulse width modulation control circuit and the synchronous rectification driving circuit are disposed on the fourth surface of the second substrate, i.e., the recessed portion of the fourth surface.

[0055] In practical applications, the circuit structure implementation of the GaN power module described above includes a total of 128 components, such as resistors, capacitors, diodes, transistors, transformers, chips, and electrical connectors; the product has an input voltage of 70~120V, an output voltage of 5V, an output current of 24A, and a power of 120W. Considering actual production and processing capabilities, in... Figure 3 As shown in Figure A, a layout area of ​​55.0mm x 36.6mm is determined. Therefore, in... Figure 3 Within the layable area shown, a first substrate and a second substrate are designed to encapsulate this type of GaN power module, such as... Figure 6 As shown, the first substrate 10 is used to house the power chip and its peripheral resistors and capacitors included in the half-bridge current-doubler synchronous rectification main power circuit. T1 and T3 are transformers in the half-bridge current-doubler synchronous rectification main power circuit, DX, CX, and RX are peripheral passive devices, VMX and QX are transistors, and X represents the serial number of each peripheral resistor and capacitor. Figure 7 and Figure 8 As shown, the second substrate 20 is used to set the primary-side driving circuit, pulse width modulation control circuit, synchronous rectification driving circuit, which belong to the driving chip and its peripheral resistors and capacitors. The chip and its corresponding resistors and capacitors are placed as concentrated as possible in the perspective view direction, and the low parasitic interconnection between the chip and the substrate is achieved through vias. Figure 7 In the middle, the third surface m3 of the second substrate 20 is provided with a primary-side driving circuit, a pulse width modulation control circuit, and a synchronous rectification driving circuit, wherein T2 represents a transformer, U1, U2, U3, and U4 represent the chip part in the above circuit, and D10 represents a diode; Figure 8 In the second substrate 20, the fourth surface m4 is provided with peripheral resistors and capacitors for the primary-side drive circuit, peripheral resistors and capacitors for the pulse width modulation control circuit, and peripheral resistors and capacitors for the synchronous rectification drive circuit, including CX and RX, where X represents the serial number of each peripheral resistor and capacitor.

[0056] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A semiconductor module packaging structure, applied in the field of GaN devices, characterized in that, include: The first substrate includes a first surface and a second surface facing away from each other, and the first surface is provided with a first bonding finger; The second substrate includes a third surface and a fourth surface facing away from each other. The fourth surface is recessed towards the third surface to form a groove. The unrecessed portion of the fourth surface is electrically connected to the first surface to form a cavity that is open from front to back. The third surface is provided with a second bonding finger. The fourth surface is adjacent to the first surface, and the third surface is away from the first surface. A metal casing has a cavity for accommodating the first substrate and the second substrate. The first substrate is mounted in the cavity, and the second surface is in contact with the bottom of the metal casing. Each of the two opposite sidewalls of the metal casing is provided with an external pin, and the second bonding finger is also connected to the external pin via a bonding wire. The other two opposite sidewalls of the metal casing face the cavity that connects the front and back. The first substrate is used to set a target unit in the target semiconductor module that performs the same function, and the second substrate is used to set another target unit in the target semiconductor module that performs the same function. The target unit set on the first surface is electrically connected to the first bonding finger through bonding leads, and the target unit set on the third surface is electrically connected to the second bonding finger through bonding leads. The target semiconductor module includes a GaN power module, and the first substrate and the second substrate are made of AlN ceramic substrates. The second substrate is partially hollowed out by milling to form a left vertical sidewall and a right vertical sidewall, or a left trapezoidal sidewall and a right trapezoidal sidewall.

2. The semiconductor module packaging structure as described in claim 1, characterized in that, The target unit that performs another identical function is disposed in the recessed portion of the fourth surface and the third surface.

3. The semiconductor module packaging structure as described in claim 1, characterized in that, It includes N second substrates, all of which are used to set the target unit in the target semiconductor module to achieve the same function; The first second substrate includes a third surface and a fourth surface facing away from each other. The fourth surface is recessed in the direction of the third surface to form a groove. The unrecessed portion of the fourth surface is electrically connected to the first surface. The third surface is provided with a second bonding finger. The (n+1)th second substrate includes an (n+4)th surface and an (n+5)th surface facing away from each other. The (n+4)th surface is provided with an (n+2)th functional chip and an (n+2)th bonding finger. The (n+2)th functional chip is electrically connected to one of the (n+2)th bonding fingers via bonding leads. The (n+5)th surface is recessed towards the (n+4)th surface to form a groove. The unrecessed portion of the (n+5)th surface is electrically connected to the (n+2)th surface, forming a cavity that is open at both ends. The (n+5)th surface is adjacent to the (n+2)th surface, and the (n+4)th surface is away from the (n+2)th surface. N is a positive integer greater than or equal to 1, and n+1 ≤ N. If only one second substrate is included, the second bonding finger of the first second substrate is connected to the external pin via a bonding lead; if at least two second substrates are included, the bonding finger of the last second substrate is connected to the external pin via a bonding lead.

4. The semiconductor module packaging structure as described in claim 3, characterized in that, The two opposing surfaces of the second substrate are interconnected through pre-set vias.

5. The semiconductor module packaging structure as described in claim 4, characterized in that, The target units that achieve the same function are arranged on two opposite surfaces of each second substrate.

6. The semiconductor module packaging structure as described in claim 2 or 5, characterized in that, The groove is rectangular or trapezoidal in shape.

7. The semiconductor module packaging structure as described in claim 2 or 5, characterized in that, The bottom of the metal casing also includes an extension portion, which is formed by extending the bottom of the metal casing and the two opposite sidewalls of the metal casing with external pins for a predetermined length away from the two opposite sidewalls.

8. The semiconductor module packaging structure as described in claim 7, characterized in that, The target unit with the highest heat dissipation requirements is located on the first surface.

9. The semiconductor module packaging structure as described in claim 7, characterized in that, It also includes a metal cover plate, which is sealed to the top of the metal casing by parallel seam welding.

10. The semiconductor module packaging structure as described in claim 7, characterized in that, The extension has a package pin and a mounting hole on one surface near the outer pin.

11. The semiconductor module packaging structure as described in claim 7, characterized in that, The external pin includes a connection portion located within the inner cavity of the metal casing, and a heat dissipation portion exposed from the inner cavity of the metal casing.

12. The semiconductor module packaging structure as described in claim 2 or 5, characterized in that, The solder used to set the target unit on the first substrate and the second substrate, the solder used to attach the second surface to the bottom of the metal casing, and the solder used to electrically connect the non-recessed portion of the fourth surface to the first surface are all different.

13. A semiconductor module packaging method, characterized in that, Using the semiconductor module packaging structure as described in any one of claims 1 to 12, comprising: The target semiconductor module is modularly decomposed to obtain target units that perform one function and target units that perform another function. A target unit that performs the same function is disposed on a first substrate, and a target unit that performs another function is disposed on a second substrate.

14. The semiconductor module packaging method as described in claim 13, characterized in that, The target units that achieve one function and the target units that achieve another function are sorted according to the heat dissipation requirement level, and each target unit is classified according to the device characteristics to obtain a first target unit including a first functional chip and a first peripheral resistor and capacitor device, and a second target unit including a second functional chip and a second peripheral resistor and capacitor device. The first functional chip and the first peripheral resistor are disposed on the first surface of the first substrate, and the first functional chip is electrically connected to a first bonding finger via a bonding wire; the second functional chip is disposed on the third surface of the second substrate and is electrically connected to a second bonding finger via a bonding wire; the second peripheral resistor is disposed in a recessed portion of the fourth surface of the second substrate.

15. The semiconductor module packaging method as described in claim 13 or 14, characterized in that, The GaN power module includes a primary-side drive circuit, a pulse width modulation control circuit, a synchronous rectification drive circuit, and a half-bridge current multiplier synchronous rectification main power circuit. The half-bridge current multiplier synchronous rectification main power circuit is disposed on the first surface, the primary-side drive circuit, the pulse width modulation control circuit, and the synchronous rectification drive circuit are disposed on the third surface, and the peripheral resistors and capacitors of the primary-side drive circuit, the pulse width modulation control circuit, and the synchronous rectification drive circuit are disposed on the fourth surface.

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