A three-level bus voltage equalization control system

Abstract

This application discloses a three-level bus voltage equalization control system, including an equalization module, an algorithm adjustment module, and an enable module. The algorithm adjustment module is located before the equalization module and is adapted to calculate and output different average bus voltage command values ​​based on the positive and negative cycle states of the phase voltage through non-zero sequence calculation. A first duty cycle signal is obtained by dividing the phase voltage by the average bus voltage command value. The enable module is adapted to judge the degree of bus voltage imbalance and control the algorithm adjustment module and / or the equalization module to operate based on the judgment result. The beneficial effects of this application are: compared with traditional methods, using an algorithm adjustment module in the process of obtaining the duty cycle through phase voltage can suppress bus voltage imbalance to a certain extent; and through the hierarchical bus voltage equalization control method of the enable module, the impact of implementing bus equalization on the system can be minimized.

Description

Technical Field

[0001] This application relates to the field of new energy power generation technology, and in particular to a three-level bus voltage balancing control system. Background Technology

[0002] For grid-connected systems, a three-phase three-wire system is generally used, such as Figure 1 As shown, the DC / AC unit of the grid-connected system adopts a three-level circuit, the three-phase grid-connected current is a symmetrical current, and the control method is generally the traditional dq control.

[0003] When controlling a DC / AC unit, balancing the three-level midpoint voltage is a problem that needs to be addressed, because the midpoint current can cause fluctuations in the bus capacitor voltage and even affect the voltage V of the upper and lower capacitors. dc1 and V dc2 Uneven distribution jeopardizes the safe operation of the system. Therefore, such as Figure 3 As shown, the existing technology adds a voltage equalization module 101 to the traditional dq control. The voltage equalization module 101 can complete the bus voltage difference V dif =V dc1 -V dc2 After calculation, the difference is taken from the reference value of 0 and sent to the PI controller to obtain the duty cycle common mode offset Δd, which is then added to the original duty cycle to obtain the new three-phase duty cycles da and d. b d c This is to achieve bus voltage equalization. The essence of the voltage equalization module 101 is to regulate the bus voltage by adjusting the zero-sequence current. A major problem with this method is that the introduced zero-sequence current increases system losses. Summary of the Invention

[0004] One objective of this application is to provide a three-level bus voltage equalization control system that can solve at least one of the defects in the above-mentioned background art.

[0005] To achieve at least one of the above objectives, the technical solution adopted in this application is as follows: a three-level bus voltage balancing control system, applied to the control loop of a grid-connected system, including a voltage equalization module, an algorithm adjustment module, and an enable module; the voltage equalization module is adapted to add a duty cycle common-mode offset to the first duty cycle signal output from the previous stage, thereby obtaining a second duty cycle signal that suppresses bus voltage imbalance; the algorithm adjustment module is located in the stage preceding the voltage equalization module; the algorithm adjustment module is adapted to calculate and output different average bus voltage command values ​​according to the positive and negative period states of the phase voltage through non-zero sequence calculation; by dividing the phase voltage by the corresponding average bus voltage command value, the first duty cycle signal that suppresses bus voltage imbalance is obtained; the enable module is adapted to judge the degree of bus voltage imbalance and control the algorithm adjustment module and / or the voltage equalization module to work according to the judgment result.

[0006] Preferably, the algorithm adjustment module is adapted to receive the upper bus voltage, the lower bus voltage, and the phase voltage; the algorithm adjustment module includes a filtering unit and a calculation unit; the filtering unit filters the upper bus voltage and the lower bus voltage to obtain the average value of the upper bus voltage and the average value of the lower bus voltage; based on the obtained average value of the upper bus voltage and the average value of the lower bus voltage, the calculation unit is adapted to output different average bus voltage command values ​​according to the different periodic states of the phase voltage.

[0007] Preferably, when the phase voltage is in the positive half-cycle, the calculation unit is adapted to directly use the average value of the lower bus voltage as the average command value of the bus voltage; when the phase voltage is in the negative half-cycle, the calculation unit is adapted to directly use the average value of the upper bus voltage as the average command value of the bus voltage.

[0008] Preferably, the calculation unit is adapted to subtract the upper bus voltage and the lower bus voltage from the average value of the upper bus voltage and the average value of the lower bus voltage, respectively, to obtain the AC value of the upper bus voltage and the AC value of the lower bus voltage; based on the obtained average value of the upper bus voltage, average value of the lower bus voltage, AC value of the upper bus voltage, and AC value of the lower bus voltage, the calculation unit outputs different average bus voltage command values ​​according to the different periodic states of the phase voltage.

[0009] Preferably, when the phase voltage is in the positive half-cycle, the calculation unit is adapted to add the average value of the lower bus voltage and the AC value of the upper bus voltage as the average command value of the bus voltage; when the phase voltage is in the negative half-cycle, the calculation unit is adapted to add the average value of the upper bus voltage and the AC value of the lower bus voltage as the average command value of the bus voltage.

[0010] Preferably, the calculation unit is adapted to subtract the average value of the upper bus voltage and the average value of the lower bus voltage to obtain the DC bus deviation value; based on the obtained upper bus voltage, lower bus voltage and DC bus deviation value, the calculation unit outputs different average bus voltage command values ​​according to the different periodic states of the phase voltage.

[0011] Preferably, when the phase voltage is in the positive half-cycle, the calculation unit is adapted to subtract the average value of the upper bus voltage and the lower bus voltage from the DC bus deviation value to obtain the average command value of the bus voltage; when the phase voltage is in the negative half-cycle, the calculation unit is adapted to add the average value of the upper bus voltage and the lower bus voltage to the DC bus deviation value to obtain the average command value of the bus voltage.

[0012] Preferably, the calculation unit is adapted to subtract the upper bus voltage and the lower bus voltage from the average value of the upper bus voltage and the average value of the lower bus voltage, respectively, to obtain the AC value of the upper bus voltage and the AC value of the lower bus voltage; the calculation unit is adapted to subtract the average value of the upper bus voltage and the average value of the lower bus voltage to obtain the DC bus deviation value; based on the obtained upper bus voltage, lower bus voltage, AC value of the upper bus voltage, AC value of the lower bus voltage, and DC bus deviation value, the calculation unit outputs different average bus voltage command values ​​according to the different periodic states of the phase voltage.

[0013] Preferably, when the phase voltage is in the positive half-cycle, the calculation unit is adapted to add the average value of the upper bus voltage and the lower bus voltage to the AC value of the upper bus voltage and then subtract the DC bus deviation value to obtain the average command value of the bus voltage; when the phase voltage is in the negative half-cycle, the calculation unit is adapted to add the average value of the upper bus voltage and the lower bus voltage to the AC value of the lower bus voltage and the DC bus deviation value to obtain the average command value of the bus voltage.

[0014] Preferably, the upper bus voltage and the lower bus voltage are filtered to obtain the average value V of the upper bus voltage. dc1_avg and the average value of the lower bus voltage V dc2_avg The enabling module is equipped with a first threshold value V. th1 Second threshold value V th2 And the hysteresis value ΔV; where V th2 >V th1 When |V dc1_avg -V dc2_avg |<(V th1 When (V) is -ΔV, the enabling module controls the algorithm adjustment module to work, and the voltage equalization module does not work at this time; when (V) is -ΔV, the enabling module controls the algorithm adjustment module to work, and the voltage equalization module does not work. th1 +ΔV)<|V dc1_avg -V dc2_avg |<(V th2 When |ΔV) is reached, the enabling module controls the voltage equalization module to operate, and the algorithm adjustment module does not operate; when |ΔV) is reached, the enabling module controls the voltage equalization module to operate. dc1_avg -V dc2_avg |>(V th2 When +ΔV), the enabling module controls the algorithm adjustment module and the voltage equalization module to work simultaneously; when |V dc1_avg -V dc2_avg |Located in [V] th1 -ΔV, V th1 +ΔV] or [V] th2 -ΔV, V th2 When +ΔV], the enabling module controls the equalization module and the algorithm adjustment module in the same way as in the previous moment.

[0015] Compared with the prior art, the beneficial effects of this application are as follows:

[0016] Compared to traditional methods, an algorithm adjustment module is used in the process of obtaining the duty cycle through phase voltage, which can suppress the imbalance of bus voltage to a certain extent; and through the hierarchical bus voltage balancing control method of the enable module, the impact of implementing bus balancing on the system can be minimized. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the architecture of a conventional grid-connected inverter system according to this application.

[0018] Figure 2 For this application Figure 1 The diagram shows the specific process of DPWM zero-sequence generation in the architecture shown.

[0019] Figure 3 For this application Figure 1 A schematic diagram showing the addition of a voltage equalization module to the architecture shown.

[0020] Figure 4 This is a schematic diagram of the overall architecture for bus voltage balancing control in this application.

[0021] Figure 5 This is a schematic diagram of the workflow of Example 1 of the algorithm adjustment module in this application.

[0022] Figure 6 This application is approved. Figure 5 The diagram shows the waveform changes of the bus equalization process performed by the algorithm adjustment module.

[0023] Figure 7 This is a schematic diagram of the workflow of Example 2 of the algorithm adjustment module in this application.

[0024] Figure 8 This is a schematic diagram of the workflow of Example 3 of the algorithm adjustment module in this application.

[0025] Figure 9 This is a schematic diagram of the workflow of Example 4 of the algorithm adjustment module in this application.

[0026] Figure 10 This is a schematic diagram of the workflow of the enabling module in this application.

[0027] Figure 11 A timing diagram illustrating the bus voltage balancing control implemented in this application using a hysteresis region.

[0028] In the diagram: equalization module 101, algorithm adjustment module 102, and enable module 103. Detailed Implementation

[0029] The present application will now be further described in conjunction with specific embodiments. It should be noted that, in the description of this specification, the use of terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicates that the specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0030] In the description of this application, it should be noted that the terms "center", "lateral", "longitudinal", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., which indicate the orientation and positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and should not be construed as limiting the specific protection scope of this application.

[0031] It should be noted that the terms "first," "second," etc., in the specification and claims of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0032] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0033] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0034] The terms “comprising” and “having”, and any variations thereof, in the specification and claims of this application are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or device.

[0035] To facilitate understanding of the technical solution of this application, we can first refer to... Figure 1 The control loop of the grid-connected system shown is described below. It is understood that the DC / AC unit is the primary factor affecting the bus voltage balance of the grid-connected system; therefore, the specific working process of the control loop of the three-level DC / AC unit will be described below.

[0036] like Figure 1 As shown, the control loop of the DC / AC unit uses the bus voltage loop as the outer loop, and the bus voltage loop uses the bus voltage setpoint V. dc_sum * and bus voltage value V dc_sum =V dc1 +V dc2 After the difference is calculated, the d-axis current command I is generated by the PI controller. d * Simultaneously, by controlling the three-phase current i a i b and i c After data acquisition and transformation by abc / dq0, the current feedback I is obtained. d , I q And I0. Given the current I... d * and I q * Respectively with current feedback I d and I q After the difference is calculated, the voltage is controlled by a PI controller and then converted by dq0 / abc to obtain the three-phase voltage reference V. a v b and v cThen, divide by the average bus voltage (V). dc1 +V dc2 ) / 2, to obtain the duty cycle signal d a d b and d c The duty cycle signal d a d b and d c The signal d is fed into the DPWM zero-sequence generation unit to obtain the signal d. z Then add it to the original duty cycle signal d. a d b and d c Above, the final duty cycle d is generated. az d bz and d cz Finally, the signal S driving each switch transistor in the DC / AC unit is generated through modulation. Where V... dc1 Indicates the voltage of the upper bus, V dc2 This indicates the voltage of the lower bus.

[0037] like Figure 2 The diagram shown illustrates the specific workflow of the DPWM zero-sequence generation unit. Specifically, based on the obtained duty cycle signal d... a d b and d c When a corresponds to the duty cycle signal d a When >0, generate the minimum duty cycle d corresponding to a. ha 1-d a The second smallest duty cycle d corresponding to a al =d a When a corresponds to the duty cycle signal d a When ≤0, generate the minimum duty cycle d corresponding to a. ha -d a The second smallest duty cycle d corresponding to a al =1+d a When b corresponds to the duty cycle signal d b When >0, the minimum duty cycle d corresponding to b is generated. hb 1-d b b corresponds to the second smallest duty cycle d bl =d b When b corresponds to the duty cycle signal d b When b ≤ 0, generate the minimum duty cycle d corresponding to b. hb -d b b corresponds to the second smallest duty cycle d bl =1+d b When c corresponds to the duty cycle signal d c When c > 0, the minimum duty cycle d corresponding to c is generated. hc1-d c c corresponds to the second smallest duty cycle d cl =d c When c corresponds to the duty cycle signal d c When ≤0, generate the minimum duty cycle d corresponding to c. hc -d c c corresponds to the second smallest duty cycle d cl =1+d c .

[0038] Based on the obtained minimum duty cycle d ha d hb and d hc The minimum duty cycle d corresponding to the three can be calculated. min_hk d min_hk =min(d ha d hb d hc ); based on the obtained second smallest duty cycle d al d bl and d cl The second smallest duty cycle d corresponding to the three can be calculated. min_kl d min_ kl =min(d al d bl d cl When the calculated d min_hk <d min_k1 At that time, a signal d can be output. z =d min_hk When the calculated d min_hk ≥d min_k1 At that time, a signal d can be output. z =-d min_k1 .

[0039] like Figure 3 As shown, after adding the voltage equalization module 101, the three-phase voltage reference v a v b and v c The acquired duty cycle signal can be labeled as the first duty cycle signal d. a ´、d b ´ and d c The voltage equalization module 101 mainly includes a comparator and a PI controller. The comparator is suitable for converting the bus voltage difference V... dif =V dc1 -V dc2 The difference between the value and the reference value 0 is calculated, and the result is fed into a PI controller. Limiting the output of the PI controller yields the duty cycle common-mode offset Δd. This duty cycle common-mode offset Δd is then compared with the first duty cycle signal d. a ´、d b´ and d c By superimposing these signals, the second duty cycle signal d can be obtained and fed into the DPWM zero-sequence generation unit. a d b and d c .

[0040] One preferred embodiment of this application, such as Figure 4 As shown, a three-level bus voltage balancing control system, applied to the control loop of the aforementioned grid-connected system, includes a voltage equalization module 101, an algorithm adjustment module 102, and an enable module 103. The voltage equalization module 101 adds a common-mode offset to the first duty cycle signal output from the previous stage to obtain a second duty cycle signal that suppresses bus voltage imbalance. The algorithm adjustment module 102 is located before the voltage equalization module 101; it can calculate and output different average bus voltage command values ​​based on the positive and negative cycle states of the phase voltage through non-zero sequence calculation; by dividing the phase voltage by the corresponding average bus voltage command value, a first duty cycle signal that suppresses bus voltage imbalance can be obtained. The enable module 103 can determine the degree of bus voltage imbalance and control the algorithm adjustment module 102 and / or the voltage equalization module 101 to operate based on the determination result.

[0041] Understandably, the algorithm adjustment module 102's ability to suppress bus voltage imbalance is weaker than that of the voltage equalization module 101. This is because the voltage equalization module 101 requires zero-sequence current to regulate the bus voltage, which increases system losses. Therefore, when the bus voltage imbalance is weak, the algorithm adjustment module 102 can suppress it, ensuring no additional system losses. However, when the bus voltage imbalance is severe, the voltage equalization module 101, or both the voltage equalization module 101 and the algorithm adjustment module 102, can work simultaneously to maximize the suppression of bus voltage imbalance. The enabling module 103 is used to enable the algorithm adjustment module 102 and the voltage equalization module 101 under different conditions.

[0042] It should be noted that when the algorithm adjustment module 102 is not working, the first duty cycle d a d b and d c The value is obtained through traditional methods, namely, through a three-phase voltage reference v. a v b and v c Divide by the average bus voltage (V) dc1 +V dc2 To obtain the required first duty cycle d, use 1 / 2. a ´、d b ´ and d cWhen the algorithm adjustment module 102 is working, it can replace the traditional first duty cycle d. a ´、d b ´ and d c The method of obtaining ´; that is, the algorithm adjustment module 102 based on the phase voltage v a v b and v c The periodic state is used to output different average bus voltage command values ​​V. dc_a V dc_b and V dc_c Furthermore, the voltage reference for each phase can be divided by the corresponding average command value of the bus voltage to obtain a first duty cycle signal d that can suppress bus voltage imbalance to a certain extent. a ´、d b ´ and d c For ease of description in the following content, phase voltage will be expressed in terms of V. x The average commanded value of the bus voltage is expressed in V. dc_x Let x be represented as {a, b, c}.

[0043] In simpler terms, the algorithm adjustment module 102 in this embodiment can generate the average bus voltage command value V corresponding to each phase. dc_x And the average commanded value V of the bus voltage for each phase dc_x The specific value varies depending on the phase voltage period; that is, the average command value of the bus voltage V. dc_x It can adapt to the bus voltage imbalance state, thereby suppressing the bus voltage imbalance.

[0044] Therefore, compared with the traditional method, the technical solution of this application can suppress the imbalance of bus voltage to a certain extent by using the algorithm adjustment module 102 in the process of obtaining the duty cycle through phase voltage; and by using the hierarchical bus voltage balancing control method of the enable module 103, the impact of implementing bus balancing on the system can be minimized.

[0045] Since the specific structure and working process of the voltage equalization module 101 are well known to those skilled in the art and have been described above, the specific structure and working process of the algorithm adjustment module 102 will be described in detail below. There are various specific structures of the algorithm adjustment module 102 that can achieve the above functions. For ease of understanding, four specific examples will be used to illustrate these points in detail below.

[0046] Example 1: such as Figure 5 As shown, the algorithm adjustment module 102 can receive the upper bus voltage V dc1 Lower bus voltage V dc2 and phase voltage vx The algorithm adjustment module 102 includes a filtering unit and a calculation unit; the filtering unit can be used to adjust the upper bus voltage V. dc1 and lower bus voltage V dc2 After filtering, the average value V of the upper bus voltage is obtained. dc1_avg and the average value of the lower bus voltage V dc2_avg Based on the obtained average value V of the upper bus voltage. dc1_avg and the average value of the lower bus voltage V dc2_avg The calculation unit can calculate based on the phase voltage v x Different periodic states result in different average command values ​​for the bus voltage.

[0047] Specifically, such as Figure 5 As shown, when the reference signal v of the phase voltage x When in the positive half-cycle, i.e. v x When >0; the calculation unit can calculate the average value V of the lower bus voltage. dc2_avg Directly used as the average command value V of the bus voltage dc_x V dc_x =V dc2_avg When the reference signal v of the phase voltage x When in the negative half-cycle, i.e. v x When ≤0; the calculation unit can calculate the average value V of the upper bus voltage. dc1_avg Directly used as the average command value V of the bus voltage dc_x V dc_x =V dc1_avg .

[0048] It is understandable that the imbalance in bus voltage is the same as the upper bus voltage V. dc1 and lower bus voltage V dc2 The imbalance. For example Figure 6 As shown in (1), when the bus voltage is balanced, the phase current i x The output waveform of (x=a, b, c) is symmetrical vertically. Meanwhile, the average value of the current bus voltage V... dc2_avg Less than the average voltage of the upper bus V dc1_avg During the positive half-cycle of the phase voltage, the algorithm adjustment module 102 will divide the following average bus voltage V... dc2_avg During the negative half-cycle, the average bus voltage V will be divided by the above. dc1_avg Therefore, the phase current i x The output waveform will show a positive offset, that is, as shown below. Figure 6 As shown in (2), a positive bias current will be generated flowing into the midpoint of the bus, so that the lower bus will be charged, thereby balancing the voltage of the upper and lower buses.

[0049] Similarly, the current average bus voltage V dc2_avg Greater than the average voltage of the upper bus Vdc1_avg During the positive half-cycle of the phase voltage, the algorithm adjustment module 102 will divide the following average bus voltage V... dc2_avg During the negative half-cycle, the average bus voltage V will be divided by the above. dc1_avg Therefore, the phase current i x The output waveform will show a negative offset, that is, as shown below. Figure 6 As shown in (3), a negative bias current will be generated flowing out of the midpoint of the busbar, so that the upper busbar will be charged, thereby balancing the voltage of the upper and lower busbars.

[0050] Example 2: such as Figure 7 As shown, this example adds a comparison unit to the calculation unit based on Example 1. The comparison unit can compare the bus voltage V. dc1 With the average voltage V of the upper bus dc1_avg Subtracting the two values ​​yields the AC component of the upper bus voltage, i.e., the AC value V of the upper bus voltage. dc1_ac Similarly, the comparison unit can also compare the lower bus voltage V. dc2 With the average value of the lower bus voltage V dc2_avg Subtracting the two values ​​yields the AC component of the lower bus voltage, i.e., the AC value V of the lower bus voltage. dc2_ac Based on the obtained average value V of the upper bus voltage. dc1_avg Average value of the lower bus voltage V dc2_avg AC value of upper bus voltage V dc1_ac and the AC value of the lower bus voltage V dc2_ac The calculation unit can calculate based on the phase voltage v x Different periodic states result in different average bus voltage command values ​​V. dc_x .

[0051] Specifically, such as Figure 7 As shown, when the reference signal v of the phase voltage x When in the positive half-cycle, i.e. v x When >0; the calculation unit can calculate the average value V of the lower bus voltage. dc2_avg AC value of the upper bus voltage V dc1_ac The sum is used as the average command value V of the bus voltage. dc_x V dc_x =V dc2_avg +V dc1_ac When the reference signal v of the phase voltage x When in the negative half-cycle, i.e. v x When ≤0; the calculation unit can calculate the average value V of the upper bus voltage. dc1_avg AC value of the lower bus voltage V dc2_ac The sum is used as the average command value V of the bus voltage. dc_x V dc_x =V dc1_avg +Vdc2_ac .

[0052] Understandably, this example separates the DC and AC components of the bus; the DC components are crossed, i.e., the phase voltage v x The average bus voltage V during the positive half-cycle dc2_avg During the negative half-cycle, the average value of the upper bus voltage V is used. dc1_avg This is to suppress bus voltage imbalance; AC components do not cross over, i.e., phase voltage v x The positive half-cycle uses the AC value of the upper bus voltage V dc1_ac During the negative half-cycle, the AC value of the lower bus voltage V is used. dc2_ac Since AC does not affect bus offset, no crossing is required, thus ensuring the phase current i x The quality of the output waveform.

[0053] Example 3: such as Figure 8 As shown, this example adds a comparison unit and a PI controller to the calculation unit, based on Example 1. The comparison unit can calculate the average value V of the upper bus voltage output from the filtering unit. dc1_avg and the average value of the lower bus voltage V dc2_avg By performing the difference operation, and then passing it through a PI controller and limiting it, the DC bus deviation value ΔV can be obtained. dc Based on the obtained upper bus voltage V dc1 Lower bus voltage V dc2 and DC bus deviation value ΔV dc The calculation unit can calculate based on the phase voltage v x Different periodic states result in different average bus voltage command values ​​V. dc_x .

[0054] Specifically, such as Figure 8 As shown, when the reference signal v of the phase voltage x When in the positive half-cycle, i.e. v x When >0; the calculation unit can calculate the upper bus voltage V dc1 and lower bus voltage V dc2 The average value and the deviation value ΔV of the DC bus dc Subtraction is used as the average command value V of the bus voltage. dc_x V dc_x =(V dc1 +V dc2 ) / 2-ΔV dc When the reference signal v of the phase voltage x When in the negative half-cycle, i.e. v x When ≤0; the calculation unit can calculate the upper bus voltage V dc1 and lower bus voltage V dc2 The average value and the deviation value ΔV of the DC bus dcThe sum is used as the average command value V of the bus voltage. dc_x V dc_x =(V dc1 +V dc2 ) / 2+ΔV dc .

[0055] Understandably, compared to Examples 1 and 2, this example employs closed-loop control, which can better achieve bus voltage control. Specifically, the current average bus voltage V... dc2_avg Less than the average voltage of the upper bus V dc1_avg At that time, after PI control, the DC bus deviation value ΔV dc It will shift in the positive direction. According to the algorithm adjustment module 102's operating process, at phase voltage v... x The value divided by the positive half-period is (V dc1 +V dc2 ) / 2-ΔV dc This value will be too small; in the phase voltage v x The value divided by the negative half-cycle is (V dc1 +V dc2 ) / 2+ΔV dc This value will be too large. Therefore, the phase current i x The output waveform will show a positive offset, which will generate a positive bias current flowing into the midpoint of the bus, thus charging the lower bus and balancing the voltage of the upper and lower buses.

[0056] Similarly, the current average bus voltage V dc2_avg Greater than the average voltage of the upper bus V dc1_avg At that time, after PI control, the DC bus deviation value ΔV dc It will shift in the negative direction. According to the algorithm adjustment module 102's operation, at phase voltage v... x The value divided by the positive half-period is (V dc1 +V dc2 ) / 2-ΔV dc This value will be too large; in the phase voltage v x The value divided by the negative half-cycle is (V dc1 +V dc2 ) / 2+ΔV dc This value will be too small. Therefore, the phase current i x The output waveform will show a negative offset, which will generate a bias current flowing out of the midpoint of the bus. This will charge the upper bus and make the voltage of the upper and lower buses reach balance.

[0057] Example 4: This example is a combination of Example 2 and Example 3, such as... Figure 9 As shown, this example adds a comparison unit and a PI controller to the calculation unit, based on Example 1. The comparison unit can compare the bus voltage V.dc1 With the average voltage V of the upper bus dc1_avg Subtracting the two values ​​yields the AC value V of the upper bus voltage. dc1_ac Similarly, the comparison unit can also compare the lower bus voltage V. dc2 With the average value of the lower bus voltage V dc2_avg Subtracting the two values ​​yields the AC value V of the lower bus voltage. dc2_ac Simultaneously, the comparison unit can output the average value V of the upper bus voltage from the filter unit. dc1_avg and the average value of the lower bus voltage V dc2_avg By performing the difference operation, and then passing it through a PI controller and limiting it, the DC bus deviation value ΔV can be obtained. dc Based on the obtained upper bus voltage V dc1 Lower bus voltage V dc2 AC value of upper bus voltage V dc1_ac AC value of the lower bus voltage V dc2_ac and DC bus deviation value ΔV dc The calculation unit can calculate based on the phase voltage v x Different periodic states result in different average bus voltage command values ​​V. dc_x .

[0058] Specifically, such as Figure 9 As shown, when the reference signal v of the phase voltage x When in the positive half-cycle, i.e. v x When >0; the calculation unit can calculate the upper bus voltage V dc1 and lower bus voltage V dc2 The average value and the AC value of the upper bus voltage V dc1_ac After addition, subtract the DC bus deviation value ΔV dc As the average command value of bus voltage V dc_x V dc_x =(V dc1 +V dc2 ) / 2-ΔV dc +V dc1_ac When the reference signal v of the phase voltage x When in the negative half-cycle, i.e. v x When ≤0; the calculation unit can calculate the upper bus voltage V dc1 and lower bus voltage V dc2 The average value and the AC value of the lower bus voltage V dc2_ac and DC bus deviation value ΔV dc The sum is used as the average command value V of the bus voltage. dc_x V dc_x =(V dc1 +V dc2 ) / 2+ΔV dc +V dc2_ac .

[0059] Understandably, this example can combine the advantages of Examples 2 and 3 to improve the phase current i while achieving closed-loop control. x The quality of the output waveform.

[0060] In this embodiment, as described above, the enabling module 103 can achieve graded control based on the degree of bus voltage imbalance. For example... Figure 10 As shown, the enable signal for the algorithm adjustment module 102 by the enable module 103 can be set to S. 102 The enable signal for the voltage equalization module 101 from the enable module 103 is S. 101 When the enable signal is high, the corresponding module operates; conversely, when the enable signal is low, the corresponding module stops. When only the algorithm adjustment module 102 operates, the operating mode of the enable module 103 can be marked as M3, and the corresponding enable signal is: S 101 =0, S 102 =1; When only the voltage equalization module 101 is working, the operating mode of the enable module 103 can be marked as M2, and the corresponding enable signal is: S 101 =1,S 102 =0; When both the voltage equalization module 101 and the algorithm adjustment module 102 are working, the working mode of the enable module 103 can be marked as M1, and the corresponding enable signal is: S 101 =1,S 102 =1.

[0061] To ensure that the enable module 103 can accurately execute modes M1 to M3, the degree of bus voltage imbalance can be divided. Specifically, two threshold values ​​can be set, namely the first threshold value V. th1 Second threshold value V th2 Among them, V th2 >V th1 Therefore, the upper bus voltage and lower bus voltage can be filtered to obtain the average value V of the upper bus voltage. dc1_avg and the average value of the lower bus voltage V dc2_avg The average value V of the upper bus voltage can be obtained. dc1_avg and the average value of the lower bus voltage V dc2_avg The difference is used to determine the degree of bus voltage imbalance.

[0062] When |V dc1_avg -V dc2_avg |<V th1 When the bus voltage imbalance is relatively weak, the enable module 103 can execute mode M3, and then send a high-level enable signal S to the algorithm adjustment module 102. 102This enables the algorithm adjustment module 102 to operate and suppress bus voltage imbalance.

[0063] When V th1 ≤|V dc1_avg -V dc2_avg |≤V th2 When this occurs, it indicates a severe imbalance in the bus voltage. In this case, the enable module 103 can execute mode M2, and then send a high-level enable signal S to the voltage equalization module 101. 101 This enables the voltage equalization module 101 to operate and suppress bus voltage imbalance.

[0064] When |V dc1_avg -V dc2_avg |>V th2 When this occurs, it indicates that the bus voltage imbalance is severe. At this time, the enable module 103 can execute mode M1, and then send a high-level enable signal S to the voltage equalization module 101 and the algorithm adjustment module 102 respectively. 101 and S 102 This allows the voltage equalization module 101 and the algorithm adjustment module 102 to work simultaneously to suppress bus voltage imbalance.

[0065] It should be known that when the bus voltage deviation |V dc1_avg -V dc2_avg |Located at the first threshold value V th1 Or the second threshold value V th2 When the voltage is near the same level, the enable module 103 will frequently switch modes, which may easily damage the algorithm adjustment module 102 and the voltage equalization module 101. In order to avoid frequent mode switching of the enable module 103, a hysteresis setting can be applied to the enable module 103.

[0066] Specifically, such as Figure 11 As shown, a hysteresis value ΔV can be set within the enable module 103; that is, [V th1 -ΔV, V th1 +ΔV] and [V th2 -ΔV, V th2 +ΔV] can be defined as the hysteresis region. When |V dc1_avg -V dc2_avg |<(V th1 When -ΔV), the enable module 103 executes mode M3 to adjust the control algorithm module 102, and the equalizing module 101 does not work. When (V th1 +ΔV)<|V dc1_avg -V dc2_avg |<(V th2 When |ΔV) is reached, the enable module 103 executes mode M2 ​​to control the voltage equalization module 101 to operate, and the algorithm adjustment module 102 does not operate.dc1_avg -V dc2_avg |>(V th2 When +ΔV), enable module 103 executes mode M1 to control the simultaneous operation of control algorithm adjustment module 102 and voltage equalization module 101. When |V dc1_avg -V dc2_avg |Located in [V] th1 -ΔV, V th1 +ΔV] or [V] th2 -ΔV, V th2 When +ΔV], the control of the equalization module 101 and the algorithm adjustment module 102 by the enable module 103 depends on the previous moment.

[0067] It is understandable that if Figure 11 The direction indicated by the thick solid arrow is the mode execution direction of the enable module 103. When the bus voltage deviation |V dc1_avg -V dc2_avg |Located in the hysteresis zone [V] th1 -ΔV, V th1 When the bus voltage deviation is within [+ΔV], if the enabling module 103 was executing mode M3 in the previous moment, then the enabling module 103 will still execute mode M3 in the current moment; if the enabling module 103 was executing mode M2 ​​in the previous moment, then the enabling module 103 will still execute mode M2 ​​in the current moment. dc1_avg -V dc2_avg |Located in the hysteresis zone [V] th2 -ΔV, V th2 If the enable module 103 was executing mode M2 ​​in the previous moment, then the enable module 103 will still execute mode M2 ​​in the current moment; if the enable module 103 was executing mode M1 in the previous moment, then the enable module 103 will still execute mode M1 in the current moment.

[0068] The basic principles, main features, and advantages of this application have been described above. Those skilled in the art should understand that this application is not limited to the above embodiments. The embodiments and descriptions in the specification are merely the principles of this application. Various changes and modifications can be made to this application without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claims. The scope of protection claimed by this application is defined by the appended claims and their equivalents.

Claims

1. A three-level bus voltage balancing control system, applied to the control loop of a grid-connected system, characterized in that, include: Voltage equalization module; The voltage equalization module is adapted to add a duty cycle common mode offset to the first duty cycle signal output from the previous stage, thereby obtaining a second duty cycle signal that suppresses bus voltage imbalance. Algorithm adjustment module; The algorithm adjustment module is located in the stage preceding the voltage equalization module; The algorithm adjustment module is adapted to calculate and output different average bus voltage command values ​​according to the positive and negative period states of the phase voltage through non-zero sequence calculation; by dividing the phase voltage by the corresponding average bus voltage command value, the first duty cycle signal that suppresses bus voltage imbalance is obtained. as well as Enable module; The enabling module is adapted to determine the degree of bus voltage imbalance and control the algorithm adjustment module and / or the voltage equalization module to work based on the determination result.

2. The three-level bus voltage balancing control system as described in claim 1, characterized in that, The algorithm adjustment module is adapted to receive the upper bus voltage, the lower bus voltage, and the phase voltage; the algorithm adjustment module includes: Filtering unit; the filtering unit filters the upper bus voltage and the lower bus voltage to obtain the average value of the upper bus voltage and the average value of the lower bus voltage; and The calculation unit, based on the obtained average upper bus voltage and average lower bus voltage, is adapted to output different average bus voltage command values ​​according to different phase voltage period states.

3. The three-level bus voltage balancing control system as described in claim 2, characterized in that, When the phase voltage is in the positive half-cycle, the calculation unit is adapted to directly use the average value of the lower bus voltage as the average command value of the bus voltage. When the phase voltage is in the negative half-cycle, the calculation unit is adapted to directly use the average value of the upper bus voltage as the average command value of the bus voltage.

4. The three-level bus voltage balancing control system as described in claim 2, characterized in that, The calculation unit is adapted to subtract the upper bus voltage from the average value of the upper bus voltage, and to subtract the lower bus voltage from the average value of the lower bus voltage, to obtain the AC value of the upper bus voltage and the AC value of the lower bus voltage. Based on the obtained average upper bus voltage, average lower bus voltage, AC value of upper bus voltage, and AC value of lower bus voltage, the calculation unit outputs different average bus voltage command values ​​according to the different periodic states of the phase voltage.

5. The three-level bus voltage balancing control system as described in claim 4, characterized in that, When the phase voltage is in the positive half-cycle, the calculation unit is adapted to add the average value of the lower bus voltage and the AC value of the upper bus voltage as the average command value of the bus voltage. When the phase voltage is in the negative half-cycle, the calculation unit is adapted to add the average value of the upper bus voltage and the AC value of the lower bus voltage as the average command value of the bus voltage.

6. The three-level bus voltage balancing control system as described in claim 2, characterized in that, The calculation unit is adapted to subtract the average value of the upper bus voltage from the average value of the lower bus voltage to obtain the DC bus deviation value; Based on the obtained upper bus voltage, lower bus voltage, and DC bus deviation value, the calculation unit outputs different average bus voltage command values ​​according to the different periodic states of the phase voltage.

7. The three-level bus voltage balancing control system as described in claim 6, characterized in that, When the phase voltage is in the positive half-cycle, the calculation unit is adapted to subtract the average value of the upper bus voltage and the lower bus voltage from the DC bus deviation value to obtain the average command value of the bus voltage. When the phase voltage is in the negative half-cycle, the calculation unit is adapted to add the average value of the upper bus voltage and the lower bus voltage to the DC bus deviation value as the average command value of the bus voltage.

8. The three-level bus voltage balancing control system as described in claim 2, characterized in that, The calculation unit is adapted to subtract the upper bus voltage from the average value of the upper bus voltage, and to subtract the lower bus voltage from the average value of the lower bus voltage, to obtain the AC value of the upper bus voltage and the AC value of the lower bus voltage. The calculation unit is adapted to subtract the average value of the upper bus voltage from the average value of the lower bus voltage to obtain the DC bus deviation value; Based on the obtained upper bus voltage, lower bus voltage, AC value of upper bus voltage, AC value of lower bus voltage, and DC bus deviation value, the calculation unit outputs different average command values ​​of bus voltage according to the different periodic states of the phase voltage.

9. The three-level bus voltage balancing control system as described in claim 8, characterized in that, When the phase voltage is in the positive half-cycle, the calculation unit is adapted to add the average value of the upper bus voltage and the lower bus voltage to the AC value of the upper bus voltage and then subtract the DC bus deviation value to obtain the average command value of the bus voltage. When the phase voltage is in the negative half-cycle, the calculation unit is adapted to add the average value of the upper bus voltage and the lower bus voltage to the AC value of the lower bus voltage and the DC bus deviation value as the average command value of the bus voltage.

10. The three-level bus voltage balancing control system according to any one of claims 1-9, characterized in that, The upper bus voltage and lower bus voltage are filtered to obtain the average value V of the upper bus voltage. dc1_avg and the average value of the lower bus voltage V dc2_avg ; The enabling module is equipped with a first threshold value V. th1 Second threshold value V th2 And the hysteresis value ΔV; Among them, V th2 >V th1 ; When |V dc1_avg -V dc2_avg |<(V th1 When -ΔV), the enabling module controls the algorithm adjustment module to work, and the equalizing module does not work at this time; When (V) th1 +ΔV)<|V dc1_avg -V dc2_avg |<(V th2 When -ΔV), the enabling module controls the equalization module to work, and the algorithm adjustment module does not work at this time; When |V dc1_avg -V dc2_avg |>(V th2 When +ΔV), the enabling module controls the algorithm adjustment module and the equalizing module to work simultaneously; When |V dc1_avg -V dc2_avg |Located in [V] th1 -ΔV, V th1 +ΔV] or [V] th2 -ΔV, V th2 When +ΔV], the enabling module controls the equalization module and the algorithm adjustment module in the same way as in the previous moment.

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