PFM conversion hysteresis scheme for peak current mode buck converter

Abstract

A peak current mode (PCM) buck converter comprising a slope compensation element is provided, the PCM buck converter being arranged to detect entry or exit of a pulse frequency modulation (PFM) mode of operation. The slope compensation element is arranged to deactivate or reduce slope compensation when the PCM buck converter detects the entry into the PFM. The slope compensation element is arranged to enable the slope compensation when the PCM buck converter detects the exit of the PFM.

Description

Technical Field

[0001] The present disclosure relates to buck converters, and more particularly to peak current mode (PCM) controlled buck converters. Background Art

[0002] Battery-operated devices, such as personal electronic devices, robots, electric vehicles, industrial equipment, medical equipment, and wearable devices, require a stable and consistent power supply. In addition, longer battery life is required, so high efficiency (especially during light loads) is important. In these applications, an efficient voltage regulator can be used to provide a regulated voltage from the battery to the device while requiring less battery power to operate. In addition, display devices (such as organic light-emitting diode displays) also include voltage regulators. A stable output voltage with minimal ripple is important for the correct operation of these display devices.

[0003] A switching regulator, also known as a DC-DC converter, can be used to convert or regulate an input voltage to an output voltage. The input voltage can be greater than, less than, or equal to the output voltage. If the input voltage is greater than the output voltage, the converter / regulator can be called a "step-down" converter / regulator or a "buck converter." If the converter / regulator can perform both boost and buck functions, it can be called a "buck-boost converter."

[0004] A peak-current mode (PCM) controlled buck converter refers to a type of control strategy used to regulate the output voltage in a DC-DC buck converter. In this control scheme, the converter adjusts the duty cycle of the switching transistor based on the peak current flowing through an energy storage device such as an inductor. This approach helps improve the converter's dynamic response and stability. Peak current mode control is commonly used in various power supply applications where fast transient response and good overall performance are critical.

[0005] Typically, a switching regulator includes at least one power switch and one or more energy storage devices, such as an inductor and a capacitor. The power switch can be implemented using a metal oxide silicon field effect transistor (MOSFET), a bipolar junction transistor (BJT), or other types of power transistors. A switching regulator can include a high-side switch and a low-side switch or a single power switch and a diode. A transistor can be used instead of a diode. The operation of a switching regulator basically involves turning on the power switch to provide energy to the inductor and then turning off the power switch, causing the energy stored in the inductor to be transferred to the load (and the output capacitor). The power switch is turned on and off based on the load characteristics and the energy required by the load.

[0006] Different operating modes can be used to implement switching of the power switch, and the switching converter can switch from one mode to the next. Continuous conduction mode (CCM) operation occurs when the energy stored in the inductor during the on-time of the power switch increases by an amount equal to the energy released to the output during the off-time of the power switch. Any remaining energy remains stored in the inductor. During the next on-time of the power switch, energy is added from the remaining energy to the point required by the load in the next switching cycle.

[0007] Another operating mode is discontinuous conduction mode (DCM). In this operating mode, the energy stored in the inductor during the on-time of the power switch is equal to the energy required by the load during a single switching cycle plus the energy lost due to converter losses. Essentially, the energy in the inductor is depleted to zero before the end of the switching cycle in DCM, but some residual energy remains in the inductor at the end of the switching cycle in CCM. DCM is typically used for mid-range loads, while CCM is typically used for higher-range loads.

[0008] Other operating modes utilize feedback to vary the frequency or duty cycle of the switching cycle. For example, pulse frequency modulation (PFM) varies the switching frequency (with either a fixed on-duration or a fixed off-duration) in proportion to the load. In other words, as the load increases, the number of on-durations in a given period increases. Because the switching frequency increases with load, switching noise increases in a manner that is not easily filtered. For this reason, PFM offers high efficiency and reduced switching noise during lighter load conditions.

[0009] Transitioning from one mode to another can result in output voltage ripple, additional switching noise, efficiency loss, and / or audible noise. For example, when a PCM-controlled buck converter approaches DCM conversion and the converter has a PFM control loop for light-load efficiency, the converter may jump between the two control loops. As the PCM and PFM control loops switch control of the output, higher switching jitter can be observed at the switch node, potentially resulting in higher output ripple. Summary of the Invention

[0010] The following describes an overview of aspects of the specific examples disclosed herein. It should be understood that the aspects presented are intended only to provide the reader with a brief overview of these specific embodiments and are not intended to limit the scope of the present disclosure. In fact, the present disclosure may encompass multiple aspects and / or combinations of aspects that may not be described.

[0011] The present disclosure is directed to overcoming the shortcomings identified in the background section. In particular, the present disclosure is directed to reducing or eliminating switch jitter on a switch node of a buck converter, particularly a peak current mode buck converter, thereby reducing or eliminating output voltage ripple and achieving a cleaner output voltage.

[0012] According to one aspect of the present disclosure, a PCM buck converter is provided. The PCM buck converter may include a slope compensation element. The PCM buck converter may be arranged to detect entry into or exit from a pulse frequency modulation (PFM) operating mode. Hereinafter, "PFM operating mode" may also be referred to as "PFM." The slope compensation element may be arranged to disable or reduce slope compensation when the PCM buck converter detects entry into PFM. The slope compensation element may be arranged to enable slope compensation when the PCM buck converter detects exit from PFM.

[0013] In one embodiment, the PCM buck converter may further include an inductor. The PCM buck converter may be arranged to increase the peak value of the inductor current passing through the inductor by disabling or reducing slope compensation when entering PFM is detected. The PCM buck converter may be arranged to reduce the peak value of the inductor current passing through the inductor by enabling slope compensation when exiting PFM is detected.

[0014] In one embodiment, the PCM buck converter may further include an error amplifier (EA). The EA may be configured to generate an EA output voltage (VCOMP). The PCM buck converter may further include a modulator. The modulator may be configured to apply slope compensation to VCOMP when slope compensation is enabled. The modulator may be configured to stop applying slope compensation to VCOMP when slope compensation is disabled.

[0015] In one embodiment, the PCM buck converter may further include a clamp circuit. The clamp circuit may be arranged to receive VCOMP from the EA. The PCM buck converter may further include a pulse frequency modulation (PFM) comparator arranged to receive a PFM detection voltage (PFM_DET). PFM_DET may be based on VCOMP. The PFM comparator may be arranged to generate a PFM activation signal (PFM_ACT) by comparing PFM_DET with a reference voltage for PFM detection (VREF_PFM_DET). The slope compensation element may be arranged to be triggered by PFM_ACT to enable or disable slope compensation.

[0016] In one embodiment, the clamp circuit may include a clamp amplifier arranged to receive VCOMP from the EA. The clamp amplifier may be arranged to adjust VCOMP to a reference voltage (VREF_PFM) for PFM. The clamp circuit may include one or more transistors arranged to increase VREF_PFM to obtain PFM_DET.

[0017] In one embodiment, the PCM buck converter may further comprise a converter oscillator.The clamp circuit may further be arranged to generate a signal to the converter oscillator for PFM frequency foldback.

[0018] According to one aspect of the present invention, a switching regulator is provided, which may include one or more PCM buck converters having one or more of the above features.

[0019] According to one aspect of the present invention, a slope compensation element for a PCM buck converter is provided. The slope compensation element can be configured to disable or reduce slope compensation when the PCM buck converter detects entering a PFM operating mode. The slope compensation element can also be configured to enable slope compensation when the PCM buck converter detects exiting PFM.

[0020] In one embodiment, the slope compensation element may be arranged to be triggered by a PFM activation signal (PFM_ACT) from the PFM comparator to enable or disable slope compensation.

[0021] According to one aspect of the present invention, a clamping circuit for a PCM buck converter is provided. The clamping circuit may be arranged to receive an EA output voltage (VCOMP) from an EA. The clamping circuit may include a PFM comparator arranged to receive a PFM detection voltage (PFM_DET). PFM_DET may be based on VCOMP. The PFM comparator may be arranged to generate a PFM activation signal (PFM_ACT) by comparing PFM_DET with a reference voltage (VREF_PFM_DET) for PFM detection. The PFM comparator may be arranged to output PFM_ACT to a slope compensation element for triggering the slope compensation element to enable or disable slope compensation when the PCM buck converter enters or exits a PFM operating mode.

[0022] In one embodiment, the clamp circuit may include a clamp amplifier arranged to receive VCOMP from the EA. The clamp amplifier may also be arranged to adjust VCOMP to a reference voltage (VREF_PFM) for PFM. The clamp circuit may include one or more transistors arranged to increase VREF_PFM to obtain PFM_DET.

[0023] In one embodiment, the clamp circuit may also be arranged to generate a signal to the converter oscillator for PFM frequency foldback. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Embodiments of the present disclosure will now be described, by way of example only, with reference to the accompanying schematic drawings, in which corresponding reference characters indicate corresponding parts, and in which:

[0025] Figure 1 An example high-level schematic diagram of a PCM buck converter is shown.

[0026] Figure 2 Shown Figure 1 An example embodiment of a clamping circuit for a PCM buck converter.

[0027] Figure 3 is an abstract representation of a switching regulator including a PCM buck converter.

[0028] Figure 4 It is the timing diagram of the signal on the PFM input.

[0029] Figure 5 It is the timing diagram of the signal on the PFM output.

[0030] The accompanying drawings are only used for illustrative purposes and do not limit the scope of protection defined by the claims. DETAILED DESCRIPTION

[0031] It will be readily understood that the components of the embodiments, as generally described herein and illustrated in the accompanying drawings, may be arranged and designed in a variety of different configurations. Therefore, the following more detailed description of various embodiments, as illustrated in the accompanying drawings, is not intended to limit the scope of the present disclosure, but rather is merely representative of various embodiments. Although various aspects of the embodiments are presented in the drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0032] The described embodiments should be considered in all respects only as illustrative and not restrictive. Therefore, the scope of the present disclosure is indicated by the appended claims rather than by this detailed description. All changes within the equivalent meaning and range of the claims are included within their scope.

[0033] References to features, advantages, or similar language throughout this specification do not imply that all features and advantages that may be realized with the present disclosure are or should be included in any single example of the present disclosure. Rather, language referring to features and advantages should be understood to mean that a particular feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, discussions of features and advantages and similar language throughout this specification may, but do not necessarily, refer to the same example.

[0034] In addition, the described features, advantages and characteristics of the present disclosure may be combined in any suitable manner in one or more embodiments. Those skilled in the relevant art will recognize that, based on the description herein, the present disclosure may be practiced without one or more of the specific features or advantages of a particular embodiment. In other cases, additional features and advantages that may not be present in all embodiments of the present disclosure may be recognized in certain embodiments. References throughout this specification to "one embodiment," "an embodiment," or similar language mean that the particular features, structures, or characteristics described in conjunction with the indicated embodiment are included in at least one embodiment of the present disclosure. Therefore, the phrases "in one embodiment," "in an embodiment," and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

[0035] Figure 1 An example high-level schematic diagram of a PCM buck converter 100 is shown according to an example embodiment of the present disclosure.

[0036] The PCM buck converter 100 may include an error amplifier (EA) 110, a clamp circuit 120, a PFM comparator

[0037] 130, slope compensation element 140, modulator 150, power stage element 160, feedback gain element 170, converter oscillator 180, inductor 102, capacitor 104, and resistor 106. Reference numerals 2-18 denote input and output signals, including a loop reference voltage (Loop VREF) 2, a reference voltage for PFM detection (VREF_PFM_DET) 8, a PFM detection voltage (PFM_DET) 9, an EA output voltage (VCOMP) 10, a PFM activation signal (PFM_ACT) 12, a slope compensation voltage 16, and an inductor current 18.

[0038] The operation of the buck converter typically involves charging and discharging the inductor 102. The peak current mode control scheme specifically monitors the peak current flowing through the inductor 102. The peak inductor current 18 can be compared with a reference voltage, and an error signal can be generated based on the comparison. The error signal can be fed into the EA 110, and a compensation network can be used to stabilize the control loop and ensure good transient response and stability. The EA output can be used to modulate the pulse width in the pulse width modulation (PWM) signal that drives the power switch (e.g., MOSFET) in the buck converter 100. The modulated PWM signal can control the on-duration and off-duration of the power switch. During the on-duration, energy can be stored in the inductor 102, and during the off-duration, the energy can be transferred to the output capacitor 104 and the load 106. By adjusting the duty cycle of the PWM signal based on the peak inductor current 18, the PCM buck converter 100 can regulate the output voltage.

[0039] Figure 2 An example embodiment of the clamp circuit 120 is shown in more detail in FIG. Figure 2 In the Figure 1 EA 110, clamp circuit 120 and PFM comparator 130. Clamp circuit 120 may include a clamp amplifier 121, transistors 122-125 and another resistor 126. Figure 2 , the input and output signals of Loop VREF 2, feedback voltage (FB) 4, reference voltage for PFM (VREF_PFM) 6, VREF_PFM_DET 8, PFM_DET 9, VCOMP 10, PFM_ACT 12, and signal 14 to converter oscillator 180 for PFM frequency foldback are shown.

[0040] refer to Figure 1 The solution of the present disclosure introduces PFM conversion hysteresis into the converter loop of a buck converter, such as a PCM buck converter 100, by enabling and disabling slope compensation 16 when the EA 110 of the buck converter 100 enters and exits PFM. When entering PFM, slope compensation 16 can be cut off or reduced (preferably quickly), resulting in a (typically slightly) increase in the inductor current peak through the inductor 102. This helps push the EA 110 deeper into PFM. Conversely, when exiting PFM, slope compensation 16 can be added (preferably abruptly), reducing the inductor current peak and forcing the EA 110 to leave PFM more quickly.

[0041] EA 110 can clamp to a minimum voltage (e.g., at 150 mA; note that when the VCOMP voltage is clamped, it must be followed that the peak inductor current will also be clamped) and detect the strength of the clamp (typically in microamps). As the clamp strength of EA 110 increases, the current increases by the PFM gain and is used to slow down the main converter oscillator 180. At this point, clamp circuit 120 can analyze the output of EA 110 and trigger slope compensation element 140 via PFM comparator 130 (via PFM_ACT signal 12). PFM_ACT signal 12 can be used to enable and disable slope compensation 16, which also modulates the inductor peak current 18 through inductor 102.

[0042] The PFM_ACT signal 12 can be implemented as a two-level signal with a high level of 5V and a low level of 0V, for example. It should be understood that any other voltage levels can be used for the high and low signals. When PFM_ACT12 is high, the slope compensation 16 can be disabled or significantly reduced, allowing higher peaks. When PFM_ACT 12 is low, the slope compensation 16 can be (re)enabled or increased. Due to the sudden change in the inductor current peak, this introduces hysteresis at the transition between PCM and PFM, pushing the EA control output away from the boundary faster. It should be understood that the compensation element 140 can be implemented to react inversely to the PFM_ACT signal, i.e., PFM_ACT=high enables slope compensation 16, and PFM_ACT=low disables slope compensation 16.

[0043] refer to Figure 2 When attempting to regulate the EA output voltage VCOMP 10, the VREF_PFM_DET signal 8 can be used at the PFM comparator 130 to detect the clamp current of the clamp amplifier 121. When the EA 110 attempts to drive VCOMP 10 lower, the clamp amplifier 121 regulates VCOMP 10 to VREF_PFM 6 (i.e., the minimum allowed VCOMP 10 voltage).

[0044] exist Figure 2 In the example shown in FIG1 , the current used for clamping can be increased through PMOS mirrors 122-125 and another resistor 126 and detected by PFM comparator 130. The gain obtained by transistors 122-125 can be adjustable to set any desired sensitivity. Therefore, the copy of the clamping current that can be provided to PFM comparator 130 as PFM_DET 9 can be the primary mechanism after the PFM frequency foldback loop controlled by signal 14.

[0045] Once PFM_ACT 12 is asserted (e.g., PFM_ACT is high), slope compensation 16 can be disabled or (significantly) reduced in modulator 150. This can provide the immediate hysteresis needed for the loop to prevent it from getting stuck in this region. Once the peak value increases (dramatically), EA 110 will try to drive VCOMP 10 down harder, which clamp amplifier 121 will prevent, but will send more current to the frequency foldback mechanism in converter oscillator 180 (via signal 14).

[0046] When the PFM condition is exited, the clamp amplifier 121 stops sourcing current to regulate VCOMP 10. This in turn prevents current from entering another resistor 126 connected to the PFM comparator 130, which de-asserts the PFM comparator 130. When this happens, slope compensation 16 can be turned on again. Once the peak value decreases (dramatically), the EA 110 will try to drive VCOMP 10 upwards harder, moving away from the boundary.

[0047] Compared to known PCM buck converters, the disclosed solution can be constructed more simply and is safer with respect to switching in and out of various control schemes. Furthermore, because the proposed solution does not allow for inductor energy pulses and regions where the frequency constantly fluctuates, the disclosed PCM buck converter can significantly reduce jitter and output voltage ripple. This makes the solution more deterministic regarding transient response on the system.

[0048] The PCM buck converter of the present disclosure, such as the PCM buck converter 100, can be used in a switching regulator 300, such as Figure 3 The solution of the present disclosure can be applied to various forms of switching regulators that regulate the inductor current 18 in some form.

[0049] PFM Entry( Figure 4 ) and PFM export ( Figure 5 ) shows the effect of slope compensation 16 on inductor current 18.

[0050] exist Figure 4 In FIG. 1 , at time t0, the PFM_ACT signal 12 is low and slope compensation is enabled. When entering PFM at time t1, the PFM_ACT signal 12 goes high and slope compensation 16 is cut off or rapidly reduced, causing the peak value in the inductor current 18 to increase after t1. This helps push the EA 110 deeper into PFM.

[0051] On the contrary, Figure 5In FIG, at time t3, the PFM_ACT signal 12 is high and slope compensation is disabled. When exiting PFM at time t4, the PFM_ACT signal goes low and slope compensation 16 is (abruptly) added, reducing the peak in the inductor current 18 after t4 and forcing the EA 110 to exit PFM more quickly.

[0052] Other variations of the disclosed embodiments may be understood and effected by those skilled in the art in practicing the claimed disclosure, by studying the drawings, the present disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.

Claims

1. A peak current mode (PCM) buck converter, comprising: Slope compensation components, wherein the PCM buck converter is arranged to detect entry into or exit from a pulse frequency modulation (PFM) mode of operation, wherein the slope compensation element is arranged to disable or reduce slope compensation when the PCM buck converter detects the entry into the PFM, and The slope compensation element is arranged to enable the slope compensation when the PCM buck converter detects the exit from the PFM.

2. The PCM buck converter according to claim 1 , further comprising an inductor. wherein the PCM buck converter is arranged to increase the peak value of the inductor current through the inductor by disabling or reducing the slope compensation when the entry into the PFM is detected, and Wherein the PCM buck converter is arranged to reduce a peak value in the inductor current through the inductor by enabling the slope compensation when the exit from the PFM is detected.

3. The PCM buck converter according to claim 2, further comprising: an error amplifier (EA) arranged to generate an EA output voltage (VCOMP), and A modulator is arranged to apply the slope compensation to the VCOMP when the slope compensation is enabled, and to stop applying the slope compensation to the VCOMP when the slope compensation is disabled.

4. The PCM buck converter according to claim 3, further comprising: a clamp circuit arranged to receive the VCOMP from the EA, a pulse frequency modulation (PFM) comparator arranged to receive a PFM detection voltage (PFM_DET), wherein the PFM_DET is based on the VCOMP, wherein the PFM comparator is arranged to generate a PFM activation signal (PFM_ACT) by comparing the PFM_DET with a reference voltage (VREF_PFM_DET) for PFM detection, and The slope compensation element is arranged to be triggered by the PFM_ACT to enable or disable the slope compensation.

5. The PCM buck converter of claim 4 , wherein the clamping circuit comprises a clamping amplifier arranged to receive the VCOMP from the EA and arranged to regulate the VCOMP to a reference voltage for PFM (VREF_PFM), and wherein the clamping circuit comprises one or more transistors arranged to increase the VREF_PFM to obtain the PFM_DET.

6. The PCM buck converter of claim 4, further comprising a converter oscillator, and wherein the clamp circuit is further arranged to generate a signal to the converter oscillator for PFM frequency foldback.

7. The PCM buck converter of claim 5, further comprising a converter oscillator, and wherein the clamp circuit is further arranged to generate a signal to the converter oscillator for PFM frequency foldback. 8 . A switching regulator comprising one or more PCM buck converters according to claim 1 .

9. A switching regulator comprising one or more PCM buck converters according to claim 2. 10 . A switching regulator comprising one or more PCM buck converters according to claim 3 .

11. A slope compensation element for a peak current mode (PCM) buck converter. wherein the slope compensation element is arranged to disable or reduce slope compensation when the PCM buck converter detects entry into a pulse frequency modulation (PFM) operating mode, and wherein the slope compensation element is arranged to enable slope compensation when the PCM buck converter detects exiting the PFM operating mode.

12. The slope compensation element according to claim 11, wherein the slope compensation element is arranged to be triggered by a PFM activation signal (PFM_ACT) from a PFM comparator to enable or disable the slope compensation.

13. A clamping circuit for a peak current mode (PCM) buck converter. wherein the clamp circuit is arranged to receive an EA output voltage (VCOMP) from an error amplifier (EA), wherein the clamp circuit comprises a pulse frequency modulation (PFM) comparator arranged to receive a PFM detection voltage (PFM_DET), and wherein the PFM_DET is based on the VCOMP, wherein the PFM comparator is arranged to generate a PFM activation signal (PFM_ACT) by comparing the PFM_DET with a reference voltage (VREF_PFM_DET) for PFM detection, and The PFM comparator is arranged to output PFM_ACT to a slope compensation element for triggering the slope compensation element to enable or disable slope compensation when the PCM buck converter enters or exits a pulse frequency modulation (PFM) operation mode.

14. The clamp circuit of claim 13 , wherein the clamp circuit comprises a clamp amplifier arranged to receive the VCOMP from the EA and arranged to regulate the VCOMP to a reference voltage for PFM (VREF_PFM), and wherein the clamp circuit comprises one or more transistors arranged to increase the VREF_PFM to obtain the PFM_DET.

15. The clamp circuit of claim 13, wherein the clamp circuit is further arranged to generate a signal to a converter oscillator for PFM frequency foldback.

16. The clamp circuit of claim 14, wherein the clamp circuit is further arranged to generate a signal to a converter oscillator for PFM frequency foldback.

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