A highly integrated v-band broadband multi-channel multi-mode detector front-end chip

Abstract

The application discloses a highly integrated V-waveband broadband multi-channel multi-mode detector front-end chip and belongs to the field of millimeter wave integrated circuits, comprising a phase-locked loop module (PLL), a radio frequency local oscillator chain module (LO), a double-transmit-channel module (TX), a double-receive-channel module (RX), a pulse timing control module and an SPI configuration interface module. The application solves the problems of the existing V-waveband detector chip, such as difficulty in generating a broadband signal, serious phase mismatch of multi-channels, complex and inefficient multi-mode system, and difficulty in balancing the speed and power consumption of a transmitting link.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of millimeter wave integrated circuits, and particularly relates to a highly integrated V-band wideband multi-channel multi-mode detector front-end chip. BACKGROUND

[0002] With the wide application of millimeter wave detection technology in the fields of security inspection and radio astronomy, the performance requirements of V-band (60-90GHz) detector front-end chips are increasingly improved. In the prior art, the detector usually has the following defects and bottlenecks: it is extremely difficult to realize direct oscillation VCO in the V-band with a wide tuning range (such as 6GHz+). The traditional scheme usually adopts frequency multiplication (sacrificing phase noise and efficiency) or switching of multiple narrow-band VCOs (increasing complexity and area). There is a strong contradiction between wide tuning range and low phase noise, low power consumption. Integrating multiple millimeter wave transceiver channels (such as 2T2R) on a single chip faces great challenges: insufficient channel isolation leads to crosstalk, signal path matching is difficult, power consumption and heat are concentrated, and chip area increases. Most importantly, ensuring the phase consistency (homogeneous phase) of all channels is crucial for advanced applications such as MIMO and beamforming, but it is extremely complex and easily affected by process deviation and temperature to realize precise phase synchronization of multiple channels in the millimeter wave frequency band. Modern radar systems (such as automobiles and industries) often need to support FMCW (continuous wave frequency modulation) and pulse Doppler modes. The traditional scheme usually needs complex off-chip waveform generation circuits (such as DAC+FPGA to generate a triangular wave) and precise off-chip timing control circuits to manage the opening / closing, delay and pulse width of the pulse mode, which leads to complex system board design, large size, high cost and introduces additional delay, jitter and signal integrity risks, limiting the switching speed and timing accuracy. It is already very difficult to design a high-efficiency, high-power power amplifier (PA) in the millimeter wave frequency band. Integrating it with the driver stage (TXDA) and the transmit switch (TXSW) that needs to handle high power and achieve fast opening / closing (steep rising / falling edge) on a single chip is even more challenging: TXDA needs to provide sufficient driving capability and itself is efficient, TXSW needs to maintain low insertion loss (efficiency), high isolation (off state) and extremely fast switching speed (critical for pulse mode) when handling high power output from PA. SUMMARY

[0003] In view of the above deficiencies in the prior art, the highly integrated V-band wideband multi-channel multi-mode detector front-end chip provided by the application solves the problems of difficulty in generating wideband signals, serious phase mismatch of multiple channels, complex and inefficient multi-mode systems, and difficulty in balancing speed and power consumption of the transmit link in the existing V-band detector chips.

[0004] In order to achieve the above-mentioned purposes, the technical scheme adopted by the present application is as follows: a highly integrated V-band wideband multi-channel multi-mode detector front-end chip comprises:

[0005] A phase-locked loop module PLL comprises a phase-locked comparator, a loop filter and a voltage-controlled oscillator VCO;

[0006] A radio frequency local oscillator chain module LO comprises a voltage-controlled oscillator VCO, a local oscillator buffer LOBUF, a receiving pulse switch RXSW, a transmitting pulse switch TXSW and a transmitting driver amplifier TXDA;

[0007] A dual-transmitting channel module TX comprises a power amplifier PA;

[0008] A dual-receiving channel module RX comprises a low-noise amplifier LNA, a low-noise trans-impedance amplifier LNTA, a mixer MIX, a mixer local oscillator buffer MIXBUF, a trans-impedance amplifier TIA, a trans-impedance amplifier output buffer TIABUF, a high-pass filter HPF, an intermediate frequency variable gain amplifier VGA, a low-pass filter LPF and a baseband output buffer BBBUF;

[0009] A pulse timing control module outputs transmitting timing pulses and receiving timing pulses and is provided with independent channel selection pins;

[0010] An SPI configuration interface module is connected with the phase-locked loop module, the radio frequency local oscillator chain module, the dual-transmitting channel module, the dual-receiving channel module and the pulse timing control module respectively and uniformly configures parameters of the modules.

[0011] Further, the voltage-controlled oscillator VCO output in the phase-locked loop module PLL is buffered by the local oscillator buffer LOBUF, one way of which enters the mixer MIX in the dual-receiving channel module RX, and the other way of which returns to the frequency discriminator phase detector PFD through an internal feedback frequency divider to lock the frequency in a closed loop.

[0012] Further, the local oscillator buffer LOBUF in the radio frequency local oscillator chain module LO is connected with one end of the receiving pulse switch RXSW, one end of the transmitting pulse switch TXSW and one end of the voltage-controlled oscillator VCO respectively, the other end of the transmitting pulse switch TXSW is connected with the input end of the transmitting driver amplifier TXDA, and the other end of the voltage-controlled oscillator VCO is connected with the pins VT33, VCOSEL33, BANDSEL33 and PREO respectively.

[0013] Further, the dual-transmitting channel module TX is of two-way structure and comprises the power amplifier PA, the input end of the power amplifier PA is connected with the output end of the transmitting driver amplifier TXDA, and the output end of the power amplifier PA is connected with the pin TXOL or TXOU.

[0014] Further, the double-receiving-channel module RX is a two-way structure same receiving channel, comprising:

[0015] The input end of the low-noise amplifier LNA is connected with the pin RXIL or RXIU, the output end is connected with the input end of the low-noise transconductance amplifier LNTA, the output end of the low-noise transconductance amplifier LNTA is connected with the input end of the mixer MIX, the output end of the mixer MIX is connected with the input end of the mixer local oscillator buffer MIXBUF and the input end of the transimpedance amplifier TIA respectively, the output end of the mixer local oscillator buffer MIXBUF is connected with the receiving pulse switch RXSW, the output end of the transimpedance amplifier TIA is connected with the input end of the high-pass filter HPF and the input end of the transimpedance amplifier output buffer TIABUF respectively, the output end of the high-pass filter HPF is connected with the input end of the intermediate frequency variable gain amplifier VGA and one end of the receiving pulse switch RXSW respectively, the output end of the intermediate frequency variable gain amplifier VGA is connected with the input end of the low-pass filter LPF, the output end of the low-pass filter LPF is connected with the input end of the baseband output buffer BBBUF, the output end of the baseband output buffer BBBUF is connected with the pin IFON_BB_RXU, IFOP_BB_RXU, IFON_BB_RXL or IFOP_BB_RXL, the other end of the receiving pulse switch RXSW is connected with the pin VGA_INN_RXU, VGA_INP_RXU, VGA_INN_RXL or VGA_INP_RXL, the output end of the transimpedance amplifier output buffer TIABUF is connected with the pin IFO_TIA_RXU or IFO_TIA_RXL.

[0016] Further, the pulse timing control module comprises the pin TXPULSE33, the pin RXPULSE33, the pin TXPULSEL33 and the pin RXPULSEL33.

[0017] The pin TXPULSE33 is connected with the external transmitting driver, for generating the transmitting timing pulse.

[0018] The pin RXPULSE33 is connected with the external receiving driver, for generating the receiving timing pulse.

[0019] The pin TXPULSEL33 is coupled with the ground potential through the bypass capacitor, for realizing the independent gating of the upper and lower transmitting channels.

[0020] The pin RXPULSEL33 is coupled with the ground potential through the bypass capacitor, for realizing the independent gating of the upper and lower receiving channels.

[0021] Further, the SPI configuration interface module comprises a pin SPI_ENB, a pin SPI_CLK, a pin SPI_DI and a pin SPI_DO.

[0022] The pin SPI_ENB enables the SPI bus when pulled low by the host MCU.

[0023] The pin SPI_CLK receives a clock signal provided by the host MCU, for synchronizing data shifting and sampling.

[0024] The pin SPI_DI transmits configuration words, register addresses and control commands to the internal registers of the chip.

[0025] The pin SPI_DO serially returns the internal register state data of the chip to the host MCU when reading the register, and outputs along the CLK edge.

[0026] Further, the chip further comprises an antenna output matching network, the antenna output matching network comprises a ground capacitor C1, a capacitor C2, a ground capacitor C3, a ground capacitor C4, a ground resistor R2, a resistor R3, a resistor R4 and a ground resistor R5, one end of the capacitor C2 is connected with the ground capacitor C1, one end of the resistor R3 and a chip pin CP33 respectively, the other end of the capacitor C2 is connected with the ground resistor R2, the other end of the resistor R3 is connected with the ground capacitor C3 and one end of the resistor R4 respectively, the other end of the resistor R4 is connected with the ground capacitor C4, a chip pin VT33 and one end of the resistor R5 respectively, the other end of the resistor R5 is connected with the interface J3.

[0027] Further, the chip further comprises an interface J8, an interface J9, an interface J10 and an interface J11.

[0028] The port 1, the port 2, the port 3 and the port 4 of the interface J8 are all connected with one end of an inductor L1, the other end of the inductor L1 is connected with a ground capacitor C6 and a pin VDD12_RXRF_RXMIX of the chip respectively, the port 5, the port 6, the port 7 and the port 8 of the interface J8 are all grounded.

[0029] The port 1 of the interface J9 is connected with the pin LD33 of the chip, the port 2 is connected with one end of the inductor L3, the other end of the inductor L3 is connected with the ground capacitor C12, the pin VDD12_XO and VDD12_SPI of the chip respectively, the port 3 of the interface J9 is connected with one end of the inductor L2, the other end of the inductor L2 is connected with the ground capacitor C10, the pin VDD33_PFDCP and VDD33_PST of the chip respectively, the port 4 of the interface J9 is connected with the pin SPI_DO of the chip, the port 5 of the interface J9 is connected with the pin SPI_DI of the chip, the port 6 of the interface J9 is connected with the pin SPI_CLK of the chip, the port 7 of the interface J9 is connected with the pin SPI_ENB of the chip, the port 8 of the interface J9 is connected with the pin RXPULSEU33 of the chip, the port 9 of the interface J9 is connected with the pin TXPULSEU33 of the chip, the port 10 of the interface J9 is connected with the pin RXPULSEL33 of the chip, the port 11 of the interface J9 is connected with the pin TXPULSEL33 of the chip, the port 12 of the interface J9 is connected with the pin TRIG_PULSE33 of the chip, the port 13 and the port 14 of the interface J9 are grounded respectively.

[0030] The port 1, the port 2, the port 3 and the port 4 of the interface J10 are connected with one end of the inductor L4 respectively, the other end of the inductor L4 is connected with the ground capacitor C15 and the pin VDD12_PA of the chip respectively, the port 5, the port 6, the port 7 and the port 8 of the interface J10 are grounded respectively.

[0031] The port 1 and the port 2 of the interface J11 are connected with one end of the inductor L7 respectively, the other end of the inductor L7 is connected with the ground capacitor C20 and the pin VDD33_VT of the chip respectively, the port 3 and the port 4 of the interface J11 are connected with one end of the inductor L6 respectively, the other end of the inductor L6 is connected with the ground capacitor C18 and the pin VDD12_DIV of the chip respectively, the port 5 of the interface J11 is connected with the pin VCOSEL33 of the chip, the port 6 of the interface J11 is connected with the pin BANDSEL33 of the chip, the port 7, the port 8 and the port 9 of the interface J11 are grounded respectively, the port 10, the port 11 and the port 12 of the interface J11 are connected with one end of the inductor L5 respectively, the other end of the inductor L5 is connected with the ground capacitor C16 and the pin VDD12_PA1 of the chip respectively.

[0032] The application has the beneficial effects that the highly integrated V-band wideband multi-channel multi-mode probe front-end chip provided by the application solves the problems of difficulty in generating wideband signals, serious multi-channel phase mismatch, complex and inefficient multi-mode system, and difficulty in balancing the speed and power consumption of the transmission link of the existing V-band probe chip through the design of four-section coverage of 6GHz+ bandwidth, single-chip integration of 2T2R and guarantee of phase consistency, integration of triangular wave generator and programmable pulse timing control, and high-efficiency high-speed integration of TXDA and TXSW. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 It is a basic block diagram of the highly integrated V-band wideband multi-channel multi-mode probe front-end chip.

[0034] Figure 2 It is a schematic diagram of the highly integrated V-band wideband multi-channel multi-mode probe front-end chip.

[0035] Figure 3 It is a schematic diagram of each interface connection. DETAILED DESCRIPTION

[0036] The application will be further described below in combination with the drawings and specific embodiments.

[0037] As shown in Figure 1 and Figure 2 , a highly integrated V-band wideband multi-channel multi-mode probe front-end chip comprises:

[0038] A phase-locked loop module PLL comprising a phase-locked comparator, a loop filter and a voltage-controlled oscillator VCO;

[0039] A radio frequency local oscillator chain module LO comprising a voltage-controlled oscillator VCO, a local oscillator buffer LOBUF, a receiving pulse switch RXSW, a transmitting pulse switch TXSW and a transmitting driver amplifier TXDA;

[0040] A double transmitting channel module TX comprising a power amplifier PA;

[0041] A double receiving channel module RX comprising a low-noise amplifier LNA, a low-noise transimpedance amplifier LNTA, a mixer MIX, a mixer local oscillator buffer MIXBUF, a transimpedance amplifier TIA, a transimpedance amplifier output buffer TIABUF, a high-pass filter HPF, an intermediate frequency variable gain amplifier VGA, a low-pass filter LPF and a baseband output buffer BBBUF;

[0042] A pulse timing control module outputting transmitting timing pulses and receiving timing pulses and being provided with independent channel selection pins;

[0043] SPI configuration interface module: respectively with phase-locked loop module, radio frequency local oscillator chain module, double transmission channel module, double receiving channel module and pulse timing control module are connected with each other, the unified parameter configuration is carried out to each module.

[0044] The output of the voltage controlled oscillator VCO in the phase-locked loop module PLL is buffered by the local oscillator buffer LOBUF, one way into the mixer MIX in the double receiving channel module RX, and the other way back to the phase frequency detector PFD through the chip internal feedback frequency divider, to lock the frequency in a closed loop. The pin VDD33_PFDCP / PST of the chip is the power supply of the PLL submodule, and TRIG_PULSE33 (filtered through R5 / C3 and connected to the E12 pin) is the lock start trigger signal.

[0045] The phase-locked loop module PLL integrates phase-locked comparator, loop filter and VCO internally, wherein REF_CLK is an external crystal oscillator input port, and the VCO ground is tightly coupled with the ground network; all PLL-related digital control signals are set through the SPI configuration interface, so that the radio frequency local oscillator frequency is programmable. The module works with the double transmission, double receiving channel and pulse timing controller to form a complete transceiver management subsystem.

[0046] The phase-locked loop module PLL and the radio frequency local oscillator chain module LO:

[0047] Chirp Gen (triangular wave generator): started by SPI in FMCW mode, generates a linear slope control signal to PLL. The phase-locked loop module PLL includes a phase-locked comparator, a loop filter and a programmable frequency divider network, which works with the VCO feedback loop to realize frequency locking and frequency sweeping of the V-band local oscillator. The voltage controlled oscillator VCO directly oscillates in the V-band (60-90 GHz), and the output signal is first input into LOBUF and then distributed to the LO input terminals of the transmit and receive mixers.

[0048] The local oscillator buffer LOBUF in the radio frequency local oscillator chain module LO is connected with one end of the receiving pulse switch RXSW, one end of the transmitting pulse switch TXSW and one end of the voltage controlled oscillator VCO, respectively. The other end of the transmitting pulse switch TXSW is connected with the input terminal of the transmitting driver amplifier TXDA, and the other end of the voltage controlled oscillator VCO is connected with the pins VT33, VCOSEL33, BANDSEL33 and PREO, respectively.

[0049] The double transmission channel module TX is two transmission channels with the same structure, including a power amplifier PA, the input terminal of which is connected with the output terminal of the transmitting driver amplifier TXDA, and the output terminal of which is connected with the pin TXOL or TXOU.

[0050] As Figure 2As shown, the dual transmit channel module includes two radio frequency output pins TXOU (Q7) and TXOL (Q5) corresponding to transmit channel 1 and transmit channel 2 respectively; the transmit output signal is sent to the external antenna interface (NC) through the off-chip impedance matching network from the TXOU and TXOL pins. The transmit stage power amplifier power supply is also supplied by the 1.2 V power supply network, all the transmit channel internal integrated pre-stage power devices, the VSS_PA pin at the output end is grounded, to ensure the stability of the radio frequency power output.

[0051] The dual receive channel module RX is two receive channels with the same structure, including:

[0052] The input end of the low noise amplifier LNA is connected with the pin RXIL or RXIU, the output end of the low noise amplifier LNA is connected with the input end of the low noise transconductance amplifier LNTA, the output end of the low noise transconductance amplifier LNTA is connected with the input end of the mixer MIX, the output end of the mixer MIX is connected with the input end of the mixer local oscillator buffer MIXBUF and the input end of the transimpedance amplifier TIA respectively, the output end of the mixer local oscillator buffer MIXBUF is connected with the receive pulse switch RXSW, the output end of the transimpedance amplifier TIA is connected with the input end of the high pass filter HPF and the input end of the transimpedance amplifier output buffer TIABUF respectively, the output end of the high pass filter HPF is connected with the input end of the intermediate frequency variable gain amplifier VGA and one end of the receive pulse switch RXSW respectively, the output end of the intermediate frequency variable gain amplifier VGA is connected with the input end of the low pass filter LPF, the output end of the low pass filter LPF is connected with the input end of the baseband output buffer BBBUF, the output end of the baseband output buffer BBBUF is connected with the pin IFON_BB_RXU, IFOP_BB_RXU, IFON_BB_RXL or IFOP_BB_RXL, the other end of the receive pulse switch RXSW is connected with the pin VGA_INN_RXU, VGA_INP_RXU, VGA_INN_RXL or VGA_INP_RXL, the output end of the transimpedance amplifier output buffer TIABUF is connected with the pin IFO_TIA_RXU or IFO_TIA_RXL.

[0053] Wherein, the LNA and the LNTA perform primary amplification and impedance conversion on the weak echo signal fed into the antenna. MIXBUF+ MIX mixes the LNA / LNTA output with the LO signal to obtain the intermediate frequency IF. HPF + VGA + LPF + BB_BUF (high pass filter → variable gain amplifier → low pass filter → baseband buffer) is used to filter out high frequency spurs, amplify the intermediate frequency signal with adjustable gain, and then output the low frequency baseband signal. The final baseband signal is led out from the pins.

[0054] As Figure 2As shown, the model of the chip is yx8922_wlcsp_v1, wherein the dual-receiving channel module further comprises RXIU (B6) and RXIL (B4) two radio frequency input pins, and a common low-noise front end (TIA_IF_OUT_RXU / C1, TIA_IF_OUT_RXL / E1). The RXIU and RXIL pins respectively feed external antenna signals into the chip; the signals amplified by the TIA are output from the TIA_IF_OUT_RXU and TIA_IF_OUT_RXL pins to the post-stage in the chip, and the post-stage uses VGA_INN_RXU (J1) / VGA_INP_RXU (J2) and VGA_INN_RXL (L2) / VGA_INP_RXL (L1) to perform variable gain amplification on the uplink and downlink channels, and the baseband output is led out from the IF_OUTP_RXL (N1) and IF_OUTN_RXL (O1) pins. The pins C1, E1, G1, H1, J1, J2, L2, L1, N1, and O1 are respectively connected in parallel with decoupling capacitors C21, C22, C23, C24, C25, C26, C27, C28, C29, and C30, and the other ends of the capacitors are respectively connected with external interfaces J14, J15, J16, J17, J18, J19, J20, J21, J13, and J12.

[0055] The pin REF_CLK (E12) is connected in parallel with a decoupling capacitor C6 (200 pF) to ground as a PLL reference clock decoupling, and the pin PREO (O10) is connected in parallel with a decoupling capacitor C5 (50 pF) to ground for VCO output bypass. All VSS_LO pins are grounded.

[0056] The pins VSS_RX, VSSPST, VSS_XO_DIV, VSS33_PFDCP, VSS_PKG, and vss10_SPI are all grounded.

[0057] The SPI configuration interface module communicates with an external host through four pins for configuring internal registers, including PLL division ratio, transmission / reception gate timing, FMCW triangular wave parameters, etc. The module provides programmable control of key parameters such as PLL loop parameters, LO output power, probe channel gain, and baseband filter bandwidth, realizing flexible configuration and real-time monitoring of the V-band probe.

[0058] The pulse timing control module comprises a pin TXPULSE33, a pin RXPULSE33, a pin TXPULSEL33, and a pin RXPULSEL33.

[0059] The pin TXPULSE33 is connected with an external transmission driver for generating a transmission timing pulse.

[0060] The pin RXPULSE 33 is connected with an external receiving driver for generating a receiving timing pulse.

[0061] The pin TXPULSEL 33 is coupled with a ground potential through a bypass capacitor to realize independent gating of the upper and lower transmitting channels.

[0062] The pin RXPULSEL 33 is coupled with a ground potential through a bypass capacitor to realize independent gating of the upper and lower receiving channels.

[0063] The pulse timing control module generates various timing pulses (TXSW, RXSW gating signals) after receiving the SPI configuration, and cooperates with an external trigger (for example, an FPGA) through the bottom TRIG_PULSE 33, RXPULSEL 33 and other pins to complete the pulse Doppler or FMCW start / stop control.

[0064] The SPI configuration interface module includes a pin SPI_ENB, a pin SPI_CLK, a pin SPI_DI and a pin SPI_DO.

[0065] The pin SPI_ENB is enabled when pulled low by the host MCU; when high, the chip select is released, and all SPI pins enter high resistance to avoid conflicts with other SPI devices.

[0066] The pin SPI_CLK receives a clock signal provided by the host MCU for synchronizing data shifting and sampling; all DI / DO are latched at the rising or falling edge of CLK, and the specific timing is determined by the timing table.

[0067] The pin SPI_DI transmits configuration words, register addresses and control commands to the internal registers of the chip.

[0068] The pin SPI_DO serially returns the internal register state data of the chip to the host MCU when reading the register, and outputs along the CLK edge.

[0069] The chip further includes an antenna output matching network, which includes a ground capacitor C1, a capacitor C2, a ground capacitor C3, a ground capacitor C4, a ground resistor R2, a resistor R3, a resistor R4 and a ground resistor R5, one end of the capacitor C2 is connected with the ground capacitor C1, one end of the resistor R3 and the chip pin CP33, respectively, and the other end is connected with the ground resistor R2, the other end of the resistor R3 is connected with one end of the ground capacitor C3 and the resistor R4, respectively, the other end of the resistor R4 is connected with one end of the ground capacitor C4, the chip pin VT33 and the resistor R5, respectively, and the other end of the resistor R5 is connected with the interface J3.

[0070] As Figure 3As shown, the chip further comprises an interface J8, an interface J9, an interface J10 and an interface J11, and each interface is connected with an external device;

[0071] The port 1, the port 2, the port 3 and the port 4 of the interface J8 are connected with one end of an inductor L1, the other end of the inductor L1 is connected with a grounding capacitor C6 and a pin VDD12_RXRF_RXMIX of the chip respectively, and the port 5, the port 6, the port 7 and the port 8 of the interface J8 are grounded;

[0072] The port 1 of the interface J9 is connected with a pin LD33 of the chip, the port 2 is connected with one end of an inductor L3, the other end of the inductor L3 is connected with a grounding capacitor C12, a pin VDD12_XO and a pin VDD12_SPI of the chip respectively, the port 3 of the interface J9 is connected with one end of an inductor L2, the other end of the inductor L2 is connected with a grounding capacitor C10, a pin VDD33_PFDCP and a pin VDD33_PST of the chip respectively, the port 4 of the interface J9 is connected with a pin SPI_DO of the chip, the port 5 of the interface J9 is connected with a pin SPI_DI of the chip, the port 6 of the interface J9 is connected with a pin SPI_CLK of the chip, the port 7 of the interface J9 is connected with a pin SPI_ENB of the chip, the port 8 of the interface J9 is connected with a pin RXPULSEU33 of the chip, the port 9 of the interface J9 is connected with a pin TXPULSEU33 of the chip, the port 10 of the interface J9 is connected with a pin RXPULSEL33 of the chip, the port 11 of the interface J9 is connected with a pin TXPULSEL33 of the chip, the port 12 of the interface J9 is connected with a pin TRIG_PULSE33 of the chip, and the port 13 and the port 14 of the interface J9 are grounded;

[0073] The port 1, the port 2, the port 3 and the port 4 of the interface J10 are connected with one end of an inductor L4, the other end of the inductor L4 is connected with a grounding capacitor C15 and a pin VDD12_PA of the chip respectively, and the port 5, the port 6, the port 7 and the port 8 of the interface J10 are grounded;

[0074] The port 1 and the port 2 of the interface J11 are connected with one end of the inductor L7, the other end of the inductor L7 is connected with the ground capacitor C20 and the pin VDD33_VT of the chip respectively, the port 3 and the port 4 of the interface J11 are connected with one end of the inductor L6, the other end of the inductor L6 is connected with the ground capacitor C18 and the pin VDD12_DIV of the chip respectively, the port 5 of the interface J11 is connected with the pin VCOSEL33 of the chip, the port 6 of the interface J11 is connected with the pin BANDSEL33 of the chip, the port 7, the port 8 and the port 9 of the interface J11 are grounded, the port 10, the port 11 and the port 12 of the interface J11 are connected with one end of the inductor L5, the other end of the inductor L5 is connected with the ground capacitor C16 and the pin VDD12_PA1 of the chip respectively.

[0075] The power supply used in the chip includes:

[0076] VDD12_PA: 1.2 V bias power supply, which is led out to all power amplifier PA bias points.

[0077] VDD12_RX: 1.2 V bias power supply, which is led out to all receiving channel low noise amplifiers LNAs, transconductance amplifiers LNTAs and detector bias.

[0078] VDD12_SPI: 1.2 V power supply, which is supplied to SPI configuration logic and pulse timing control PULSE CTRL.

[0079] VDD3V3: 3.3 V main power supply, which is led out to PLL, VCO, LO buffer and other digital / analogue modules.

[0080] The signal flow and working mode of the chip are as follows:

[0081] FMCW mode: the SPI issues triangular wave parameters, Chirp Gen. generates a slope, PLL / VCO continuously linearly sweeps; TXSW is always on, TXDA → PA transmits a signal with continuously changing frequency; after the echo signal is mixed, a difference frequency IF varying with distance is generated, and the latter stage is amplified, filtered and output to the external ADC.

[0082] Pulse Doppler mode: SPI configures a fixed LO frequency; external or internal trigger generates pulse timing (TXSW on → transmission → off → RXSW on → reception); multiple receiving channels can work simultaneously or in time-sharing mode, and the output intermediate frequency stage is provided for ranging and speed algorithm processing.

[0083] The modules are connected with each other through pins to form a complete V-band detection link. The SPI configuration interface module is responsible for unified parameter configuration of the PLL, LO and detection channel functional units; the pulse timing controller realizes time-sharing gating of the detection channel; the double detection channel completes mixing and envelope detection of the V-band signal; and the LO chain and the PLL module provide high-stability local oscillator signals for the mixer, and together meet the detection requirements of high sensitivity and low noise of the V-band.

[0084] Those skilled in the art will appreciate that the embodiments described herein are presented for the purpose of aiding the reader in understanding the principles of the present application, and should be understood as not limiting the scope of protection of the present application to such specific recitations and embodiments. Those skilled in the art can make various other specific modifications and combinations according to the technical inspiration disclosed by the present application without departing from the spirit of the present application, and these modifications and combinations are still within the scope of protection of the present application.

Claims

1. A highly integrated V-band broadband multi-channel multi-mode detector front-end chip, characterized in that: include: Phase-locked loop module PLL: includes phase-locked comparator, loop filter and voltage-controlled oscillator VCO; RF local oscillator chain module LO: includes voltage-controlled oscillator VCO, local oscillator buffer LOBUF, receive pulse switch RXSW, transmit pulse switch TXSW and transmit driver amplifier TXDA; Dual transmit channel module TX: including power amplifier PA; Dual receiving channel module RX: includes low noise amplifier LNA, low noise transconductance amplifier LNTA, mixer MIX, mixer local oscillator buffer MIXBUF, transimpedance amplifier TIA, transimpedance amplifier output buffer TIABUF, high pass filter HPF, intermediate frequency variable gain amplifier VGA, low pass filter LPF and baseband output buffer BBBUF; Pulse timing control module: outputs transmit timing pulses and receive timing pulses, and is equipped with independent channel selection pins; SPI configuration interface module: interconnected with the phase-locked loop module, RF local oscillator chain module, dual-transmit channel module, dual-receive channel module and pulse timing control module respectively, and performs unified parameter configuration for each module; The local oscillator buffer LOBUF in the RF local oscillator chain module LO is respectively connected to one end of the receiving pulse switch RXSW, one end of the transmitting pulse switch TXSW and one end of the voltage-controlled oscillator VCO, the other end of the transmitting pulse switch TXSW is connected to the input end of the transmitting driver amplifier TXDA, and the other end of the voltage-controlled oscillator VCO is respectively connected to pins VT33, VCOSEL33, BANDSEL33 and PREO.

2. The highly integrated V-band broadband multi-channel multi-mode detector front-end chip according to claim 1, characterized in that: The output of the voltage controlled oscillator (VCO) in the phase-locked loop (PLL) module is buffered by the local oscillator (LOBUF), enters the mixer (MIX) in the dual-receive channel module (RX), and returns to the phase frequency detector (PFD) via the chip's internal feedback divider to lock the frequency in a closed loop.

3. The highly integrated V-band broadband multi-channel multi-mode detector front-end chip according to claim 2, characterized in that: The dual-transmitting channel module TX is two transmitting channels with the same structure, including a power amplifier PA. The input end of the power amplifier PA is connected to the output end of the transmitting driver amplifier TXDA, and the output end thereof is connected to the pin TXOL or TXOU.

4. The highly integrated V-band broadband multi-channel multi-mode detector front-end chip according to claim 3, characterized in that: The dual receiving channel module RX is a two-way receiving channel with the same structure, including: The input end of the low noise amplifier LNA is connected to the pin RXIL or RXIU, and the output end thereof is connected to the input end of the low noise transconductance amplifier LNTA. The output end of the low noise transconductance amplifier LNTA is connected to the input end of the mixer MIX. The output end of the mixer MIX is respectively connected to the input end of the mixer local oscillator buffer MIXBUF and the input end of the transimpedance amplifier TIA. The output end of the mixer local oscillator buffer MIXBUF is connected to the receiving pulse switch RXSW. The output end of the transimpedance amplifier TIA is respectively connected to the input end of the high pass filter HPF and the input end of the transimpedance amplifier output buffer TIABUF. The output end of the high pass filter HPF is respectively connected to the input end of the intermediate frequency variable gain amplifier VGA and the receiving pulse switch RXSW. One end of the intermediate frequency variable gain amplifier VGA is connected to the input end of the low-pass filter LPF, the output end of the low-pass filter LPF is connected to the input end of the baseband output buffer BBBUF, the output end of the baseband output buffer BBBUF is connected to the pin IFON_BB_RXU, IFOP_BB_RXU, IFON_BB_RXL or IFOP_BB_RXL, the other end of the receiving pulse switch RXSW is connected to the pin VGA_INN_RXU, VGA_INP_RXU, VGA_INN_RXL or VGA_INP_RXL, and the output end of the transimpedance amplifier output buffer TIABUF is connected to the pin IFO_TIA_RXU or IFO_TIA_RXL.

5. The highly integrated V-band broadband multi-channel multi-mode detector front-end chip according to claim 4, characterized in that: The pulse timing control module includes a pin TXPULSE33, a pin RXPULSE33, a pin TXPULSEL33 and a pin RXPULSEL33; The pin TXPULSE33 is connected to an external transmitting driver for generating a transmitting timing pulse; The pin RXPULSE33 is connected to an external receiving driver for generating a receiving timing pulse; The pin TXPULSEL33 is coupled to the ground potential through a bypass capacitor to achieve independent gating of the upper and lower transmit channels; The pin RXPULSEL33 is coupled to the ground potential through a bypass capacitor to achieve independent gating of the upper and lower receiving channels.

6. The highly integrated V-band broadband multi-channel multi-mode detector front-end chip according to claim 5, characterized in that: The SPI configuration interface module includes a pin SPI_ENB, a pin SPI_CLK, a pin SPI_DI and a pin SPI_DO; The SPI_ENB pin is pulled low by the host MCU to enable the SPI bus; The SPI_CLK pin receives the clock signal provided by the host MCU and is used for synchronizing the shifting and sampling of data; The pin SPI_DI transmits configuration words, register addresses and control commands to the internal registers of the chip; When the SPI_DO pin is in register reading operation, the chip returns the internal register status data to the host MCU serially through this pin and outputs it along the CLK edge.

7. The highly integrated V-band broadband multi-channel multi-mode detector front-end chip according to claim 6, characterized in that: The chip also includes an antenna output matching network, which includes a grounding capacitor C1, a capacitor C2, a grounding capacitor C3, a grounding capacitor C4, a grounding resistor R2, a resistor R3, a resistor R4 and a grounding resistor R5. One end of the capacitor C2 is respectively connected to the grounding capacitor C1, one end of the resistor R3 and the chip pin CP33, and the other end is connected to the grounding resistor R2. The other end of the resistor R3 is respectively connected to the grounding capacitor C3 and one end of the resistor R4. The other end of the resistor R4 is respectively connected to the grounding capacitor C4, the chip pin VT33 and one end of the resistor R5. The other end of the resistor R5 is connected to the interface J3.

8. The highly integrated V-band broadband multi-channel multi-mode detector front-end chip according to claim 7, characterized in that: The chip also includes interface J8, interface J9, interface J10 and interface J11; Port 1, port 2, port 3 and port 4 of the interface J8 are all connected to one end of the inductor L1, and the other end of the inductor L1 is respectively connected to the ground capacitor C6 and the pin VDD12_RXRF_RXMIX of the chip, and port 5, port 6, port 7 and port 8 of the interface J8 are all grounded; The port 1 of the interface J9 is connected to the pin LD33 of the chip, and the port 2 is connected to one end of the inductor L3. The other end of the inductor L3 is respectively connected to the ground capacitor C12 and the pins VDD12_XO and VDD12_SPI of the chip. The port 3 of the interface J9 is connected to one end of the inductor L2. The other end of the inductor L2 is respectively connected to the ground capacitor C10 and the pins VDD33_PFDCP and VDD33_PST of the chip. The port 4 of the interface J9 is connected to the pin SPI_DO of the chip. The port 5 of the interface J9 is connected to the pin SPI_DI of the chip. The port 6 of the interface J9 is connected to the pin SPI_DO of the chip. Connected to the pin SPI_CLK of the chip, port 7 of the interface J9 is connected to the pin SPI_ENB of the chip, port 8 of the interface J9 is connected to the pin RXPULSEU33 of the chip, port 9 of the interface J9 is connected to the pin TXPULSEU33 of the chip, port 10 of the interface J9 is connected to the pin RXPULSEL33 of the chip, port 11 of the interface J9 is connected to the pin TXPULSEL33 of the chip, port 12 of the interface J9 is connected to the pin TRIG_PULSE33 of the chip, and ports 13 and 14 of the interface J9 are both grounded; Port 1, port 2, port 3 and port 4 of the interface J10 are all connected to one end of the inductor L4, and the other end of the inductor L4 is respectively connected to the ground capacitor C15 and the pin VDD12_PA of the chip, and port 5, port 6, port 7 and port 8 of the interface J10 are all grounded; Port 1 and port 2 of the interface J11 are both connected to one end of the inductor L7, and the other end of the inductor L7 is respectively connected to the ground capacitor C20 and the pin VDD33_VT of the chip. Port 3 and port 4 of the interface J11 are both connected to one end of the inductor L6, and the other end of the inductor L6 is respectively connected to the ground capacitor C18 and the pin VDD12_DIV of the chip. Port 5 of the interface J11 is connected to the pin VCOSEL33 of the chip, and port 6 of the interface J11 is connected to the pin BANDSEL33 of the chip. Ports 7, 8 and 9 of the interface J11 are all grounded. Ports 10, 11 and 12 of the interface J11 are all connected to one end of the inductor L5, and the other end of the inductor L5 is respectively connected to the ground capacitor C16 and the pin VDD12_PA1 of the chip.

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