A radiation-resistant D flip-flop based on interconnect crosstalk calculation

Abstract

The present invention relates to a radiation-resistant D-type flip-flop based on interconnect crosstalk calculation. The flip-flop comprises a cascaded structure of a master latch module and a slave latch module. The master latch module converts input signals into dual-node redundant signals via a first interconnect crosstalk circuit (CC1), utilizing L1-L3 and L2-L3 capacitive coupling to implement logical storage where only two high-level inputs trigger high-level outputs. The slave latch module generates redundant signals L4 / L5 via a second interconnect crosstalk circuit and uses a Muller C unit to perform error correction on CC2 outputs and direct transmission signals. The D-type flip-flop requires only 16 minimum-size transistors, a 67% reduction compared to conventional TMR flip-flops. It supports asynchronous reset, forcing L3 / L6 to charge to a high level during reset. The capacitive coupling strength is controlled through metal layer routing, significantly improving the reliability of aerospace electronic systems in radiation environments.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, in particular to an anti-radiation D trigger based on interconnection line crosstalk calculation. Background Art

[0002] With the development of the aerospace industry, an increasing number of integrated circuit chips are being used in various aerospace equipment. However, aerospace equipment in outer space is subject to intense radiation effects. Integrated circuit chips operating in the radiation environment of space are susceptible to the effects of high-energy radiation particles, which can cause serious failures. When radiation particles pass through semiconductor devices or integrated circuits, they generate a large number of electron-hole pairs along their paths. These radiation-induced electron-hole pairs diffuse and drift under the influence of concentration gradients and electric fields, and are collected by reverse-biased PN junctions in the semiconductor device or circuit, ultimately causing performance degradation or functional failure of the semiconductor device or integrated circuit. This radiation phenomenon is collectively referred to as single-event effects (SEEs). For digital circuits, the main concerns are single-event transients (SETs), which often occur in combinational circuits, and single-event upsets (SEUs), which occur in memory circuits. Therefore, digital circuits for high-reliability applications such as space applications require radiation-hardened designs.

[0003] The D flip-flop is the most commonly used information storage device in digital integrated circuits. It is easily affected by radiation effects, which can affect the normal function of subsequent circuits. Therefore, it is very important to design radiation hardening for the D flip-flop.

[0004] Existing radiation hardening technologies for D-type flip-flops primarily employ triple modular redundancy (TMR) or a dual interlocked storage cell (DICE) structure. These techniques store data at different nodes and employ circuit self-recovery mechanisms to achieve SEU resistance in individual storage cells. However, the area overhead remains significant, with TMR increasing both area and power consumption by approximately 200%. Summary of the Invention

[0005] In order to solve the above technical problems, the present invention provides a radiation-resistant D flip-flop based on interconnect crosstalk calculation, comprising a cascade structure of a master latch module and a slave latch module;

[0006] The core of the master latch module is the first interconnect crosstalk calculation circuit CC1. Through the capacitive coupling mechanism between the interconnects L1, L2 and L3, when the positive clock CLK1 is valid, the input signal D is converted into a dual-node redundant signal L1 / L2 and stored in the interconnects. Only when L1 and L2 are simultaneously high, L3 is triggered to output a high level, and the master output signal Master_Out is generated through the second inverter NOT2.

[0007] The core of the slave latch module is a combination of a second interconnect crosstalk calculation circuit CC2 and a Muller C unit. Through the capacitive coupling mechanism of interconnects L4, L5, and L6, the master output signal is converted into a dual-node redundant signal L4 / L5 and stored when the reverse clock CLK2 is valid. Only when L4 and L5 are simultaneously high, L6 is triggered to output a high level. Combined with the error correction mechanism of the Muller C unit for CC2 output L6 and the directly transmitted signal, an anti-radiation output signal Q is generated.

[0008] Among them, the dual-node redundant storage works together with the Muller C error correction mechanism to disperse radiation-sensitive nodes through a physically isolated interconnect structure, thereby suppressing the propagation of single-event upsets (SEUs).

[0009] In one embodiment of the present invention, the primary latch module further includes:

[0010] The input signal port D is connected to the first inverter NOT1 and the first transmission gate TG1 in sequence. The first transmission gate TG1 is composed of a PMOS transistor MP2 and an NMOS transistor MN1. The gate of MP2 is connected to the positive clock CLK1, and the gate of MN1 is connected to the negative clock CLK2.

[0011] The output end of the first transmission gate TG1 is divided into two paths to drive the interconnection lines L1 and L2 of the first interconnection line crosstalk calculation circuit CC1 respectively, and the output end of L3 generates the main output signal Master_Out through the second inverter NOT2;

[0012] The asynchronous reset port Reset is connected to L3 through the PMOS tube MP1. When Reset is low, L3 is forced to charge to a high level.

[0013] In one embodiment of the present invention, the capacitive coupling mechanism of the first interconnect crosstalk calculation circuit CC1 is specifically:

[0014] The parallel trace spacing between L1 and L3 and L2 and L3 is controlled by layout design so that the coupling capacitance values ​​of L1 / L2 to L3 are the same;

[0015] The level state of L3 is jointly determined by L1 and L2: when L1 and L2 are both high, the coupling capacitor causes L3 to sense a high level; when either L1 or L2 is low, L3 maintains a low level due to charge leakage.

[0016] In one embodiment of the present invention, the slave latch module further includes:

[0017] The master output signal Master_Out is connected to the third inverter NOT3 and the second transmission gate TG2 in sequence. The second transmission gate TG2 is composed of a PMOS transistor MP4 and an NMOS transistor MN2. The gate of MP4 is connected to the reverse clock CLK2, and the gate of MN2 is connected to the forward clock CLK1.

[0018] The output end of the second transmission gate TG2 is divided into three paths: the first path drives L4, the second path drives L5, and the third path is directly connected to the first input end C1 of the Muller C unit; the output end L6 of the second interconnection line crosstalk calculation circuit CC2 is connected to the second input end C2 of the Muller C unit.

[0019] In one embodiment of the present invention, the logic rule for the Muller C unit to perform error correction is:

[0020] When C1 and C2 are both high, the output is high; when C1 and C2 are both low, the output is low; when the levels of C1 and C2 are inconsistent, the previous state remains unchanged;

[0021] Through this rule, when a single event effect causes any node of L4 / L5 / L6 to flip, the Muller C unit can shield the erroneous signal.

[0022] In one embodiment of the present invention, the capacitive coupling mechanism of the second interconnect crosstalk calculation circuit CC2 includes:

[0023] L4 and L5 are arranged in parallel on both sides of L6, and the symmetrical coupling capacitor structure ensures that L6 is driven to a high level only when L4 and L5 are both at a high level.

[0024] The asynchronous reset port Reset is connected to L6 through the PMOS tube MP3. When forced reset, L6 is charged to VDD.

[0025] In one embodiment of the present invention, the control logic of the clock is:

[0026] The master latch module samples the input signal D during the high level period of CLK1; the slave latch module samples the master output signal Master_Out during the low level period of CLK1 (i.e., the high level of CLK2);

[0027] The master-slave alternating latching mechanism blocks the propagation path of the single-particle transient SET pulse.

[0028] In one embodiment of the present invention, the capacitive coupling value between interconnects is set to 0.67 fF to 0.82 fF to achieve the signal coupling strength required for single event upset (SEU) protection.

[0029] In one embodiment of the present invention, the radiation-resistant D flip-flop circuit is composed of 16 transistors: 9 PMOS transistors, including MP1 to MP9, and 7 NMOS transistors, including MN1 to MN7, wherein:

[0030] MP1 and MP3 are dedicated to asynchronous reset; MP2, MP4 and MN1, MN2 form a transmission gate; MP5~MP7 and MN3~MN5 form an inverter; MP8~MP9 and MN6~MN7 form a Muller C unit.

[0031] In one embodiment of the present invention, the trigger integrates a total of 16 transistors, including 9 PMOS transistors, including MP1-MP9 and 7 NMOS transistors, including MN1-MN7. All transistors adopt minimum size design (channel length 40nm, width 120nm).

[0032] The above technical solution of the present invention has the following advantages over the existing technology: the radiation-resistant D-type flip-flop based on interconnect crosstalk calculation described in the present invention has an asynchronous reset port, which is conducive to function expansion; when the Reset signal is at a high level, the circuit is in a normal working state; when the Reset signal is at a low level, regardless of the state of the input signal and the clock signal, the output signal is immediately set to 0 and remains unchanged.

[0033] The invention eliminates the bistable structure of inverters connected end to end in the master-slave D flip-flop in the prior art, and utilizes the Muller C unit to effectively correct the error caused by the single event upset effect.

[0034] Compared with the existing radiation hardening technology, the radiation-hardened D flip-flop based on interconnect crosstalk calculation proposed in the present invention has a simple structure and a small area overhead, and is implemented with only 16 minimum-size transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0036] Figure 1 This is a schematic structural module block diagram of a radiation-resistant D flip-flop based on interconnect crosstalk calculation according to the present invention;

[0037] Figure 2 Schematic diagram of the interconnect crosstalk calculation circuit of the present invention;

[0038] Figure 3 This is a schematic diagram of the radiation-resistant D flip-flop circuit of the present invention;

[0039] Figure 4 This is a functional simulation diagram of the radiation-resistant D flip-flop described in the present invention. DETAILED DESCRIPTION

[0040] like Figure 1 As shown, this embodiment provides a radiation-resistant D flip-flop based on interconnect crosstalk calculation, which is composed of a master-level latch module and a slave-level latch module based on interconnect crosstalk calculation; the master-level latch module samples the input signal port signal D, stores the input signal D in the interconnect crosstalk calculation circuit, and transmits the obtained master-level output signal to the slave-level latch module; the slave-level latch module samples the master-level output signal, stores the master-level output signal in the interconnect crosstalk calculation circuit, and transmits the obtained slave-level output signal to the output signal port Q.

[0041] Specifically, the interconnect crosstalk calculation circuit principle is as follows Figure 2 As shown, it includes interconnects L11, L22, L33, and a PMOS transistor MP. The PMOS transistor MP is used as a charging transistor for the interconnect L33, with its source connected to the power supply, its gate connected to the external control port R, and its drain connected to one end of the interconnect L33. The interconnect crosstalk calculation is mainly realized by the interconnect capacitive coupling mechanism. Controlling the physical distance of the interconnect L11, L22, and L33 to control the capacitive coupling can achieve Figure 2 In the truth table, L33 senses a high level only when L11 and L22 are high. Furthermore, when the external control port R is low, the PMOS transistor MP can be turned on at any time to charge L33 to the power supply voltage VDD.

[0042] Specifically, the present invention proposes a radiation-resistant D flip-flop based on interconnect crosstalk calculation, such as Figure 3 As shown, it includes an input signal port D, a first inverter NOT1, a first transmission gate TG1, a first interconnection line crosstalk calculation circuit CC1, a second inverter NOT2, a third inverter NOT3, a second transmission gate TG2, a second interconnection line crosstalk calculation circuit CC2, a Muller C unit, an asynchronous reset Reset port, a master stage output signal port, a positive clock signal CLK1 port, a reverse clock signal CLK2 port, a slave stage input signal port, and an output signal port Q. It is composed of 9 PMOS transistors MP1 to MP9 and 7 NMOS transistors MN1 to MN7.

[0043] The first inverter NOT1 is composed of a PMOS transistor MP5 and an NMOS transistor MN3. The source of the PMOS transistor MP5 is connected to the power supply voltage VDD, the source of the NMOS transistor MN3 is connected to the ground, the drain of the PMOS transistor MP5 and the drain of the NMOS transistor MN3 are connected as the output end of the first inverter NOT1, and the gate of the PMOS transistor MP5 and the gate of the NMOS transistor MN3 are connected as the input end of the first inverter NOT1.

[0044] The first transmission gate TG1 is composed of a PMOS transistor MP2 and an NMOS transistor MN1. The gate of the PMOS transistor MP2 is connected to the positive clock signal CLK1 port, and the gate of the NMOS transistor MN1 is connected to the negative clock signal CLK2. The drain of the PMOS transistor MP2 and the drain of the NMOS transistor MN1 are connected as one end of the first transmission gate TG1, and the source of the PMOS transistor MP2 and the source of the NMOS transistor MN1 are connected as the other end of the first transmission gate TG1.

[0045] The first interconnect crosstalk calculation circuit CC1 is composed of interconnects L1, L2, L3, and a PMOS transistor MP1. The PMOS transistor MP1 is used as a charging transistor for the interconnect L3 and performs an asynchronous reset function. Its source is connected to the power supply, its gate is connected to the asynchronous reset port, and its drain is connected to one end of the interconnect L3.

[0046] The second inverter NOT2 is composed of a PMOS transistor MP6 and an NMOS transistor MN4. The source of the PMOS transistor MP6 is connected to the power supply voltage VDD, the source of the NMOS transistor MN4 is connected to the ground, the drain of the PMOS transistor MP6 and the drain of the NMOS transistor MN4 are connected as the output end of the second inverter NOT2, and the gate of the PMOS transistor MP6 and the gate of the NMOS transistor MN4 are connected as the input end of the second inverter NOT2.

[0047] The input end of the first inverter NOT1 serves as the input port D of the proposed radiation-resistant D-type flip-flop based on interconnect crosstalk calculation. One end of the first transmission gate TG1 is connected to the output end of the first inverter NOT1. The other end of the first transmission gate TG1 is connected to the L1 and L2 ends of the first interconnect crosstalk calculation circuit CC1 in two ways. The other end of the interconnect line L3 is connected to the input end of the second inverter NOT2. The output end of the second inverter NOT2 serves as the main-stage output signal.

[0048] The third inverter NOT3 is composed of a PMOS transistor MP7 and an NMOS transistor MN5. The source of the PMOS transistor MP7 is connected to the power supply voltage VDD, the source of the NMOS transistor MN5 is connected to ground, the drain of the PMOS transistor MP7 and the drain of the NMOS transistor MN5 are connected as the output end of the third inverter NOT3, and the gate of the PMOS transistor MP7 and the gate of the NMOS transistor MN5 are connected as the input end of the third inverter NOT3.

[0049] The second transmission gate TG2 is composed of a PMOS transistor MP4 and an NMOS transistor MN2. The gate of the PMOS transistor MP4 is connected to the reverse clock signal CLK2 port, and the gate of the NMOS transistor MN2 is connected to the forward clock signal CLK1. The drain of the PMOS transistor MP4 and the drain of the NMOS transistor MN2 are connected as one end of the second transmission gate TG2, and the source of the PMOS transistor MP4 and the source of the NMOS transistor MN2 are connected as the other end of the second transmission gate TG2.

[0050] The second interconnect crosstalk calculation circuit CC2 is composed of interconnects L4, L5, L6, and a PMOS transistor MP3. The PMOS transistor MP9 serves as a charging transistor for the interconnect L6 and performs an asynchronous reset function. Its source is connected to the power supply, its gate is connected to the asynchronous reset port, and its drain is connected to one end of the interconnect L6.

[0051] The Muller C unit is composed of two PMOS transistors MP8 and MP9 and two NMOS transistors MN6 and MN7. The source of the PMOS transistor MP8 is connected to the power supply voltage VDD, the source of the NMOS transistor MN7 is connected to the ground, the source of the PMOS transistor MP9 is connected to the drain of the PMOS transistor MP8, the drain of the NMOS transistor MN7 is connected to the source of the NMOS transistor MN6, the drain of the PMOS transistor MP9 and the drain of the NMOS transistor MN6 are connected as the output end of the Muller C unit, the gate of the PMOS transistor MP8 and the gate of the NMOS transistor MN7 are connected as the first input end C1 of the Muller C unit, and the gate of the PMOS transistor MP9 and the gate of the NMOS transistor MN6 are connected as the other input end C2 of the Muller C unit.

[0052] The input end of the third inverter NOT3 (the slave input signal port) is connected to the output end of the second inverter NOT2 (the master output signal). The output end of the third inverter NOT3 is connected to one end of the second transmission gate TG2. The other end of the second transmission gate TG2 is divided into three signal paths, two of which are respectively connected to one end of L4 and one end of L5 of the second interconnect crosstalk calculation circuit CC2. The third signal path at the other end of the second transmission gate TG2 is connected to the first input end C1 of the Muller C unit. The other end of the second interconnect L6 is connected to the other input end C2 of the Muller C unit. The output end of the Muller C unit serves as the slave output signal, which serves as the output signal port Q of the circuit proposed in the present invention.

[0053] Specifically, Figure 4 This is a functional simulation diagram of a radiation-resistant D flip-flop based on interconnect crosstalk calculation proposed by the present invention. Figure 4As can be seen in the figure, the radiation-resistant D-type flip-flop proposed in the present invention, based on interconnect crosstalk calculation, operates normally when the asynchronous reset signal Reset remains high. It is triggered by the rising edge of the positive clock CLK. Only when the positive clock CLK rises does the output signal Q flip to D, and at all other times, the output signal Q maintains its previous state. When the asynchronous reset signal Reset goes low, PMOS transistors MP1 and MP3 conduct, interconnects L3 and L6 are charged to the power supply voltage VDD, and output signal Q is set to a low level, implementing the asynchronous reset function. Furthermore, at 5ns, when a single-event transient pulse is injected into a sensitive node of the D-type flip-flop circuit, the radiation-resistant D-type flip-flop proposed in the present invention, based on interconnect crosstalk calculation, maintains normal operation without state flipping, demonstrating the proposed circuit's excellent single-event upset resistance.

[0054] Furthermore, if Figure 4 As shown, the anti-radiation mechanism verification of the functional simulation diagram includes:

[0055] Simulation conditions: process node: 40nm CMOS; operating voltage: 1.1V; temperature: 25°C; clock frequency: 500MHz; single-event injection model: double-exponential current source (pulse width 100ps, charge 15fC).

[0056] In addition, the key waveforms are analyzed in sections, including:

[0057] Normal operation phase (0-4ns): When the asynchronous reset signal Reset = 1 (high level), the output signal Q is synchronously updated to the input D value (D = 1 → Q = 1) at the rising edge of CLK (such as 2ns).

[0058] Capacitive coupling verification: At 3.5ns, when D jumps from 1 to 0, the main-level interconnect lines L1 / L2 synchronously return to zero, and L3 senses a low level after a delay of <10ps, proving that the capacitive coupling mechanism of the interconnect lines is effective.

[0059] Asynchronous reset phase (4-6ns): Reset = 0 triggers reset; PMOS tubes MP1 / MP3 are instantaneously turned on → L3 / L6 are forcibly charged to VDD (1.1V) → through inverter NOT2 and Muller C unit → Q is built-in to 0 in <200ps; at this time, the changes of CLK and D signals are blocked, proving that the reset priority mechanism is effective.

[0060] SEU immunity demonstration (5ns single-event injection): Injection location: Main-stage sensitive node of interconnect L1 (simulation intentionally weakens protection). Particle effect: Brief voltage drop on L1 (amplitude 0.8V, pulse width 100ps).

[0061] Error correction process: L1 is abnormal → but L2 remains normal → the output L3 of the first interconnect crosstalk circuit (CC1) does not fluctuate (dual-node redundancy tolerates single-point flipping); the Muller C unit detects C1 / C2 consistency → maintains output Q=0.

[0062] At the same time, the specific layout structure: interconnection line layer: M4 thick copper layer (thickness ≥ 0.5μm, to reduce resistance noise); geometric parameters: parallel trace length 2.5μm, line width 0.1μm, spacing 0.08μm;

[0063] And the capacitance calculation model: ;

[0064] (A: subtended area, d: spacing, L: parallel length); Substituting 40nm process parameters: C = 0.746fF;

[0065] Therefore, 0.746fF is the optimal solution: at 100% SEU suppression, the delay (42ps) accounts for only 2.1% of the clock period (2ns), meeting the <5% high-speed circuit timing constraint.

[0066] In summary, this example uses the Spectre module in Cadence Virtuoso software to simulate the proposed radiation-resistant D-type flip-flop based on interconnect crosstalk calculation. Both the N-type and P-type transistors used have a 40nm feature size, that is, the channel length is fixed at 40nm, the channel width is fixed at 120nm, and the interconnect crosstalk capacitive coupling is set to 0.746fF.

[0067] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.

Claims

1. A radiation-resistant D flip-flop based on interconnect crosstalk calculation, characterized in that: A cascade structure comprising a master latch module and a slave latch module; The primary latch module includes: an input signal port connected in sequence to a first inverter and a first transmission gate, wherein the first transmission gate is composed of a PMOS transistor MP2 and an NMOS transistor MN1, wherein the gate of MP2 is connected to a positive clock and the gate of MN1 is connected to a reverse clock; The output end of the first transmission gate is divided into two paths to respectively drive the interconnection lines L1 and L2 of the first interconnection line crosstalk calculation circuit, and the output end of L3 generates a main-stage output signal through the second inverter; The asynchronous reset port is connected to L3 through the PMOS tube MP1. When Reset is low, L3 is forced to charge to a high level. The core of the primary latch module is the first interconnect crosstalk calculation circuit. Through the capacitive coupling mechanism between the interconnects L1, L2, and L3, the input signal is converted into a dual-node redundant signal and stored in the interconnect when the positive clock is valid. Only when L1 and L2 are simultaneously high, L3 is triggered to output a high level, and the primary output signal is generated through the second inverter. The slave latch module includes: the master output signal is connected to the third inverter and the second transmission gate in sequence, the second transmission gate is composed of a PMOS transistor MP4 and an NMOS transistor MN2, the gate of MP4 is connected to the reverse clock, and the gate of MN2 is connected to the forward clock; The output of the second transmission gate is divided into three paths: the first path drives L4, the second path drives L5, and the third path is directly connected to the first input terminal C1 of the Muller C unit; the asynchronous reset port is connected to L6 through the PMOS transistor MP3, and the output terminal L6 of the second interconnect crosstalk calculation circuit is connected to the second input terminal C2 of the Muller C unit; The core of the slave latch module is a combination of a second interconnect crosstalk calculation circuit and a Muller C unit. Through the capacitive coupling mechanism of interconnects L4, L5, and L6, the master output signal is converted into a dual-node redundant signal and stored when the reverse clock is valid. Only when L4 and L5 are simultaneously high, L6 is triggered to output a high level. Combined with the error correction mechanism of the Muller C unit for the CC2 output terminal and the directly transmitted signal, a radiation-resistant output signal is generated. Among them, the dual-node redundant storage works together with the Muller C unit error correction mechanism to disperse radiation-sensitive nodes through a physically isolated interconnect structure, thereby suppressing the propagation of single-particle upsets.

2. The radiation-resistant D flip-flop based on interconnect crosstalk calculation according to claim 1, characterized in that: The capacitive coupling mechanism of the first interconnect crosstalk calculation circuit is specifically: The parallel trace spacing between L1 and L3 and L2 and L3 is controlled by layout design so that the coupling capacitance values ​​of L1 / L2 to L3 are the same; The level state of L3 is jointly determined by L1 and L2: when L1 and L2 are both high, the coupling capacitor causes L3 to sense a high level; when either L1 or L2 is low, L3 maintains a low level due to charge leakage.

3. The radiation-resistant D flip-flop based on interconnect crosstalk calculation according to claim 1, characterized in that: The logical rule for error correction performed by the Muller C unit is: When C1 and C2 are both high, the output is high; when C1 and C2 are both low, the output is low; when the levels of C1 and C2 are inconsistent, the previous state remains unchanged; Through this rule, when a single event effect causes any node of L4 / L5 / L6 to flip, the Muller C unit can shield the erroneous signal.

4. The radiation-resistant D flip-flop based on interconnect crosstalk calculation according to claim 1, characterized in that: The capacitive coupling mechanism of the second interconnect crosstalk calculation circuit includes: L4 and L5 are arranged in parallel on both sides of L6, and the symmetrical coupling capacitor structure ensures that L6 is driven to a high level only when L4 and L5 are both at a high level. The asynchronous reset port is connected to L6 through the PMOS tube MP3. When forced reset, L6 is charged to VDD.

5. The radiation-resistant D flip-flop based on interconnect crosstalk calculation according to claim 1, characterized in that: The control logic of the clock is: The master latch module samples the input signal during the high level period of CLK1; the slave latch module samples the master output signal during the low level period of CLK1; The master-slave alternating latching mechanism blocks the propagation path of single-particle transient pulses.

6. The radiation-resistant D flip-flop based on interconnect crosstalk calculation according to claim 1, characterized in that: The capacitive coupling value between interconnects is set to 0.67fF to 0.82fF.

7. The radiation-resistant D flip-flop based on interconnect crosstalk calculation according to claim 1, characterized in that: The radiation-resistant D flip-flop circuit consists of 16 transistors: 9 PMOS transistors and 7 NMOS transistors, of which: MP1 and MP3 are dedicated to asynchronous reset; MP2 and MN1 form the first transmission gate, MP4 and MN2 form the second transmission gate; MP5 and MN3 form the first inverter, MP6 and MN4 form the second inverter, MP7 and MN5 form the third inverter; MP8~MP9 and MN6~MN7 form the Muller C unit.

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