A method for parsing and collecting data of a high-speed analog-to-digital converter

Abstract

The application discloses a kind of high-speed analog-digital converter data's analysis and acquisition method, it is related to integrated circuit mass production test field, comprising: the clock of the high-speed analog-digital converter to be tested is synchronized with the clock of automatic test equipment;The high-speed analog-digital converter to be tested sends synchronization feature code, and automatic test equipment writes synchronization feature code as vector file;Clock data recovery is realized by stepping scanning to vector file;Collect the output data of the high-speed analog-digital converter to be tested until test ends;A plurality of sampling data are acquired, each sampling data is identified and displacement comparison is obtained data conversion starting position;Based on the starting position of data conversion, all sampling data are correspondingly combined to obtain final conversion data, based on final conversion data, corresponding performance index is obtained by calculation, and test is completed;The purpose of the application is to use the PSSL board card of test machine V93000 to realize the collection and protocol analysis of high-speed ADC JESD204B interface data.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit mass production testing, in particular, to a method for analyzing and collecting data of high-speed analog-to-digital converter. BACKGROUND

[0002] JESD204B protocol is a general data interface for current high-speed analog-to-digital converter (hereinafter referred to as high-speed ADC), and the maximum rate of a single data lane under this protocol can reach 12.5Gbps, supporting simultaneous transmission of multiple data lanes.

[0003] Automatic test equipment (hereinafter referred to as ATE) is a general batch production test equipment in the field of integrated circuits, which is highly integrated, developed and data standardized, and has the best development and test efficiency in the mass production testing of integrated circuits. Therefore, high-speed converter chips still mainly rely on ATE in testing. Currently, only A brand V93000 and B brand ultraflex on the market support serdes interface, among which ultraflex can currently support up to 10.7Gbps, and V93000 can support up to 16Gbps. Only the PSSL board card resource of A brand V93000 of the two manufacturers can meet the demand of JESD204B 12.5Gbps. The PSSL board card supports this rate, but the board card does not support protocol analysis, so it cannot collect data.

[0004] However, the high-speed serdes board cards currently launched by leading ATE manufacturers, such as US10G on ultraflex of B brand and PS9G on V93000 of A brand, cannot support the maximum rate of JESD204B 12.5Gbps. Currently, only the PSSL board card of V93000 can reach a maximum rate of 15Gbps, but the board card only supports eye diagram analysis function, and the official does not support protocol analysis. The eye diagram analysis function is simple and cannot meet the test requirements, and cannot use the JESD204B protocol interface to transmit data.

[0005] In summary, the existing technology has the following disadvantages:

[0006] The ATEs on the market cannot support the protocol analysis of JESD204B interface with a rate of up to 12.5Gbps, because the only board card that can support 12.5Gbps in the ATEs on the market is the PSSL board card of A brand V93000, and the board card can only perform physical layer testing and does not provide related tools for protocol analysis. Therefore, it cannot complete the testing of high-speed ADCs with this type of interface. SUMMARY

[0007] The application aims at realizing the collection and protocol analysis of the JESD204B interface data of the high-speed ADC by using the PSSL board card of the test platform V93000.

[0008] To realize the above-mentioned application purposes, the application provides a kind of high-speed analog-digital converter data analysis and collection method, the method comprises:

[0009] Step 1: configure the interface rate of the high-speed analog-digital converter to be tested and the automatic test equipment to be consistent, synchronize the clock of the high-speed analog-digital converter to be tested and the clock of the automatic test equipment;

[0010] Step 2: use the automatic test equipment to force the SYNC pin level of the high-speed analog-digital converter to be tested to be low, send a synchronization request signal to the high-speed analog-digital converter to be tested, and the high-speed analog-digital converter to be tested sends a synchronization signature, and the automatic test equipment writes the synchronization signature as a vector file;

[0011] Step 3: use the automatic test equipment to step scan the vector file, obtain the clock offset of the automatic test equipment and the high-speed analog-digital converter to be tested on the signal transmission link, and realize clock data recovery based on the clock offset;

[0012] Step 4: use the automatic test equipment to force the SYNC pin level of the high-speed analog-digital converter to be tested to be high, and the automatic test equipment collects the output data of the high-speed analog-digital converter to be tested until the test is completed;

[0013] Step 5: collect a plurality of sampling data, identify each sampling data by taking a preset data as a signature word, and obtain the starting position of data conversion by comparing the bit displacement of each sampling data;

[0014] Step 6: based on the starting position of data conversion, all sampling data are correspondingly combined to obtain the final conversion data, and the corresponding performance index is calculated based on the final conversion data, and the test is completed.

[0015] The application is based on the bert test, the signature of the JESD204B protocol is edited, the code shape is scanned and compared by using the loop function, the data clock recovery is finally realized, the collection and analysis of the JESD204B data are realized, and the mass production test problem of the high-speed ADC is finally solved.

[0016] Preferably, the interface rate of the automatic test equipment is greater than the preset rate, and the automatic test equipment supports physical layer test but does not support protocol layer test. The interface rate of the automatic test equipment is greater than 12.5Gbps, and the automatic test equipment does not support the protocol analysis of the JESD204B interface.

[0017] Preferably, to ensure the reliability of clock data recovery, the step 2 further comprises: repeating the control word in the vector file at least 3 times.

[0018] Preferably, the step 3 utilizes the scan function of the automatic test equipment to step scan the vector file.

[0019] Preferably, the step 5 shifts and compares each piece of sampling data with a window of 10 bit length.

[0020] Preferably, the step 6 specifically comprises: converting each piece of sampling data based on the starting position of data conversion to obtain converted data, combining all the converted data to obtain final converted data, calculating the corresponding performance index based on the final converted data to complete the test.

[0021] Preferably, the step 3 utilizes the scan function fastAdjustment of the automatic test equipment to step scan the vector file.

[0022] The one or more technical solutions provided by the present application have at least the following technical effects or advantages:

[0023] 1. By fully utilizing the PSSL board card of the existing V93000, the test of the high-speed ADC with the JESD204B interface is realized.

[0024] 2. The test structure is simple. The test of the high-speed ADC with the JESD204B interface can be completed by connecting the test board card on the V93000 machine, without the need of additional auxiliary equipment, and the test is more concise.

[0025] 3. The cost is low. The data acquisition and analysis of JES204B can be realized by code, without the need of purchasing expensive logic analyzers and protocol analyzers.

[0026] 4. The test platform has high stability. Since the method has a simple structure, in addition to the ATE, only the test board is needed, and after removing other peripherals, the control of the entire test platform is relatively simple, which ensures the stability of the platform. BRIEF DESCRIPTION OF DRAWINGS

[0027] The accompanying drawings, which are included to provide a further understanding of the embodiments of the present application and constitute a part of the present application, illustrate embodiments of the present application and do not constitute a limitation of the embodiments of the present application.

[0028] Figure 1 is a schematic diagram of JESD204B protocol interaction logic;

[0029] Figure 2 is a schematic diagram of the technical solution implementation platform structure of the method;

[0030] Figure 3is a flowchart of the implementation process of the method;

[0031] Figure 4 is a schematic diagram of the scanning result;

[0032] Figure 5 is a schematic diagram of the feature code matching process. DETAILED DESCRIPTION

[0033] In order to enable the above-mentioned objects, features and advantages of the present application to be more clearly understood, the present application will be further described below with reference to the drawings and specific embodiments. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0034] In the following description, many specific details are set forth in order to provide a thorough understanding of the present application, however, the present application can also be practiced in other ways different from those described herein, and therefore, the scope of protection of the present application is not limited by the specific embodiments disclosed below.

[0035] Embodiment one;

[0036] PSSL is the highest speed board card sold by V93000 type ATE, which can support a maximum of 16Gbps, and its official manual describes that only bert test, i.e. physical layer test, is supported, and at the protocol layer, any protocol is not supported because the manufacturer does not provide any tool and interface. The JESD204B protocol interaction logic is as shown in Figure 1 The JESD204B protocol interaction logic is as follows: the receiver pulls down the SYNC to initiate a synchronization request, the transmitter sends K28.5 (0xBC), the receiver completes the clock data recovery (CDR) to realize the transceiver clock synchronization and pulls up the SYNC, the transmitter starts the initial lane alignment (ILAS) at the edge of the local multi-frame clock (LMFC), and the transmitter starts transmitting data after 4 or more multi-frames.

[0037] The present application is based on bert test, through editing the feature code shape of JESD204B protocol, and using the scanning function to compare the code shape, finally realizing the data clock recovery, and then through the program to realize the collection and analysis of JESD204B data, finally solving the production test problem of high-speed ADC.

[0038] The embodiment of the present application is made into an automatic program according to the mode of Figure 2 Platform structure diagram, and then the ADC is tested one by one.

[0039] The technical solution adopted by the present application to solve the technical problem is to implement a platform as shown in Figure 2 , which includes a test system ATE and a test board.

[0040] Please refer to Figure 3 The method for analyzing and collecting data of a high-speed analog-to-digital converter (ADC) in an embodiment of the application is implemented by the following steps:

[0041] Step 1: The serdes interface rate of the high-speed ADC and the V93000 is configured to be consistent, and the ADC clock is synchronized with the V93000 clock to ensure that the sending end and the receiving end have a deterministic phase relationship.

[0042] Step 2: The V93000 pulls down the SYNC pin of the high-speed ADC to initiate a synchronization request to the high-speed ADC, and the high-speed ADC sends a synchronization signature K28.5, while the V93000 writes the signature K28.5 into a vector file pattern (used as a marker for subsequent comparison), to ensure the reliability of clock data recovery, the control word in the pattern needs to be repeated more than 3 times.

[0043] Step 3: The pattern in step 2 is step-scanned by using the scan function fastAdjustment of the V93000, and the step length is generally not more than 0.1 times the serdes period (the smaller the scan step, the more accurate the offset found, but the longer the time spent), to find the clock offset between the V93000 and the high-speed ADC on the serdes link, and to realize clock data recovery (CDR).

[0044] Step 4: The SYNC pin of the ADC is pulled high, and at the same time the V93000 starts collecting the output data of the high-speed ADC until the test is completed (the storage depth of the ATE determines the length of the collected data, and the total amount of test data cannot exceed the size of the storage depth).

[0045] Step 5: D25.1 (0x259) and D26.1 (0x25A) are used as signature words for identification, where D25.1 and D26.1 are chapter numbers in the JESD204B protocol, and 0x259 / 0x25A are signature words. Since the frame length of the protocol JESD204B is 10 bits, a 10-bit window is used to determine the starting position of the converted data by shifting the program. The purpose of identifying each sample data with a preset data as a signature word is to determine the specific position of the data by taking the signature word as a reference. The specific program shifting step or method is: the data is in binary format, and it is determined whether the data from the first bit to the 10th bit is the signature code. If not, it is determined whether the data from the second bit to the 11th bit is the signature code, and so on.

[0046] Step 6: According to the framing format in the high-speed ADC manual, a program is written to automatically combine the sampling data of each LANE to obtain the final conversion data, and the related performance indicators are calculated to complete the test. The specific steps of the program are as follows: the JESD204B link is configured as shown in Table 2, the first 8-bit data and the second 8-bit data of LANE0 are combined to form the data of the first ADC, and the subsequent data is sequentially combined.

[0047] Wherein, the ADC has many interfaces, each interface will transmit part of the data, and the complete data needs to be combined with the data of the corresponding interface, for example, data A may be from interface 1 and interface 3 respectively, at this time, the data of interface 1 and interface 3 needs to be combined.

[0048] Wherein, the method obtains the final conversion data, and the related performance indicators are calculated by the existing calculation method, and the specific calculation method and performance indicator type are not limited in the embodiments of the application.

[0049] In the 8B and 10B (i.e. 8bit and 10bit) encoding used in JESD204B, to realize direct current balance, 8bit data will be converted into 1 10bit or 2 10bit (i.e. 20bit) data, so the 8bit data sent by the physical layer cannot be directly located from the original code stream, resulting in data parsing failure. The following Table 1 lists the typical characteristic encoding rules:

[0050] Table 1-8B10B encoding rules

[0051] Character 8B 10B (RD-) 10B (RD+) K28.0 0x1C 0x0F4 0x30B K28.5 0xBC 0x17C 0x283 D25.1 0x39 0x259 0x259 D26.1 0x3A 0x25A 0x25A

[0052] The PSSL board card of V93000 does not support the protocol, but can record the vector state through the pattern. Here, K28.5 is used as the characteristic code shape of clock data recovery, and since K28.5+(0x283) and K28.5-(0x17C) are continuously sent after receiving the synchronization request in the synchronization stage, the code shape is edited as the vector file pattern for the judgment condition of clock data recovery. The specific method is to use the scan function fastAdjustment, the step size is set to less than one tenth of the SerDes period, the scan range is from 0 clock to 10bit period, the SerDes data is repeatedly collected, and compared with the K28.5± characteristic code shape, and the comparison result is fail-pass-fail (as shown in Figure 4 ).

[0053] Figure 4The middle white color is pass, and the black color is fail, the maximum window area of pass is found, and the stepping amount corresponding to the center of the area is the clock offset amount of the V93000 and the high-speed ADC (the center is the center of the eye diagram, and represents a typical value of the clock deviation). The offset amount is used as a fixed time difference for subsequent data acquisition, that is, the data clock recovery (CDR) is realized.

[0054] After the CDR is completed, the ATE needs to control the high-speed ADC to set the SYNC low (indication of the end of synchronization, and the ADC will send the local multi-frame synchronization and data), and simultaneously input the test waveform to the ADC, and collect the SerDes until the test is completed. The collected data can involve multiple lanes, and the number of lanes is determined according to the SerDes interface number of the ADC. The data of each lane is processed respectively, and the characteristic code shape is compared bit by bit with a 10-bit length window. It can be seen from the 8B10B encoding rule table that the data of 10B+ and 10B- of the two characteristic codes [D25.1, D26.1] is consistent, and it is easier to select the characteristic code as the starting bit of the channel data, so [D25.1, D26.1] is used as the trigger code of the starting bit of the channel data, as shown in the following table. Figure 5

[0055] After the starting bit of each lane is identified, the 8B10B encoding rule in the JESD204B protocol is used for decoding. Since the PSSL board card does not support the protocol, the high-speed ADC data needs to be set to the non-scrambling mode. The decoded data is combined according to the frame format description in the ADC manual, so that the final conversion data is obtained. Taking the AD9208 as an example, the frame grouping format is shown in Table 2, and Table 2 is a data frame grouping table. In Table 2, Bx represents the xth conversion data of sub-ADC2; L represents the number of lanes; M represents the number of sub-ADCs; F represents the length of a frame period; S represents the number of conversion data contained in a frame period; Ax represents the xth conversion data of sub-ADC1; in Table 2, L=4, M=2, F=12, S=16, octet=8bits, which is a basic unit for ensuring data standardization in networks and computers.

[0056] Table 2

[0057] octet0 octet1 octet2 octet3 octet4 octet5 octet6 octet7 octet8 octet9 octet10 octet11 LANE0 A0[11:4] A0[3:0], A1[11:8] A1[7:0] A2[11:4] A2[3:0], A3[11:8] A3[7:0] A4[11:4] A4[3:0], A5[11:8] A5[7:0] A6[11:4] A6[3:0], A7[11:8] A7[7:0] LANE1 A8[11:4] A8[3:0], A9[11:8] A9[7:0] A10[11:4] A10[3:0], A11[11:8] A11[7:0] A12[11:4] A12[3:0], A13[11:8] A13[7:0] A14[11:4] A14[3:0], A15[11:8] A15[7:0] LANE2 B0[11:4] B0[3:0], B1[11:8] B1[7:0] B2[11:4] B2[3:0], B3[11:8] B3[7:0] B4[11:4] B4[3:0], B5[11:8] B5[7:0] B6[11:4] B6[3:0], B7[11:8] B7[7:0] LANE3 B8[11:4] B8[3:0]，89[11:8] B9[7:0] B10[11:4] B10[3:0], B11[11:8] B11[7:0] B12[11:4] B12[3:0], B13[11:8] B13[7:0] B14[11:4] B14[3:0], B15[11:8] B15[7:0]

[0058] The combined data is processed and calculated (such as FFT), and the related indexes and parameters of the high-speed ADC are obtained.

[0059] The application realizes the data acquisition and analysis of the JESD204B without frame synchronization and alignment on the test platform V93000.

[0060] ​While the preferred embodiments of the application have been described, additional variations and modifications can be made to these embodiments by those skilled in the art once they have the benefit of the present disclosure without departing from the spirit and scope of the application. Accordingly, it is intended that the appended claims include all such modifications and variations as fall within the scope of the present application.

[0061] It is apparent that those skilled in the art can make various changes and modifications to the application without departing from the spirit and scope of the application. It is therefore intended that the present application cover all such changes and modifications that are within its scope.

Claims

1. A method for parsing and acquiring data from a high-speed analog-to-digital converter, characterized in that, The method includes: Step 1: Configure the interface rate of the high-speed analog-to-digital converter under test and the automatic test equipment to be consistent, and synchronize the clock of the high-speed analog-to-digital converter under test with the clock of the automatic test equipment; Step 2: Use the automatic test equipment to force the SYNC pin level of the high-speed analog-to-digital converter under test to be low, send a synchronization request signal to the high-speed analog-to-digital converter under test, the high-speed analog-to-digital converter under test sends a synchronization feature code, and the automatic test equipment compiles the synchronization feature code into a vector file; Step 3: Use an automated test device to perform a step scan on the vector file to obtain the clock offset between the automated test device and the high-speed analog-to-digital converter under test on the signal transmission link, and realize clock data recovery based on the clock offset; Step 4: Use an automated test device to force the SYNC pin level of the high-speed analog-to-digital converter under test to be high, and the automated test device will collect the output data of the high-speed analog-to-digital converter under test until the test is completed; Step 5: Collect multiple sample data, identify each sample data using preset data as feature codewords, and perform displacement comparison on each sample data to obtain the starting position of data conversion; Step 6: Based on the starting position of the data transformation, combine all the sampled data accordingly to obtain the final transformed data. Based on the final transformed data, calculate the corresponding performance indicators to complete the test. Step 6 specifically includes: transcoding each sampled data based on the starting position of the data conversion to obtain converted data, combining all the converted data accordingly to obtain the final converted data, and calculating the corresponding performance indicators based on the final converted data to complete the test.

2. The method for parsing and acquiring high-speed analog-to-digital converter data according to claim 1, characterized in that, The interface rate of the automatic test equipment is greater than the preset rate. The automatic test equipment supports physical layer testing but does not support protocol layer testing.

3. The method for parsing and acquiring high-speed analog-to-digital converter data according to claim 1, characterized in that, Step 2 further includes repeating the control word in the vector file at least 3 times.

4. The method for parsing and acquiring high-speed analog-to-digital converter data according to claim 1, characterized in that, In step 3, the vector file is scanned stepwise using the scanning function of the automated testing equipment.

5. The method for parsing and acquiring high-speed analog-to-digital converter data according to claim 1, characterized in that, Step 5 involves shifting and comparing each sampled data point using a 10-bit window.

6. The method for parsing and acquiring high-speed analog-to-digital converter data according to claim 1, characterized in that, In step 3, the fastAdjustment function of the automated testing equipment is used to perform a step scan on the vector file.

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